VIT UNIVERSITY VELLORE,TAMILNADU-632014

Mr. CHAVAN SUYOG MADHUKAR M.Tech (VLSI Design)

E-mail: suyogelectronics@gmail.com Mobile No: (+91)8680929463 LinkedIn : in.linkedin.com/pub/suyog-chavan/6a/703/65a

Objective:

Looking for a responsible position as a VLSI design engineer with a view to utilize and enhance my skills and experience towards professional growth.

Academic Qualifications:

Degree/ Examination

Board/University School/Institute Year of passing

Percentage / CGPA

M.Tech (VLSI Design)

Vellore Institute of Technology(VIT) University,Vellore.(TN)

Vellore Institute of Technology(VIT), Vellore.(TN)

May-2015

8.16 CGPA (First Class with Distinction)

B.Tech (Electronics and Telecom.)

Dr.BATU,Lonere-Raigad (MS)

Dr.BATU,Lonere-Raigad (MS)

May-2012

7.58 CGPA (First Class With Distinction)

H.S.C Maharashtra State Board

Y.C.College Of Science,Karad (MS)

Feb-2008

83.50% (First Class with Distinction)

S.S.C Maharashtra State Board

Jijamata Vidyalaya Chore.(MS)

Mar-2006

85.33% (First Class with Distinction)

Technical Skills :

Programming languages- Verilog HDL,Systm Verilog HVL,VHDL,C

Thorough Knowledge of Universal Verification Methodology (UVM)

ASIC Design Tools –Cadence Virtuoso Analog Design Environment , Virtuoso Spectre Circuit Simulator and Assura Physical Verification ,Cadence NCLaunch RTL Compiler, SoC Encounter Digital Implementation System, Virtuoso Schematic Editor

Scripting Languages : PERL

Good knowledge of Static Timing Analysis

Design and Verification Tools : Mentor Graphics-Modelsim 6.6d, QuestaSim

Publication:

Published Journal paper on “ASIC Implementation of High Throughput PID Controller” in International Journal of Engineering Development and Research (IJEDR),Volume-2,Issue no-3. ISSN:2321-9939.

Areas of Interest:

ASIC Design and Verification.

FPGA Based System Design.

Digital System Design.

Academic Projects:

[1]Design and Verification of SPI IP using UVM. (M.Tech Master Thesis)

HVL: SystemVerilog

Methodology: UVM

EDA Tools: Modelsim, Questa - Verification Platform and ISE

Serial Peripheral Interface (SPI) is an interface that facilitates the transfer of synchronous serial data. I designed open core SPI IP using Verilog . I Architected the class based verification environment using UVM,verified the RTL model using class based UVM TB and generated functional and code coverage for the RTL verification sign-off

[2] SRAM Verification Using Verilog. (PG)

Tool and Language Used: Modelsim,Verilog

Verilog code for DUT, Bus Function Module (BFM), checker module and monitor Module for SRAM have been written and verification has been done by passing various testcases to DUT also checked coverage reports for various testcases.

[3] ASIC Implementation of High Throughput PID Controller.(PG)

Tools Used: Modelsim, RTL Compiler(Cadence), SoC Encounter (Cadence)

The PID Architecture using Pipelining and Han Carlson adder has been simulated and implemented using Verilog HDL. Synthesis has been done using RTL compiler and Back end has been done using SoC Encounter Tool.

[4] FPGA Implementation of Low Power FIR Filter. (PG)

Tools and languages Used: Modelsim, RTL Compiler (Cadence) and Verilog

A low power FIR filter using Booth multiplication algorithm and carry save adder designed in verilog. RTL Compiler used for synthesis and for calculating the speed, power and area of the implemented architecture The results are Verified on Altera DE2 FPGA board.

[5] Design of Multistage Noise Shaping Sigma Delta ADC.(PG)

Tool Used : Virtuoso (Cadence)

A first-order 1-bit sigma-delta (Σ-Δ) analog-to-digital converter is designed and simulated using Cadence Virtuoso with 90nm CMOS process technology. We cascaded the three stages of Sigma delta ADC which is useful for the noise shaping applications. We compared the simulation results for the noise reduction purpose with the traditional architecture

[6] VHDL Implementation of 16 bit CPU. (B.Tech Project)

Tools and language used: Xilinx ISE and VHDL

In this project, a 16-bit CPU has been designed, simulated and implemented using VHDL. In the implementation part, the codes have been downloaded as a single CPU unit on the SPARTAN 2 FPGA Kit using Xilinx ISE7.2.

Courses and Workshops:

Completed One month Course on C Programming with A Grade from State Institute.

Attended One day workshop on “System Verilog for Verification” at VIT University Organized by MAVEN SILICON.

Achievement:

Qualified GATE-2015 Exam with 311 score

Personal Profile:

Date Of Birth : 28 March, 1991. Marital Status : Single Permanent Address : Madhusuman,Umbraj,Satara-415109 (Maharashtra) Languages Known : English, Hindi and Marathi