Jason (Chi-Sheng) Chang (C) (408)368-9344, Email: jason_chang@yahoo.com

OBJECTIVE Looking for ASIC Design/Architect position

EDUCATION MSEE, University of Southern California, CA (Dec./1995)

SKILLS

Language Verilog, Perl, Makefile, TCL

Tools Synopsys Synthesis, PrimeTime, Spyglass, Formality/LEC, VCS

Specialist Area IC Design and Development methodology, SOC architect

Protocol PCI, PCIe, AMBA AXI, USB

WORK EXPERIENCE: >15 Years IC Design/Verification Experience

10/06 – Now PMTS. AMD

Low Power Client SOC Project: (04/15 - Now)

Managing USB3.1 host controller integration in Low Power Client SOC. Involving with

architecture defining for performance, power, and clocking with SOC. Working crosses

functional teams, including AMD internal and external teams.

Server SOC Project: (06/14 - 06/15)

Define micro architecture spec for AMD proprietary data fabric design to connect

between South-Bridge and North-Bridge functions inside SOC. Lead design and

verification teams and delivered IP design to server SOC based on 14nm technology.

Managed and defined USB3.0 host controller integration strategy for server SOC.

Working cross functional team between System architect, RTL design, verification, DFT,

Synthesis, Physical Design teams, and external IP teams. Works involved 3rd party

digital IP, PHY integration into AMD SOC.

PMTS. AMD

Client SOC Project: (02/13 - 05/14)

Architected the USB3.0 OTG 3rd party IP integration into mobile platform SOC. Lead

the execution to integrate USB3.0 OTG and working with platform team, driver team on

platform solution.

SMTS. AMD

Client SOC Projects: (02/10 - 12/12)

Architected and designed internal bridge to connect all IO controllers with North-Bridge

into single SOC. Design needs to communicate between PCI, PCIe, and AMBA AXI

protocols. PCIe Ordering between different bus protocol was the main challenge.

Worked with platform team on silicon bring-up and debug. SOC has gone mass

production.

SMTS. AMD

SB900 Project: (01/09 – 01/10)

Leading a functional team with US and China resource to work on PCI Express 2.1

bridge RTL design, verification, and integration. Design includes PCIe 2.1 ECN for

server platform requirement and making sure timing requirement between core and PHY

interface can be met. Bridge between front-end and back-end teams to smooth P&R

process.

SB800 project: 7M gates (04/08 – 03/09)

Responsible for PCI Express 2.0 bridge micro-architecture definition, Verilog RTL

(300K gates) design, and PHY integration. In charge of improving front-end design flow

for South Bridge team. Responsible for full chip netlist generation and worked with P&R

team for netlist delivery. Created new timing analysis flow, including OCV and

PrimeTime-SI, for SB800 and took responsibility in timing closure for 65nm process

(functional/scan/tester modes). Worked with P&R team on full chip clock tree synthesis

constraints and balancing. Leading functional block team on lab debugging and bring-up.

Chip is ready for mass-production.

SB700 project: (01/07 – 03/08)

Responsible for full chip top level RTL integration including the PAD ring arrangement,

initial floor plan, full chip synthesis, full chip PrimeTime STA with Celtic, full chip clock

tree balancing scripts and worked with P&R team to make whole flow smooth.

Introduced clock-domain checking tool (Spyglass) and created Spyglass design flow to

improve design quality.

02/03 – 10/06 SB600 project: (06/05 – 12/06)

Worked on Verilog RTL design for proprietary bus protocol to improve chip performance

and make the design configurable for different clients and easy to re-use. Used Verilog to

design PCIE to PCI interface conversion logic in FPGA to enable early lab debugging

before chip tape-out. Highly involved in chip bring-up and lab debugging.

SB400/SB450 projects: The first PCIE enabled chipset in ATI. (03/03 – 05/05)

Worked on Verilog RTL design for PCI to PCIE bridge to make South-Bridge product

line transitioning from PCI to PCI Express 1.0a. Worked with system group to use FPGA

for early debugging before tape-out. Worked on silicon bring-up and lab debugging.

12/01 – 12/02 Senior Staff Design Engineer. Broadcom Corp.

Terabit Switch Fabric, BCM8320 (12/01 – 12/02)

Responsible for CSIX interface RTL logic modification to meet 250 MHz clock and full

chip Synthesis. Worked closely with backend team to meet 250 MHz high speed timing

specification. Responsible for PrimeTime STA for full chip level and all sub-blocks

after P&R database, debugging back annotation issues, and generating ECO files to close

timing. ILM model approach was used for top level STA. Formal verification by using

Verplex. Silicon bring-up and tests in lab.

09/00 – 11/01 ASIC Engineer. Maple Optical Systems

GigaBit Ethernet Interface FPGA Design (05/01 – 11/01) Design ASIC by using Xilinx Virtex II 6000 FPGA to implement interface chip between

Gigabit Ethernet PHY and MPLS routing switch egress side. MPLS, IPv4, 32 bits CRC,

Ethernet header operation are implemented in the chip. Main clock domain is 125 MHz

and minor clock domain is 62.5 MHz. I was also responsible for the FPGA synthesis,

P&R, and lab debugging.

Routing Scheduling ASIC Verification (09/00 - 04/01) Building testbench and creating 100+ test cases by Specman E language. This chip is a

million-gates ASIC, which functions as core routing scheduling engine of MPLS routing

switch. Synopsys covermeter was used and test coverage reached 98%. I was also in

charge regression scripts and self checking mechanism for RTL and gate simulation.

12/97 – 09/00 IC Design Engineer. AMD Inc.

Gigabit NIC (10/99 - 09/00)

This chip is 802.3z compliant. It includes PCI-X, IPSec, IPv4, QoS features. I was

responsible for PCI-X interface logic design, full duplex, and half duplex control logic

design. I also involved reference model and verification testbench building.

AM79C901, Kilimanjaro 1/10 Mbps Home Networking PHY (01/98 - 10/99)

This is a mixed-signal chip, which enables home networking by using existing phone

wire and jack instead of using twist wire and hub. The HomePNA compliant technology

was co-designed from Tut System Corp. My main role in this project was responsible for

designing MII/GPSI interface by Verilog. I was also in charge the whole verification

team, maintaining the verification bench. Fibmill and metal layer ECO are also included.

03/96 – 12/97 ASIC Design Engineer. Allied Telesyn International Corp.

Advance Intelligent Fast Ethernet Switch IC design (08/97 – 12/97)

Using Verilog, Synthesis, and simulation tools (VCS and Virsim) to design and develop

Fast Ethernet Switch ASIC. My responsibilities included SSRAM memory interface, MII

interface, and Routing interface, per port queuing link list.