RESUME, NOVEMBER 2007 1

A 10b 100MS/s Time-Interleaved SAR ADC

Abstract— Analog-to-Digital Converters (ADC) are electroniccircuits which translate analog signals to its binary representation(digital). Since the signal processing is easier in digital domain,this type of circuits is extremely important in several areas, forexample in the communications sector. This dissertation proposesa new implementation for an Analog-to-Digital Converter (ADC)with 100 MS/s of sampling frequency and 10 bits of resolution.This proposal consists in an 11-channel time-interleaved ADC,each sub-converter with a SAR (Successive Approximation Reg-ister) topology. The first part of this work presents the sub-converter SAR project. To optimize the sub-converter hardwareit is implemented using a segmented topology; it combinesdifferent DAC architectures and different bit decoding methods(unary/binary). Moreover, it is provided a performance limita-tions analysis of the time-interleaved structure. The second partof the thesis describes in more detail the design of the SAR blocks.Firstly the comparator, which consists in a pre-amplifier and alatched comparator. Secondly some digital blocks used to controlthe converter, namely: (i) a state machine; (ii) a successive ap-proximation register; (iii) a row/column decoder for the capacitormatrix; and (iv) an output register. Finally, some simulations wereperformed in order to evaluate the proposed architecture. Thepresented results show that the proposed architecture achievesthe initial requirements. Besides, the implementation proposedyield good power performance results as shown by the Factor ofMerit (FOM) obtained.

Index Terms— Analog-to-Digital Converter (ADC), SuccessiveApproximation Register (SAR), Segmented Topology, Time-Interleaved, Sub-Converter.

I. INTRODUCTION

THE quick development of the wireless communicationssector have been demanding for improvements. Wireless

communications often require the use of analog signals, sincesignal processing is easier in the digital domain, circuitscapable of convert signals between the two domains areessential. Analog-to-Digital Converters (ADC), produce thebinary representation of an analog signal, while Digital-to-Analog Converters (DAC) have the opposite function.

The 2 parameters used to characterize any signal converterare: sampling frequency (fS) and resolution (N ). The fS

parameter give the number of results per second and the Nparameter corresponds to the number of bits for each sample,thus it determines the minimum amplitude of the signal thatcan be distinguished. In practice, is hard to improve bothparameters at the same time, so a trade-off is needed betweenthem.

Nowadays, for wireless applications, it is common to utilizeADCs with a sampling frequency around 80 MHz and 10bit of resolution. Typically this is obtained with a Pipelinedarchitecture, but it is becoming harder to satisfy the linearityrequirements. Therefore, is important to explore other possibleimplementations.

This work proposes a solution for a 10 bit ADC with afS of 100 MHz. In order to avoid the linearity issues, thenew solution is based in a Successive Approximation Register

SAR

S/H

DAC

...b N-1b1 b0

vIN

DACv

Fig. 1. SAR ADC block diagram.

(SAR). However this type of converter tends to be slower.Therefore a parallel architecture with an 11-channel time-interleaved ADC is used to achieve the above requirements.Besides the performance limitations of this parallel architec-ture will be discussed.

The rest of this article is organized as follows: Section IIreviews two different SAR ADC topologies. this topologieswere merged and optimized to achieve better performance.This section also provides an analysis of a parallel structure.Section III presents the design of the analog blocks. SectionIV presents the digital blocks needed to control the ADC.Section V shows some simulation results. Finally, we concludein Section VI.

Luıs SimoesNovember 2007

II. TOPOLOGY

The proposed converter is based on a successive approxima-tion topology comprising four parts (see Fig. 1): a comparator,a S/H mechanism, a DAC and a register. The comparatordetermines if the sampled voltage (by the S/H) is higher/lowerthan the DAC generated voltage, which is given according tothe SAR value.

The successive approximation algorithm has the followingsteps: (i) the comparator verify if vIN is higher than 1

2Vref1,

to determine MSB; (ii) if the decision of the most significantbit (MSB) is ”1”, the DAC voltage to compare with vIN is34Vref ; (iii) otherwise the DAC will generate 1

4Vref ; and soon and so forth. So this algorithm needs N cycles to determinethe complete binary word.

There are several ways to implement the DAC unit, e.g.with a resistive ladder, or a capacitor array utilizing chargeredistribution. The following sections are dedicated to explainthe DAC design.

1Vref is the maximum scale voltage.

RESUME, NOVEMBER 2007 2

SAR

...

2N

2N-1

2N-2

1

2

3

S/HvIN

DAC

DACv

Fig. 2. SAR ADC block diagram.

2 C 2C C C...N-22 CN-1

v

SARInterruptores

Array de Condensadores

INv REFPV

REFNV

X

Fig. 3. SAR ADC block diagram.

A. DAC with Resistive Ladder

In this case the DAC is implemented with a resistive ladderand a group of switches. The switches permit to access thevoltages generated in the ladder, as shown in Fig. 2. The ladderhas 2N resistors and the same number of switches, i.e. 1024resistors and 1024 switches, becoming impracticable.

B. DAC with Capacitor Array

Another possible DAC architecture uses a capacitor array asrepresented in Fig. 3. In this method, power consumption isreduced and the input signal is sampled and holded directly inthe capacitor array, so it does not need a dedicated S/H block.

As in the previous design (section II-A) the great disad-vantage here is the number of components used, becausethe capacitor array needs 2N capacitors. This architecturealso needs switches to control the capacitors. Two differentmethods can be used, unary and binary. In the first oneeach capacitor is controlled by one switch, so it requires 2N

switches, besides the capacitors. In the binary method it needsjust N switches, since the number of capacitors to commutedepends on the weight.

Bellow are described the sample and charge-redistribuitonfunctionalities, to simplify we consider binary decoding.

1) Sample: First the input signal is sampled, to do so vX

goes to ground (vX = 0), then all capacitors are switched tovIN . This makes the total charge of X:

QX = −2NCvIN . (1)

2) Charge-Redistribuition: This stage is divided in N steps,where N is the resolution (number of bits to determine). Firstly,to find the value of MSB, it is forced at ”high” in the SAR,this ensure that half of the capacitors switch to VREFP andthe other half to VREFN (VREFN = 0).

Now the charge of X node is given by,

QX = 2N−1C(vX − VREFP ) + 2N−1C(vX − VREFN ), (2)

the charge in X node is constant, so we have

−2NCvIN = 2N−1C(vX−VREFP )+2N−1C(vX−VREFN ), (3)

simplifying its possible to obtain,

vX =12VREFP − vIN . (4)

Clearly the comparator has conditions to verify if vIN ishigher than the middle of the scale ( 1

2VREFP ).Secondly, if the previous decision was ”1”, vX will be,

vX =34VREFP − vIN . (5)

and the opposite case (MSB=0), vX is given by,

vX =14VREFP − vIN . (6)

One can easily verify that the comparator is deciding ifthe input voltage is higher than 3

4VREFP or than 14VREFP ,

according to the previous decision. This continues untill all Nbits are determined. Finally vX is given by

vX = VREFP

[N∑

i=1

(bN−i

2i

)]− vIN , (7)

each bit-weight contributes to make DAC generate the nearestvoltage to vIN .

C. Segmented Topology

Taking into account the previous hardware limitations, thiswork adopts a segmented topology. This alternative permitsto use a reasonable number of components without modifyingthe paradigm of the previous methods.

The segmented topology uses a resistive ladder to decode4 bits and a capacitor array to decode the remaining 6 bits.Therefore only 16 resistors and 16 switches are used in theladder. Concerning the capacitor array, only 64 capacitors arerequired; and another segmentation is performed (unary/binarydecoding) to reduce the number of switches.

There is no straightforward decision for the number of bitsused for each segment (unary/binary), thus a Matlab modelwas used to simulate the influence of different segmentationson the DNL results. The simulations results are shown inFig. 4.

Cases (c) and (d) have missing codes, because the minimumDNL value reaches -1, so, it is only possible to choosebetween (a) and (b). The first case is clearly better, but itsimplementation uses more hardware, for this reason the (b)

RESUME, NOVEMBER 2007 3

Fig. 4. DNL histograms to decide the segmentation (unary/binary): (a) - 5+1(b) - 4+2 (c) - 3+3 (d) - 2+4.

Escada de Resistências

Vreflsb

...

vrefpVin

vrefn

2C C C... 4C

Vx

Array de Condensadores

4C

60C

1

2

3

16

15

14

DescodificaçãoUnária

DescodificaçãoBinária

b 4b 5 b 4b 5Descodificador

b 9 b 6...

b 3 b 0...DescodificadorInterruptores

Fig. 5. Connection between resistive ladder and capacitor array and, thedifferent segmentations.

segmentation was adopted (i.e. 4 bits unary and 2 binarydecoding). Such implementation only requires 18 switches inthe capacitor array instead of 64.

The final topology is presented in Fig. 5 where the SARbits b0 to b3 control the resistive ladder switches through adecoder; b4 and b5 directly control the binary switches fromcapacitor array; and b6 to b9 control the unary switches fromthe capacitor array through another decoder. The variation ofvX is calculated according to the scheme in Fig. 5, the totalcharge of X node:

QX = 2NcC(VCM − vIN ), (8)

where Nc is the number of bits determined by the capacitorarray. Following the procedure used in section II-B.2 todetermine (7), vX is:

vX = VCM + VREFP

[10∑

i=1

(b10−i

2i

)]− vIN . (9)

Thus vX has a known evolution and the comparator candetermine if the tested bit should be ”1” or ”0”.

Array de Condensadores

SAR

Array de Condensadores (dummy)

Escada de Resistências

Vreflsb

Fig. 6. Block diagram of the adopted topology.

VCM is a DC voltage and an unwanted charge injection canhave a significant impact in the result of expression (9). Toavoid this, a dummy capacitor array is used to sample VCM

all the time, and both nodes suffer similar charge injections;the blocks diagram is shown in Fig. 6.

D. Time-Interleaved

In order to obtain the sampling frequency of 100 MHz, aparallel structure with 11-channel time-interleaved is used toget one sample per clock cycle, as can be seen in Fig. ??.This architecture permits to use some common blocks, savingpower and circuit area. Although, time-interleaving ADCsbring some issues that can limit the overall performance. Thus,some considerations are discussed in the sections below.

1) Channel Offset Mismatches: This type of mismatchcan be modeled as a voltage source serially connected witheach ideal channel. This means that ADC has a pattern ofmismatches along the time with a period of M/fS , this ismanifested in the frequency domain as tones at multiplesof fS/M . With the Discrete Fourier Transform (DFT), theFourier coefficients are [1, 2, 3]:

Vk =M−1∑i=0

Vosie−j( 2π

M )ki. (10)

This error is independent from the input signal frequency andlevel.

There are two ways to solve this potential problem; ananalog method, which consists in a comparator with a loweroffset, using more area and power; and a digital method, whichgenerates an offset correction. The latter needs a mechanismto determine the offset in each channel and digitally correctthem.

2) Channel Gain Mismatches: Channel gain mismatchcan be modeled as the previous mismatch, but with a gainstage instead of the voltage source. Each fixed gain factoris multiplied to the input signal in time domain, obtaininga periodical pattern. The multiplication in the time domaincorresponds to the convolution of the gain pattern with theinput signal in the frequency domain. The convolution resultsin side bands centered around multiples of fS/M . Assumingthis mismatches are time invariant, the output spectrum Y (jω)is [1, 3]:

Y (jω) =1T

∞∑k=−∞

GkX

(j

(ω − 2πk

MT

)), (11)

RESUME, NOVEMBER 2007 4

where X(jω) is the input spectrum and the Fourier coefficientsGk are

Gk =M−1∑i=0

gie−j( 2π

M )ki. (12)

The effect of this error only depends on the input level. Sincethis issue is caused by mismatches in the reference voltages, allchannels need to share the same reference voltages generators.

3) Timing Mismatches: Finally, the timing mismatches con-sists in different sampling times between the channels, thisis caused by non-idealities of multi-phases. The fixed timingdeviations lead to fixed side bands around fS/M in frequencydomain.

Considering ideal instants, each clock signal has a ∆Ti

delay, the output spectrum is [1, 2, 3]:

Y (jω) =1T

∞∑k=−∞

Φk(ω)X(j

(ω − 2πk

MT

)), (13)

where X(jω) is the input spectrum and the Fourier coeffi-cients Φk(ω) are given by

Φk(ω) =M−1∑i=0

ej(ω− 2πiMT )∆Tie−j( 2π

M )ki. (14)

In order to avoid the timing mismatches, all channels needto share a S/H block, this strategy allows to control all thesamples with the same phase signal.

III. ANALOG BLOCKS

In this section is discussed the comparator design. Thisblock is responsible for determining if the input voltage ishigher/lower than the voltage generated in the DAC. In orderto implement it, a latched comparator is used, as well as apre-amplifier to reduce the offset contribution.

A. Dynamic Latched Comparator

This work adopted a latched comparator with a topology ofthe Fig. 7, based on [4, 5].

When latch is ”0”, the transistors M4a/M4b and M5a/M5b

reset the output nodes (q and qz) and the drains of differentialpair (M1a/M1b) to VDD. M6 is off and no supply currentexists. When latch rise, M4a/M4b and M5a/M5b are switchedoff, and current starts flowing through M6 and through thedifferential pair, discharging the M1a/M1b drains, this leads toa vDN and vDP reduction. When this voltages become smallerthsn VDD−Vt, M2a/M2b switch on and cause an output nodesvoltage reduction. When this voltages reach smaller valuesthan VDD−Vt, transistors M3a/M3b turn on. In this moment,considering a positive input voltage, M2a current is higherthan M2b, so vON decrease faster than vOP . This in turn,makes the vGS2a increase faster than vGS2b, which causes afurther increase of the difference between the currents in thistransistors - there is a positive feedback mechanism.

Analyzing the incremental model of the circuit, is possibleto get an expression for vod evolution

vod(t) = ∆Viet

τreg , (15)

M4a M3a M3b M4b

VDD

latch

latch latchM5a

M2a M2b

M1a M1b

M5b

vIP vIN

vON vOP

M6

vDPvDN

Fig. 7. Dynamic Latched comparator.

M4a M3a M3b M4b

M2a M2b

M1a M1b

q qzrs

VDD

Fig. 8. Latched SR.

where τreg is

τreg =CL + CDBp + CGSp + 2CGDp + CDBn + CGSn + 2CGDn

gmp + gmn.

(16)

Considering the total capacitance of 20 fF and a total gm

of 200 µS, it is possible to obtain τreg ,

τreg =20 f200

= 0.1 ns, (17)

to achieve a voltage level vodfinal = 2 V, with ∆Vi = 1 mV,we can get a regeneration time estimation:

t = τreg ln(vodfinal

∆Vi

)= 0.76 ns. (18)

Since the latch impulse is very short, it is needed a circuitto save the decision for the rest of the cycle, so it is useda latch SR (see Fig. 8), this permits SAR to update the newiteration value.

When s signal is high and r is low, M1a and M4b turn on,M4b drain current charge qz node that goes to VDD, this in

RESUME, NOVEMBER 2007 5

I SS

vIN

M2a M3a M3b M2b

M1bM 1a

vIP

vID

vON

vOP

VDD

Fig. 9. Dynamic pre-amplifier.

turn, switch on M2a, putting ground at q output node. Whenthe latch goes zero (reset phase of the comparator), s and rsignals go high, this way M4a/M4b turn off and M1a/M1b

switch on, this leads to M2a/M2b and M3a/M3b connectedas a back-to-back inverters, saving the compared result.

With a simulation the worst case was when the inputchanged from vindiff = 2 mV to vindiff = −2 mV andthe regeneration time is 646 ps, that is accordingly with theexpected.

B. Pre-Amplifier

To reduce the offset error, the comparator is enhanced witha pre-amplifier as the one presented in the Fig. 9.

Analyzing the small signal model of the circuit it is possibleto obtain the gain expression, which is given by:

Avd =vod

vid= gm1Req, (19)

where Req is

Req =1

gm2 − gm3. (20)

The goal of the pre-amplifier is to achieve 95% of VFINAL

in 8 ns, considering the parasitic capacitances, it is possibleto write the vod(t) expression:

vod(t) = Vidgm1

gm2 − gm3

(1− e− t

τ

), (21)

where τ isτ =

Ca + 2Cb

gm2 − gm3, (22)

with,

Ca = CL + CDB1 + CGD1 + CGS2 + CDB2 + CGS3, (23)

andCb = 2CGD3. (24)

Fig. 10. Pre-amplifier simulation with a vid = 1 mV.

Considering expression (21), the 95% voltage level isachieved when

t = 3τ, (25)

to reach the targeted voltage level in 8 ns,

τ <8 ns

3. (26)

To obtain a first iteration, some parameters were assumed,as

CLtot = 100 fF (27)

and a gm relation,gm3 = 0.6gm2. (28)

The differential gain was assumed to be

Avd > 5. (29)

Based on [6] for the strong inversion, it is considered Vod =200 mV.

Assuming this values allowed to achieve a first shot andafter some iterations to obtain the results presented in Fig.10.The final W/L relations are shown in Table I.

TABLE IFINAL W/L RELATIONS.

Transistor W/LM1 10M2 10.56M3 5.56

Finally the simulation results show a pre-amplifier gain ofAvd = 5.186 and an amplification time tamp95% = 6.35 ns.

IV. DIGITAL CONTROL

A. Global State MachineIn order to control the sub-converter states, it was created

one global state machine, this measure allowed to reduce cir-cuit area and power consumption. Since we have 11 channelsand each one has 11 states, the state machine has 11 flip-flopsorganized as a shift register. This way, each sub-converter onlyneed to see a different state machine output, i.e. each sub-converter is working in a different state.

RESUME, NOVEMBER 2007 6

Fig. 11. Output spectrum without random deviations.

B. Successive Approximation Register

This block goal is to save the successive approximationsand consequently the final result of each channel. It is imple-mented by a register with 10 flip-flops, each flip-flop is singlecontrolled by a state signal to know when it needs to save aresult coming from the comparator block.

C. Row/Collumn Decoding

The unary decoding mechanism needs a complex controlsystem for the capacitors, to implement it, the capacitors areplaced with a matrix format, and the SAR’s bits connected torow/column decoder. This permits to switch only the requiredcapacitors, avoiding the binary procedure.

D. Output Register

Intuitively, to obtain a converter with a single output, theADC requires an output register.

The 11 channels are connected to a multiplexer to correctlyhandle the several results.

V. SIMULATION RESULTS

In order to evaluate the proposed architecture some simu-lations were performed. The simulations allowed to verify theperformance of the complete converter. Since this siluationstake lots of time it was used HSIM, which permits somecalculus simplifications.

A. Output Spectrum Without Monte Carlo Distributions

The first simulation has a sinusoid with fi = 10449219MHz as input signal. The simulation results have been ana-lyzed by a Matlab script in order to obtain the output spectrum.As can be seen in Fig. 11 the tones coincide with the inputfrequency multiples, as expected and the ENOB is 8.9 bit.Only an ideal converter could reach 10 bit.

Fig. 12. Output spectrum with Monte Carlo parameters.

Fig. 13. Output spectrum with Monte Carlo parameters and offset compen-sation.

B. Output Spectrum With Monte Carlo Distributions

In this simulation, the input wave used is the same of theprevious simulation (section V). The output spectrum wasobtained with the same Matlab script and can be seen inFig. 12.

Analyzing the results, they clearly are lower than expected,since the ENOB is only 6.55 bit. This can result from randomdeviations, but also from the simplifications taken by HSIM.

As indicated in Fig. 12, the higher tones coincide withfS/11 multiples, which correspond to channel offset mis-matches. However, other tones result from timing mismatches.In order to solve the offset problem, a calibration can be imple-mented. To comfirm this an offset calibrations was performedwith Matlab, resulting in the output spectrum of Fig. 13, ascan be seen the ENOB increased from 6.55 to 8.07. Fig. 14presents both spectrums (Fig. 12 and Fig. 13) becoming easierto verify that the offset’s tones had a significant reduction andthe timing mismatches tones did not suffered any changes.

C. Factor of Merit

In order to compare the several performances of many ADCtypes, it is possible to calculate the Factor of Merit (FOM),

RESUME, NOVEMBER 2007 7

Fig. 14. Output spectrum with Monte Carlo parameters, with and withoutoffset calibration.

Fig. 15. FOM comparison between this project and some projects presentedin ISSCC’07.

its value is given by the following expression [7]:

FOM =Ptotal

2ENOBfS

[pJ/conv], (30)

where ENOB is the effective number of bits. It is noticeablethat lower FOM values correspond to better performances.

Applying to the obtained simulation results, with 2.6 mAin the analog voltage source, 490 µA in the digital voltagesource and considering 9 effective bits, we have:

FOM =(2.6 mA)2.5 V + (490 µA)1.2 V

29 100 MHz= 0.138 pJ/conv (31)

In the Fig.15 is represented some FOM values in order to thefrequency from ADC projects presented in ISSCC’07.

As can be seen the obtained FOM is better than thepublished results.

VI. CONCLUSION

This work consists in an ADC project, with a parallelstructure, it was verified that with this topology it is possible

to obtain a better converter without significant disadvantages.An overview of the steps performed in this project is

presented below:• In order to design an ADC sub-converter, this work

studied some possible topologies and adopted the onewith less circuit area and most power efficient.

• This work analyzed some issues of a parallel structure,namely, the influences of offset, gain and timing mis-matches.

• To implement this project some analog parts needed amore careful design, namely the latch comparator andthe pre-amplifier. In the end the expected results wereachieved.

• To control the entire converter some blocks were de-signed, e.g. a global state machine and a SAR (registerto contain the intermediate iterations and the final result).This work always intended to save circuit area andpower consumption, so when possible, the channels shareblocks, as well as reference voltages generators.

• Finally, combining all converter parts, some simulationswere effectuated to verify its performance. The resultswere a little below expectations, mainly because of theused simulator, due to some calculus simplifications.

Some improvements can be considered, as shown in sectionV-B an offset calibration is important to improve the overallperformance.

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