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Resistive Threshold Logic

Alex Pappachen James, Linu Rose V. J. Francis,and Dinesh S. Kumar

Abstract— We report a resistance-based threshold logic family usefulfor mimicking brain-like large variable logic functions in VLSI. A univer-sal boolean logic cell based on an analog resistive divider and thresholdlogic circuit is presented. The resistive divider is implemented usingmemristors, and provides output voltage as a summation of weightedproduct of input voltages. The output of the resistive divider is convertedinto a binary value by a threshold operation implemented by CMOSinverter and/or Opamp. A universal cell structure is presented to decreasethe overall implementation complexity and number of components. Whenthe number of input variables becomes very high, the proposed cell offersadvantages of smaller area and design simplicity in comparison withCMOS-based logic circuits.

Index Terms— CMOS logic circuits, memristors, resistive circuits,threshold logic.

I. INTRODUCTION

Logic gates implement boolean algebraic expressions obtainedfrom truth tables. Increase in functional requirements of digitalintegrated circuits, such as in microprocessors and ASICs results incomplex logic state implementations. A complex set of logic stateswhen represented as a truth table would have a large number of inputand output variables. As the number of input variables increases,it is often not possible to manually reduce the boolean logicexpressions to reduce the number of components required for itsimplementation. The most common approach to reduce the numberof components required with a large number of variables is by usinglogic minimization based on prime implicant logics. Techniques,such as Karnaugh map [1], QuineMcCluskey [2], Petrick’s method,Buchberger’s algorithm [3], and Espresso minimization algorithm [4],are the widely used approaches. However, when the number ofinputs increases significantly, logic minimization methods becomeinefficient. In addition, implementations using existing logic familiesbecome challenging as they are often restricted by the gate delays,the number of inputs, and the number of components.

The common approach employed to implement boolean algebrawith a large number (>10) of variables, is to apply the minimizationtechniques for standard gates with a limited number of inputs (<10).This always results in more number of circuit components than thatwas possible with gates that could support as many number of inputsas the number of variables. In addition to this issue, the number ofcomponents required to implement a gate vary from one booleanlogic to another, which results in increased structural complexityand increased investment in production scale verification and testingcycles.

Generic digital circuits, such as a single 2n to 1 multiplexer canbe used to implement n-input boolean logic function in canonicalsum-of-products form. As the number of inputs to the multiplexerincreases, a typical AND-OR logic would have large number of

Manuscript received February 5, 2012; revised September 15, 2012;accepted December 2, 2012. Date of publication January 11, 2013; date ofcurrent version December 20, 2013.

The authors are with Intelligent Machines and Neuromorphic EngineeringLaboratory, Indian Institute of Information Technology and Management,Trivandrum 695581, Kerala (e-mail: apj@ieee.org; linurosevj@gmail.com;dinesh.mscit3@iiitmk.ac.in).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2012.2232946

1063-8210 © 2013 IEEE

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 1, JANUARY 2014 191

Fig. 1. Circuit diagram of the proposed resistive divider boolean logic cellthat consists of a two input resistive divider and a variable threshold CMOSinverter.

inputs per gate for its implementation. In order to implement largevariable boolean logic functions, such as using multiplexers, weintroduce the concept of resistance threshold logic that minimizesnumber of components and design complexity. The proposed resistivethreshold logic is made up of a resistive divider and a thresholdlogic circuit. The idea of such an analog-binary cell is inspired bythe implementation challenges of the long established theory andpractices of neuron cell modeling and logic circuits [5]. Conventionalneuron inspired logic gate implementations [6] are complex due tothe requirements of multivalued weights and neuron-like thresholdfunctions. In addition, they fail to meet the original aim of havinglarge input logic gates useful for mimicking brain-like logic functions.In contrast, the resistive threshold logic is aimed to be simple instructure having the ability to realize large variable logic functions,and is intended to be used as a new standard cell universal logicfamily with a possible ability to mimic brain logic.

II. PROPOSED CELL

The proposed logic cell, shown in Fig. 1, consists of a resistivedivider and a variable threshold inverter. In contrast to the earlierreported work on cognitive memory network [7], in this brief wepropose a significantly different configuration, implementation, andapplication of the structurally similar and conceptually different cell.The input to the resistive divider is the digital values that can beequated to the logic inputs of a digital logic gate. Based on the outputof the resistive divider and a predefined inverter threshold, we proposeto implement the basic boolean logic functions. The selection of thethreshold and the use of resistive logic in designing a generalizedlogic cell is the primary contribution of this research.

An N-input resistance divider circuit consists of N inputresistors Ri and one reference resistor R0. The outputvoltage V0 for N-input voltages Vi can be represented asV0 = ∑N

i=1(Vi/Ri )/[(1/R0) + ∑Ni=1(1/Ri )]. The inputs Vi

have either of the two logical levels VH or VL , representing a binarylogic [1, 0]. We keep equal values to R′

i s and R0 = m Ri , whichresults in: V0 = (

∑Ni=1 Vi )/[(1/m) + N].

A straightforward approach to implement resistors is by usingsemiconductor resistors. Semiconductor resistors consist of a resistivebody that is surrounded by an insulator often developed over asubstrate, and two terminal contacts implemented using conductivemetallic strips. The value of semiconductor resistance can be obtainedfrom the expression, (ρL)/(x j W ), where ρ is the resistivity, L is thelength, x j is the layer thickness, and W is the width of the resistivebody.

A concern while using resistance devices (such as semiconductorresistors) is the impact of change in resistance value due to second

Fig. 2. Impact of change in input resistance on the output voltage V0 of theresistive divider. The results are demonstrated for 100 input resistive divider,with each line showing the relative change in V0 for the corresponding numberof resistors are uniformly perturbated within a ±10% tolerance level of resistorvalues. Note: here, we keep Vi = 1.

order implementation effects, such as improper junctions and defects.Fig. 2 shows a simulated study of the impact of change in resistancevalues on the output voltage of a resistive divider circuit. It is assumedhere that the changes in the resistor values are limited within atolerance level of ±10% of the actual resistive values. It can beseen that a maximum of ±10% resistive values introduces onlyabout .0894% change in output voltage, which makes the practicalimplementation of the resistive divider feasible even under realisticconditions. While using semiconductor resistors, when the numberof inputs increases, the leakage current through the semiconductorresistance becomes prohibitively high. This drawback is overcomeby replacing semiconductor resistors with memristors [8], which hasnegligible amount of leakage current.

The proposed resistive divider circuit uses the memristor modeledby HP [8]. The device has a thin film of titanium dioxide (TiO2)sandwiched between two platinum terminals. The titanium dioxidelayer is doped on one side with oxygen vacancies, TiO2−x . Thedoped region has lower resistance than that of the insulated undopedregion. The boundary between doped and undoped region determinesthe effective resistance of the device. Let D be the total widthof the TiO2 layer and W be the width of the doped TiO2 layer.When a positive voltage is applied at the doped side, the oxygenvacancies move toward the undoped region, increasing the widthof the doped region, W and hence the effective resistance of thememristor decreases. The effective resistance Meff of the memristoris Meff = (W/D)RON + (1 − (W/D))ROFF, where RON (=1 k�)is the resistance of the memristor if it is completely doped, andROFF (=100 k�) is the resistance of the memristor if it is undoped.When input voltage is withdrawn or when there is no potential dif-ference between the terminals, the memristor maintains the boundarybetween the doped and undoped region, since the oxygen ions remainimmobile after removal of the input voltage. Thus, the resistancewill be maintained at the same value before withdrawing the inputvoltage. From the equation, i = v/M(q) [9], where v and i arethe voltage and current across the memristor, and M(q) is charge-dependent resistance of the memristor, we can see that when thevoltage difference across the memristor is 0, the current throughthe memristor is 0. If there is reverse potential across the memristor,the width of the undoped region increases, resulting in an increasein the effective resistance of the memristor. This high resistance willblock the reverse leakage current through the memristor. When thenumber of inputs increases, the collective forward current through the

192 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 1, JANUARY 2014

TABLE IEFFECT OF INCREASE IN NUMBER OF INPUTS ON THE FORWARD

CURRENT FLOWING THROUGH THE MEMRISTOR IN THE CIRCUIT

Number of inputs Current through asingle memristor

Current through thepotential divider

circuits

2 3.33 μA 6.66 μA

10 0.909 μA 9.09 μA

100 0.99099 nA 9.90099 μA

TABLE IITRUTH TABLE OF TWO INPUT RESISTIVE DIVIDER LOGIC CELL

WHEN USED AS NAND AND NOR GATES

Input Voltage (Vi ) OutputVoltage

NANDa NORb

V1 V2 V0

VL VL2VL

3 VH VH

VL VHVL +VH

3 VH VL

VH VLVL +VH

3 VH VL

VH VH2VH

3 VL VL

a NAND threshold rangeVL +VH

3 < Vth <2VH

3

b NOR threshold range2VL

3 < Vth <VL +VH

3

circuit does not increase significantly, since the effective resistance inthe memristor is constant. Table I shows the effect of increasein number of inputs on the collective current flowing through thecircuit.

Table II shows the truth table of the two input resistive divider logiccell, that implements the NAND and NOR gates using a predefinedinverter threshold Vth. Assuming that VDD = 1V, VH = 1V,VL = 0V , it is clear from Table II that if the threshold voltageof the inverter is set between 0V and 1/3V , the cell will work asNOR logic and if it is between 2/3V and 1/3V the cell will workas NAND logic. That means by varying the threshold voltage of theinverter, NAND and NOR logic can be implemented using a singlecell. In general, the range of threshold voltage, Vth of NOR gate is(NmVL/(1 + Nm)) ≤ Vth ≤ (((VH + (N − 1)VL )m)/(Nm + 1)),and NAND gate is, ((m(VL + (N − 1)VH ))/(Nm + 1)) ≤ Vth ≤(mNVH /(Nm + 1)). To find the m value, the lower limit of NAND

gate threshold range (m(VL + (N − 1)VH )/(Nm + 1)) is equated to(VH + VL )/2. Now if we assume VL as 0V then we get the m valueas 1/(N − 2) and we can say that the threshold voltage of NAND

gate must be between (VH + VL)/2 and mNVH /(Nm + 1).The threshold voltage of the MOSFET is dependent on

several parameters, such as substrate bias voltage Vbs, thesurface potential φs , and substrate doping concentration[10]. The threshold voltage Vtn of the MOSFET can bevaried by changing its substrate bias, Vbs. The dependenceof substrate bias and the threshold voltage is expressed as,Vtn = Vtn0 + K1(

√φs − Vbs −√

φs)+C where Vtn0 is the zero biasthreshold voltage, the surface potential φs = 2(kB T /q) ln(Na/ni ),K1 is a parameter derived by considering non-uniform dopingand short channel effects K1 = γ2 − 2K2

√φs − Vbm where

K2 = (γ1 − γ2)(√

φs − Vbx − √φs )/2

√φs(

√φs − Vbm − √

φs ) +Vbm γ1 and γ2 are body bias coefficient when substratedoping concentration is equal to Nch and Nsub, respectively.γ1 = √

2qεSi Nch/Cox, γ2 = √2qεSi Nsub/Cox and Vbm

is the maximum substrate bias voltage. And C shows theeffect of narrow channel on threshold voltage. The threshold

Fig. 3. Relation between output voltage of the inverter and output voltageof the resistive divider, for ten input and 20 input boolean logic, when it isworking as a NOR gate.

voltage of the inverter can be represented as, Vth =((Vtn + (VDD − |Vtp |)) √

μpWp/μn Wn)/

(1 + √

μpWp/μn Wn),

which shows the role of the threshold voltages of the MOSFETs indetermining the threshold of the inverter.

Fig. 3 shows the relationship between the output voltage ofthe resistive divider cell (input to the inverter) and the outputvoltage of an inverter, for ten input and 20 input situations, whenthe cell is working in NOR logic. V0 value when the inputs areV1 = 1 and V2 = V3 = · · · = V10 = 0 is 0.0556V , and whenV1 = V2 = · · · = V10 = 0 is 0, so the threshold voltage of theinverter must be between 0 and 0.0556, to work as a NOR logic.Similarly for 20 input boolean logic, the threshold voltage ofthe inverter must be between 0 and 0.026. This shows that if thethreshold voltage of the inverter can be lowered to a very small valuewe can implement resistive threshold logic with large number ofinputs.

In order to reduce the threshold voltage, here, we introduced threeinverters with three different VDDs. Fig. 4 shows a universal gatestructure, which can be used to implement AND, NAND, OR, NOR,and NOT logic. For the cell to work as a NAND logic, the switchesS1 and S4 are closed, and the output is taken from Vout. So inthis case, three inverters will be enabled. To implement AND logic,the switches S1 and S3 are closed, and the output is taken fromVout. For the AND logic, two inverters need to be enabled. If theswitches S2 and S4 are closed, we get a NOR logic from Vout,here only one inverter has to be enabled. If both S2 and S3 areclosed, OR logic can be implemented, here two inverters are used. Theapproach, shown in Fig. 4, demonstrates the concept of generalizationof resistive threshold logic cell to implement the most basic booleanlogic functions. To maintain practical relevance of the approach, allthe results reported are based on device parameters from 0.25-μmTSMC process. Note that as VDD decreases, Vth also decreases. WhenVDD changes, the VGS of pMOS in the CMOS inverter will alsochange. As a result, in the case of the proposed cell with ten inputs,the pMOS will be in cut off state when the input condition is V1 = 1and V2 = V3 = · · · = V10 = 0 and we get a low level output fromthe first inverter. Since the first inverter can only provide a high valueof 0.25V , we use other two inverters in order to get a high value of1 V. The working of the proposed cell, in Fig. 4, as a NAND or NOR

gate purely rests on the values of Vtn and Vth of the inverter, for agiven number of inputs.

If VH is set as 1V and VL as 0, then the threshold voltage Vth rangefor NAND gate must be between 0.5V and the V0 value obtained when

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 1, JANUARY 2014 193

Fig. 4. Circuit diagram to implement NAND, NOR, AND, OR, and NOT logicfunctions consisting of memristive resistance divider and CMOS inverters withthree different power supply values.

Fig. 5. Graph indicating the dependence of threshold voltage of the CMOSinverter and threshold voltage of the nMOS. The threshold values shown inthe graph are a result of changing the number of inputs from 3 to 100, andcalculating the minimum inverter threshold voltages required to implementthe circuit as a NAND gate.

all inputs are VH . Fig. 5 shows the relationship that exists betweenVtn and Vth to implement the proposed cell as NAND gate, as thenumber of inputs changes from 3 to 100. For each number of inputs,the Vth is calculated for a particular Vtn and with a fixed Vtp, Wp ,μp , Wn , μn , and VDD values. For a given number of inputs, thethreshold voltage is above 0.5 V, so by using a single inverter withVDD as 1V , NAND logic can be implemented. That means NAND

logic can be implemented using the proposed cell with one invertersuch as in Fig. 1. Using three inverters with different VDD, a 100input NOR logic can be realized. For implementing NOR logic, for alarger number of inputs, the threshold voltage of the inverter circuithas to be reduced to a very low value. This problem can be overcomeby boosting the signal, using an Opamp amplifier, before applying tothe inverter. Table III shows the leakage power and the spectral noisedue to Johnson, shot and flicker noise in multi-VDD logic proposed inFig. 4. The maximum noise levels are very low (i.e., in nV) relativeto signal reference of 1 V range.

The universal circuit in Fig. 4 is modified to incorporate Opampthreshold logic as shown in Fig. 6. The threshold logic whenimplemented using Opamp [11], offers the advantage of scalabilityover increase in number of inputs. The Opamp is designed usingeight MOSFETs and in the same technology as that of the CMOSNOT gate. The Opamp reference voltage for NOR logic, VREF is fixedas VL + δ and for NAND logic, VREF is fixed as VH − δ, where δ issmall voltage defined to ensure the bounds of Vth. The Opamp shiftsthe voltage to a high value or low value depending on the inputvoltage, V0. It also acts as a buffer helping to isolate the inputs fromthe output enabling realistic implementations of very large numberof inputs per gate.

TABLE IIILEAKAGE POWER AND NOISE SPECTRAL DENSITY FOR 100 INPUT GATE

PROPOSED MULTI-VDD GATE CONFIGURATION IN FIG. 4

Performance Measure NAND AND NOR OR

Noise spectral density per unit squareroot bandwidth (nV/Hz1/2)

7.94 9.75 75.71 10.15

Leakage power (nW) 0.014 0.017 0.967 0.971

Fig. 6. Universal gate structure that implements NAND, NOR, AND, OR, andNOT logic functions, using memristive resistance divider and Opamp thresholdcircuit.

Fig. 7. Bar graph shows the area comparison of CMOS with that of resistivethreshold logic (with Opamp threshold circuit, Fig. 6), using NAND and NORgate implementations.

A. Comparisons

Fig. 7 indicates the area required to implement NOR and NAND

universal logic gates for 2, 10, and 1000 input logic gates imple-mented using CMOS logic, and that using the resistive thresholdlogic. In implementing CMOS logic, the maximum number of inputsper gate is taken as five. The Fan in of the proposed cell using Opampis very high (=14.498 × 106), indicating that we can implement alarge variable boolean logic using a single resistive divider cell. Forincreasing number of inputs, the proposed cells contain lesser numberof components and area, when compared to the CMOS logic. SinceCMOS-based logic gates are practically limited to small number ofinputs, we have used a layered combination of five input gates toimplement gates with ten or more inputs. Table IV compares thepower dissipation of the proposed logic with that of CMOS logicfor NAND and NOR gates. CMOS gates dissipate lesser power asagainst its memristive counterparts. The use of low power memristivedevices [12] would be required to reduce the power dissipation.Table V shows the comparison of the noise margin of the logicfamilies for single input NAND and NOR logic, indicating that theproposed logic has comparable noise tolerance levels to that with theexisting techniques. In addition, the averaging nature of the potentialdivider can further help to increase the noise tolerance levels thanspecified through noise margins. Table VI shows a comparison ofpropagation delay when a square pulse with 40-μs time period and

194 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 1, JANUARY 2014

TABLE IVCOMPARISON OF THE RESISTIVE LOGIC WITH CMOS LOGIC

Logic Familya LogicFunction

Power Dissipation

10 i/p 100i/p

CMOS Logic 0.009 nW 0.036 nW

Resistive logic(Opamp threshold)

NOR 10.6 μW 11.49 μW

CMOS Logic 0.062 nW 0.753 nW

Resistive logic(Opamp threshold)

NAND 9.2 μW 10.09 μW

a The technology size of all the components in the circuit iskept same for all the gates for fairness in comparison.

TABLE VNOISE MARGIN OF DIFFERENT LOGIC FAMILIES

Logic Families NAND NOR

NML NMH NML NMH

CMOS 0.363 V 0.587 V 0.233 V 0.616 V

Pseudo nMOS 0.429 V 0.413 V 0.276 V 0.461 V

Domino CMOS 0.407 V 0.376 V 0.104 V 0.43 V

Resistive Logic 0.369 V 0.558 V 0.132 V 0.777 V

TABLE VIPROPAGATION DELAY OF DIFFERENT LOGIC FAMILIES FOR DIFFERENT

NUMBER OF INPUTS

Logic Families NAND Delay NOR Delay

3 i/p 10 i/p 1000 i/p 3 i/p 10 i/p 1000 i/p

CMOS 0.47 μs 0.54 μs 0.65 μs 0.50 μs 0.52 μs 0.66 μs

Pseudo nMOS 0.48 μs 0.60 μs 0.85 μs 0.51 μs 0.58 μs 0.72 μs

Domino CMOS 0.48 μs 0.51 μs 0.75 μs 0.51 μs 0.58 μs 0.75 μs

Resistive Logic(Opamp threshold)

0.45 μs 0.45 μs 0.45 μs 0.60 μs 0.60 μs 0.60 μs

50% duty cycle is applied. The resistive threshold logic shows betterresponse when the number of inputs becomes very high and when alower number of inputs show comparable delays.

As the resistance elements do not significantly introduce the delaywith increase in number of inputs, a large number of inputs (>100) ispractically possible for the proposed cell. In contrast with the existingtechnologies that are practically limited to about five–ten inputs pergate, the ability of the proposed resistive threshold logic to handlea large number of inputs reduces the complexity of the design andlayout of the large variable digital circuits.

B. Example Circuits

The proposed logic is compared with the CMOS implementationusing a 16-b adder and a 16 × 1 MUX. The simulation was performedin SPICE using feature size of 0.25-μm TSMC process BSIM modelsand HP memristor model. A ripple carry adder without applyingreduction technique is implemented using 16 single bit adders. Thesingle bit adder requires 3 NOT, 3 two input AND, 1 three input OR,4 three input AND, and 1 four input OR gates. Hence, a total of48 NOT, 24 AND, 16 OR, 64 AND, and 16 OR gates are required forthe 16-b adder. Fig. 8 shows an example of 16th output bit of theadder simulated using input pulses with initial start delay of 10 μs,rise and fall time of 5 ns, and ON period of either 20 μs or 10 μswith 50% duty cycle.

The 16-b MUX when using the proposed logic required 16 inputOR gate and five input AND gates, while CMOS logic required two,four, and five input AND/OR gates. In the case of adder, CMOS logic

Fig. 8. Signal output of the 16th b of the designed ripple adder using theproposed resistive threshold logic. Vin is the inputs, Cin and Cout is the inputand output carry, and Vout the output sum bit.

TABLE VIICOMPARISON OF CIRCUIT IMPLEMENTED USING RESISTIVE THRESHOLD

LOGIC WITH THAT OF CMOS LOGIC

Logic Families 16 b Full Adder 16 × 1 MUX

Power Area Power Area

CMOS Logic 2.5 nW 4.557 μm2 0.189 nW 1.070 μm2

Resistive Logic (Opampthreshold)

3.277 mW 8.081 μm2 0.447 mW 0.825 μm2

Note: The power dissipation for Opamps in the 16 b full adder is 2.47 mW.

has lesser area in comparison to the resistive threshold logic, whilein 16× 1 MUX implementation, proposed logic results in lesser areawhen compared to CMOS logic. Table VII demonstrates that whenthe number of inputs for the AND and OR gates is increased, theproposed logic requires lesser area than its CMOS counterpart. Powerdissipation, on the other hand, is higher for the proposed logic dueto higher forward currents in memristor as compared to CMOS. Thisissue can be addressed by using low power memristors [12] and lowpower Opamps.

III. CONCLUSION

The concept of resistive threshold logic was presented in anapplication to implement conventional digital logic gates. The pre-sented resistive threshold logic family, due to its ability to support alarge number of inputs, can significantly help to reduce the designcomplexity. Although, the presented resistive threshold outperformsthe conventional CMOS logic implementations in large input gatesin terms of performance parameters, such as area, delay, and power,for small input gates. Further developments on low power and highspeed Opamp designs are required. The CMOS, resistance thresholdLOGIC co-design, can optimize the circuit design of conventionalCMOS-based large variable boolean logic problems. A disadvantageof the proposed threshold logic using the memristor technology in[8] as compared with CMOS logic is the higher power dissipation.However, with the advancements of newer low power memresitivedevices, such as [12], the problem of lowering power dissipation tothe levels of CMOS can be a realistic task. The proposed logic canbe extended to technologies, such as carbon nanotubes and organiccircuits. In addition, the ability of the proposed logic to developa large number of input gates can be seen as an early step inachieving the goal of mimicking brain-like large variable booleanlogic applications in VLSI.

ACKNOWLEDGMENT

The authors would like to thank the anonymous reviewers for theirtime and thoughtful review comments, which has resulted in theimprovement of the overall quality of the manuscript of this paper.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 1, JANUARY 2014 195

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