Research Report

University of Wisconsin-MadisonCollege of Engineering

Wisconsin Power Electronics Research Center2559D Engineering Hall1415 Engineering DriveMadison WI 53706-1691

© Confidential

2014-18

A Novel Topology for a Voltage Source Inverter with Reduced Transistor Countand Utilizing Naturally Commutated Thyristors with Simple Commutation

S.H. Rafin, T.A. Lipo*, B. Kwon

Electronic Systems EngineeringHanyang UniversityAnsan, South Korea

*Electrical & Computer EngineeringUniversity of Wisconsin-Madison Madison

WI, USA

A Novel Topology for a Voltage Source Inverter with

Reduced Transistor Count and Utilizing Naturally

Commutated Thyristors with Simple Commutation

Sajjad H. Rafin

Electronic Systems Engineering

Hanyang University

Ansan, South Korea

rafin@hanyang.ac.kr

Thomas A. Lipo

Electrical & Computer Engineering

University of Wisconsin-Madison

Madison WI, USA

lipo@engr.wisc.edu

Byung-il Kwon

Electronic Systems Engineering

Hanyang University

Ansan, South Korea

bikwon@hanyang.ac.kr

Abstract— This paper discloses a novel topology for a voltage

source inverter with certain advantages over conventional

topologies. In particular, the circuit uses only three high

performance transistor switches rather than six switches as in the

conventional three leg inverter circuit. Thus, this circuit could

prove to be attractive in applications requiring high cost

switching components such as new silicon carbide and gallium

nitride based devices. In addition to the three switches, two low

cost thyristors are used per phase to provide commutation from

positive to negative current. Theoretical analysis and simulation

results are provided to verify its performance and feasibility.

Keywords—Novel Topology, Inverter, VSI, Transistor,

Thyristor.

I. INTRODUCTION

Voltage source (VSI) and current source inverters (CSI) are widely utilized in various applications such as, adjustable-speed drives (ASD) for AC motors, induction heating, uninterruptable power supplies (UPS), standby power supplies, electronic frequency changer circuits, distributed generation units, HVDC systems to name a few [1],[2]. In this paper, a three phase voltage source inverter (VSI) topology is proposed which utilizes a combination of thyristors and transistors in a configuration which has not been yet previously reported (Fig. 1). This VSI has similar features compared to conventional the six switch VSI (Fig. 2) in terms of its output voltage-current waveforms. However, a major reduction in the number of expensive transistor switches is obtained by using inexpensive thyristors instead. Hence, the circuit could be an economical alternative to the conventional VSI and CSI in cost sensitive applications. In particular, this topology could be an alternative for the conventional VSI or CSI in a high power multi motor drive application where new and evolving but high cost silicon carbide or gallium nitride switches are employed. In addition, this topology could also inspire manufacturers to design and manufacture low current inverter grade thyristors for lower power inverter applications.

Generally, thyristor based VSIs require complex and expensive forced commutation techniques [4]. Load or line commutation can also be done only with a leading power factor

load [4], [5]. However, the proposed topology utilizes thyristors which are naturally commutated by means of utilizing the switching capabilities of the transistors. Hence, the extra cost of commutation circuits can be avoided along with the associated complexity by this topology. Moreover, conventional pulse width modulation (PWM) techniques can be utilized for the transistor switching and thyristors commutation. Finally, the topology can also be extended and used in an indirect AC-AC converter.

This paper discusses the novel topology, its basic operation and switching technique. System level simulation results are given to verify its feasibility and performance. Simulation study is conducted by using MATLAB/SIMULINK to demonstrate its performance. Experimental setup is designed, assembled, and built properly according to the novel topology requirements. However, the experiment is in process and the experiment results will be provided soon.

Fig. 1. Schematic of the proposed novel VSI topology.

(a) (b)

Fig. 2. Schematic of conventional six switch VSI topology.

II. PROPOSED TOPOLOGY

The schematic of the proposed topology is illustrated in Fig. 1. As may be observed that, unlike conventional VSI this topology is equipped with both transistors (Sa, Sb, and Sc) and thyristors (Stap, Stan, Stbp, Stbn, Stcp, and Stcn). As for the conventional VSI, diodes are also connected antiparallel with all the switches for bidirectional current flow. The output voltage equation of the inverter are given below, where the “S” elements take on a value of one or zero when the corresponding switch is turned on or opened respectively.

n

p

cncp

bnbp

anap

n

p

tcntcp

tbntbp

tantap

c

b

a

V

V

SS

SS

SS

V

V

SS

SS

SS

V

V

V

..

It is to be noted that, transistors Sa, Sb, and Sc operate both on the positive and negative cycle of the current flow.

Therefore, in equation (1) for the positive cycle, transistors Sa,

Sb, and Sc become Sap, Sbp, and Scp and for the negative cycle they become San, Sbn, and Scn respectively.

III. COMMUTATION AND PWM CONTROL SCHEME

In this chapters the commutation technique for the thyristors and PWM control for the transistors will be discussed. The DC voltage input of the inverter considered to be stiff with negligible impedance. In addition, it is assumed that the output currents are,

)π

οtο

(ωo

Ic

i

)π

οtο

(ωo

Ib

i

)ο

tο

(ωo

Ia

i

3

2cos

3

2cos

cos

The quantities Iₒ, ωₒ, and φₒ are amplitude of the output current, output angular frequencies, and initial angle of the phase output current respectively.

A. Basic operation and commutation technique

In this section a typical switching sequence for the converter will be discussed. Again, for simplicity only one leg (i.e. phase “a”) of the converter will be covered at first and then the three phase switching sequence will be described in the following sections of this chapter.

1) Positive current commutation:

a) For positive ia current, thyristor Stap is turned on first

with Stan off, as shown in Fig. 3(a).

b) Transistor Sa is then switched on and off using an

appropriate PWM technique.

c) Within this period, positive current flows through

Stap, Sa, D2, and Dt2, (Fig. 3(a)).

d) At the end of this positive half cycle when current

reaches zero, Stap is turned off by removing the gate signal

from Sa.

Fig. 3. Basic operation and commutation technique of phase “a”.

2) Negative current commutation:

a) After the recovery period of Stap, Stan is turned on

with Stap remaining off, as shown in Fig. 3(b).

b) Again, for this negative half a cycle Sa is turned on

and off using pulse width modulation.

c) And, in this period negative current flows through

D1, Dt1, Sa, and Stan (Fig. 3(b)).

d) The basic strategy continues for the rest of the legs

according to their phase order.

(a) (b)

(c) (d)

(e) (f)

B. Switching states of the topology

Similar to conventional topology, this novel three phase three leg inverter has total eight active and zero voltage switching states. Out of the eight, the six active switching states are illustrated in Fig. 4(a) to 4(f) where only the conducted devices and their current flowing paths are shown. In case of any switching state only one thyristor and the transistor of a phase conduct at any instance. However, complimentary thyristors of any phase cannot be turned on at the same time in order to avoid short circuit condition.

Fig. 4. Active swiching states and current flowing path.

It can be seen in Fig. 4(a) that, from the top three thyristors only Stcp is turned on with keeping Stap and Stbp off. And, bottom thyristors are fired on or commutated off according to their complimentary thyristors’ switching condition. In accordance to that, Stan and Stbn is kept on with Stcn off. Nevertheless, transistor Sa, Sb, and Sc are switched on until the current reaches

zero to their specific phase notation. In addition, at this switching state current flows through thyristor Stcp, Stan, and Stbn; transistor Sa, Sb, and Sc; also diode D1, D3, D6, Dt1, Dt3, and Dt6. However in Fig 4(b) illustrates the next switching state, current circulating path through conducted devices. Furthermore, rest of the four active switching states are described pictorially from Fig. 4(c) to Fig. 4(f).

In Fig. 5, switching sequences (firing/triggering pulses) are illustrated for all the thyristors and transistors. Where, bold red marked sections specify the delay periods between the conduction of the complimentary thyristors (i.e. Stap and Stan, Stbp and Stbn, Stcp and Stcn). And these delay periods are introduced by removing gate triggering pulses from the transistors (Sa, Sb, and Sc) placed in between the per phase thyristors. Once the pulses are removed from the gats of the transistors, they act like an open path at that instance (considering ideal case) and they resist the current flow through them. Thus, these transistors turn off the thyristors according to the sequence and offer them the adequate recovery time for the next interval.

Fig. 5. Swiching sequences of the devices and their conduction periods.

Now, considering all the conditions of conduction states described-shown in Fig. 4(a) to 4(f) and the switching sequences shown in Fig. 5, it can be written that,

Stap.Sa Stan.Sa

Stbp.Sb Stbn.Sb

Stcp.Sc Stcn.Sc

Eight switching state of the inverter are given in Table I. Switching state 1 and 8 produce zero AC output line voltage, and the remaining states produce non-zero output AC line voltage. Thus, the resulting AC output line to line voltages consist of discrete values of voltages, -VDC, 0, and VDC. Note that, for simplicity, the output line voltages are considered without utilizing PWM techniques rather using simple continuous 1800 conduction. Nonetheless, in the following section of this chapter line to line voltage equations will be given with utilization of the PWM techniques.

TABLE I. SWITCHING STATES OF THE NOVEL TOPOLOGY

Switching

state

Devices Output line voltages

Stap.Sa Stbp.Sb Stcp.Sc Vab Vbc Vca

1 0 0 0 0 0 0

2 0 0 1 0 - VDC VDC

3 0 1 0 -VDC VDC 0

4 0 1 1 - VDC 0 - VDC

5 1 0 0 VDC 0 - VDC

6 1 0 1 VDC - VDC 0

7 1 1 0 0 VDC VDC

8 1 1 1 0 0 0

C. PWM control scheme

As mentioned earlier, the transistors are switched on and off using appropriate PWM techniques, and any PWM techniques can be applied with the topology. However in this paper, naturally sampled sine-triangle PWM (ST-PWM) method was selected to verify the topology. The ST-PWM method uses a single triangular carrier signal to compare against three sinusoidal reference waveforms displaced in time by 120o [3]. This type of modulation is generally termed double-edge naturally sampled modulation.

In order to simplify the analysis, it is considered that there is no delay given between the conduction periods of per phase thyristors. That implies, the PWM switching of the transistors will also have no delay between the positive and negative current flow. In addition, transistor’s (i.e. Sa) triggering pulses or the PWM switching sequences are identical for both positive and negative sequence, it is because per phase thyristors (i.e. Stap and Stan) provide commutation from positive to negative current. Eventually the combination of these devices per phase ensures a typical PWM control scheme (also from equation 3-5).

Fig. 6(a), 6(f), and 6(k) illustrate the ST-PWM generation methodology by comparing triangular carrier signal to three sinusoidal reference waveforms displaced in time by 1200 for three different phase “a”, “b”, and “c” respectively. However, the resulting switching pulses by ST-PWM method per phase transistors are shown accordingly in Fig. 6(c) and 6(e), Fig. 6(h) and 6(j), and in Fig. 6(m) and 6(o). Moreover, thyristor firing pulses and their conduction periods are given pictorially in Fig. 6(b) and 6(d), Fig. 6(g) and 6(j), and in Fig. 6(l) and 6(n) in sequence. It is to be noted that, small blocks represent the firing pulses but the bigger rectangular blocks denote the conduction period of the thyristors. To conclude, Fig. 6(p) shows a typical three phase sine triangle PWM method. Nonetheless, the ST-PWM method described in above sections which is used to operate the novel inverter is the exact same

compared to the conventional ST-PWM method shown in Fig. 6(p).

Fig. 6. Naturally sampled sine-triangle modulation for the proposed

topology; thyristor firing pulses and conduction periods; transistors switching pulses.

Hence, the equations for phase voltages using ST-PWM for this novel topology without the delay periods can be written as follows,

)3

2cos()

3

2cos(

)3

2cos()

3

2cos(

coscos

tο

ωMVtο

ωo

Vcz

V

tο

ωMVtο

ωo

Vbz

V

tο

ωMVtο

ωo

Vaz

V

DC

DC

DC

The fundamental target three-phase line-line output voltages are,

)6

5cos(

)2

cos(

)6

cos(

tο

ωV3Maz

Vcz

Vca

V

tο

ωV3Mcz

Vbz

Vbc

V

tο

ωV3Mbz

Vaz

Vab

V

DC

DC

DC

Where, Vₒ = output voltage peak magnitude, M = modulation index = Vₒ/VDC, and the reference waveforms are defined by considering “z” as a fictitious DC bus center point.

IV. SIMULATION RESULTS

The proposed topology has been extensively investigated utilizing system level simulation with MATLAB/SIMULINK. Moreover, simulation has been performed to observer the output current, line voltage, and total harmonics distortion (THD) of it. The simulation software represents all the switches and the components as ideal. Simulation parameters taken for analysis are as follows,

Input DC voltage: 220 V (peak to peak);

Output inductance: 25 mH;

Output resistance: 10 Ω;

Carrier frequency: 5400 Hz;

Modulation index M: 0.8;

Output frequency: 60Hz

Fig. 7. Three phase output current of the proposed VSI.

Fig. 7 shows the waveform of 3 phase output current in which the switching frequency of the ST-PWM algorithm is 5400 Hz. In addition, from the figure it can be observed that the three phase output current found through simulations are not purely sinusoidal as compare to the conventional inverters. However, it can be improved by utilizing better transistor switching techniques.

Fig. 8. THD of output current-5400 switching frequency of the novel VSI.

Fig. 8 depicts the THD response on output current for the 5400 kHz switching frequency. Because of the slight zero current intervals needed to allow the thyristor’s recover blocking ability a very slight increase in the current THD was obtained compared to the conventional arrangements.

Fig. 9. Three phase output line voltage of the novel VSI topology.

Finally, Fig. 9 illustrates three phase output line voltage waveforms of the inverter circuit. Although the waveforms are slightly distorted but it also can be improved by developing or utilizing better switching technique. In addition, it is to be noted that the ST-PWM technique cannot utilize the maximum DC bus voltage to produce maximum peak fundamental output line voltage to the load, whereas the third harmonic injected ST-PWM or space vector PWM (SVPWM) gives 15% enhanced fundamental output with better quality [3].

V. EXPERIMENTAL SETUP

To demonstrate the performance and feasibility of the topology and to verify the simulation results, it is necessary to perform an experiment. Thus, hardware implementation is a vital area to work on. More to that, the experimental setup is designed, assembled and built according to the requirement for the novel topology. Fig. 10 shows the inverter circuit arrangement. Furthermore, Powerex inverter grade stud-type SCR T507064034AQ are used as thyristors, ST Microelectronics IGBT STGE50NC60VD as transistors, and the antiparallel diodes are used in the circuit are Fairchild Semiconductor RHRG5060 type.

Fig. 10. Inverter circuit containing transistors, thyristors, and diodes.

Fig. 11. Transistor (IGBT) driver board (top left), Thyristor (SCR) firing

board (top right), and DSP (TMS320F28335) control board.

Fig. 11 depicts the driver board and firing board for the transistors and thyristors along with the DSP control circuit board. A controllable DC power supply DS2000S is used for the input DC supply for the inverter. Furthermore, a 1.5kW, 380V, and 60Hz induction motor is used as the load for the inverter circuit. To conclude, the experiment is in process and the results will be reported soon.

VI. CONCLUSION

This paper proposes a novel topology that could be an attractive alternative to the conventional inverter topologies. The functionality of conventional three phase inverter could be achieved in different power level by utilizing combination of transistors and naturally commutated thyristors. The focal point of this research is developing an attractive yet inexpensive alternative topology at the high power level system. Cost advantages can potentially be achieved from this topology over conventional arrangements. The performance and feasibility has been substantiated with system level simulation. Performance wise it resembles conventional topologies with some certain advantages over them. Thus, it could be an attractive alternative considering all of the features provided by this novel inverter topology. However, as stated before, the hardware implementation is completed and the experiment is in process to demonstrate the performance and feasibility of the topology. Nevertheless, in near future the experimental results will be reported.

Finally, future topics of research will concern improvement of the switching technique to utilize maximum DC bus supply voltage, reducing the harmonic content, and minimizing switching losses. Furthermore, this converter and extended multi-level topologies based on this converter can be investigated for a number of future power system applications in both medium and high power systems. i.e. a standby power system, a distributed generation unit, or a HVDC system to name a few.

REFERENCES

[1] N. Mohan, W. P. Robbin and T. Undeland, “Power Electronic: Converters, Applications, and Design”, 2nd ed. (book), New York: Wiley, 1995.

[2] B. K. Bose, “Power Electronics and Variable Frequency Drives: Technology and Applications” (book), IEEE Press, 1997.

[3] D. G. Holmes, T. A. Lipo, “Pulse Width Modulation for Power Converters: Principles and Practice” (book), IEEE Press Series on Power Engineering, 2003.

[4] G. K. Dubey, Classification of Thyristor Commutation Methods, IEEE Trans. On Industry Applications., Vol. IA-19, No. 4, July/Aug 1983, pp. 600-606.

[5] R. Dixit, B. Singh et al., “Adjustable Speed Drives: Review on Different Inverter Topologies”, International Journal of Reviews in Computing, 2012, Vol. 09, pp. 54-6