Research of long distance clock distribution system

Université Libre de Bruxelles (IIHE)Yifan Yang, Kael Hanson, Aongus Ó Murchadha, Thomas Meures, Michael Korntheuer

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OVERVIEW

• Askaryan Radio Array background

• Clock distribution over optical fiber based on low cost FPGA and jitter cleaner.

• Fixed latency link implementation.

• Conclusion and future plan.

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• Askaryan Radio Array background

• Clock distribution over optical fiber based on low cost FPGA and jitter cleaner.

• Fixed latency link implementation.

• Conclusion and future plan.

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37 stationsSpacing: 2 kmDepth under ice surface: 200 mSurface coverage: ~160 km2

Ice thickness below: ~3000 m

Each station:16 + 4 sub-firn antennas (sensitive between 250 and 800 MHz):8 vertically polarized8 horizontally polarized4 calibration pulsers (v-pol + h-pol)X surface antennas

Askaryan Radio Array

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Askaryan Radio Array

• Current ARA uses analog optical fiber • Easy, COTS (commercial off-the-shelf) item  • 1 antenna = 1 fiber => 4 fibers per hole • slightly high power draw• price > 10 kEUR per station  • 4 ADC board on surface controlled by single processor board

• Digital system• Custom designed• 4 antenna =1 fiber => 1 fiber per hole• Half the price• Extended communication system • 1 ADC board downhole controlled by one FPGA board • 50 ps skew stability is required in one station• 800Mbps data rate

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• Askaryan Radio Array background

• Clock distribution over optical fiber based on low cost FPGA and jitter cleaner.

• Fixed latency link implementation.

• Conclusion and future plan.

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Clock embedded in data

• self-clocking signal

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GTP

To SFP

From SFP

Recovered clock is synchronized with transfer clock but with larger jitter

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SI5368

Generates any frequency from 2 kHz to 945 MHzUltra-low jitter clock outputs with jitter generation aslow as 300 fs rms (50 kHz–80 MHz)Integrated loop filter with selectable loop bandwidth

Footprint compatible Interface compatiblewith on-surface processor board

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Evaluation board and measurement setting

IRS2 Control module

System clock

After switching to recovered clock, a synchronized link is established

Spartan 6 lx45t with 4 GTPs

SI5368

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Clock and data measurements

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Latency measurements

Before clock switching After clock switching

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Clock skew measurement

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• Askaryan Radio Array background

• Clock distribution over optical fiber based on low cost FPGA and jitter cleaner.

• Fixed latency link implementation.

• Conclusion and future plan.

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Latency uncertain from GTP

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Latency uncertain from GTP

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Latency uncertain from jitter cleaner

Fixed phase difference between input and output of the jitter cleaner is also needed to establish a fixed latency link.Cdce62005 and LMK03200 both are used in new evaluation board.

IRS2 Control module

System clock

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New evaluation board and measurement setting

Spartan 6 lx45t with 4 GTPs

Cdce62005(fixed delay)

Lmk03200(0 delay)

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Mean

(ps)

Std dev(ps)

P-p

(ps)

Popul-ation

1 934.46 9.7717 105.37 1.375M

2 925.43 10.100 99.239 1.25M

3 908.4 10.001 105.68 1.25M

4 934.98 10.047 103.64 1.25M

Clock skew measurement

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• Askaryan Radio Array background

• Clock distribution over optical fiber based on low cost FPGA and jitter cleaner.

• Fixed latency link implementation.

• Conclusion and future plan.

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Conclusion and future plan

• Achieved:• Clock distribution over optical fiber

• 50ps skew stability achieved

• Latency of the link is kept in a certain range after power cycle on both direction

• Things to do:• Long term, long distance, low temperature experiments

• Automatic calibration

• Remotely firmware upgrade

• System optimum

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Thank you!

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backup

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Clock separate with data transfer

250 meters standard cat5 cable