Microelectronics Reliability 44 (2004) 1157–1163

www.elsevier.com/locate/microrel

Reliability enhancement of electronic packagesby design of optimal parameters

Ashish Batra, Pradeep Ramachandran, Poornima Sathyanarayanan,Susan Lu *, Hari Srihari

Department of Systems Science and Industrial Engineering, State University of New York at Binghamton, Parkway East,

Binghamton, NY 13902-6000, United States

Received 1 February 2004; received in revised form 1 March 2004

Available online 14 May 2004

Abstract

Reliability growth testing involves the selection of optimal design parameters to enhance a product’s reliability. This

paper proposes a split plot experimental design that accommodates the restriction on randomization on the order of

experimental runs caused by the experimental nature of accelerated reliability testing. The proposed experimental

design provides statistically relevant solutions about the choice of design parameters, in terms of their reliability impact,

in a much shorter time. A degradation model that aids in predicting the failure time for the given problem further

supplements this discussion.

� 2004 Elsevier Ltd. All rights reserved.

1. Introduction

The objective of reliability growth testing is to im-

prove reliability over time through changes in product

design and manufacturing processes. Reliability tests

and assessments are conducted on prototypes to deter-

mine whether reliability goals are met. The failure modes

are eliminated or minimized through engineering rede-

sign, and the cycle is repeated [1]. The two fundamental

tasks that are essential to achieve continuous improve-

ment in the product reliability are estimating the existing

reliability and identifying the factors that influence the

product reliability [2]. For a highly reliable product, the

first task may be achieved by accelerated degradation

testing (ADT), which can provide information about

product reliability without necessarily waiting for com-

plete failures to occur [3]. The second task is generally to

employ DOE (design of experiment) tools to identify the

significant factors influencing product reliability. The

* Corresponding author. Fax: +1-607-777-4094.

E-mail address: slu@binghamton.edu (S. Lu).

0026-2714/$ - see front matter � 2004 Elsevier Ltd. All rights reserv

doi:10.1016/j.microrel.2004.03.013

commonly used DOE tools are full/fractional factorial

designs that are applicable only when there is no

restriction on randomization for experimental runs [4].

But in accelerated degradation testing (ADT) a given

combination of design parameters undergo accelerated

testing in a fixed order and this poses a restriction of

randomization on time/cycles. For example, consider

thermal cycling, one of the common ADT techniques, if

number of thermal cycles is regarded as one of the fac-

tors then the different levels or treatments of this factor

cannot be randomly selected due to the inherent nature

of the experiment posing a restriction on randomization

in the design [4]. This paper proposes a split plot

experimental design that recognizes the restriction on

randomization in the experimental setup for any accel-

erated degradation tests.

The product or experimental unit under consider-

ation is an electronic component that is packaged in an

area array package. Accelerated testing of electronic

components usually degrades the reliability of inter-

connects which can be monitored, over time, by tracking

resistance increase of the interconnects. These area array

packages (flip-chip, chip scale packages (CSP) and ball

grid array (BGA)) require the formation of solder joints

ed.

1158 A. Batra et al. / Microelectronics Reliability 44 (2004) 1157–1163

between the chip and board surfaces. Solder joint fatigue

is a main concern in area array packages as it degrades

the joint reliability [5]. Thermal strains and stresses

caused by coefficient of thermal expansion (CTE) mis-

match are the major causes of failure in solder joint

interconnections. Numerous factors affect solder joint

fatigue performance, such as chip size, joint geometry,

interface metallurgy, underfill and substrate materials

[5].

This paper elaborates on a set of experiments con-

ducted on chip scale packages for reliability character-

ization and prediction purposes. The reliability of daisy

chained area array interconnects at different levels of

various important factors is of interest. The character-

ization of the package is achieved by conducting accel-

erated testing on different designs to understand the

effect of the design on the overall reliability of the

package. In order to accommodate the restriction on

randomization on the order of experimental runs due to

the experimental nature of thermal cycles, the use of the

split-plot experimental design was proposed. Further-

more, a degradation model is presented for predicting

the failure of the product over time. The proposed ap-

proach is to track resistance change at varying periods of

the thermal cycles.

2. Proposed experimental design

2.1. Problem under consideration

A set of designed experiments was conducted on four

different combinations of design parameters. The objec-

tive of carrying out such an experiment was to determine

the most reliable design combination to facilitate the

determination of final design parameter. The electronic

packages under study were chip scale packages having

two columns of solder balls with a ball diameter of 22

mils. Due to proprietary concerns specific details of the

package are not disclosed in the paper. Temperature

cycling was used to evaluate their reliability. Packages

were subjected to alternating high and low temperature

extremes to induce mechanical stresses on the component

and the solder interconnects. Permanent changes in the

electrical and/or physical characteristics can result from

these mechanical stresses. The response variable was the

change in the resistance of the daisy chain interconnects

over varying numbers of thermal cycles.

Table 1

Experimental test conditions as per JEDEC standards

Test condition Ts(Min) (�C) Ts(Max) (�C)

Pre-conditioning )40(+0,)10) +60(+10,)0)J )0(+0, )10) +100(+15, )0)

2.1.1. Experimental procedure

This accelerated thermal cycling was conducted in

accordance with JEDEC standards to determine the

ability of the components and solder interconnects to

withstand mechanical stresses induced by alternating

high and low temperature extremes. Samples are placed

in an environmental chamber and are subjected to the

specified temperature cycling test condition for the

specified number of cycles. Typical temperature cycle

rates are in the range of 1–3 cycles per hour (cph).

Typical failure mechanisms include, but are not limited

to, fatigue (such as solder-joint fatigue). Table 1 shows

the test conditions:

Testing consisted of 5 cycles of pre-conditioning that

simulates the shipping and handling conditions that the

package might experience. This is followed by 500 cycles

of test condition J , which is the expected environmentalcondition that the package would experience during its

normal operating life. Table 2 shows the percent change

in resistance (DR=R) monitored during thermal cycling.The failure criteria set for the test included mechan-

ical damage of the solder joint causing more than 50%

increase in the resistance of the sample during the

accelerated cycling. Mechanical damage did not include

damage induced by fixturing or handling or damage not

critical to the package performance for this specific

application.

2.1.2. Experimental factors

Four different combinations of package designs were

considered in this experiment. One of the designs had a

symmetrical geometry with 12 interconnects in 2 col-

umns of 6 solder balls. This symmetrical design comes in

two different pad sizes of 12 and 18 mils respectively.

The other design had an unsymmetrical geometry with

13 interconnects in 2 columns of 6 and 7 solder balls.

This unsymmetrical design geometry also comes in pad

sizes of 12 and 18 mils, respectively. Measurements were

made on 3 replicates of the above-mentioned design

combinations over the varying number of thermal cy-

cles, spanning a total range of 500 thermal cycles. The

following three factors were studied to examine their

effects and interactions on output resistance as measured

in ohms:

• Factor A: Variations in the pad size (12 and 18 mil

pad, corresponding to low and high values, respec-

tively).

Soak mode Soak time (min) Cycles/h

3 10 2–3

3 10 1–3

Table 2

Percent change in resistance due to thermal cycling (DR=R)

Pad size Thermal cycles

0th Cycle 100th Cycle 250th Cycle 500th Cycle

12 mil 18 mil 12 mil 18 mil 12 mil 18 mil 12 mil 18 mil

Design

geometry

Symmetrical 0 0 )3.2 3.2 2.2 4.5 4.8 8.2

0 0 )3.8 4.9 0 8.7 0.8 10.1

0 0 )5.7 5.6 0.7 5.6 1.0 9.2

Unsymmetrical 0 0 2.5 2.0 9.4 9.8 11.0 12.6

0 0 2.5 6.7 6.9 11.8 9.6 18.3

0 0 5.4 5.0 7.0 6.9 13.5 16.9

A. Batra et al. / Microelectronics Reliability 44 (2004) 1157–1163 1159

• Factor B: Design geometry (symmetrical and unsym-

metrical geometry, corresponding to low and high

values of the design geometry).

• Factor C: Number of temperature cycles (0, 100, 250

and 500 cycles, corresponding to the four different

levels across which resistance measurements were

taken).

2.2. Split-plot design

In reliability testing, complete randomization of the

order of runs within a block may not always be possible

while carrying out multifactor factorial experiments.

Such situations lead to a generalization of the factorial

design called the split-plot design. The research and

applications of the split plot design is observed in the

literatures [4,6]. However, this type of design is often

overlooked in the design and analysis of reliability tests

in which some of the factors, such as temperature or

thermal cycles, are difficult to randomize due to the

nature of test. The scheme for split plot design consists

of factors that are divided into whole plot and subplot

treatments with each of the whole plots comprising all

the subplot factors at their various levels. The random-

ization is complete with respect to the whole plot

treatments; however, it is not with respect to the subplot

treatments. Thus, the effect of the factors in the whole

plots will be confounded while the subplot treatments

will not be confounded. It must also be noted that

the various levels of the subplots (applied at different

Fig. 1. Split plot design layout

instances of time to the same whole plot) makes the use

of the split plot design unique and indispensable for

experiments that have these constraints [7].

2.3. Split plot model

In the experiment under study, for an electronic

package with different design parameters specified as

factors A (pad size) and B (design geometry), the various

levels of the factor C (no. of thermal cycles) are applied.

Since the primary interest here is to know how the factor

C (no. of thermal cycles) influence the response with

respect to factors A and B, it is desired that the different

levels of factor C be applied in a block involving a

specific combination of factors A and B. Thus, a split

plot design with two factors in the whole plot is con-

sidered with a block consisting of a specific combination

of factors A and B to which all the levels of factor C is

applied. This is expected to enhance the precision with

which the effect of factor C influences the response in

relation to factors A and B.

The split plot design layout is explained with the help

of Fig. 1. In the layout that is shown below, the two

design factors––pad size and the number of intercon-

nects are considered to represent the whole plot. They

are considered as fixed factors in the experiment. These

two factors have two levels shown by A+ , A) and B+ ,B). For each of the possible combinations of levels offactors A and B (whole plot), the four different levels of

factor C (subplot) is applied at different instances of time

for the example problem.

1160 A. Batra et al. / Microelectronics Reliability 44 (2004) 1157–1163

for a given block, and the response variable is measured.

The factor C is also considered to be fixed.

The model developed for this experiment is as fol-

lows:

yijkl ¼ l þ ðsÞi þ ðbÞj þ ðcÞk þ ðbcÞjk þ ðhÞijk þ ðdÞlþ ðbdÞjl þ ðcdÞkl þ ðbcdÞjkl þ ðsbcdÞijkl þ ðeÞijkl

where si is the blocking effect (or effect of replicate i); bj

the effect of the whole plot factor––Design geometry; ckthe main effect of the whole plot factor––number of

pads; hijk the whole plot error; dl the main effect of sub-

plot factor––number of thermal cycles; 2ijkl the subplot

error.

The term ðsÞi þ ðbÞj þ ðcÞk þ ðbcÞjk þ ðhÞijk is referredto as the whole plot term that includes the main effects of

the whole plot factors A and B and their interaction

effect together with the effect of blocking. The sub-plot

term ðdÞl þ ðbdÞjl þ ðcdÞkl þ ðbcdÞjkl þ ðsbcdÞijkl þ ð2Þijklincludes the effect for the subplot factor C together with

the interaction of the subplot factors with the whole plot

factors. The model is developed according to the rules as

stated in [6]. Table 3 describes the developed model.

Table 3

Split-plot model for the example problem

Source of variation Sum of squares D

Blocks(sI ) SSBLOCKS 2

AðbÞj SSA 1

BðcÞk SSB 1

AB SSAB 1

ðhÞijk SSWP 3

CðdÞl SSC 3

AC SSAC 3

BC SSBC 3

ABC SSABC 6

ðeÞijkl SSSP 2

SST 4

Table 4

ANOVA table developed using split plot model

Source DF SS

Replicate 2 0.0002

Pad-size (factor A) 1 0.0152

Design geometry (factor B) 1 0.0212

Pad-size· design geometry 1 0.0034

Whole plot error 3 0.0005

Thermal-cycles (factor C) 3 0.0662

Pad-size· thermal cycles 3 0.0058

Design geometry· thermal cycles 3 0.0097

Pad-size· design geometry· thermal cycles 3 0.0023

Error 27 0.0079

Total 47

3. Experimental results and analysis

3.1. Results of ANOVA analysis

The split-plot model discussed in Section 2.3 allows

us to calculate the F -values for each factor by compar-ing the expected mean square model that was developed

in Table 3.

From the ANOVA table (Table 4), we infer with 95%

confidence level that the main effects of factors A (pad-

size), B (design geometry) and C (thermal cycles) are

highly significant. Fig. 2 describes the effect graphically.

It is also noted that, the interaction effects of the pad

size with the thermal cycles and that of the design

geometry with the thermal cycles are significant as their

F -values are greater than the F -critical values. This re-sult is graphically shown in Fig. 3.

In particular the 12 mil pad size and the symmetrical

design geometry with 12 bumps of solder joints seem to

show the least change in resistance over the 500 thermal

cycles that it was tested on. Fig. 4 shows the surface plot

that compares the response (DR=R) of the two design

factors vs. the thermal cycles and once again graphically

describes our conclusion.

egrees of freedom Expected mean square

16r2s þ 4r2hijk þ r2224

Pbj2 þ 4r2hijk þ r2

24P

c2k þ 4r2hijk þ r2212

PðbcÞ2 þ 4r2hijk þ r22

4r2hijk þ r224P

dl2=1þ r222P

ðbdÞ2=1þ r222P

ðcdÞ2=1þ r22PðbcdÞ2=1þ r22

7 r227

MS F F (0.95)

845 0.0001423 0.7526455 9.5521

453 0.0152453 80.662963 10.128

119 0.0212119 112.23228 10.128

647 0.0034647 18.331746 10.128

665 0.0001888

537 0.0220846 74.610023 2.96

613 0.0019538 6.6005631 2.96

484 0.0032495 10.977928 2.96

19 0.000773 2.6114865 2.96

821 0.0002956

Fig. 2. Main effects plot.

Fig. 4. Surface plot for DR=R vs. thermal cycles, pad size, and Design geometry.

Fig. 3. Interaction plot (fitted means) for DR=R.

A. Batra et al. / Microelectronics Reliability 44 (2004) 1157–1163 1161

3.2. Degradation data analysis

Degradation data analysis is a powerful tool for

reliability assessment. It involves the measurement of the

degradation of a product, which can be directly related

to the expected failure of the product. One of the main

advantages of degradation analysis is that it enables us

to make reliability inferences, even without complete

failures [3]. Degradation models are useful to predict the

failure of a product when the parameters of the product

degrade with time. In the problem discussed (Section

2.1), four different design combinations of the package

are considered. The reliability of each type degrades as

the number of thermal cycles increases (time). Thus, a

degradation data analysis for each of the four combi-

nations will help to determine which combination fails

last without actually waiting for the failure to occur.

3.2.1. Method for modeling degradation data

The fundamental assumptions made in this discussion

are that the parameter D (percentage change in resis-

tance) drifts monotonically towards a specified critical

value DF (50% of the initial resistance that is measured)

and we believe it is reasonable to assume a linear change

within this range with a slope (or rate of degradation) R.

• Using a least squares regression method, a regression

equation is developed with the percentage change in

resistance as the dependent variable and the number

of thermal cycles as the independent variable, for

each of the four combinations [8].

• The calculated DF represents a 50% change in the

initial resistance. Hence, the DF value is 0.5.

• The regression equation gives the number of thermal

cycles after which the package is expected to fail.

Failure times are determined for each of the three

samples for a given package combination to compute

the life distribution parameter estimates.

• Assuming a lognormal model, natural logarithms of

all failure times and treating the resulting data as a

sample from a normal distribution, the sample mean

and the sample standard deviation are computed.

1162 A. Batra et al. / Microelectronics Reliability 44 (2004) 1157–1163

These are estimates of ln T50 and r, respectively, forthe package combination [8]. The following table

shows the computations.

In the computation shown in Tables 5 and 6, m de-

notes the slope of the regression equation while c de-notes the y intercept. The value of DF is calculated to bea 50% increase over the initial resistance (0.5). Using the

regression equation and the value of DF, the value of

projected time is calculated. The natural logarithms of

the projected time are seen as data points from a normal

distribution (lognormal distribution) and the mean and

the standard deviation of the distribution indicate the

reliability of the package.

3.2.2. Conclusions from the degradation data analysis

Commensurate with the findings from the split plot

design are the observations that the symmetrical design

geometry and 12-mil pad size package combination

outperforms the other combinations. The ln T50 value is

Table 5

Computation describing the degradation model for the design combi

Symmetrical design and 12 mil pad size combina

N_TC DR=R1 DR=R2 DR=R

0 0 0 0

100 )0.031609 )0.03763 )0.05250 0.0220307 0 0.007

500 0.0478927 0.008065 0.010

DF 0.5 0.5 0.5

Projected time 4045.7454 11198.72 7743.

log(PT) 8.3054211 9.323555 8.954

ln T50 8.8611865

Sigma 0.5154525

c )0.017608 )0.01721 )0.02m 0.0001279 4.62E)05 6.77E

Table 6

Computation describing the degradation model for the design combi

Unsymmetrical design and 12 mil pad size com

nation

N_TC DR=R1 DR=R2 DR=R3

0 0 0 0

100 0.025 0.024806 0.0541

250 0.0941176 0.068992 0.0700

500 0.1102941 0.096124 0.1335

DF 0.5 0.5 0.5

Projected time 2149.2063 2552.861 1981.2

log(PT) 7.6728539 7.84497 7.5914

ln T50 7.7031048

Sigma 0.1294191

c 0.0087847 0.006393 0.0121

m 0.0002286 0.000193 0.0002

the highest for this combination indicating that the

package is capable of withstanding more number of

thermal cycles than the other packages.

4. Conclusion

In summary, it is important to understand the

restriction on randomization during the execution of

reliability tests on electronic packages. This restriction

necessitates the use of the split plot design, which has

also been shown to be the least time consuming in

making statistically relevant conclusions about product

reliability. In the example problem it was inferred with

95% confidence that the symmetrical design geometry

and 12-mil pad size is the optimal design out of the four

combinations and it did so within 500 thermal cycles.

Further, the degradation data analysis coupled with the

split plot technique not only gives an insight about the

significant factors contributing to the products reliability

nations

tion Symmetrical design and 18 mil pad size combination

3 N_TC DR=R1 DR=R2 DR=R3

0 0 0 0

738 100 0.032286 0.049261 0.055833

286 250 0.045375 0.087028 0.055833

018 500 0.082024 0.100985 0.091667

0.5 0.5 0.5

306 3227.254 2549.329 3087.336

584 8.079387 7.843585 8.035064

7.986012

0.12532

441 0.007492 0.019245 0.017632

)05 0.000153 0.000189 0.000156

nations

bi- Unsymmetrical design and 18 mil pad size combi-

nation

N_TC DR=R1 DR=R2 DR=R3

0 0 0 0

52 100 0.02028 0.067153 0.050283

36 250 0.097902 0.118248 0.069405

74 500 0.125874 0.183212 0.168555

0.5 0.5 0.5

65 1869.853 1380.206 1549.649

91 7.533615 7.229988 7.345784

7.369796

0.153231

12 0.004729 0.017933 0.004053

46 0.000265 0.000349 0.00032

A. Batra et al. / Microelectronics Reliability 44 (2004) 1157–1163 1163

but also predicts the failure time. This method can aid in

reliability characterization and prediction purposes.

References

[1] Ebeling CE. An introduction to reliability and maintain-

ability engineering. New York: McGraw-Hill; 1997.

[2] Yu H-F, Chiao C-H. An optimal designed degradation

experiment for reliability improvement. IEEE Trans Reliab

2002;51(4).

[3] Elsayed EA, Liao H. An accelerated degradation rate model

for reliability prediction at field conditions. Department of

Industrial and Systems Engineering, Rutgers, The State

University of New Jersey, 96 Frelinghuysen Road, Piscat-

away, NJ 08854-8018.

[4] Anderson VL, McLean RA. Design of experiments: a

realistic approach. New York: Marcel Dekker; 1974.

[5] Liu X, Xu S, Lu GQ, Dilard DA. Stacked solder bumping

technology for improved solder joint reliability. J Micro-

electron Reliab 2001;41:1979–92.

[6] Gregory WL, Taam W. A split plot experiment in an

automobile windshield fracture resistance test. Quality

Reliab Eng Int 1996;12:79–87.

[7] Montgomery DC. Design and analysis of experiments. 5th

ed. New York: John Wiley & Sons, Inc; 2001.

[8] NIST/SEMATECH e-Handbook of Statistical Methods.

http://www.itl.nist.gov/div898/handbook/apr/section4/

apr423.htm.