RELEASED FOR PUBLICATION C COPYRIGHT ALL RIGHTS …€¦ · 14.4 ref 0.73 10.5 15.34 16.07 0.2 x v...
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A1 REVISIONS 0 PLC 1 PLC 2 PLC 3 PLC 4 PLC ANGLES OF SCALE SHEET REV NAME SIZE CAGE CODE DRAWING NO DIMENSIONS: TOLERANCES UNLESS OTHERWISE SPECIFIED: DWN CHK APVD MATERIAL FINISH PRODUCT SPEC APPLICATION SPEC WEIGHT P LTR DATE APVD DWN DESCRIPTION LOC DIST 5 6 7 8 3 4 2 1 D B A A B C C D ALL RIGHTS RESERVED. RELEASED FOR PUBLICATION C COPYRIGHT THIS DRAWING IS UNPUBLISHED. 4805 (3/11) RESTRICTED TO THIS DRAWING IS A CONTROLLED DOCUMENT. TE Connectivity -X- 4.9 4.4 TYP 1.62 0.18 14.4 REF 0.73 10.5 15.34 16.07 0.2 XV Z 18.6 -V- 12.07 16.1 -Z- 1.8 7 PLC 1.8 8 PLC 8 SPACES AT 1.8 = 14.4 0.1 SEE NOTE 72 PLC 1.7 REF 7 SPACES AT 1.8 = 12.6 4.5 0.1 1.43 0.05 2.03 REF 1.8 1.8 1.39 7.2 REF 0.65 REF 12.6 REF 6.95 REF 0.65 REF 2.1 REF 2.1 REF 1.52 REF PART NO PLATING 1410186-1 1410186-2 PC BOARD LAYOUT (CONNECTOR SIDE) SEE SHEET 2 FOR RTM) SCALE 5:1 TOP OF DAUGHTERCARD (CONNECTOR SIDE) OF DAUGHTERCARD WAFER #1 SLOT PIN "a1" PIN "i8" CONNECTOR KEEPOUT AREA OF WAFER #1 SLOT OF -V- CONTACT HOUSING OF -Z-
Transcript of RELEASED FOR PUBLICATION C COPYRIGHT ALL RIGHTS …€¦ · 14.4 ref 0.73 10.5 15.34 16.07 0.2 x v...
A1
REVISIONS
0 PLC1 PLC2 PLC3 PLC4 PLCANGLES
OFSCALE SHEET REV
NAME
SIZE CAGE CODE DRAWING NO
DIMENSIONS: TOLERANCES UNLESSOTHERWISE SPECIFIED:
DWN
CHK
APVD
MATERIAL FINISH
PRODUCT SPEC
APPLICATION SPEC
WEIGHT
P LTR DATE APVDDWNDESCRIPTION
LOC DIST
5678 34 2 1
D
B
AA
B
C C
D
ALL RIGHTS RESERVED.
RELEASED FOR PUBLICATION
C COPYRIGHT
THIS DRAWING IS UNPUBLISHED.
4805 (3/11)
RESTRICTED TO
THIS DRAWING IS A CONTROLLED DOCUMENT.
TE Connectivity
-X-
4.9
4.4TYP
1.62 0.18
14.4 REF
0.73
10.5
15.34
16.07
0.2 X V Z
18.6
-V-
12.07
16.1
-Z-
1.87 PLC
1.88 PLC
8 SPACES AT1.8 = 14.4
0.1
SEE NOTE
72 PLC
1.7REF
7 SPACES AT 1.8 = 12.6
4.5
0.1
1.43 0.05
2.03 REF
1.8
1.8
1.39
7.2 REF
0.65 REF
12.6 REF
6.95 REF0.65 REF
2.1 REF
2.1 REF
1.52 REF
PART NOPLATING
1410186-1
1410186-2
PC BOARD LAYOUT(CONNECTOR SIDE)
SEE SHEET 2 FOR RTM)
SCALE 5:1
TOP OF DAUGHTERCARD(CONNECTOR SIDE)
OF DAUGHTERCARDWAFER #1 SLOT
PIN "a1"
PIN "i8"
CONNECTORKEEPOUT AREA
OF WAFER #1 SLOT
OF -V-
CONTACT
HOUSING
OF -Z-
A1
REVISIONS
0 PLC1 PLC2 PLC3 PLC4 PLCANGLES
OFSCALE SHEET REV
NAME
SIZE CAGE CODE DRAWING NO
DIMENSIONS: TOLERANCES UNLESSOTHERWISE SPECIFIED:
DWN
CHK
APVD
MATERIAL FINISH
PRODUCT SPEC
APPLICATION SPEC
WEIGHT
P LTR DATE APVDDWNDESCRIPTION
LOC DIST
5678 34 2 1
D
B
AA
B
C C
D
ALL RIGHTS RESERVED.
RELEASED FOR PUBLICATION
C COPYRIGHT
THIS DRAWING IS UNPUBLISHED.
4805 (3/11)
RESTRICTED TO
THIS DRAWING IS A CONTROLLED DOCUMENT.
TE Connectivity
-X-
12.6 REF
12.07
-V-
0.65 REF
18.6
0.73
16.07
15.34
16.1
4.9
4.4
7.2 REF
14.4 REF
TYP1.62 0.18
10.5
6.95 REF
1.522.03 REF
1.88 PLC
7 SPACES AT 1.8- = 12.6
1.7REF
1.8
1.8
2.1 REF
8 SPACES AT1.8 = 14.4
0.65 REF
2.1 REF
0.1
SEE NOTE
72 PLC
REAR TRANSITION MODULE APPLICATION
a
b
c
d
e
f
g
h
i
1 8
a
b
c
d
e
f
g
h
i
HOUSING
CONTACT
OF -V-
OF WAFER #1 SLOT
TOP OF DAUGHTERCARD(CONNECTOR SIDE)
RTM PC BOARD LAYOUT(CONNECTOR SIDE)
SCALE 5:1
OF DAUGHTERCARDWAFER #1 SLOT
PIN a1
PIN a8
CONNECTORKEEPOUT AREA
