Reinforced Self-Assembled Nanodielectrics for High-Performance Transparent Thin Film Transistors

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Jun Liu , Jonathan W. Hennek , D. Bruce Buchholz , Young-geun Ha , Sujing Xie , Vinayak P. Dravid , * Robert P. H. Chang , * Antonio Facchetti , * and Tobin J. Marks *

Reinforced Self-Assembled Nanodielectrics for High-Performance Transparent Thin Film Transistors

Transparent thin fi lm transistors (TFTs) have stimulated great scientifi c and technological interest due to potential applications in “invisible” electronics, such as transparent touch panels and see-through displays. [ 1–6 ] Since the fi rst demonstration of trans-parent TFTs using a crystalline ZnO semiconductor, [ 7 ] exten-sive efforts have sought to enhance performance by increasing the fi eld-effect mobility ( μ FE ) and/or lowering the operating voltage. [ 8–12 ] Principal foci have included the semiconductor and gate dielectric, two essential TFT materials. Among the diverse transparent semiconductors, amorphous transparent oxide semiconductors (a-TOSs) offer distinctive attractions vis-à-vis organics and crystalline TOSs, including good mobility, excel-lent environmental stability, low-temperature processability, optical transparency, smooth surfaces, and compositional uni-formity. [ 4 , 13–15 ] For example, amorphous Zn-In-Sn-O (a-ZITO) fi lms afford moderate TFT performance at operating voltages ≥ 10 V when paired with a SiO 2 gate dielectric. [ 16–20 ]

An effective approach to enhancing TFT performance is to introduce a self-assembled nanodielectric (SAND; Figure 1 a ) composed of a saturated hydrocarbon layer, a π -polarizable stilba-zolium layer, and a chlorosiloxane-derived SiO x “capping” layer. These gate dielectrics can be deposited near room temperature by straightforward wet chemistry, and have large capacitances, low leakage, high breakdown fi elds, and suppress trapped charge between the dielectric and semiconductor for many classes of organic and inorganic semiconductors. [ 21–23 ] Nevertheless, while SANDs exhibit good chemical and thermal stability, [ 24–26 ] recent work suggests that direct exposure to high-energy ions and plasmas present in pulsed laser deposition (PLD) semicon-ductor growth processes, seriously degrades SAND dielectric properties and TFT performance. [ 27 ] It would therefore be highly desirable to devise approaches to enhancing SAND robustness. We report here that a simple vapor-derived hexachlorodisiloxane (HCDS, Cl 3 SiOSiCl 3 ) coating (“v-SiO x ”) greatly enhances SAND

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J. Liu , J. W. Hennek , Y.-g. Ha , Prof. A. Facchetti , Prof. T. J. Marks Department of Chemistry and the Materials Research CenterNorthwestern University2145 Sheridan Road, Evanston, IL 60208, USAE-mail: [email protected]; [email protected] Dr. D. B. Buchholz , Dr. S. Xie , Prof. V. P. Dravid , Prof. R. P. H. Chang Department of Materials Science and Engineering and the Materials Research CenterNorthwestern University2220 Campus Drive, Evanston, IL 60208, USAE-mail: [email protected]; [email protected]

DOI: 10.1002/adma.201004198

durability with respect to PLD laser plumes. This “reinforced” SAND (R-SAND) enables the growth of high-quality, optically transparent a-ZITO TOS channels and TFTs operating at volt-ages of ≤1.0 V with mobilities as high as 140 cm 2 /V · s.

After SAND fi lms were fabricated via solution processing, [ 21 ] a ∼ 5 nm thick v-SiO x layer was grown by HCDS vapor deposition, followed by ambient exposure for crosslinking. [ 28 ] Figure 1b shows capacitance vs. frequency (at 2.0 V) data for SAND, R-SAND, and v-SiO x fi lms measured as n + -Si/dielec-tric/Au devices. Compared to SAND, which exhibits a high capacitance ( C i ) of ∼ 220 nF/cm 2 at 2.0 V/10 KHz, C i for R-SAND is ∼ 180 nF/cm 2 measured under the same conditions. The slightly smaller R-SAND C i is not unexpected considering the series-connected nature of the top v-SiO x layer, which by itself exhibits C i ∼ 750 nF/cm 2 . While v-SiO x alone exhibits moderate gate leakage, both SAND and R-SAND exhibit excellent insu-lating properties with leakage current densities < 10 − 6 A/cm 2 at a fi eld of ± 1.0 MV/cm using Au top-contact electrodes (Figure 1c).

PLD is a versatile growth method using laser pulses to vaporize target materials, and produces fi lms with compositions nearly identical to those of the target, making it an ideal explor-atory technique for multi-component oxide fi lms. [ 29 , 30 ] However, the dense forward-directed plume generated between the target and substrate is composed of high-energy species [ 31 , 32 ] which can resputter the substrate surface and potentially damage soft materials. To assess SAND durability under PLD conditions, a-ZITO transparent oxide conductor (TOC) fi lms were grown by PLD as top-contact electrodes for leakage current vs. elec-tric fi eld measurements. Note that all a-ZITO TOC deposition parameters are identical to those for a-ZITO TOS growth in TFT fabrication, except for a slightly lower oxygen partial pres-sure ( P O2 ) of 7.0 × 10 − 3 vs. 2.2 × 10 − 2 Torr used for a-ZITO TOS growth. [ 20 ] Figure 1c shows leakage data for n + -Si/dielectric/a-ZITO TOC devices with a-ZITO electrodes grown on top of SAND or R-SAND fi lms by PLD. The SAND samples have unac-ceptably large leakage current densities, from ∼ 10 − 4 to > 10 − 2 A/cm 2 at a ± 1.0 MV/cm electric fi eld, indicating severe damage. In contrast, the R-SAND samples having the v-SiO x reinforcing layer retain excellent insulating properties with leakage cur-rent densities < 10 − 6 A/cm 2 at a ± 1.0 MV/cm electric fi eld. These results indicate that the ∼ 5 nm thick v-SiO x protective layer (vs. the ∼ 0.8 nm SAND capping layer; Figure 1a) signifi cantly enhances SAND durability under PLD conditions. Low gate leakage is of course essential for acceptable TFT performance.

a-ZITO TOS-based TFTs were fi rst fabricated on n + -Si substrates using either SAND or R-SAND dielectrics and Au source/drain electrodes, with devices fabricated in parallel on p + -Si/SiO 2 (300 nm thermal oxide) substrates serving as

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Figure 1 . a) Schematic of the R-SAND gate dielectric microstructure, having three layers of type III SAND, each with a ∼ 0.8 nm “capping” layer; this trilayer is topped with a ∼ 5.0 nm v-SiO x reinforcing layer. b) Capacitance vs. frequency characteristics of SAND, R-SAND, and v-SiO x fi lms grown on n + -Si substrates (having a 1.2 nm native oxide coating) with Au top-contact electrodes. (c) Representative gate leakage current density vs. electric fi eld plots for SAND, R-SAND, and v-SiO x fi lms on n + -Si substrates using either Au or PLD-derived a-ZITO TOC top-contact electrodes.

controls. AFM images (Figure S1, Supporting Information) indicate smooth SAND, R-SAND, and a-ZITO TOS coverage on p + -Si/SiO 2 with RMS roughnesses of 2.2, 2.8, and 3.0 nm, respectively. A cross-sectional high-angle annular dark-fi eld scanning transmission electron microscopy (HAADF STEM) image of the R-SAND device ( Figure 2 a ) reveals a continuous and uniform contrast for the individual phases, with an atomi-cally abrupt interface between the a-ZITO TOS and R-SAND layers. That no interface is evident between the SAND and the v-SiO x layer in the HAADF and high- resolution TEM (HRTEM)

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Figure 2 . a) Cross-sectional HAADF STEM image of the R-SAND TFT having the structure n + -Si/SAND/v-SiO x /a-ZITO TOS/Au. b) HRTEM image of the indicated dielectric region, c) EELS spectral imaging map of the carbon k -edge in the same area.

images (Figure 2b) underscores the very good interfacial connec-tivity and similar electron density. The R-SAND layer thickness is determined to be ∼ 21 nm, thicker than ∼ 16 nm for regular SAND. [ 13 ] The ∼ 5 nm thickness difference is reasonably attrib-uted to the v-SiO x layer. [ 27 ] To further assess the R-SAND layer microstructure, electron energy loss spectroscopy (EELS) map-ping (i.e. spectral imaging) using the carbon k -edge was car-ried out in the same area as for the HRTEM image. As shown in Figure 2c, the R-SAND layer is clearly distinguishable as a bottom light area and a top dark area, corresponding to the carbon-rich SAND and the carbon-free v-SiO x layers, respectively. The measured thicknesses of ∼ 16 and ∼ 5 nm for the SAND and v-SiO x layers, respectively, agree well with the above estimate.

Regarding TFT performance, the data compiled in Table 1 were acquired on devices having channel dimensions of 100 μ m ( L ) × 2000 μ m ( W ) to ensure negligible fringing electric fi eld effects on parameter accuracy. [ 33 ] Figure 3 a,b show the typical output and transfer characteristics of control TFTs using a 300 nm thick thermally-grown SiO 2 gate dielectric. These devices show modest performance with μ FE ∼ 10 cm 2 /V · s, drain-source current ( I DS ) on/off ratio ( I on : I off ) ∼ 10 6 , operating voltages (including both the gate voltage, V G , and the drain-source voltage, V DS ) ∼ 100 V, threshold voltage ( V T ) ∼ 21 V, and sub-threshold gate voltage swing ( SS ) ∼ 5.3 V/decade, all comparable to previous results. [ 20 ] Slight clockwise hysteresis in the transfer plot of the 300 nm SiO 2

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Figure 3 . Typical output (a,c) and transfer (b,d) characteristics of a-ZITO TOS-based TFTs using n + -Si gate and Au source/drain electrodes, but with either 300 nm thermally grown SiO 2 (a,b) or R-SAND (c,d) gate dielectrics, respectively.

Table 1. Component materials and device performance parameters for a-ZITO TFTs fabricated using a PLD-derived 40 nm thick a-ZITO TOS channel.

Gate electrode Gate dielectric Source/drain d [a] [nm] C i [nF/cm 2 ] V DS [V] μ FE [cm 2 /V · s] I on [A] I on :I off V T [V] SS [V/dec] D it [b] [/cm 2 /eV]

p + -Si SiO 2 Au 300 10 100 9.7 ± 0.5 10 − 3 10 6 21 5.3 5.5 × 10 12

p + -Si SiO 2 Au 30 120 10 0.8 ± 0.2 10 − 5 10 5 –0.34 0.5 5.1 × 10 12

p + -Si SiO 2 + v-SiO x Au 30 + 5 100 10 1.2 ± 0.3 10 − 5 10 5 –0.38 0.4 4.0 × 10 12

n + -Si SAND Au 16 220 – [c]

n + -Si R-SAND Au 21 180 1.0 175 ± 8 10 − 4 10 5 0.20 0.13 1.4 × 10 12

glass/ITO R-SAND a-ZITO TOC 21 200 1.0 136 ± 7 10 − 4 10 5 0.25 0.13 1.5 × 10 12

[a] d = Dielectric layer thickness. [b] Interface state density, calculated from D it = ( q · SS /2.3 kT –1) C i / q , where q is the charge of the carrier, k the Boltzmann constant, and T the absolute temperature. [c] These devices did not function because of excessive gate leakage.

control device with a positive V G shift of ∼ 5.0 V in the reverse scan is likely due to traps at the SiO 2 /a-ZITO TOS interface. [ 34 , 35 ]

Note that the a-ZITO TOS-based TFTs using SAND-only die-lectrics fail to function because of high gate leakage, doubtless

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refl ecting PLD-induced SAND damage at the onset of a-ZITO deposition. In marked contrast, TFTs fabricated with R-SAND exhibit excellent performance. Figures 3c,d show typical output and transfer plots for these TFTs. Due to the large R-SAND C i ,

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these TFTs operate at a signifi cantly lower voltage of ∼ 1.0 V vs. ∼ 100 V for devices using the 300 nm SiO 2 dielectric. As seen inFigure 3c, I DS increases sharply with V DS in the linear region atpositive V G values and reaches saturation with clear pinch-off atlow V DS , as expected for an n-channel material. [ 1 ] Furthermore,a high saturation I DS of ∼ 0.36 mA is achieved at a low posi-tive V G of only 1.0 V. The transfer plot (Figure 3d) also exhibitslow I off ( ∼ 10 − 9 A), high I on ( > 10 − 4 A), and a good I on : I off ratio( > 10 5 ). Relatively small counterclockwise hysteresis of < 0.2 V isobserved when V G is swept from –0.5 to 1.0 V and then back-wards. Further increasing the positive V G sweep range resultsin a slight backward scanning current increase with no obviouseffect on the forward scan characteristics (Figure S2, SupportingInformation), suggesting that this slight hysteresis may arisefrom known polarization and/or mobile ion effects. [ 36–38 ] The μ FE and V T values extracted from the forward I DS 1/2 vs. V G plots

Figure 4 . (a) Optical transmission spectrum of an array of 80 TTFTs fabricated on 1.1 mm thick Corning 1737F glass having the structure: glass/ITO/R-SAND/a-ZITO TOS/a-ZITO TOC. The inset shows a photograph of the 80-TTFT array fabricated on 1.1 mm thick Corning 1737F glass. (b) Typical output and (c) transfer characteristics of these TTFTs.

are ∼ 180 cm 2 /V · s and ∼ 0.20 V, respectively. The origin of the high μ FE likely refl ects: 1) a conformal, contiguous, chlorine-free (evidenced by a negligible Cl 1s signal and a single symmetric O 1s signal in the XPS spec-trum; Figure S3, Supporting Information) v-SiO x layer having properties similar to those of the thinner SAND capping layer, known to dramatically reduce interface trap state densi-ties, as established by low frequency noise and I – V measurements, and to enhance mobility for diverse oxide fi lms and nanowires. [ 11 , 39 , 40 ] Note that the interface state density ( D it ) is signifi cantly lower in the R-SAND-based TFTs than in those using the 300 nm SiO 2 dielec-tric (Table 1; 1.4 × 10 12 vs. 5.5 × 10 12 /cm 2 /eV), suggesting superior semiconductor/dielectric interfacial properties. In control experiments with TFTs using a 30 nm SiO 2 dielectric ( C i ∼ 120 nF/cm 2 ), only a minor improvement in μ FE , SS , and D it is achieved after v-SiO x addition (Table 1; Figure S4, Supporting Infor-mation). These results argue that the signifi -cantly enhanced R-SAND TFT performance derives not only from the protective qualities of the v-SiO x layer, but also from the known dielectric properties of the underlying SAND as discussed above; 2) the established high electron mobilities of ZITO ceramics having comparable compositions (Hall effect mobility ∼ 250 cm 2 /V · s); [ 41 ] 3) the amorphous nature of the a-ZITO TOS. Note that a-TOS and crystal-line TOS materials have similar electronic structures and carrier transport mechanisms because the conduction bands are composed of non-directional metal s orbitals. [ 4 , 42 , 43 ] Besides microstructural uniformity and smoothness, there should be minimal grain boundary scat-tering in a-TOSs; 4) the very small measured effective mass of a-ZITO fi lms ( m ∗ ∼ 0.23), [ 20 ] the electron mobility of which should increase with the falling carrier concentrations under high P O2 growth; [ 44 , 45 ] 5) the microstructural


continuity between v-SiO x and SAND, and the atomically abrupt interface between a-ZITO TOS and R-SAND indicated by TEM ( Figure 2 ). Finally, from the reciprocal of the maximum slope of the log( I DS ) vs. V G plots below V T , a very small SS of ∼ 0.13 V/decade is estimated for the R-SAND TFTs. This is ∼ 1/40 of that for the 300 nm SiO 2 control devices, again underscoring the attraction of R-SAND gate dielectrics.

TTFTs were next fabricated on glass substrates by replacing the n + -Si gate (having a native oxide coating) and Au source/drain electrodes with TOC fi lms. ITO fi lms grown by ion-assisted deposition (IAD) were used as gate electrodes because of their ultra-smooth surfaces (RMS roughness ∼ 1.0 nm vs. > 2.0 nm for most commercial ITO fi lms), [ 46 ] and a-ZITO TOC fi lms were chosen as the top-contact source/drain electrodes to ensure Ohmic contacts to the a-ZITO TOS channel. [ 47 , 48 ] Figure 4 a shows the optical transmission spectrum of an 80 TTFT



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array taken through the a-ZITO TOC source/drain region. The average visible transmittance ( T , 400–700 nm) is ∼ 73% for the entire device including the 1.1 mm thick Corning 1737F glass substrate ( T ∼ 90%). The photographic image (Figure 4a, inset) also illustrates the good transparency. As can be seen in Figures 4b,c, the present TTFTs also operate impressively at a voltage of ∼ 1.0 V. The steep linear increase of I DS with V DS in the low V DS region at different V G values (Figure 4b) sug-gests good Ohmic contact between the a-ZITO TOC source/drain electrodes and the a-ZITO TOS channel. The satura-tion I DS reaches ∼ 0.24 mA at V G = 1.0 V. The μ FE , I off , I on : I off , and V T values extracted from the transfer plots at a V DS of 1.0 V (Figure 4c) are ∼ 140 cm 2 /V · s, ∼ 10 − 9 A, > 10 5 , and ∼ 0.25 V, respectively ( Table 1 ). The slightly higher gate leakage current of ∼ 10 − 6 A at V G = 1.0 V (Figure S5, Supporting Information ) can be related to the unpatterned gate or semiconductor structure used here, which should decrease signifi cantly in a patterned device. Furthermore, these transparent TFTs show a low SS of ∼ 0.13 V/decade, similar to the devices discussed above using an n + -Si gate and Au electrodes. Note that low operating voltages, high μ FE , low I off , small SS , and large I on : I off characteristics are all important in realizing the low power consumption needed for battery-powered portable electronics.

In summary, R-SAND gate dielectrics were prepared by depositing a thin protective layer on top of SAND fi lms via post-crosslinking of vapor-deposited HCDS fi lms. The properties of this layer were characterized by a battery of electrical and micro-structural techniques. The strategy of reinforcing SAND with a thin v-SiO x layer greatly improves SAND durability under PLD growth conditions, thereby expanding SAND compatibility with a broad range of semiconductors and semiconductor growth techniques. Furthermore, integrating R-SAND and PLD-derived a-ZITO TOS fi lms with TOC gate and source/drain electrodes affords TFTs having excellent performance parameters, μ FE ∼ 140 cm 2 /V · s, I on > 10 − 4 A, I on : I off > 10 5 , SS ∼ 0.13 V/decade, operating voltages ∼ 1.0 V, and good optical transparency.

Experimental Section Film and Device Fabrication: Using the procedure described previously,

ITO fi lms ( ∼ 100 nm) serving as the TFT gate electrodes were grown on 1.1 mm thick Corning 1737F glass by IAD at room temperature using an ITO target (99.99%, In:Sn = 9:1) from Williams Advanced Materials, Inc. with no prepatterning. [ 46 ] The a-ZITO TOS and TOC fi lms were grown by PLD from a hot-pressed Zn 0.33 In 1.40 Sn 0.27 O 3 target at room temperature and with P O2 settings of 2.2 × 10 − 2 and 7.0 × 10 − 3 Torr, respectively. [ 20 ] Type III SAND fi lms were fabricated on n + -Si (100) (Montco Silicon Tech; 1.2 nm native oxide coating) and glass/ITO substrates using the published layer-by-layer self-assembly method. [ 21 ] R-SAND was prepared by depositing a ∼ 5 nm thick v-SiO x layer on the as-fabricated SAND via the post-crosslinking of a vapor-deposited HCDS fi lm. [ 28 ] For capacitance and leakage current characterization, ∼ 50 nm Au or ∼ 80 nm a-ZITO TOC top contact electrodes were deposited on the n + -Si/SAND and n + -Si/R-SAND samples by vacuum thermal evaporation at ∼ 2.0 × 10 − 6 Torr or by PLD, respectively, using shadow masks to defi ne 200 μ m × 200 μ m electrodes. For TFTs, ∼ 40 nm a-ZITO TOS fi lms were fi rst deposited, followed by Au or ZITO source/drain electrode deposition through shadow masks to produce 100 μ m × 2000 μ m channels. In addition to the n + -Si/R-SAND and glass/ITO/R-SAND samples, TFTs were also fabricated in parallel on p + -Si/SiO 2 substrates having 300 nm thermal oxide (Montco Silicon Tech.) as controls. Additional controls were

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[ 1 ] A. Facchetti , T. Marks ,(Eds.) Transparent Electronics, Wiley-VCH, Weinheim, Germany 2010 .

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similarly fabricated on p + -Si/SiO 2 substrates having 30 nm thermal oxide (from IBM Corp.) to provide capacitance similar to that of R-SAND. All TFTs had bottom-gate top-contact structures.

Thin Film and Device Characteration: Film thicknesses were measured with a Veeco Dektak 150 Surface Profi ler by making a step during or after fi lm deposition. Tapping-mode AFM images were recorded on a JEOL-5200 Scanning Probe Microcope with silicon cantilevers (Model: ACTA; Applied NanoStructures, Inc.). Cross-sectional TEM specimens were prepared by focused ion beam (FIB) milling using an FEI Helios Nanolab Dual-Beam system. HAADF STEM, HRTEM, and EELS mapping images were obtained using a 200 KV fi eld-emission gun (FEG) JEOL 2100 FasTEM with a 2 Å nominal probe size and 0.7 eV energy resolution. X-ray photoelectron spectroscopic (XPS) data were collected using an Omicron ESCA probe equipped with a monochromatic Al K α (1486.8 eV) 300 W X-ray source and an EA125 energy analyzer at a photoelectron take-off angle of 15 ° , and binding energies are referenced to the C1 s peak set at 284.7 eV. Optical transmission spectra were recorded with a Cary 5000 UV-vis-NIR spectrophotometer. Capacitance measurements were carried out on a Hewlett-Packard 4192A impedance spectrometer. Dielectric leakage properties and TFT performance characterizations were performed on a Signatone probe station with a Keithley 6430 sub-femtoamp remote source meter and a Keithley 2400 source meter using locally written Labview software. All electrical measurements were carried out at room temperature in ambient with no intentional light blocking.

Supporting Information Supporting Information is available from the Wiley Online Library or from the author.

Acknowledgements The research was supported by the MRSEC program of NSF (DMR-0520513) at the Northwestern University Materials Research Center and by AFOSR (FA9550–08-1–0331). Microscopy studies were performed in the EPIC and NIFTI facilities of NUANCE Center at Northwestern University. NUANCE Center is supported by NSF-NSEC, NSF-MRSEC, Keck Foundation, the State of Illinois, and Northwestern University. The authors also thank Polyera Corp. for assistance in TFT device testing, Dr. C.Y. Sung and IBM Corp. for supplying silicon wafers, and Mr. M.-G. Kim for helpful discussions.

Received: November 13, 2010 Published online: January 20, 2011

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Reinforced Self-Assembled Nanodielectrics for High-Performance Transparent Thin Film Transistors

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