Reiner Hartenstein University of Kaiserslautern
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Transcript of Reiner Hartenstein University of Kaiserslautern
Enabling Technologies for System-on-Chip Development
Reconfigurable Computing Architectures and Methodologies for System-on-Chip
Monday, November 19, 10:15 - 11:00 hrs.
Reiner Hartenstein
University ofKaiserslautern
November 19-20, 2001, Tampere, Finland
© 2001, [email protected] http://www.fpl.uni-kl.de2
University of Kaiserslautern
Xputer Labdownloadable “handout”
•Viewgraphs downloadable from:http://www.fpl.uni-kl.de
•Paper dowloadable from:http:// www.fpl.uni-kl.de/staff/hartenstein/lot/Tampere01.pdf
/staff/hartenstein/lot/Tampere01.ppt
if you use part of it, please, quote me and e-mail me to:
© 2001, [email protected] http://www.fpl.uni-kl.de3
University of Kaiserslautern
Xputer LabConferences on Reconfigurable Logic
•topic adoption by congresses: ASP-DAC, DAC, DATE, ISCAS, SPIE ….
•FCCM, FPGA (founded 1992), and FPL (founded 1991 at Oxford, UK):
•FPL 2002, La Grande Motte (Montpellier, France), Sept. 2 – 4
http://www.lirmm.fr/fpl2002/
Paper Submission deadline : 15th March 2002
The International Conference on Field-programmable Logic and Applications
Laboratoire d‘Informatique, de Robotique et deMicroélectronique de MontpellierMontpellier
de
© 2001, [email protected] http://www.fpl.uni-kl.de4
University of Kaiserslautern
Xputer Lab>> Introduction
• Conclusions & Future Developmentshttp://www.uni-kl.de
fine grain
coarse grain
• Introduction
• FPGA boom
• Coarse Grain Architectures
• Programming rDPAs
© 2001, [email protected] http://www.fpl.uni-kl.de5
University of Kaiserslautern
Xputer LabThe Impact of Reconfigurable
Logic• Reconfigurable platforms bring a new dimension to digital
system development and have a strong impact on SoC design.
• A rapidly growing large user base of HDL-savvy designers with FPGA experience.
• Flexibility supports spin-around times of minutes instead of months for real time in-system debugging, profiling, verification, tuning, field-maintenance, and field upgrades
• A New Business Model (in-field debugging and upgrading ... )
• A Fundamental Paradigm Shift in Silicon Application
Revenue/ month
Time / months
Update 1
Product
Update 2
1 10 20
ASIC Product
reconfigurable Product with download
30
[Kean]
© 2001, [email protected] http://www.fpl.uni-kl.de6
University of Kaiserslautern
Xputer LabThe History of
Paradigm Shifts
“Mainstream Silicon Applicationis switching every 10 Years”
TTL µproc.,memory
“The Programmable System-on-a-Chipis the next wave“
custom
standard
1957
1967
1977
1987
1997
2007
Makimoto’s Wave
ASICs,accel’s
LSI,MSI
1st D
esig
n C
risis
2n
d D
esig
n C
risis
reconfigurablePublished
in 1989
© 2001, [email protected] http://www.fpl.uni-kl.de7
University of Kaiserslautern
Xputer LabHow’s next Wave ?
2007FPGAs
custom
standard
1957
1967
1977
1987
1997
Tredennick’sParadigm Shifts
procedural programming
algorithm: variable
resources: fixed
hardwired
algorithm: fixed
resources: fixed
2007
?
structural programming
algorithm: variable
resources: variable
rDPAs
no further wave !
?4th wave ?
Hartenstein’s Curve
© 2001, [email protected] http://www.fpl.uni-kl.de8
University of Kaiserslautern
Xputer LabThe Impact of
Makimoto’s Paradigm Shifts
TTL µproc.,memory
custom
standard
ASICs,accel’s
LSI,MSI
reconfigurable
1957
1967
1977
1987
1997
2007
Proceduralpersonalization via RAM-based
Machine Paradigm
Personalization(CAD) beforefabrication
structuralpersonalization:
RAM-basedbefore run time
Dr. Makimoto: FPL 2000 keynote
Software Industry’sSecret of Success
Repeat Success Story bynew Machine Paradigm !
© 2001, [email protected] http://www.fpl.uni-kl.de9
University of Kaiserslautern
Xputer Lab>> FPGA boom
• Introduction
• FPGA boom
• Coarse Grain Architectures (rDPAs)
• Programming rDPAs
• Conclusions & Future Developmentshttp://www.uni-kl.de
© 2001, [email protected] http://www.fpl.uni-kl.de10
University of Kaiserslautern
Xputer LabWhat is an FPGA ?
single-length lines
double-length lines
S S
S S
L
L L
LL
L
L LL
lon
glin
es
S = Switch BoxL = Logic Block
Xilinx XC400E
reconfigurableinterconnectfabric
L
L L
LL
L
L LL
configurablelogic blocks
(CLBs)
© 2001, [email protected] http://www.fpl.uni-kl.de11
University of Kaiserslautern
Xputer LabTop 4 FPGA Manufacturers 2000
Xilinx42%
Altera37%
Lattice15%
Actel6%
Top 4 PLD Manufacturers 2000total: $3.7 Bio
•[Dataquest] > $7 billion by
2003.
•"pre-fabricated" components and IP reuse for PLDs
•FPGAs going into every type of application – also SoC
•soon reach 50 million system gates / Chip
•PLD vendors provide libraries to support their products
soft IPs
Configware•fastest growing semiconductor market segment
•killing the ASIC market
•improved design flow & libraries
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
12
Away from complex design flow
UserCode Compiler Executable
Netlister NetlistPlaceand
Route..
Bitstream
Schematics/HDL
[S. Guccione]
use CPU for congfiguration management
CompilerHLL
[S. Guccione]
HLL Compiler
[S. Guccione]
CompilerHLL
[S. Guccione]
Embedded CPU: Configware / Software
Co-design is commonplace
from HDL to HLL
supporting ....dynamically reconfigurable (RTR)
© 2001, [email protected] http://www.fpl.uni-kl.de13
University of Kaiserslautern
Xputer LabConfigware as the Key Enabler
• Growing no. of independent configware houses (soft IP core vendors) and design services
• Xilinx AllianceCORE & Reference Design Alliance et al.
• Top FPGA vendors Currently the key innovators
• Design productivity and quality by configware libraries (soft IP cores) from various application areas.
• Cadence, Mentor, Synopsys just jumped in.
• Emerging separate EDA software market (comparable to compiler / OS market in computers)
© 2001, [email protected] http://www.fpl.uni-kl.de14
University of Kaiserslautern
Xputer Lab>> Coarse Grain Architectures
• Introduction
• FPGA boom
• Coarse Grain Architectures (rDPAs)
• Programming rDPAs
• Conclusions & Future Developments
for detailed
overview see
proceedings
http://www.uni-kl.de
© 2001, [email protected] http://www.fpl.uni-kl.de15
University of Kaiserslautern
Xputer LabWhy coarse-grained ?
S S
S Sresources needed for reconfigurability
partly for configuration code storage
L
L L
LL
L
L LL
area used by application
“hidden RAM”not shown
Reconfigurability Overhead
© 2001, [email protected] http://www.fpl.uni-kl.de16
University of Kaiserslautern
Xputer LabCommercial rDPAs
XPU family (IP cores):PACT corp., Munich
XPU128
flexible array: MorphICs
CALISTO: Silicon Spice*
CS2000 family:Chameleon Systems
MECA family: Malleable*
FIPSOC: SIDSA
ACM: Quicksilver Tech
CHESS array: Elixent
*) bought
© 2001, [email protected] http://www.fpl.uni-kl.de17
University of Kaiserslautern
Xputer Lab
KressArray Family generic Fabrics: a few examples
Examples of 2nd Level Interconnect:layouted overrDPU cell - no separate routing areas !
+
rout-through and function
rout-throug
h only more NNports:
rich Rout Resources
Select Function
Repertory
select Nearest Neighbour (NN) Interconnect: an example
16 32 8 24
4
2 rDPU
Select mode, number, width of NNports
http://kressarray.de
© 2001, [email protected] http://www.fpl.uni-kl.de18
University of Kaiserslautern
Xputer Lab
rDPU not used used for routing only operator and routing port location markerLegend: backbus connect
array size: 10 x 16 = 160 rDPUs
http://kressarray.de
SNN filter KressArray Mapping Example
rout thru only
not usedbackbus connect
© 2001, [email protected] http://www.fpl.uni-kl.de19
University of Kaiserslautern
Xputer Lab It’s a General Paradigm Shift !
• Using FPGAs (fine grain reconfigurable): just Logic Synthesis on a strange platform
• replaceConcurrent Processes by much more efficient parallelism: Stream-based DPAs1
1 ) systolic array* [1980]
KressArray** [1995]
____
*) hardwired
**) reconfigurable
and rDPAs2
converging design flows
2 ) chip-on-a-day* [2000]
[Broderson]
• Coarse Grain rDPAs (Reconfigurable Computing): a fundamental Paradigm Shift
terms:DPU: datpath unitDPA: data path arrayrDPU: reconfigurable DPUrDPA: reconfigurable DPA
Kress: a generalization of systolic array synthesis:super systolic synthesis
© 2001, [email protected] http://www.fpl.uni-kl.de20
University of Kaiserslautern
Xputer Lab Concurrent Computing
DPUinstructionsequencer
DPUinstructionsequencer
DPUinstructionsequencer
DPUinstructionsequencer
....
Bus(es) or switch box
CPUextremely inefficient
• control flow overhead• instruction fetch / interpretation overhead • address computation overhead - may be massive• massive bottleneck phenomena at run time
© 2001, [email protected] http://www.fpl.uni-kl.de21
University of Kaiserslautern
Xputer LabStream-based Computing: (r)DPA
for both,• reconfigurable, and• hardwired [Brodersen]
DPU DPUDPU
DPU DPUDPU
DPU DPUDPU
•transport-triggered execution
driven by data stream from / to memory or, from / to peripheral interface
•no instruction sequencer inside !
avoids run time overhead and bottleneck
phenomena
rDPA: drastically reduced reconfigurability overhead
© 2001, [email protected] http://www.fpl.uni-kl.de22
University of Kaiserslautern
Xputer Lab>> Programming rDPAs
• Introduction
• FPGA boom
• Coarse Grain Architectures (rDPAs)
• Programming rDPAs
• Conclusions & Future Developments
http://www.uni-kl.de
© 2001, [email protected] http://www.fpl.uni-kl.de23
University of Kaiserslautern
Xputer Lab
linearprojection
or algebraicmapping
equations
a12
a11 a21
a32
a31
a23 a33
a22
a13
DPU architecturey
+*
x
a
computingin space
placement
y10
y20
y30
---
y1
y2
y3
---
x1
x2
x3
-
- -
datastreams
Systolic Stream-based Computing System
this dichotomy iscompletely ignoredby our CS curricula
computingin time
systolicarrays etc.
and other transformationsmigration by re-timing
linear pipelinesand uniformarrays only The Mathematician’s
Synthesis Method
norouting!
Systolic Array [H. T. Kung, 1980]: a DPA (Data Path Array)
© 2001, [email protected] http://www.fpl.uni-kl.de24
University of Kaiserslautern
Xputer Lab
2
General Stream-based Computing Systemheterogenous DPA or rDPA
Scheduler
Mapper
expression treeDPU architectures
y
+*
x
a
1
simultaneousplacement& routing
3
+
++
+
***sh
*sh
sh sh
xf
xf
-
- datastreams
4
The same mapper for both:Reconfigurable,or hardwired
Kress DPSS [1995]
simulated
annealing
free form
pipe network
© 2001, [email protected] http://www.fpl.uni-kl.de25
University of Kaiserslautern
Xputer Lab
Architecture &Mapping Editor
Stat
istics
KressArray DPSS
DatastreamGenerator
HDLGeneratorSimulator
DatapathGeneratorGenerator
Delay & Power
EstimatorImprovement
ProposalGeneratorhttp://kressarray.de
KressArray(Design Space)Platform SpaceExplorer
ApplicationSet
Xplorer
User DPSS
SourceInput
intermediateform
© 2001, [email protected] http://www.fpl.uni-kl.de26
University of Kaiserslautern
Xputer Lab
application not usedLegend:
http://kressarray.de
•an example by Nageldinger’s KressArray Xplorer
Memory Communication Architecture …•hot research topic in embedded systems
•storage context transformations [Cathoor, Herz, Kougia, Soudris]
•Synthesizable Memory Communication Architecture
• startups provide memory IP or generators
sequencersmemory ports
Optimized ParallelMemory Controller
GAG generic sequencer methodology vailable
Herz
© 2001, [email protected] http://www.fpl.uni-kl.de27
University of Kaiserslautern
Xputer Lab... for a Stream-based Soft Machine
SchedulerMemory(data memory)
memory bank
memory bank
memory bank
memory bank
memory bank
...
...
rDPACompiler
Sequencers(data stream
generator)
© 2001, [email protected] http://www.fpl.uni-kl.de28
University of Kaiserslautern
Xputer Lab
datacounter
programcounter:
state register
CompilerMemory
Datapath
hardwired
Sequencer
Computer Computer tightly coupledby compact
instruction code
“von Neumann”
“von Neumann”does not supportsoft data pathsdoes not supportsoft data paths
Datapath
reconfigurable
Xputer Xputer
SchedulerCompiler
Memory
multiplesequencer
DatapathArray
University of Kaiserslautern
Xputer Lab
loosely coupledby decision data bits only
Xputer:Xputer:The Soft Machine Paradigm
The Soft Machine Paradigm reconfigurablereconfigurable
Computer:the wrong Machine Paradigm“von Neumann”
Fundamentals available
(course on Wednesday)also for hardwiredalso for hardwired[Broderson]
© 2001, [email protected] http://www.fpl.uni-kl.de29
University of Kaiserslautern
Xputer Lab
Processor
Co-Compilation
partitioning compiler
Computer
Machine Paradigm
Software running on
Xputer
“Soft” Machine Paradigm
Configware running onGNU C
compiler Analyzer/ Profiler
Hardware / Software Co-Design turnsto Configware / Software Co-Design
supportingdifferentplatforms
Resource Parameters
inte
rfac
e
X-Ccompiler
ReconfigurableAcceleratorsKressArray
DPSS
high level programming language sourceX-C
Partitioner
Jürgen Becker’s Co-DE-X Co-Compiler[ASP-DAC’95]
© 2001, [email protected] http://www.fpl.uni-kl.de30
University of Kaiserslautern
Xputer LabLoop Transformation
Examples
loop 1-8bodybodyendloop
loop 1-8bodyendloop
loop 9-16bodyendloop
fork
joinstrip mining
loop 1-4triggerendloop
loop 1-2triggerendloop
loop 1-8triggerendloop
reconf.array:host:loop 1-16bodyendloop
sequential processes: resource parameter drivenCo-Compilation
loop unrolling
© 2001, [email protected] http://www.fpl.uni-kl.de31
University of Kaiserslautern
Xputer Lab>> Conclusions
• Introduction
• FPGA boom
• Coarse Grain Architectures (rDPAs)
• Programming rDPAs
• Conclusions & Future developments
http://www.uni-kl.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
32
FPGA CPUs
softCPU
FPGA
MemorycoreFPGA
CompilerHLL
core architecture platform
MicroBlaze 125 MHz 70 D-MIPS
32 bit st‘d RISC32 reg. by 32 LUT RAM-based reg.
Xilinx up to 100 on one FPGA
Nios 16-bit instr. set Altera Mercury
Nios 50 MHz
32-bit instr. set Altera 22 D-MIPS
Nios 8 bit Altera Mercury
gr1040 16-bit
gr1050 32-bit
My80 i8080A FLEX10K30 or EPF6016
DSPuva16 16 bit DSP Spartan-II
core architecture platform
Leon 25 Mhz
SPARC
ARM7 clone ARM
uP1232 8-bit
CISC, 32 reg. 200 XC4000E CLBs
REGIS 8 bit instr. 2 Xilinx 3020 LCA
Reliance-1 12 bit DSP Lattice 4 isp30256, 4 isp1016
1Popcorn-1 8 bit CISC Altera, Lattice, Xilinx
Acorn-1 1 Flex 10K20
YARD-1A 16-bit RISC old Xilinx FPGA Board
xr16 RISC integer C
SpartanXL
• UCSC: 1990!
• Märaldalen University, Eskilstuna, Sweden • Chalmers University, Göteborg, Sweden• Cornell University• Hiroshima City University, Japan• Tokai University, Japan • Universidad de Valladolid, Spain• Washington University, St. Louis
• Gray Research• Georgia Tech • Michigan State• Virginia Tech• New Mexico Tech• UC Riverside
academic FPGA CPUs
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
33
Soft rDPA ?
Memorysoft CPU
miscellanous
soft
soft
DPUDPU
arra
y
arra
ysoft
soft
DPUDPU
arra
y
arra
y
HLL Compiler
•Rapid technology progress
•50 mio system gates soon
•FPGAs f. relocateble configware code ?
•Compatibility at configuration code level ?
•Slower clock: compensated by more
parellelism
•Even large rDPAs as a soft IP become feasible•By >2005: don’t care about area efficiency ?
© 2001, [email protected] http://www.fpl.uni-kl.de34
University of Kaiserslautern
Xputer LabMain problems to be solved
•object code compatibility
Dominant FPGA vendor needs:
•widely accepted OS & tools
•most software written for it•most configware written for it•conf‘w. object code compatibility•widely accepted „OS“ & tools
Most successful µprocessor:
•de facto standard configware libraries
•configw. code compatibility by de facto standard RC platform family
•scalable FPGA architectures supp‘n relocatable configuration code
computingin space
computingin time
systolicarrays etc.
•widely spread dichotomy and FPGA awareness•curricular innovations are urgently needed
•compilers to avoid needing HDL-savvy users
FPGA-based de facto Standards:
Education:
•relocatable code•scalable memory
important:
© 2001, [email protected] http://www.fpl.uni-kl.de35
University of Kaiserslautern
Xputer LabHowever, current CS Education ….
Hardware invisible:under the surface
… is based on the Submarine Model
Brain usage:procedural-only
Software Faculty Colleagues shy away from the Paradigm Shift:their Brain hurts? - can’t be: this Half has been amputated
Algorithm
Assembly Language
procedural high level Programming
Language
Hardware
Software
This model disables ...
© 2001, [email protected] http://www.fpl.uni-kl.de36
University of Kaiserslautern
Xputer Lab
Hardware,Configware
Hardware and Software as Alternatives
Algorithm
Software
partitioning
Software onlySoftware & Hardw/Configw
procedural structural
Brain Usage:both Hemispheres
Hardw/Configw only
© 2001, [email protected] http://www.fpl.uni-kl.de37
University of Kaiserslautern
Xputer LabThe Dominance of the Submarine
Model ...
Hardware
... indicates, that our CS education system produces zillions of mentally disabled
Persons
(procedural) structurallydisabled
… completely disabled to cope with solutions other than software only
It‘s time to attack the software faculty dictatorship.Get
involved!
© 2001, [email protected] http://www.fpl.uni-kl.de38
University of Kaiserslautern
Xputer Lab>>> thank you
thank you for listening
© 2001, [email protected] http://www.fpl.uni-kl.de39
University of Kaiserslautern
Xputer Lab>>> END
END