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I/O MUX CONTROL REGIESTER A (MCRA REGISTER) (PORT A & B CONTROL)MCRA15MCRA14MCRA13MCRA12MCRA11MCRA10MCRA9MCRA8MCRA7MCRA6
MCRA5MCRA4MCRA3MCRA2MCRA1MCRA0
PORT B (IOPB7 IOPB0)PORT A (IOPA7 IOPA0)
IOPB7
IOPB6IOPB5IOPB4IOPB3IOPB2IOPB1IOPB0IOPA7IOPA6IOPA5IOPA4IOPA3IOPA2IOPA1IOPA0
TCLK
INATDIRT2PWM
T2CMPT1PWM
T1CMPPWM6PWM5PWM4PWM3PWM2PWM1CAP3CAP2CAP1XINT1SCI
RXDSCI TXD
I/O MUX CONTROL REGIESTER B (MCRB REGISTER) (PORT C & D CONTROL)MCRB15MCRB 14MCRB13MCRB 12MCRB11MCRB 10MCRB9MCRB 8MCRB 7MCRB 6MCRB 5MCRB 4MCRB 3MCRB 2MCRB 1MCRB 0
PORT D (IOPD0)PORT C (IOPC7 IOPC0)
RESERVED
IOPD0IOPC7IOPC6IOPC5IOPC4IOPC3IOPC2IOPC1IOPC0
TMS2TMSTD0TDITCKEMU1EMU0XINT2
ADCSOCCANRXCANTXSPISTESPICLKSPISOMISPISIMOBIOW / R
I/O MUX CONTROL REGIESTER C (MCRC REGISTER) (PORT E & F CONTROL)MCRC15MCRC14MCRC13MCRC 12MCRC11MCRC 10MCRC9MCRC 8MCRC 7MCRC 6MCRC 5MCRC 4MCRC 3MCRC 2MCRC 1MCRC 0
PORT F (IOPF5-IOPF0)PORT E (IOPE7 IOPE0)
RESERVED
IOPF5IOPF4IOPF3IOPF2IOPF1IOPF0IOPE7IOPE6IOPE5IOPE4IOPE3IOPE2IOPE1IOPE0
RESERVED
TCLK
INBTDIRBT3PWM
T3CMPT3PWM
T3CMPCAP6CAP5 / QEP4CAP4 / QEP3PWM12PWM11PWM10PWM9PWM8PWM7CLK
OUT
STATUS AND CONTROL REGISTER 0 (ST0)1514131211109876543210
ARPOVOVM1INTMDP
STATUS AND CONTROL REGISTER 1 (ST1)1514131211109876543210
ARBCNFT/CSXMC1111XF11PM
DATA AND DIRECTION CONTROL REGISTER A (FOR PORT A)
DIRECTIONDATA
1514131211109876543210
A7DIRA6DIRA5DIRA4DIRA3DIRA2DIRA1DIRA0DIRIOPA7IOPA6IOPA5IOPA4IOPA3IOPA2IOPA1IOPA0
PRIMARY PIN NAMECMP2
IOPA7CMP1
IOPA6CAP3
IOPA5CAP2
QEP2
IOPA4CAP1
QEP1
IOPA3XINT1
IOPA2SCIRXD IOPA1SCITXD IOPA0
DATA AND DIRECTION CONTROL REGISTER B (FOR PORT B)DIRECTIONDATA
1514131211109876543210
B7DIRB6DIRB5DIRB4DIRB3DIRB2DIRB1DIRB0DIRIOPB7IOPB6IOPB5IOPB4IOPB3IOPB2IOPB1IOPB0
PRIMARY PIN NAMETCLKIN
IOPB7TDIR
IOPB6T2CMP
IOPB5T1CMP
IOPB4CMP6
IOPB3CMP5
IOPB2CMP4
IOPB1CMP3
IOPB0
DATA AND DIRECTION CONTROL REGISTER C (FOR PORT C)
DIRECTIONDATA
1514131211109876543210
C7DIRC6DIRC5DIRC4DIRC3DIRC2DIRC1DIRC0DIRIOPC7IOPC6IOPC5IOPC4IOPC3IOPC2IOPC1IOPC0
PRIMARY PIN NAMECANRX
IOPC7CANTX
IOPC6SPISTE
IOPC5SPICLK
IOPC4SPISOMI
IOPC3SPISIMO
IOPC2BIO
IOPC1W / R
IOPC0
DATA AND DIRECTION CONTROL REGISTER D (FOR PORT D)
DIRECTIONDATA
1514131211109876543210
RESERVEDD0DIRRESERVEDIOPD0
PRIMARY PIN NAMERESERVEDXINT2 / ADCSOC / IOPD0
DATA AND DIRECTION CONTROL REGISTER E (FOR PORT E)
DIRECTIONDATA
1514131211109876543210
E7DIRE6DIRE5DIRE4DIRE3DIRE2DIRE1DIRE0DIRIOPE7IOPE6IOPE5IOPE4IOPE3IOPE2IOPE1IOPE0
PRIMARY PIN NAMECAP4
QEP
IOPE7PWM12IOPE6PWM11IOPE5PWM10IOPE4PWM9IOPE3PWM8IOPE2PWM7IOPE1CLKOUTIOPE0
DATA AND DIRECTION CONTROL REGISTER F (FOR PORT F)
DIRECTIONDATA
1514131211109876543210
RESERVEDF6DIRF5DIRF4DIRF3DIRF2DIRF1DIRF0DIRRESERVEDIOPF6IOPF5IOPF4IOPF3IOPF2IOPF1IOPF0
PRIMARY PIN NAMERESERVEDIOPF6TCLKIN2
IOPF5TDIR2
IOPF4T4PWM
T4CMP
IOPF3T3PWM
T3CMP
IOPF2CAP6
IOPF1
CAP5
QEP4
IOPF0
TIMER CONTROL REGISTER 1(T1 CON REGISTER)1514131211109876543210
FREE
SOFTRESERVEDTMODE1TMODE0TPS2TPS1TPS0RESERVEDTENABLETCLKS1TCLKS0TCLD1TCLD0TECMPRRESERVED
TIMER CONTROL REGISTER 2 (T2 CON REGISTER)
1514131211109876543210
FREE
SOFTRESERVEDTMODE1TMODE0TPS2TPS1TPS0T2SWT1TENABLETCLKS1TCLKS0TCLD1TCLD0TECMPRSELT1PR
TIMER CONTROL REGISTER 3 (T3 CON REGISTER)1514131211109876543210
FREE
SOFTRESERVEDTMODE1TMODE0TPS2TPS1TPS0RESERVEDTENABLETCLKS1TCLKS0TCLD1TCLD0TECMPRRESERVED
TIMER CONTROL REGISTER 4 (T4CON REGISTER)
1514131211109876543210
FREE
SOFTRESERVEDTMODE1TMODE0TPS2TPS1TPS0T4SWT3TENABLETCLKS1TCLKS0TCLD1TCLD0TECMPRSELT3PR
GP TIMER CONTROL REGISTER A (GPTCON A)1514131211109876543210
RESERVEDT2STATT1STATRESERVEDT2TOADCT1TOADCTCOMPOERESERVEDT2PINT1PIN
GP TIMER CONTROL REGISTER B (GPTCON B)1514131211109876543210
RESERVEDT4STATT3STATRESERVEDT4TOADCT3TOADCTCOMPOERESERVEDT4PINT3PIN
COMPARE CONTROL REGISTER A (COMCON A)
1514131211109876543210
CENABLE
CLD1CLD0SVENABLEACTRLD1ACTRLD0FCOMPOEPDPINTA
STATUSRESERVED
COMPARE CONTROL REGISTER B (COMCON B)1514131211109876543210
CENABLE
CLD1CLD0SVENABLEACTRLD1ACTRLD0FCOMPOEPDPINTA
STATUSRESERVED
COMPARE ACTION CONTROL REGISTER A (ACTRA)
1514131211109876543210
SVRDIRD2D1D0CMP6
ACT1CMP6
ACT0CMP5
ACT1CMP5
ACT0CMP4
ACT1CMP4
ACT0CMP3
ACT1CMP3
ACT0CMP2
ACT1CMP2
ACT0CMP1
ACT1CMP1
ACT0
COMPARE ACTION CONTROL REGISTER B (ACTRB)
1514131211109876543210
SVRDIRD2D1D0CMP12
ACT1CMP12
ACT0CMP11
ACT1CMP11
ACT0CMP10
ACT1CMP10
ACT0CMP9
ACT1CMP9
ACT0CMP8
ACT1CMP8
ACT0CMP7
ACT1CMP7
ACT0
DEADBAND TIMER CONTROL REGISTER A(DBTCON A)
1514131211109876543210
RESERVED
DBT3DBT2DBT1DBT0EDBT3EDBT2EDBT1DBTPS2DBTPS1DBTPS0RESERVED
DEADBAND TIMER CONTROL REGSITER B(DBTCON B)
1514131211109876543210
RESERVED
DBT3DBT2DBT1DBT0EDBT3EDBT2EDBT1DBTPS2DBTPS1DBTPS0RESERVED
CAPTURE CONTROL REGISTER A(CAPCON A)
1514131211109876543210
CAPRES
CAP12ENCAP3ENRESERVEDCAP3TSELCAP12TSELCAP3TOADCCAP1EDGECAP2EDGECAP3EDGERESERVED
CAPTURE CONTROL REGISTER B(CAPCON B)1514131211109876543210
CAPRES
CAP45ENCAP6ENRESERVEDCAP6TSELCAP45TSELCAP6TOADCCAP4EDGECAP5EDGECAP6EDGERESERVED
CAPTURE FIFO STATUS REGISTER A (CAPFIFO A)
1514131211109876543210
RESERVED
CAP3FIFOCAP2FIFOCAP1FIFORESERVED
CAPTURE FIFO STATUS REGISTER B (CAPFIFO B)1514131211109876543210
RESERVEDCAP6FIFOCAP5FIFOCAP4FIFORESERVED
EVA INTERRUPT FLAG REGISTER A
1514131211109876543210
RESERVED
T1OFINT
FLAGT1UFINT
FLAGT1CINT
FLAGT1PINT
FLAGRESERVEDCMP3INT
FLAGCMP2INT
FLAGCMP1INT
FLAGPDPINTA
FLAG
EVA INTERRUPT FLAG REGISTER B
1514131211109876543210
RESERVEDT2OFINT
FLAGT2UFINT
FLAGT2CINT
FLAGT2PINT
FLAG
EVA INTERRUPT FLAG REGISTER C
1514131211109876543210
RESERVEDCAP3INT
FLAGCAP2INT
FLAGCAP1INT
FLAG
EVA INTERRUPT MASK REGISTER A (EVAIMRA REGISTER)1514131211109876543210
RESERVEDT1OFINT
ENABLET1UFINT
ENABLET1CINT
ENABLET1PINT
ENABLERESERVEDCMP3INT
ENABLECMP2INT
ENABLECMP1INT
ENABLEPDPINTA
ENABLE
EVA INTERRUPT MASK REGISTER B (EVAIMRB REGISTER)1514131211109876543210
RESERVED
T2OFINT
ENABLET2UFINT
ENABLET2CINT
ENABLET2PINT
ENABLE
EVA INTERRUPT MASK REGISTER C (EVAIMRC REGISTER)1514131211109876543210
RESERVEDCAP3INT
ENABLECAP2INT
ENABLECAP1INT
ENABLE
EVB INTERRUPT FLAG REGISTER A
1514131211109876543210
RESERVEDT3OFINT
FLAGT3UFINT
FLAGT3CINT
FLAGT3PINT
FLAGRESERVEDCMP6INT
FLAGCMP5INT
FLAGCMP4INT
FLAGPDPINTBFLAG
EVB INTERRUPT FLAG REGISTER B
1514131211109876543210
RESERVEDT4OFINT
FLAGT4UFINT
FLAGT4CINT
FLAGT4PINT
FLAG
EVB INTERRUPT FLAG REGISTER C
1514131211109876543210
RESERVEDCAP6INT
FLAGCAP5INT
FLAGCAP4INT
FLAG
EVB INTERRUPT MASK REGISTER A
1514131211109876543210
RESERVED
T3OFINT
ENABLET3UFINT
ENABLET3CINT
ENABLET3PINT
ENABLERESERVEDCMP6INT
ENABLECMP5INT
ENABLECMP4INT
ENABLEPDPINTBENABLE
EVB INTERRUPT MASK REGISTER B
1514131211109876543210
RESERVEDT4OFINT
ENABLET4UFINT
ENABLET4CINT
ENABLET4PINT
ENABLE
EVB INTERRUPT MASK REGISTER C1514131211109876543210
RESERVEDCAP6INT
ENABLECAP5INT
ENABLECAP4INT
ENABLE
MAXIMUM CONVERSION CHANNELS REGISTER (MAXCONV)
1514131211109876543210
RESERVED
MAXCONV2_2MAXCONV2_1MAXCONV2_0MAXCONV1_3MAXCONV1_2MAXCONV1_1MAXCONV1_0
ADC CONTROL REGISTER (ADCTRL1)1514131211109876543210
RESERVEDRESETSOFTFREEACQPS3ACQPS2ACQPS1ACQPS0CPSCONTRUNINT PRISEQ CASCCAL ENABRG ENAHI / LOSTEST ENA
ADC CONTROL REGISTER (ADCTRL2)
1514131211109876543210
EVB SOC SEQRST SEQ1 / STRT CALSOC SEQ1SEQ1 BSYINT ENA SEQ1
(MODE 1)INT ENA SEQ1(MODE 0)INT FLAGSEQ1EVA SOC SEQ1EVA SOC SEQ1EXT SOC SEQ1RST SEQ2SEQ2 BSYINT ENA SEQ2 (MODE 0)INT ENA SEQ2 (MODE 0)INT FLAG SEQ2EVB SOC SEQ2
AUTOSEQUENCE STATUS REGISTER (AUTO_SEQ_SR)
1514131211109876543210
RESERVEDSEQ
CNTR3SEQ
CNTR2SEQ
CNTR1SEQ
CNTR0RESERVEDSEQ2-
STATE2SEQ2-
STATE1SEQ2-
STATE0SEQ1-
STATE3SEQ1-
STATE2SEQ1-
STATE1SEQ1-
STATE0
ADC INPUT CHANNEL SELECT SEQUENCING CONTROL REGISTER (CHSELSEQn) ( n=1,2,3,4 )CHSELSEQ1 REGISTER1514131211109876543210
CONV03CONV02CONV01CONV00
CHSELSEQ2 REGISTER1514131211109876543210
CONV07CONV06CONV05CONV04
CHSELSEQ3 REGISTER1514131211109876543210
CONV11CONV10CONV09CONV08
CHSELSEQ4 REGISTER1514131211109876543210
CONV15CONV14CONV13CONV12
EVENT MANAGER INTERRUPT REGISTERS , DEADBAND TIMER AND GP TIMER CONTROL REGISTERS
ADC REGISTERS CAPTURE UNIT CONTROL REGISTERS SPI & ITS INTERRUPT CONTROL REGISTERS
COMPARE UNIT CONTROL REGISTERS SCI & ITS INTERRUPTS CONTROL REGISTERS
PRIMARY/SECONDARY FUNCTION MULTIPLEXED PIN REGISTERS CAN CONTROL REGISTERS
