REFERENCE DESIGN IRDCiP2021C-1 - irf.com
Transcript of REFERENCE DESIGN IRDCiP2021C-1 - irf.com
International Rectifier 233 Kansas Street, El Segundo, CA 90245 USA
RREEFFEERREENNCCEE DDEESSIIGGNN IRDCiP2021C-1
IRDCiP2021C-1: 500kHz, 40A, Single Output, Dual Phase Synchronous Buck Converter Featuring iP2021C and IR3623M
Overview This reference design is capable of delivering a continuous current of 40A, single output without heatsink at an ambient temperature of 45ºC and airflow of 200LFM. Fig. 4 – Fig. 16 provide performance graphs, thermal images, and waveforms. Fig. 1 – Fig. 3 are provided to engineers as design references for implementing an IR3623+iP2021C solution.
The components installed on this demoboard were selected based on operation at an input voltage of 12V (+/-10%), a switching frequency of 500kHz (+/-15%), and an output voltage of 1.2V. Major changes from these set points may require optimizing the control loop and/or adjusting the values of input/output filters in order to meet the user’s specific application requirements. Refer to iP2021C and IR3623 datasheets for more information.
IRDCiP2021C-1 Recommended Operating Conditions (refer to the iP2021C datasheet for maximum operating conditions)
Input voltage: 8.5V – 14.5V
Output voltage: 0.8 – 5V
Switching Freq: 500kHz
Output current: This reference design is capable of delivering a continuous current of 40A without heatsink at an ambient temperature of 45ºC and airflow of 200LFM.
Demoboard Quick Start Guide Initial Settings: VOUT is set to 1.2V, but can be adjusted from 0.8V to 5V by changing the values of R11 and R15 according to the following formula:
R11 = R15 = (10k * 0.8) / (VOUT - 0.8)
The switching frequency is set to 500kHz, but can be adjusted by changing the value of R26. See Fig. 4 for the relationship between R26 and the switching frequency.
8/13/2009
IRDCiP2021C-1 Power Up Procedure: 1. Apply input voltage across VIN and PGND.
2. Apply load across VOUT pads and PGND pads.
3. Toggle the SEQ (SW1) and EN (SW2) switches to the ON position.
4. Adjust load to desired level. See recommendations above.
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IRDCiP2021C-1
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Demoboard Schematic
Fig. 1 Schematic
12
34
56
ABCD
65
43
21
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Size
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Date
:
Rev
isio
n:
Shee
tof
:
Time
:
Tabl
oid
C15
100u
FC
1710
uF
L1
0.22
uH L2
0.22
uH
R17
3.65
K
R18
3.65
K
C1
10uF
16V
C2
10uF
16V
C5
10uF
16V
C6
10uF
16V
C3
10uF
16V
C7
10uF
16V
T5 PGN
D
T3 VOU
T1
T1 VIN
TP3
+VO
UTS
1
TP4
-VOU
TS1
C4
10uF
16V
C8
10uF
16V
R22
open
C16
100u
FC
1810
uF
C14
680u
F
T2 PGN
D
TP1
+VIN
S1
TP2
VIN
C19
100u
F
C20
100u
F
C21
10uF
B1 BOAR
D
C54
1uF
T6 PGN
D
T4 VOU
T2
TP5
+VO
UTS
2
TP6
-VOU
TS2
C24
open
R12
open
R10
open
R16
0
R6
open
R26
78.7K
(500
kHz)
R14
open
C36
open
C42
open
C34
open
C33
0.1u
F
TP23
SYN
C
C31
1uF
C32
100p
F
R8
open
C38
open
C40
open
R11
20K
R9
10K
R15
20K
R5
11K
R13
10K
C35
5.6p
F
C41
100p
F
R7
200
C37
2700
pF
C39
390p
F
C23
open
C25
open
C26
open
C22
10uF
1.2V
1.2V
R4 0
R21
open
R19 0 R20 op
enPG
OO
D11
VREF
27
COM
P118
Ph_E
n115
RT
30
SYN
C23
SS1
17
SS2
8
PWM
114
VP1
25
TRAC
K122
VSEN
121
SEQ
24
OCS
ET1
16
ENAB
LE31
VCC
12
5V_SNS32FB
119
VOUT313
TRAC
K23
PGND 29
GND 28
PGO
OD2
2
VP2
26
COM
P27
Ph_E
n210
PWM
211
VSEN
24
OCS
ET2
9
FB2
6
OCGnd 20
FAU
LT5
PGND 0
U3
IRU3
623M
TP18
TRAC
K2
TP17
TRAC
K1 TP24
FAU
LT
C28
open
C30
open
R1
10K R2
10KR3 0
R25
30.1K
R23
10K
R24
10K
TP15
PGO
OD1
TP16
PGO
OD2
C27
open
C29
open
TRK2
TRK1
SEQ
SYN
C
PGD
1
PGD
2
VREF
EN SS1
SS2
RT
FLT
FB1
FB2
VSEN
1
CC1
CC2
OC1
OC2
EN1
EN2
PWM
1
PWM
2
VSW
1
VSW
2
VSEN
2
VIN
VOU
T3
VOU
T3
VOU
T1
VOU
T1
VOU
T2
VIN
VOU
T3
VOU
T3
C13
0.1u
FC
431u
F
R28
0
R33
10K
VOU
T3
R35 0
R27
0
R34
10K
PH_E
N1
PH_E
N2
C51
100p
F
C52
100p
F
R36
open
VP2
R45
open
R29
1.62
KC
490.
47uF
R39 0
VP2
R30
1.62
KC
500.
47uF
R40 0
FB2
R46
9.31
KC
5710
00pF
R47
open
R44 0
R43 0
R42 0
R41 0
VOU
T1
VOU
T2
C45 1uF
C53
1uF
R31
0
R32
0
PWM
1_IC
VCC
VDD
VDD
PWM
2_IC
TP10
EN2
TP12
PWM
2
TP9
EN1
TP11
PWM
1
TP21
VSW
1 TP22
VSW
2
TP13
SS1
TP14
SS2
TP7
VDD
TP8
PGN
D
TP19
CC1
TP20
CC2
TP25
FB1
TP26
FB2
TP27
+VIN
S2
TP28
PGN
D
C55
open
C56
open
SW1
ENSW
2SE
Q
TP29
VO1A
TP30
VO1B
TP31
VO2A
TP32
VO2B
TP35
VOU
T1
TP33
PGN
D
TP36
VOU
T2
TP34
PGN
D
TP37
PGN
DTP
38PG
ND
VOS1
-
VOS2
-
-VOU
TS1
-VOU
TS2
T7 PGN
D
T9 PGN
D
VIN12
ENA1
11
PWM
15
CVCC4
VIN11
VIN29 PGND 7
VSW
12
ENA2
10
PWM
26
PGND 3
VSW
28
U1
iP20
21
OC1
VIN
C9
10uF
16V
C10
10uF
16V
C11
10uF
16V
C12
10uF
16V
1 2
C44
open
1 2
C46
220u
F
1 2
C47
open
1 2
C48
open
VOU
T1
1 2
C58
open
1 2
C59
220u
F
1 2
C60
open
1 2
C61
open
VOU
T2
R37
open
R38 0 R48
open
R49 0
VOS1
+
VOS1
D+
VOS1
D-
VOS1
S+
VOS1
S-
C62
1uF
59.0K
(600
kHz)
16.2K
(1M
Hz)
IRDCiP2021C-1 Bill of Material
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paci
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elec
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680u
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Pan
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28,
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29,
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test
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x 15
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Key
ston
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16
20
TP
9, T
P10
, T
P11
, T
P12
, T
P13
, T
P14
, T
P15
, T
P16
, T
P17
, T
P18
, T
P19
, T
P20
, T
P21
, T
P22
, T
P23
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P24
, T
P25
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tre
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FIR
3623
M
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IRDCiP2021C-1
Demoboard Component Placement
Fig. 2 Top Layer (Face View)
Fig. 3 Bottom Layer (Through View)
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IRDCiP2021C-1 Description of Test Points and Connectors
1. Jumpers
Jumper Pin Name Description
SW1 EN Board Enable ( switch Up = On ) - Vin pin on top Off, Down =
SW2 SEQ Sequence ( switch Up = Off, Down = On ) - Vin pin on top
2. Points ctors Test /Conne
Test Point Pin Name Description
T1 / T2 VIN / P Vin supply voltage GND
T ense P2 / TP28 VIN / PGND Vin supply voltage s
T3 / T5 / T7 VOUT1 / PGND / PGND to DC load Channel 1 Output, connect
TP35 / TP33 VOUT1 / PGND Channel 1 Output sense
TP21 / TP37 VSW1 / PGND Channel 1 switch node / PGND test points
TP9 EN1 Channel 1 Enable test point
TP11 PWM1 Channel 1 PWM test point
TP19 CC1 Channel 1 error amplifier output
TP25 FB1 Channel 1 error amplifier non-inverting input
T4 T2 / PGND / PGND / T6 / T9 VOU Channel 2 Output, connect to DC load
TP36 / TP34 VOUT2 / PGND Channel 2 Output sense
TP22 / TP38 VSW2 / PGND Channel 2 switch node / PGND test points
TP10 EN2 Channel 2 Enable test point
TP12 PWM2 Channel 2 PWM test point
TP20 CC2 Channel 2 error amplifier output
TP26 FB2 Channel 2 error amplifier non-inverting input
TP7 / TP8 / PGND le VDD Supply voltage for IRU3623 and iPOWIR modu
TP23 SYNC External frequency synchronization input
TP17 TRACK1 if not used Channel 1 tracking input, pull-up to Vout3
TP18 TRACK2 Track2 test point
TP15 PGOOD1 Channel 1 Power good test point
TP16 PGOOD2 Channel 2 Power good test point
TP13 SS1 Channel 1 Soft start test point
TP14 SS2 Channel 2 Soft start test point
TP24 FAULT Fault monitor test point
3. points ement Test for Efficiency Measur
Test Point Pin Name Description
TP1 / TP4 +VINS 1 Channel 1 Vin sense for eff rement 1 / -VOUTS iciency measu
TP3 / TP4 +VOUTS1 / -VOUTS1 nt Channel 1 Output sense for efficiency measureme
TP27 / TP6 +VINS2 / -VOUTS2 Channel 2 Vin sense for efficiency measurement
TP5 / TP6 +VOUTS2 / -VOUTS2 nt Channel 2 Output sense for efficiency measureme
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IRDCiP2021C-1
Test Results
Fig. 4 Relationship Between Switching Frequency and R2
6
Fig. 5 Power Up Sequence (C3: EN, C1: SS1, C4: VOUT)
Fig. 6 Power Down Sequence (C3: EN, C1: SS1, C4: VOUT)
VIN = 12V, VOUT = 1.2V, Iout = 40A, fsw = 500 kHz
VIN = 12V, VOUT = 1.2V, Iout = 40A, fsw = 500 kHz
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IRDCiP2021C-1
g. 7 Hiccup Mode Over Current Protection (C1: SS1, C4: Iout, C3: VOUT)
VIN = 12V, VOUT = 1.2V, fsw = 500 kHz
Fi
Fi
g. 8 Hiccup Mode Over Current Protection (C1: SS1, C4: Iout, C3: VOUT)
VIN = 12V, VOUT = 1.2V, fsw = 500 kHz
Fig. 9 Deadtime and Ringing on Switch Node
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IRDCiP2021C-1
Fig. 2)
Fig. 10 Output Voltage DC Ripple
Vp-p = 20 mV
out sw
Fig. 11 Output Voltage DC Ripple
12 Load Transient Response (C1: VOUT – AC, C2: Iout divided by
VIN = 12V, VOUT = 1.2V, I = 20A, f = 500 kHz
VIN = 12V, VOUT = 1.2V, Iout = 20A, fsw = 500 kHz
VIN = 12V, VOUT = 1.2V, Iout = 0-40A, 0.5A/µs, Hfsw = 500 k z
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IRDCiP2021C-1
Fig. 13 Bode Plot (VIN = 12V, VOUT = 1.2V, Iout = 20A) Current Sharing Accuracy The accuracy of current sharing is tested by measuring the DC voltage across the two inductors at the following operating conditions: VIN = 12V; VOUT = 1.2V; Iout = 10 – 40A. The test results are shown below:
Table 1 Inductor DC Voltages at Different Currents for Single Output Configuration
Iout (A) VL1 (mV) VL2 (mV)
fc = 65 kHz PM = 49
10 1.5 1.9 20 3.4 3.8 30 5.5 5.8 40 7.5 7.9
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IRDCiP2021C-1
VIN = 12V, VOUT = 1.2V, 200LFM, fsw = 500kHz, No Heatsink
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 5 10 15 20 25 30 35 40
Load Current (A)
Po
wer
Lo
ss (
W)
45CRoom Temperature
Fig. 14 Power Loss
VIN = 12V, VOUT = 1.2V, 200LFM, fsw = 500kHz, No Heatsink
72%
74%
76%
78%
80%
82%
84%
86%
88%
90%
92%
0 5 10 15 20 25 30 35 40
Load Current (A)
Eff
icie
ncy
45C
Room Temperature
Fig. 15 Efficiency
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IRDCiP2021C-1
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IRDCiP2021C-1
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Fig. 16 Thermal Image: Iout = 40A, VIN = 12V, VOUT = 1.2V, TA = 45oC, fsw = 500kHz, 200LFM, No Heatsink, Maximum IC Temperature = 94.2oC
Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR Technology products: AN-1043: Stabilize the Buck Converter with Transconductance Amplifier This paper explains how to design the voltage compensation network for Buck Converters with Transconductance Amplifier. The design methods and equations for Type II and Type III compensation are given. AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s iPowIR Technology BGA and LGA and Packages This paper discusses optimization of the layout design for mounting iPowIR BGA and LGA packages on printed circuit boards, accounting for thermal and electrical performance and assembly considerations. Topics discussed include PCB layout placement, and via interconnect suggestions, as well as soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1047: Graphical solution for two branch heatsinking Safe Operating Area Detailed explanation of the dual axis SOA graph and how it is derived. Use of this design for any application should be fully verified by the customer. Internation l Rectifier cannot guarantee suitability for your applications, and is not liable for any result of usage for such applications including, without limitation, erty damage or violation of third party intellectual property rights. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
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