Rectifier applications handbook - Educypedia

HB214/DRev. 2, Nov-2001

Rectifier ApplicationsHandbook

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800-282-9855 Toll Free USA/Canada

JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: [email protected]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local Sales Representative

PUBLICATION ORDERING INFORMATION

Rectifier Applications Handbook

Reference Manual and Design Guide

HB214/DRev. 2, Nov–2001

SCILLC, 2001Previous Edition 1997“All Rights Reserved’’

COVER ARTThe NCP1200 10 W AC/DC Power Supply Demo Board featuring the MBRS360T3 and MUR160 Rectifiers. For more information, pleasesee Appendix B on page 259.

Rectifier Applications

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Acknowledgments

Technical Editor William D. Roehr, Staff Consultant

ContributionsSamuel J. Anderson Rex Ivins William C. RomanDon Baker Nick Lycoudes Howard Russell, Jr.Kim Gauen Michael Pecht Aristide TintikakisDavid Hollander William D. Roehr

Cho–Therm is a registered trademark of Chromerics, Inc.Grafoil is a registered trademark of Union Carbide.Kapton is a registered trademark of du Pont de Nemours & Co., Inc.Kon Dux is a trademark of Aavid Thermal Technologies, Inc.POWERTAP, SCANSWITCH, MEGAHERTZ, Surmetic, and SWITCHMODE are trademarks of Semiconductor Components Industries,LLC (SCILLC).Sync–Nut is a trademark of ITW Shakeproof.Thermalsil is a registered trademark and Thermalfilm is a trademark of Thermalloy, Inc.Thermal Clad is a trademark of the Bergquist Company.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATIONJAPAN: ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031Phone: 81–3–5740–2700Email: [email protected]


For additional information, please contact your localSales Representative.

Literature Fulfillment:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303–675–2175 or 800–344–3860 Toll Free USA/CanadaFax: 303–675–2176 or 800–344–3867 Toll Free USA/CanadaEmail: [email protected]

N. American Technical Support: 800–282–9855 Toll Free USA/Canada


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Table of Contents

Page

Chapter 1. Power Rectifier Device Physicsand Electrical Characteristics

Formation of Energy Bands 9. . . . . . . . . . . . . . . . . . . . . . . . Doping of Semiconductors 12. . . . . . . . . . . . . . . . . . . . . . . . The Electrical Resistivity and Conductivityof Silicon and Gallium Arsenide 13. . . . . . . . . . . . . . . . . . .

The Fermi Level Concept 15. . . . . . . . . . . . . . . . . . . . . . . . . Surface Properties of Semiconductors 15. . . . . . . . . . . . . . Semiconductor Junctions 17. . . . . . . . . . . . . . . . . . . . . . . . .

pn Junctions 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Bias 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Bias 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metal Semiconductor Junctions 19. . . . . . . . . . . . . . . . . Forward Bias (VA>0) and Reverser Bias (VA<0) 20. . .

Real Diode Characteristics 22. . . . . . . . . . . . . . . . . . . . . . . . Forward Bias 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Bias 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakdown Voltage 24. . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Switching 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . Silicon Temperature Coefficient Formula forForward Voltage 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Design Tradeoffs 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2. Basic Thermal Properties of Semiconductors

Thermal Models 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case–Mounted Rectifiers 33. . . . . . . . . . . . . . . . . . . . . . Lead–Mounted Parts 34. . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Chip Devices 36. . . . . . . . . . . . . . . . . . . . . . . . .

Transient Response of Semiconductors 38. . . . . . . . . . . . Thermal Response 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . Use of Thermal Response Data 40. . . . . . . . . . . . . . . . . Handling Nonretangular Pulses 41. . . . . . . . . . . . . . . . . Example Peak Temperature Calculations 43. . . . . . . . .

Thermal Runaway 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3. The SPICE Diode ModelIntroduction 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The SPICE Diode Model 49. . . . . . . . . . . . . . . . . . . . . . . . .

The Large–Signal DC Model 49. . . . . . . . . . . . . . . . . . . The Small–Signal AC Model 50. . . . . . . . . . . . . . . . . . . . Temperature and Area Effects 51. . . . . . . . . . . . . . . . . . The Noise Model 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Diode Model versus a Real Diode 53. . . . . . . . . . . . . SPICE Diode Model ParameterLimitations and Restrictions 55. . . . . . . . . . . . . . . . . . . . . .

Chapter 3. continued PageSPICE Diode Model Parameter Extraction Methods 56. .

Forward CD Characteristics (IS, RS, N) 56. . . . . . . . . . Junction Capacitance Characteristics (CEO, VJ, M, FC) 58. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reverse Recovery Time Characteristics (TT) 59. . . . . Temperature Characteristics (EG, XTI) 61. . . . . . . . . . . Reverse Breakdown Characteristics (BV, IBV) 62. . . .

Example Parameter Extractions for theMURHB4OCT Diode 62. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Forward DC Characteristics (IS, RS, N) 63. . . . . . . . . . Junction Capacitance Characteristics(CJO, VJ, M, FC) 67. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reverse Recover Time Characteristics (TT) 69. . . . . . Temperature Characteristics (EG, XTI) 69. . . . . . . . . . . Reverse Breakdown Characteristics (BV, IBV) 70. . . .

Summary 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 4. Rectifier Diode Specificationsand Ratings

Temperature 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Ratings 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak Repetitive Reverse Voltage (VRRM) 77. . . . . . . . . Peak Working Reverse Voltage (VRWM) 77. . . . . . . . . . DC Reverse Blocking Voltage (VR) 77. . . . . . . . . . . . . . Peak Nonrepetitive Reverse Voltage (VRSM) 77. . . . . .

Reverse Current 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum or Peak Reverse current (IRRM) 78. . . . . . . . Average Reverse Current IR(AV) 78. . . . . . . . . . . . . . . . . DC Reverse Current (IR) 78. . . . . . . . . . . . . . . . . . . . . . .

Reverse Breakdown Voltage V(BR) 78. . . . . . . . . . . . . . . . . Forward Voltage 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum (Peak) Forward Voltage (VFM) 79. . . . . . . . . Average Forward Voltage (VF(AV)) 79. . . . . . . . . . . . . . . DC Forward Voltage (VF) 79. . . . . . . . . . . . . . . . . . . . . .

Forward Power Dissipation 79. . . . . . . . . . . . . . . . . . . . . . . Current Ratings 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Average Forward Current (IO) 82. . . . . . . . . . . . . . . . . . Peak Surge Forward Current (IFSM) 83. . . . . . . . . . . .

Switching 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Recovery 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Recovery 85. . . . . . . . . . . . . . . . . . . . . . . . . . . .

References 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 5. Basic Single–PhaseRectifying Circuits

Basic Operation 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Relationships 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . Form Factor 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Utilization Factor 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Harmonics 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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Chapter 5. continued PageRipple Factor 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rectification Ratios 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Relationships 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Variations 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 6. Polyphase Rectifier CircuitsGeneral Relationships in Polyphase Rectifiers 101. . . . . .

Current Relationships 101. . . . . . . . . . . . . . . . . . . . . . . . Voltage Relationships 102. . . . . . . . . . . . . . . . . . . . . . . . Transformer Utilization 102. . . . . . . . . . . . . . . . . . . . . . . Ripple 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rectification Ratio 103. . . . . . . . . . . . . . . . . . . . . . . . . . . Overlap 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Common Polyphase Rectifier Circuits 103. . . . . . . . . . . . . Three–Phase Half–Wave Star Rectifier Circuit 103. . . Three–Phase Inter–Star Rectifier Circuit 104. . . . . . . . Three Phase Full–Wave Bridge Circuit 105. . . . . . . . . . Three–Phase Double–Wye Rectifier withInterphase Transformer 105. . . . . . . . . . . . . . . . . . . . . .

Six–Phase Star Rectifier Circuit 107. . . . . . . . . . . . . . . . . Six–Phase Full–Wave Bridge Circuits 106. . . . . . . . . . .

Comparison of Circuits 107. . . . . . . . . . . . . . . . . . . . . . . . . . High–Current Parallel–Connected Diodes 107. . . . . . . . . . References 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 7. Rectifier Filter SystemsBehavior of Rectifiers with Choke–Input Filters 111. . . . . .

Input Inductance Requirements 114. . . . . . . . . . . . . . . . Voltage Regulation in Choke Input Systems 115. . . . .

Behavior of Rectifiers Used withCapacitor–Input Filters 116. . . . . . . . . . . . . . . . . . . . . . . . . .

Analysis of Rectifiers withCapacitor–Input Systems 116. . . . . . . . . . . . . . . . . . . . .

Design of Capacitor–Input Filters 117. . . . . . . . . . . . . . Diode Peak Inverse Voltage 120. . . . . . . . . . . . . . . . . . . . . . Transformer Considerations 121. . . . . . . . . . . . . . . . . . . . . Harmonics 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Surge Current 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of Capacitor–Input and Inductance–Input Systems 122. . . . . . . . . . . . . . . . . . . . . .

Filter Sections 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage and Current Relations in Filters 123. . . . . . . . . Graded Filters 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter Component Selection 125. . . . . . . . . . . . . . . . . . . Example of Power Supply Design 126. . . . . . . . . . . . . . Passive Component Selection 126. . . . . . . . . . . . . . . . . Transformer Selection 127. . . . . . . . . . . . . . . . . . . . . . . . Diode Selection 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

References 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 8. Rectifier VoltageMultiplier Circuits

Voltage–Doubling Circuits 131. . . . . . . . . . . . . . . . . . . . . . . “Universal” Input Circuit 134. . . . . . . . . . . . . . . . . . . . . . . . . Voltage Tripling Circuits 135. . . . . . . . . . . . . . . . . . . . . . . . . Voltage Quadruples 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . High–Order Cascade Voltage Multipliers 137. . . . . . . . . . . References 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 9. Transient Protection ofRectifier Diodes

Externally Generated Voltage Surges 141. . . . . . . . . . . . . Internally Generated Voltage Surges 145. . . . . . . . . . . . . . Surge Protection Circuits 146. . . . . . . . . . . . . . . . . . . . . . . . Surge Current Protection 148. . . . . . . . . . . . . . . . . . . . . . . . Fusing Considerations 148. . . . . . . . . . . . . . . . . . . . . . . . . . References 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 10. Basic Diode Functions in Power Electronics

Rectification, Discontinuous Mode 156. . . . . . . . . . . . . . . . Catching 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clipping 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clamping 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Freewheeling 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rectification, Continuous Mode 163. . . . . . . . . . . . . . . . . . . Forced Commutation Analysis 164. . . . . . . . . . . . . . . . . . . . Practical Drive Circuit Problems 167. . . . . . . . . . . . . . . . . . Layout Considerations 168. . . . . . . . . . . . . . . . . . . . . . . . . . The Diode Snubber 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . References 171. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 11. Power Electronic CircuitsDrive Circuits for Power MOSFETs 175. . . . . . . . . . . . . . . . Drive Circuits for Bipolar Power Transistors 175. . . . . . . .

Baker Clamp 175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed Drive Circuit 177. . . . . . . . . . . . . . . . . . . . . . . . . . . Proportional Drive Circuit 178. . . . . . . . . . . . . . . . . . . . .

Transistor Snubber Circuits 179. . . . . . . . . . . . . . . . . . . . . . Power Circuit Load Lines 179. . . . . . . . . . . . . . . . . . . . . Turn–On Snubbers 180. . . . . . . . . . . . . . . . . . . . . . . . . . . Turn–Off Snubbers 182. . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Snubbers 183. . . . . . . . . . . . . . . . . . . . . . . . Snubber Diode Requirements 184. . . . . . . . . . . . . . . . .

Power Conversion Circuits 184. . . . . . . . . . . . . . . . . . . . . . . Flyback Converter 185. . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Converter 187. . . . . . . . . . . . . . . . . . . . . . . . . . . Push–Pull DC–DC Converters 187. . . . . . . . . . . . . . . . . Off–Line AC–DC Converters 191. . . . . . . . . . . . . . . . . . Synchronous Rectification 192. . . . . . . . . . . . . . . . . . . .

References 192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General References 194. . . . . . . . . . . . . . . . . . . . . . . . . . . .


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Chapter 12. Reliability ConsiderationsConcepts 197. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design for Reliability 198. . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Architecture and Device Specification 198. . . Stress Analysis 198. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Derating 198. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stress Screening 198. . . . . . . . . . . . . . . . . . . . . . . . . . . . Failure Modes, Effects andCriticality Analysis (FMECA) 199. . . . . . . . . . . . . . . . . .

Failure Data Collections and Analysis 199. . . . . . . . . . . Practical Aspects of Semiconductor Reliability 199. . . . . .

Electrical Overstress 199. . . . . . . . . . . . . . . . . . . . . . . . . Second Breakdown 199. . . . . . . . . . . . . . . . . . . . . . . . . . Ionic Contamination 200. . . . . . . . . . . . . . . . . . . . . . . . . . Electromigration 200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hillock Formation 200. . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Spiking 201. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metallization Migration 201. . . . . . . . . . . . . . . . . . . . . . . . Corrosion of Metallization and Bond Pads 201. . . . . . . Stress Corrosion in Packages 201. . . . . . . . . . . . . . . . . Wire Fatigue 202. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wire Bond Fatigue 202. . . . . . . . . . . . . . . . . . . . . . . . . . . Die Fracture 202. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Die Adhesion Fatigue 202. . . . . . . . . . . . . . . . . . . . . . . . Cracking in Plastic Packages 203. . . . . . . . . . . . . . . . . .

Design for Reliability 203. . . . . . . . . . . . . . . . . . . . . . . . . . . . Reliability Testing 204. . . . . . . . . . . . . . . . . . . . . . . . . . . . High–Temperature Operating Life 204. . . . . . . . . . . . . . Temperature Cycle 204. . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Shock 204. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature/Humidity Bias (THB) 205. . . . . . . . . . . . . . Autoclave 205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pressure/Temperature/Humidity Bias 205. . . . . . . . . . . Cycled Temperature Humidity Bias 205. . . . . . . . . . . . . Power Temperature Cycling 205. . . . . . . . . . . . . . . . . . . Power Cycling 205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low–Temperature Operating Life 205. . . . . . . . . . . . . . . Mechanical Shock 205. . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Acceleration 205. . . . . . . . . . . . . . . . . . . . . . . . Solder Heat 206. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead Integrity 206. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Solderability 206. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variable Frequency Vibration 206. . . . . . . . . . . . . . . . . .

Statistical Process Control 206. . . . . . . . . . . . . . . . . . . . . . . Process Capability 207. . . . . . . . . . . . . . . . . . . . . . . . . . . SPC Implementation and Use 208. . . . . . . . . . . . . . . . .

Chapter 13. Cooling PrinciplesThermal Resistance Concepts 211. . . . . . . . . . . . . . . . . . . Conduction 212. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Convection 212. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Natural Convection 213. . . . . . . . . . . . . . . . . . . . . . . . . . Forced Convection 214. . . . . . . . . . . . . . . . . . . . . . . . . . .

Radiation 214. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 13. continued Page

Fin Efficiency 216. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application and Characteristics of Heatsinks 218. . . . . . .

Heatsinks for Free Convection Cooling 218. . . . . . . . . Heatsinks for Forced Air Cooling 220. . . . . . . . . . . . . . . Fan Laws 221. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Liquid Cooling 221. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Component Placement 222. . . . . . . . . . . . . . . . . . . . . . . . . . References 222. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 14. Assembly Considerations for Printed Circuit Boards

Insertion Mounting 225. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Surface–Mount Technology 226. . . . . . . . . . . . . . . . . . . . . .

Surface–Mount Rectifier Packages 228. . . . . . . . . . . . . Thermal Management of Surface–Mount Rectifiers 229. . . . . . . . . . . . . . . . . . . .

Board Materials 230. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Surface–Mount Assembly 234. . . . . . . . . . . . . . . . . . . . . Flux and Post Solder Cleaning 236. . . . . . . . . . . . . . . . . Semiaqueous Cleaning Process 237. . . . . . . . . . . . . . .

Chapter 15. Heatsink Mounting Considerations

Mounting Surface Preparation 241. . . . . . . . . . . . . . . . . . . . Surface Flatness 241. . . . . . . . . . . . . . . . . . . . . . . . . . . . Surface Finish 241. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mounting Holes 242. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Surface Treatment 242. . . . . . . . . . . . . . . . . . . . . . . . . . .

Interface Decisions 243. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Compounds (Grease) 243. . . . . . . . . . . . . . . . Conductive Pads 244. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Insulation Considerations 244. . . . . . . . . . . . . . . . . . . . . . . . Insulation Resistance 247. . . . . . . . . . . . . . . . . . . . . . . . .

Insulated Electrode Packages 247. . . . . . . . . . . . . . . . . . . . Fastener and Hardware Characteristics 247. . . . . . . . . . .

Compression Hardware 247. . . . . . . . . . . . . . . . . . . . . . . Clips 248. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Machine Screws 248. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self–Tapping Screws 248. . . . . . . . . . . . . . . . . . . . . . . . . Rivets 248. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adhesives 248. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Plastic Hardware 248. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fastening Techniques 249. . . . . . . . . . . . . . . . . . . . . . . . . . . Stud Mount 249. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Press Fit 249. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flange Mount 249. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tab Mount 250. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

References 253. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A 257. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix B 259. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index 265. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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Chapter 1

Power Rectifier Device Physics andElectrical Characteristics


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The physics of power rectifiers is different in manyaspects from that of their low–power counterparts. Thereason for this is that power rectifiers must process powerwith a minimum power loss with operating conditions oftencovering a wide range of blocking voltages, currentdensities, and frequencies.

The ability to handle forward currents from 1 A to 600 A.block voltages up to 100 V, and exhibit excellent switchingbehavior at frequencies up to 1 MHz are the uniqueperformance features of today’s silicon Schottky rectifiertechnology Silicon bipolar junction rectifiers can blockvoltages up to 1500 V and have current capability up to 190A. However, in switching applications silicon bipolarjunction rectifiers require minority barrier life–timereduction to perform the switching behavior at the speedsnecessary for switching operations These devices havehigher conduction losses than slower standard andfast–recovery bipolar junction rectifiers and are selectedwhen switching loss dominates.

Circuit designers need low–loss, power rectifiers both inconduction mode and dynamic mode operations, especiallyin high–frequency applications In this domain silicon–basedtechnology is rapidly approaching its performance limit andthe current industry demand for low–loss diodes is drivingthe quest for new semiconductor materials such as galliumarsenide Schottky devices for improved performance.

To provide the necessary background for selecting andusing power rectifiers, this first chapter presents a review ofbasic semiconductor physics covering energy bands, surfaceproperties. doping. conductivity, p–n junction and m–sjunction theory. From this, the diode equations for idealbipolar p–n junctions and majority carrier m–s junctions aredeveloped. Next, properties of real diodes are shown;finally, possible tradeoffs in performance characteristics aresummarized.

Formation of Energy BandsNiels Bohr provided a model of the hydrogen atom in

which a single electron orbits the nucleus and is held in orbitdue to the attraction of a proton in the nucleus of the atom.Bohr added a rule of quantization to postulate that a discreteset of orbits exists from the continuum of possible orbits andthis explains the discrete energy levels needed to describethe line spectrum of atomic hydrogen.

If we visualize the electron in a stable orbit of radius rabout a proton of the hydrogen atom, we can equate theelectrostatic force between the charges to the centripetalforce, as shown in Figure 1.

Figure 1. Bohr Hydrogen Atom Model

r

+q

–q

–q2

4, , or2 mv2

r (1.1)

where:m = mass of the electronv = velocity of the electronSince the electron is confined to the vicinity of the nucleus

bound by a coulombic force, Bohr demonstrated that thepossible electron energies are quantized. Hence, the energystates of the electron in the hydrogen atom are given by:

En–moq4

8h22 1

n2(1.2)

where:mo is the electron mass and h is Planck’s constant.Materials used in semiconductor technology can be

described in terms of energy levels that electrons in an atomcan occupy. For the purpose of this chapter, we will focus onenergy levels theory. For a single crystal atom, the energylevel perspective can be considered in terms of an orbitalplan and an energy well plan. Both of these are shown infigure 2 for the silicon atom. Since intrinsic silicon has avalence of four and forms covalent bonds with fourneighboring silicon atoms when more than one atom ispresent, energy levels combine as the atoms are joined.

As the silicon crystal is formed, the interatomic spacingis reduced and electron conduction bands arc formed bybringing together isolated silicon atoms. Figure 3(a) showsthe formation of energy bands as the atomic separation isreduced during crystal formation. At absolute temperature0K every state in the valence band will be filled, while theconduction band will be completely empty of electrons.The arrangement of completely filled and empty energybands has an important effect on the electrical conductivity


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of a solid. Every solid has its own characteristic energy bandstructure. The primary difference between an intrinsicsemiconductor, an insulator, and a good conductor is the sizeof the energy bandgap. Silicon has a bandgap of 1.1 eV,compared to 8 eV for an oxide insulator. The relatively smallbandgap of silicon allows excitation of electrons from thelower valence band shown in Figure 3(b) to the upperconduction band by a reasonable amount of thermal oroptical excitation energy. This is why silicon is asemiconductor. In metals the valence and conduction bandsoverlap so that electrons can move freely, resulting in highelectrical conductivity.

The energy band diagram of intrinsic silicon is shown inFigure 4. The intrinsic silicon valence band is completelyfilled with valence electrons at absolute zero and no currentcan flow. But at any temperature above: absolute zero, asmall number of electrons possess enough thermal energy tobe excited to the conduction band. For every electron excitedto the conduction band, a hole is created in the valence band.The intrinsic concentration of holes and electrons isrelatively small for silicon at room temperature.

Figure 2. Orbital and Energy Well View of Electrons in Silicon

Energy Well Plan

Nucleus

IncreasingEnergy

Inner Orbital Levels

Excitation Level

Nucleus

Inner Orbits

Valence Electrons (4)

Valence Orbits

Excitation Orbit

Orbital Electrons

Hole

Free Electron

Valence Levels

Orbital Plan

14

13

12

11

10

9

8

7

6

5

4 3

2

1



Figure 3. (a) Energy Band Versus Atomic Separation Relationship; (b) Energy Band Gap of Insulators, Semiconductors, and Conductors

Conduction Band Carbon atoms6 electrons/atom

atomselectronsN6

N

“2 p”

E

states6N

states2N

2 p

2 s

states2N

states4N

states4N

Valence Band

“2 s”

“2 s – 2p”

g

1 s

Atomic Separation

DiamondLatticeSpacing

Ene

rgy

a) INSULATOR b) SEMICONDUCTOR c) CONDUCTOR

(a)

(b)

VALENCE BAND

BAND GAP BAND GAP

CONDUCTION BAND CONDUCTION BAND CONDUCTION BAND

VALENCE BAND VALENCE BAND

“1 s”

However, the intrinsic concentration doubles every 10C and is defined by Equation 1.3.In intrinsic silicon, the number of conduction electrons, n, equals the number of holes, p, or

n p ni 3.9 1016T 32 exp EGkT cm 3

(1.3)where:

n = electron concentration, cm–3

p = hole concentration, cm–3

ni = the intrinsic carrier concentration /cm3

T = temperature, KEG = bandgap, eVk = Boltzman’s constantat T = 00

At 25C ni for intrinsic silicon is:ni = 1.5 X 1010 carriers/cm3

whereas:ni = 1.8 X 106 carriers/cm3 for GaAs.



Figure 4. Energy Band Diagram for Intrinsic Silicon

Ev

Ec

Hole Forbidden Band

Valence Band

Conduction Band

ElectronEnergyEnergy

EIEg = 1.1 eV

Doping of SemiconductorsSemiconductor materials have no practical application in

their intrinsic form. To obtain useful semiconductor devices,controlled amounts of dopant atoms arc introduced into thecrystal. When dopant atoms are added, energy levels arecreated near the conduction band for n–type semiconductorsand near the valence band for p–type semiconductors. Theband diagrams for n–type and p–type semiconductors areshown in Figure 5.

The addition of dopant atoms increases either the electronor hole concentration of the host silicon crystal. Commonsilicon dopants are listed in Table 1.

The result of doping is a change in the electricalconductivity of the crystal. If pentavalent elements such asantimony, phosphorus or arsenic are introduced into thesilicon crystal, atoms will be displaced by the impurity

atoms as illustrated in Figure 6(a). Four electrons of theimpurity atom form covalent bonds with four surroundingatoms and the fifth electron is free to act as a carrier. Thepentavalent impurity is called a donor because it gives upelectrons and the material is said to be n–type because it isnegatively charged with free electrons and donates electronsto the conduction band.

Table 1. Common Silicon Dopants

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Electron–IncreasingDopants (Donors)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Hole–Increasing Dopants(Acceptors)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

P ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

B


As Column V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ga Column III


Sb Elements ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

In ElementsAl

Figure 5. Band Diagram for n–type and p–type Semiconductors

EI EI

+ + + + + + + + + + + +Donor Ions

Valence BandHoles in Valence band

Conduction Band

Acceptor Ions

Electrons in Conduction Band

–typen –typep



Figure 6. Impurity Atoms in (a) n–type Silicon; (b) p–type Silicon

Si

Si

Si

Si

Si Si

+ +Applied field Applied field

Si

Si

Si

Si

Si Si

BP+

Locked covalentbond electrons

Free electronfrom phosphorousatom drifts towardapplied positivepole

Incompletedcovalent bond

This electron jumpsinto hole left by boronatom. Hole position isdisplaced to right.This results in a driftof holes toward thenegative pole, givingthem the characterof mobile charges.

b) p–type Silicona) n–type Silicon

If a trivalent impurity atom such as boron, gallium,indium, or aluminum is added to the semiconductor, theelectrons surrounding the impurity atom cannot form astable set of locked covalent bonds The tri–electronstructure of the impurity atom causes one incomplete bondas shown in Figure 6(b). The result is a positively chargedmaterial. The trivalent impurity is called an acceptorimpurity because it accepts electrons from the valence bandand forms holes in the valence band.

When donors are added to silicon, there is a largernumber of conduction electrons or holes, respectively. Itcan be shown mathematically that

n2 n p N N 2 1020 cm6 at 26C

(1.4)i D A

where:ND is the doping concentration per cubic centimeter for

donors and NA is the acceptor doping concentration percubic centimeter.

Therefore, if n or p is known, the other carrierconcentration can be readily found.

The Electrical Resistivity andConductivity of Silicon andGallium Arsenide

Conduction of electricity through bulk silicon or galliumarsenide is by majority carriers Resistivity is the inverse ofconductivity For n–type material it is given by:

n nqn (1.5)

where:σn = conductivity (Ω–cm)–1

n = electron concentration, cm–3

q = electron chargeµn = electron mobility, cm2/V–S

Pn is 1 n1

nqn resistivity (1.6)

The mobility described above is the proportionalityconstant between the applied electric field (ε) and theresultant carrier drift velocity (Vd) for bulk carrier transportwhere:

nVd (obeys Ohms law)

(1.7)

Figure 7 shows bulk carrier mobility as a function ofdoping concentration for both electrons and holes.

Drift velocity is determined by the mean free time (Tf)between collisions within the crystal lattice, this being thetime they are accelerated in the direction of the field. UsingNewton’s law of motion, the drift velocity is given by:

VdqTf2m *

(1.8)

where:m* = conductivity effective massε = applied electric fieldTf = mean tune between collisions in the lattice

since:

nVd

qTf2m

(1.9)

In uniform extrinsic crystals where the carrierconcentration is predominantly of one type, the electricalconductivity σn, is determined by the acceleration of carriersdue to the applied electrical field and those processes whicharrest carrier motion through the lattice.

n qn qnVd q2n t

m *(1.10)

m* = 0.98 for siliconm* = 0.067 for gallium arsenideSince the effective: mass of gallium arsenide is much

lower than that of silicon, the force on an electron in anelectric field accelerates electrons in gallium arsenide muchmore quickly than electrons in silicon. For low fieldconduction (<103 V/cm) the scattering processes for galliumarsenide and silicon are similar in magnitude, so the meandrift velocity for low–energy carriers is much higher,resulting in a low–field electron mobility of 8500 cm–V–s–1

at 300K for gallium arsenide and 1500 cm–V–s–1 at 300Kfor silicon.

The effective mass of the atom determines the mobilityand hence conductivity of the semiconductor material. Forpower rectifiers this property offers the potential for faster



devices with lower on–resistance when gallium arsenide isselected over silicon.

By taking into account the fact that mobility changes withdoping concentration,one can reconstruct Irvin’s curveswhich plot resistivity as a function of doping concentration,as shown in Figure 8 for silicon and Figure 9 for galliumarsenide.

From Figure 8 if a concentration of 1016 cm–3 is selected,this equates to a resistivity of 0.5 Ω–cm for silicon. This is

the typical resistivity tax–get used for a 40 V powerSchottky. From Figure 9, for the same concentration of 1016

cm–3, a resistivity of 0.05 Ω–cm is obtained with galliumarsenide as the semiconductor material for again a 40 Vpower Schottky device. This demonstrates the feature of lowon–resistance potential with gallium arsenide over siliconbut other problems pertaining to surface properties (whichwill be discussed later in this chapter) dominate the forwardvoltage drop in gallium arsenide Schottky devices.

10–2

101

10–3

1

10–4

10–1

102

Res

istiv

ity, Ω

–cm

Impurity Concentration, cm–3

Figure 7. Bulk Mobility Versus Doping for Silicon

10

10–2

1

10–3

10–1

10–4

102

Electrons (n–type)

Holes (p–type)

Impurity Concentration, atoms/cm3

Mob

ility

, cm

2 /V

•s

1014 1018 101910171016 10201015 1021

80

800

40

400

20

200

10

14001000

600

100

60

1014 1018 101910171016 10201015 1021

Res

istiv

ity, Ω

–cm

Impurity Concentration, cm–3

Figure 8. Resistivity as a Function of DopingConcentration (Irvin’s Curve) for Silicon [1]

T = 300 Kn–typep–type

p–GaPn–GaP

p–GaAs

n–GaAs

p–Gen–Ge

1014 1018 101910171016 10201015 1021

Figure 9. Resistivity Versus Impurity Concentrationfor Ge, GaAs, and GaP at 300K [2]



The Fermi Level ConceptThe fermi level is used to describe the energy level of the

electronic state which one electron has a probability of 0.5of occupying. However, the fermi level also describes thenumber of electrons and holes in the semiconductor.

With reference to the energy band diagram of Figure 10

n ni expEf Ei

kTn type (1.11)

p ni expEi Ef

kTp type (1.12)

for intrinsic since Ef = Ei

p n ni (1.13)

In other words, for the intrinsic material, the fermi levelis at the midpoint of the band gap.

Surface Properties of SemiconductorsThe atoms in a crystal of silicon or gallium arsenide are

arranged in a well–ordered structure so that the net forceacting on each atom is zero. In the bulk crystallographicstructure of silicon, each atom is surrounded by four othersin a tetrahedral configuration. except for imperfections suchas vacancies, substitutional or interstitial impurities, ordislocations, this configuration extends throughout thesingle crystal. The situation at the surface of a crystal ofsilicon or gallium arsenide is different from that prevailingin the bulk in many important ways. First of all, the absenceof neighboring atoms causes the equilibrium positionsadopted by the surface atoms to be different from the bulk.Secondly, the chemical nature of the surface tends not to be

atomically clean (i.e., the atomic composition of the surfaceis the same as the bulk). The surfaces of semiconductors arecomplex regions where the chemistry and crystallography isquite different from the bulk Not surprisingly, thedistribution of electrons and associated energy levels alsodiffers at the surface. from those pertaining to the bulk.

Since these surfaces are critical in the formation ofoxide–semiconductor interfaces and metal–semiconductorinterfaces, it is important understand them to the fullestpossible extent. Consider a semiconductor material likesilicon freshly cleaved in high vacuum to expose anultraclean surface. From a symmetry viewpoint, two of thefour covalent bonds which hold the silicon lattice togetherwould be broken at the crystal surface in contact with thevacuum. These broken bonds are missing two electrons peratom, and hence, about. 1015 atoms/cm3 are in a position toattract negative charges onto the crystal surface and give riseto energy states in the forbidden energy gap. In practice, thesilicon surface atoms when exposed to air quickly form anative oxide layer about 40Â thick. This satisfies the silicon“dangling” bonds at the surface and reduces surface statesunder clean conditions; to 5 x 1010/cm2 or less. Figure 11(a)shows the energy band diagram for the interface between ap–type silicon crystal and a vacuum, assuming a perfectcrystal in a perfect vacuum ignoring the effects of brokenbonds at the surface This may be referred to as the flat–bandcase, but obviously does not occur in practice: The realsituation is shown in Figure 11(b). The SiO2 layer containspositive charges that result in an n–shift in thesemiconductor, i.e., an n–type semiconductor behaves moren–type, whereas p–type material behaves less p–type.

Figure 10. Energy Band Diagram for n–type and p–type with Fermi Levels Shown

Ef

Ev

Ei

Ec

Ef

Ev

Ei

Ec

Ec = Energy level of conduction bandEv = Energy level of valence band

Ef = Fermi energy levelEi = Intrinsic energy level

n–typep–type



With respect to the clean surfaces of semiconductors andmetals, surface states also significantly impact deviceproperties. The deposition of a metal onto a semiconductorusually gives rise to a barrier, if the work function fm of themetal is greater than the work function of the semiconductor.For the case of a metal to n–type semiconductor, the barrierheight (fB) is equal to the separation of the fermi level (Ef)and the conduction band minimum Ec at the semiconductormetal interface. Schottky proposed that fB be given by thedifference between the metal work function and thesemiconductor electron affinity (XS). With measured barrierheight for metals on n–type GaAs usually in the range of 0.7

to 0.9 eV, the Schottky model fails to explain the observedinsensitivity of the barrier height to metal work function ingallium arsenide. The basic explanation for this is thoughtto be surface states and interface states causing the fermilevel to be pinned at a certain level between the conductionand valence band at the semiconductor surface. Unpinningof the GaAs fermi level with heavily doped siliconoverlayers has been reported [1] but significant work in thisarea remains to be done to gain complete understanding andallow realization of improved on–conduction performanceof gallium arsenide Schottky technology.

Figure 11. (a) Ideal Surface; (b) Band Rending Due to Energy States in the Forbidden Energy Gap

Vacuum p–type Silicon

Electrons

p–type Silicon

Interface Ions

(a) (b)

Ionized Acceptors

SiliconDioxide

ChargedSlowStates

2000Å

Ef

Ef



Semiconductor Junctions

pn JunctionsThe rectifying properties of a diode can be understood

most easily from its band diagram. Prior to junctionformation, the band diagram of separated n–type and p–typesilicon is shown in Figure 12. From Equation 1.6:

P ni exp(Ei EF) kT (1.14a)

From Equation 1.5:

P ni exp(EF Ei) kT (1.14b)

Hence,

kT In (pni) Ei EF and

(1.15)kT In (nni) EF Ei

and therefore:

Ei Ef dT In pni and

(1.16)EF Ei kT In nni

When the two separated regions are joined, energy bandsbend to give a flat fermi level when an external voltage isapplied as shown in Figure 13.

(1.17)Vbi (Ei Efown20F)p side (EF Ei)n side

(1.18)Vbi kT pni kT In nni

(1.19)Vbi kT In pnni2

Since p = NA and n = ND then:

Vbi kT In NA NDni2 (1.20)

Once the equilibrium point is reached after junctionformation, the electrons on the n–type side cannot flowacross to the p–type side because of the energy barrier dueto the “built–in” contact potential similarly, holes on thep–type side cannot flow across to the n–type side.

Vbi = The “built in” voltage or contact potentialEc

Ei

Ev

Figure 12. Band Diagram Prior to Junction Formation

Ec

Ei

Ev

Ec

Ei

Ev

Ef

Ef

Figure 13. Band Diagram of Ideal Pit Junction



Forward BiasWhen an external voltage is applied to the junction, the

fermi level is offset at the terminals by the amount of theapplied voltage TIP a positive voltage is applied to thep–side of the junction, the pn junction is forward biased. Thisapplied forward bias reduces the “built–in” barrier heightand carriers’ flow across the barrier, as shown in Figure 14.

In effect. the built–in potential is now reduced, causing adiffusion current of majority carriers to flow across thedepletion region. Only holes with energies greater than the“built–in” voltage qVbi can diffuse into the n–region. Inaddition, holes in the n–region near the depletion edge driftunder the influence of the electric field in a directionopposite to the hole diffusion current, constituting a negativehole amount.

Total hole currentJp Jpdrift Jpdiffusion (1.21)

The carrier flow of holes from the p–side to n–side showsas an increase in minority carrier concentration on the n–side

of the junction. The excess minority carriers recombineoutside of the depletion layer, falling to the equilibriumvalue within one diffusion length L.

Similarly, total electron current

Jn Jndrift Jndiffusion (1.22)

The net effect of forward bias is a large diffusion currentcomponent, while the drift component remains fixed nearthe thermal equilibrium value.

Reverse BiasWhen the voltage applied to the p–type side is negative,

the junction is reverse–biased. The applied voltage addsdirectly to the “built–in” voltage and causes the fermi levelof the p–side to be displaced by an amount qVA. The netresult is that minority carriers are drawn toward the junction,and the hole diffusion current is reduced to less than itsthermal equilibrium value. The reverse bias current isextremely small because the source of current flow, theminority carrier concentration, is small.

Figure 14. Band Bending Due to Forward Bias Reduces “Built–in” Potential

Ef

hole+

p–type

n–type

Electrons(Vbi–VA)

Figure 15. Band Bending Due to Reverse Bias

Ef

Ec

Ei

Ev

Ef

(Vbi+VA )

VA applied

Ec

Ei

Ev



Metal–Semiconductor JunctionsMetal–semiconductor rectifying contacts are formed

when the metal barrier is brought into contact with thelightly doped semiconductor material, forming an energybarrier between the metal and the semiconductor The barrierheight of the metal–to–semiconductor junction depends onthe semiconductor material and its surface properties asexplained earlier in this chapter. The energy band diagramof a rectifying metal–semiconductor contact is shown inFigure 16.

According to the Schottky model, the barrier height can bedetermined by the difference between the metal workfunction (fm) and the electron affinity XS of thesemiconductor. However, in most practical situations a thininsulating oxide film exists at the metal–semiconductorinterface Such an insulation film, often referred to as aninterfacial layer, alters the properties of the semiconductorsurface from the bulk semiconductor (see section on surfaceproperties). The existence of this interfacial layer enhancesthe density of surface states near the surface and as a resultthe barrier height does not follow the Schottky model of:

b m XS (1.23)

Where φb = barrier height, φm = work function of metal,Xs = electron affinity of the semiconductor.

The barrier height consists of four components.

b m XS SS (1.24)

Where ∆SS = contribution due to surface states and A.1. isimage force lowering [3].

In practical processing of Schottky contacts, emphasis isplaced on making the metal–semiconductor contact close

to the ideal situation where the semiconductor is sensitiveto the metal work function. For silicon Schottkytechnology this is accomplished by obtaining an intimatemetal–to–semiconductor contact through the process offorming a thin silicide layer under the top metal contact.Table 2 shows the possible ranges of silicides that havebeen achieved to gain control of the barrier height onsilicon–based Schottky rectifiers. As yet, control of thebarrier height on gallium arsenide has proven elusive dueto the pinning of the fermi level.

Table 2. Schottky Barrier Heights (B) of VariousSilicides On n–Type SiliconÁÁÁÁÁÁÁÁÁÁDisilicides

ÁÁÁÁÁÁÁÁB(eV)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁOther Silicides

ÁÁÁÁÁÁB(eV)ÁÁÁÁÁ

ÁÁÁÁÁTiSi2ÁÁÁÁÁÁÁÁ0.6

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁHfSi

ÁÁÁÁÁÁ0.53ÁÁÁÁÁ

ÁÁÁÁÁVSi2

ÁÁÁÁÁÁÁÁ

0.65ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

MnSiÁÁÁÁÁÁ

0.76ÁÁÁÁÁÁÁÁÁÁ

CrSi2ÁÁÁÁÁÁÁÁ


CoSiÁÁÁÁÁÁ


ZrSi2ÁÁÁÁÁÁÁÁ


NiSiÁÁÁÁÁÁ


NbSi2ÁÁÁÁÁÁÁÁ

–ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ni2SiÁÁÁÁÁÁ


MoSi2ÁÁÁÁÁÁÁÁ


RhSiÁÁÁÁÁÁ


HfSi2ÁÁÁÁÁÁÁÁ

– ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Pd2Si ÁÁÁÁÁÁ


TaSi2ÁÁÁÁÁÁÁÁ


Pt2Si ÁÁÁÁÁÁ

0.78

ÁÁÁÁÁÁÁÁÁÁ

WSi2ÁÁÁÁÁÁÁÁ


PtSi ÁÁÁÁÁÁ

0.87


FeSi2 ÁÁÁÁÁÁÁÁ

– ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IrSi ÁÁÁÁÁÁ

0.93


CoSi2 ÁÁÁÁÁÁÁÁ


Ir2Si3 ÁÁÁÁÁÁ

0.85


NiSi2 ÁÁÁÁÁÁÁÁ

0.7 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IrSi3 ÁÁÁÁÁÁ

0.94

Figure 16. Schottky Energy Band Diagram (No–bias)

Ef

Ec

Ei

Ev

Ef

(Vbi+VA )

Ec

Ei

Ev

VA applied



Since the work function of the metal and the electronaffinity of the semiconductor are properties of the twomaterials selected to form the Schottky contact, the barrierheight to electrons remains constant and does not vary withapplied voltage. Under no bias, electrons at the edge of’ theconduction band in the bulk semiconductor see a potentialbarrier qVbi (Figure 17(a)). The number of electrons withenergies greater than Ec + qVbi traveling into the metalconstitute a semiconductor–to–metal current densitycomponent Js–m. Since under no bias the Schottky diode isin equilibrium, the number of electrons transversing themetal–semiconductor junction from metal to semiconductoris:

JSMk1NDeqVbikT (1.25)

JMSk1NCeDkT (1.26)

where:Nc is the effective density of the conduction band statesNA is the hulk majority carrier concentration from n ≡ ND.

Forward Bias (VA>0) and Reverse Bias (VA<0)The applied voltage changes the potential barrier for

electrons. In the semiconductor but not for electrons in themetal. Therefore, JS–M remains constant whereas JM–Sincreases with increasing VA. With VA applied, the barrierfor electrons in the semiconductor reduces to q(Vbi,–VA)and becomes (see Figure 17(b)):

JSM k1NDeq(VbiVA)kT (1.27)

The total current isJSM JMS

which is

(1.28)J k1NDeqVbikTeqVAkT k1NDeqVbikT

J k1NDeqVbikT[eqVAkT 1] (1.29)

Since:

JMS k1NCeDkTk1NDeqVbikT

then:

NDeqVbikT NCeDkT

Since B and Vbi do not change with VA then:

(1.30)J k1NCeDkT[eqVAkT 1]

J J0[eqVAkT 1] (1.31)

which is the form of the general diode equation.According to thermionic emission theory, to describe the

charge transport of electrons over a potential barrier thegeneral form of the diode equation can be rewritten as

J AT2e(qDkT)(eqVAkT 1) (1.32)

whereJ = Current flow across the Schottky barrier interfaceA = Richardson’s constantT = absolute temperatureq = electron chargek = Boltzman’s constantφB = barrier heightV = applied voltageFrom Figure 17 the potential barrier for electrons in the

semiconductor increases and results in a significant decreasein the number of electrons that can get to the metal.However, electrons in the metal see the same barrier asbefore fB;fB does not change with reverse bias. Therefore,the reverse current becomes

JR J0[eqVAkT 1]

Since VA → (–VR) then [eqVR

/kT– 1] → 0

JR J0

J0 AT2eq(DkT) (1.33)

This describes the reverse saturation current for the Schottkybarrier rectifier.



Figure 17. Schottky Barrier Rectifier Energy Band Diagrams (a) No Bias; (b) Forward Bias; (c) Reverse Bias

(a)

SemiconductorSemiconductor

ØB

(b)

(c)

Metal Semiconductor

ØB ØB

EFS

EFM

EFM

Ev

Ec

EFS

EFS

q(Vbi – VA)

qVA

qVbi q(Vbi – VA)

qVA

JM –S = J S–M JS –M > J M–S

Metal MetalEv

Ec

Ev

Ec

Similarly the diode equation for a pn junction obeys thegeneral diode equation, which is:

J J0(eqVAkT 1) (1.34)

where:

J0 qDPPno

Lp

Dnnpo

Ln (1.35)

and where:DP = diffusion coefficient of holesPno = concentration of minority carrier holes in n–type

material at equilibrium.Lp = diffusion length of minority carrier holes in

p–type materialDn = diffusion coefficient of electronsnpo = concentration of majority cater electrons in

p–type material at equilibrium.Ln = diffusion length of minority carrier electrons in

n–type material.



Real Diode Characteristics

Forward BiasReal diodes do not follow the ideal diode equation

because of physical limitations of the device fabrication ordesign techniques. The bipolar silicon rectifier is fabricatedusing a p–n–n+ rectifier vertical structure, shown inFigure 18.

In this device the n–epitaxial layer is flooded withminority cater holes during forward bias. The bulkresistance is given by:

R plA (1.36)

where:p = resistivity1 = drift region widthA = drift region area.This bulk resistance is reduced during forward bias as a

result. of the injection of minority carriers from the P+

region. This allows the rectifier to carry high current densityduring forward conduction. This carrier action is calledconductivity modulation. In a Schottky rectifier, the carrieraction is with majority carriers and no conductivitymodulation occurs. The charge transport mechanism in theSchottky is thermionic emission as opposed to diffusion anddrift in the p–n–n+ structure of the bipolar rectifier. Across–section of the vertical structure Schottky is shown inFigure 19 on the following page.

Typical forward characteristics of a 45 V Schottky and a1000 V ultrafast rectifier are shown in Figure 20(a) and (b),respectively.

In the case of the Schottky rectifier, the forward voltageconsists of four components:

Vf B (kTQ) 1n JFAT2 JFRspepi JFRspsub

(1.37)

where:φB is the contribution due to barrier height in (eV).(kT/q) ln (JF/AT2) is the contribution due to contact

potential (V).JF RRepi specific resistance of drift region voltage drop.JF RRsub substrate resistance voltage drop.JF RRepi and JF RRsub are the contributions due to the

specific resistance of drift region and substrate, respectively.In the case of a p–n rectifier, the forward voltage consists

of four components also:

Vf Vbi JFRspepi JFRspsub JFRlifetime(1.38)

where:Vbi the built–in potential described by equation 1.20JF Rspepi is specific resistance of drift region voltage dropJF Rspsub is specific resistance of substrate voltage dropJFRlifetime is specific resistance due to heavy metal lifetime

reduction. In a standard recovery rectifier JFRlifetime, is zero.

Figure 18. Vertical Structure of pnn+ Rectifier

Aluminum orTitanium, Nickel, Silver

Top Metal

P diffusion

N–EPI

Fired Passivation Glass

Titanium, Nickel, Silver Backmetal



Figure 19. Vertical Structure of Schottky Rectifier

Aluminum or Titanium, Nickel, Silver

Top Metal

p–type Guard Ring

n–type epi layer

Schottky Barrier Metal

Titanium, Nickel, Silver Backmetal

N ++ Substrate

Isolation Barrier Metal

Nickel

SiO2SiO2

Figure 20. Typical Forward Voltage Characteristic(a) Forward Voltage Characteristic of a 45 Volt Schottky MPR2O4SCT;(b) Forward Voltage Characteristic of 1000 Volt Ultrafast MUR8100E

i F, I

nsta

ntan

eous

For

war

d C

urre

nt (

Am

ps)

0.2

100

7050

3020

107.05.0

3.0

2.0

1.0

0.70.5

0.3

0.2

0.10.4 0.6 0.8 1.0 1.2 1.4 0.4

100

7050

3020

107.05.0

3.0

2.0

1.0

0.70.5

0.3

0.2

0.10.6 0.8 1.0 1.2 1.4 1.6 1.8

(a) (b)

28°C

TJ = 150°C 100°C

28°C

TJ = 150°C

100°C

i F, I

nsta

ntan

eous

For

war

d C

urre

nt (

Am

ps)

Vf, Instantaneous Voltage (Volts) Vf, Instantaneous Voltage (Volts)



Reverse BiasThe reverse leakage current consist of four components

for a bipolar p–n–n+ rectifier:

IR ID IG I IS (1.39)

where:ID =diffusion current, sometimes called saturation

current JoIG =space charge generation currentI =lifetime reduction current due to heavy metal

dopingIS =surface passivation.The hole diffusion current (ID) in the drift region is

minority carrier concentration in the drift region as shown inEquation 1.35. The space charge generation current (IG) isthe current that results from the charge transportmechanisms within the space charge region. The spacecharge region is the region that develops at the transitionregion between p–type and n–type materials. Under theconditions, of equilibrium described in Figure 21,hole–electron pairs continuously form in the space chargeregion as a result of thermal agitation.

However, the hole and electron forming a pair soonrecombine. The period of time during which theelectron–hole pair exists is referred to as the minority carrierlifetime. When a reverse bias is placed across the pnjunction, the space charge region expands from thetransition region into portions of the p and n materials onboth sides of the junction. At the same time a larger fielddevelops across the junction. The creation of this field, inturn, attracts mobile electrons and holes being generated inthe space charge region and sweeps them into the p and nmaterials before they can recombine. This current is referredto as the space charge generation current IG.

The lifetime reduction current (Iτ) is due to the influenceof platinum or bold when introduced into the silicon crystalto enhance switching speed. The surface leakage current (IS)is due to leakage paths on the surface of the semiconductoror charge influence in the insulation used to provide junction

passivation In general, the contribution of surfacepassivation and lifetime reduction currents tends to be muchhigher than the space charge generation and diffusioncomponents of the total reverse leakage current.

The reverse leakage current of a Schottky rectifier isdominated by the barrier height of the Schottky. In generalSchottky reverse leakage currents are approximately fivetimes higher than traditional Ultrafast rectifiers.

Figure 21. Property of pn Junction at EquilibriumShowing the Space Charge and Transition Region

Lp depletion

P N

spacecharge regionor drift region

–Lp

–Lp

chargedistribution

E(x)

electric fieldEmax

V(x)

–Lp

contact potential

Vo

ND – NA

LN

LN

LN

LN

X



Breakdown VoltageBoth Schottky and Ultrafast rectifiers exhibit avalanche

breakdown. Avalanche breakdown is a process in which asingle charge carrier ionizes an atom within the crystallattice under the influence, of a strong electric field. Eachelectron and ion formed as a result of the ionization processis itself accelerated by the electric field through the spacecharge region. This acceleration imparts sufficient energyfor the electron or ion to ionize other atoms it may impactand thereby create additional electrons and ions. The resultof this rapid increase in reverse current is called avalanchebreakdown.

For a step junction p+n–n+ structure, Poisson’s equationrelates the electric field E to the charge density P in thedepletion layer:

dE()d()

P()S0

(1.40)

where:εS = is the semiconductor dielectric constant and ε0 is the

permittivity of free space.For a step junction where one side is heavily doped the

electrical properties are determined by the characteristics ofthe lighter doped side. In p+n–n+ step junction, the maximumfield can be found by integrating from the depletion edge toχd the junction.

Emax 0

(1.41)–χd

qNDS0

d()qNDdS0

E dvd

qND

S0(1.42)

Integrating once the potential difference across thisone–sided step junction gives:

VqND2S0

d (1.43)

d2S0qND |V| (1.44)

(1.45)d2S0qND VB VA

Substitute 1.45 into 1.40:

E max2qNDS0

VB VA

When the maximum field exceeds a critical field forsilicon, then avalanche breakdown occurs.

CapacitanceUnder reverse bias conditions both Schottky and p+n–n+

junctions exhibit a voltage–dependent capacitancerelationship. This relationship is expressed as capacitanceper unit area;

(1.46)CS0qND

2|VB VA|

Capacitance is significant in Schottky rectifierapplications at high frequency.

Capacitance is a function of bulk concentration, area ofjunction and barrier height As the barrier height is lowered,the capacitance of a Schottky increases. As the active areaof the Schottky junction is increased, the capacitance.increases. As the concentration of the bulk region is.decreased; the capacitance is decreased.

Figure 22. Capacitance Versus Reverse Voltage ForSchottky Rectifier

Typ

Max

100 KMz >1 >1.0 MMz

Vr, REVERSE VOLTAGE (VOLTS)

C, C

AP

AC

ITA

NC

E (

pF)

1000

3000

700

2000

5000

0.5 5.0 7.03.02.0 201.0 30 5010



Dynamic SwitchingIn general, Schottky technology offers switching

performance because Schottky is a majority carriertechnology. In fact, switching both forward and reversedirections are major drawbacks of p+n n+ technology. Forexample, when a p+n+n+ rectifier is switched from reverseblocking to on–conduction as shown in Figure 23, itsforward voltage drop exceeds its steady–state forwardvoltage drop. This phenomenon is called forward voltageovershoot during the turn–on transport. This is due to thefact that during Ugh–speed switching from the off–state tothe on–state, current through the rectifier is limited by themaximum rate at which minority carriers are injected intothe junction. A high voltage drop therefore develops acrossthe diode for a short period of time until minority carriersdiffuse into the junction and reduce the drift regionresistance. This process was explained in an earlier sectionas conductivity modulation. The time it rakes for the diodeto recover to within 10% of its steady–state forwardconduction voltage is called the forward recovery time.

The reverse recovery of a p+n n+ rectifier is. an even moreserious drawback than the forward recovery characteristic.Reverse recovery time is the time required for injectedminority carriers to be removed from the space chargeregion when the device is “turning off.”’ The reverserecovery time. Which if we assume the reverse recoverycharacteristics are approximated to a triangle of base trr andheight Irrm peak reverse recovery current, then the reverserecovery charge Qrr can be calculated to be:

Qrr 2Irrm trr coulombs (1.47)

Figure 24 shows the reverse, recovery characteristic offour power rectifier technologies.

The abrupt and soft recovery technologies of Figure 24 aretraditional p+n+n+ diodes with lifetime control for improvedswitching. However, when the switching frequency ofpower circuits increases, the turn–off di/dt also increases.This causes an increase in both the peak current Irrm, and theresulting reverse recovery di/dt; this causes higher lossesand more noise in the circuit.

Figure 23. Forward Recovery Characteristics of p+nn+ Diode When Switched From Reverse Blocking to On Conduction

Vf

trr



Figure 24. Reverse Recovery Characteristics

GaAs Schottky

Megahertz

GaAs SCHOTTKYMEGAHERTZ BIPOLAR DIODESOFT RECOVERY P–N DIODEABRUPT RECOVERY P–N DIODE

Rectifiers such as the Megahertz technology or theGaAs Schottky technology offer reduced trr and Qrr. featuresand allow circuit operations at high frequency. Figure 25shows the potential for Megahertz and GaAs Schottkyrectifiers as enabling technologies for high–frequencyapplications.

Figure 26 shows the forward current relationship of twoSchottky rectifiers at 25C and 150C. The phenomenon of

negative temperature coefficient is observed.From Figures 27 and 28 one can see that the gallium

arsenide technology is essentially thermally stable sincelosses did not increase with temperature. whereas losses,although reduced, did increase with the Megahertz deviceover the 100C, temperature excursion and a significantincrease was exhibited by the Ultrafast rectifier.

Figure 25. Safe Switching Area Curve for Ultrafast, Megahertz and Gallium Arsenide Schottky Power Rectifiers

Ultrafast

Megahertz

GaAs

Frequency10MHz1MHz100kHz

iF(Amps)



Figure 26. Forward Current Relationship of Two Schottky Rectifiers at 25C and 150C (the phenomenon of negative temperature coefficient is observed)

30

20

10

00 200 400 600 800 1000

Vf @ 150°C pt1 Vf @ 25°C pt1Vf @ 150°C pt2Vf @ 25°C pt2

Vf (mV)

i F (

amps

)

Figure 27. The Reverse Characteristic of Ultrafast, Megahertz and GaAs at TA = 25C. All Devices Exposed to the Same Test Conditions.

25°C

Tcase = + 25°C

GaAs

Megahertz

Ultrafast

I = 1A/div

GaAs/MURH840

MUR3040

Mem C20 ns .1V

Mem D20 ns .1V

Chan 120 ns .1V

GaAs

MegaHz

Ultrafast

°25 C

Mem C20 ns .1V

Mem D20 ns .1V

Chan 120 ns .1V

GaAs

MegaHz

Ultrafast

I = 1A/div

GaAs/MURH840

MUR3040

GaAs

Megahertz

Ultrafast

Figure 28. The Reverse Recovery Characteristic of Ultrafast, Megahertz and GaAs at TA = 125C.All Devices Exposed to the Same Test Conditions.

iF = 5A

Vr = 100V

Tcase = + 25°C

iF = 5A

Vr = 100V



Silicon Temperature Coefficient Formula forForward Voltage

When current is held constant, changes in forward voltageas a result of changes in junction temperature may be foundfrom

Vf (Tj) Vf (25) (Tj 25) (1.48)

whereVf(Tj) = forward voltage at TjVf(25)= forward voltage 25CφSi = temperature coefficient for siliconTj = junction temperature

Figure 29. si of Forward Voltage for a Family of Si Diodes

4.0

1.5

4.5

0.5

3.5

–0.5

2.5

–1.5

1.0

0

3.0

–1.0

2.0

–2.0–2.5

Typical Range

0.001 1.0 5.00.50.1 100.005 500.050.01

Instantaneous Forward Current (Amp)

Tem

pera

ture

Coe

ffici

ent (

mW

/°C

)Design Tradeoffs

Table 3. Effects of Physical Change on Electrical CharacteristicsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Electrical Parameter ChangeÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Physical ChangeÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IncreaseÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DecreaseÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Increase Resistivity (Epi)ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

VfÁÁÁÁÁÁ

BVÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

tfrÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

CTÁÁÁÁÁÁ

IrÁÁÁÁÁÁ

trrÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

AreaÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

CTÁÁÁÁÁÁÁÁ

trrÁÁÁÁÁÁ

IrÁÁÁÁÁÁ

tfrÁÁÁÁÁÁ

VfÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁThickness(Epi)

ÁÁÁÁÁÁ

tfrÁÁÁÁÁÁ

VfÁÁÁÁÁÁ

BvÁÁÁÁÁÁ

CTÁÁÁÁÁÁÁÁ

trrÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ


ÁÁÁÁÁÁÁÁÁBarrier Height

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

VfÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

CTÁÁÁÁÁÁ

IrÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁLifetime

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

trrÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

VÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

tlr – Forward Recovery trr – Reverse Recovery BV – Breakdown VoltageCT – Capacitance Transient Vf – Forward Voltage Ir – Reverse Leakage

ConclusionPower rectifiers are essential components in the power

electronics industry. As power rectifiers are improved interms of conduction and switching performance theybecome enabling technologies for power conversionsystems.

ON Semiconductor has established a technologicalstrength, experience and skill resulting in functionallyvaluable products for our customers. This introductorychapter combines theory with description of real rectifierperformance for both existing and emerging rectifiertechnologies.

At ON Semiconductor we have accepted the challengefrom our customers to provide enabling power rectifiers andcontinue to strive towards the ideal device.

References1. J.G. Irvin, Resistivity of Bulk Silicon and of

Diffused Layers in Silicon, Bell System Tech J.Vol. 41, p. 387, 1962.

2. S.M. Sze and J.C. Irvin, Resistivity, Mobility andImpurity Levels in GaAs, Ge and Si at 300K,Solid State Electronics, 11; 599 (1968).

3. Sze, Physics of Semiconductors. page 364–368.



Chapter 2

Basic Thermal Properties of Semicondutors



Three basic processes play a part in the removal of heatfrom the rectifier junction to the ambient air: (1) conduction(heat traveling through a material); (2) convection (heattransfer by physical motion of a fluid); and (3) radiation(heat transfer by electromagnetic wave propagation). Heatflows by conduction from the die to the package mountingsurface in stud–, base–, or surface–mount pads, but it flowsfrom the die through the leads to the mounting terminals ina lead–mounted part For case–mounted parts, convectionand radiation are of primary importance in the design of theheat exchanger, which is covered in Chapter 13. Forlead–mounted parts, radiation and convection from the bodyboth play a role in removing heat from the die and arediscussed later in this chapter. Transient thermalconsiderations and thermal runaway are often importantdesign factors and receive treatment near the end of thischapter.

In order to simplify the analysis of heat flow, the conceptof thermal resistance is used. Just as a material offersresistance to the flow of current, it may be thought of asoffering resistance to the flow of heat. Resistance to heatflow is called thermal resistance and for steady–stateconditions is given as:

R TP (2.1a)

or

T RP (2.1b)

where:R = the thermal resistance in C/WT = the temperature difference between points in CP = the power in watts.Junction temperature of semiconductors must be held

below the rating assigned to the part The junction istherefore commonly used for one of the reference points inapplying Equation 2.1. The other reference point is the casefor semiconductors enclosed in case–mounted packages ora specified point on a lead for semiconductors enclosed in apackage intended for PCB insertion To denote the reference

point, the symbols in Equation 2.1 have subscripts. ThusRJC signifies thermal resistance, junction–to–case. WhileRJL signifies thermal resistance, junction–to–lead. Thecorresponding temperatures are denoted ∆TJC and TJL,respectively.

Thermal ModelsThermal resistance may be used to form electrical models

which permit calculation of the temperature rise at variouspoints in a system. Similar to an electrical physicalresistance, thermal resistance is not constant; changes inmounting, temperature, or power levels will cause somemodification of values. Nevertheless, the concept providesa very valuable tool in handling thermal problems.

By use of a thermal model, complex thermal systems maybe easily analyzed using electrical network theorems. Thefollowing sections discuss models for single chip case– andlead–mounted parts and for multiple chip assemblies.

Case–Mounted RectifiersThe total thermal resistance, junction–to–ease, is

composed of three identifiable thermal resistances, asshown in Figure 30. The die–bond thermal resistance isusually the largest value. Actual values are determined bythe design of the device: the size of the chip, the type of thedie bond, and the type and material of the package.Variations among parts from a given product line are theresult of variations in the die–bond thermal resistance whichis affected by the type of solder or bonding material used. Asa general guide, however, thermal resistance as a function ofthe die area for various common diode packages using solderdie bonds behaves as shown in Figure 31.

Some parts may have a piece of material inserted betweenthe die and the package to take up stresses developed bydiffering thermal coefficients of expansion of the packageand of the die. This technique allows a hard solder die attachtechnique to be used, which improves temperature cyclingbehavior Other parts may contain insulators that electricallyisolate the chip from the package. These materials addanother component of thermal resistance to the assembly.

Figure 30. Thermal Resistance Components of the Junction–to–Case Thermal Resistance

Junction

Direction of Heat Flow

Die Bond

Package Header

Junction

Die Bond

Die

Package



Figure 31. Typical thermal resistance of commonrectifier packages having copper material in the heatflow path (data averaged from measurements at ON)

Die Area (Square Mils)

DO–4

DO–5Pressfit

Rθ J

C, J

unct

ion–

to–C

ase

The

rmal

Res

ista

nce

(°C

/W)

1.0

3.0

0.8

2.0

0.6

1.5

0.4

4.0

5.0k 20k 30k15k10k 40k7.0k 50k

Thermal resistance (Rθ) follows the same generalequation as does electrical resistance:

R lA (2.2)

where:ρ = thermal resistivityl = length of thermal pathA = area of thermal pathThe equation states that thermal resistance is inversely

proportional to area; however, the data of Figure 31 does notindicate this relationship exactly. The deviation is causedbecause the area of heat flow through the package is not thesame as the die area. As heat flows, it spreads out toward theedges of the package; consequently, as larger die are placedin a given package, the area for spreading reducesproportionally.

Lead–Mounted PartsIn the axial lead–mounted rectifier, heat travels down both

leads to some kind of a heat dissipator, which is usuallynothing more than a printed–circuit wiring pattern. Heat isalso removed from the package by convection and radiation,which make the thermal circuit model immensely morecomplicated for a lead–mounted part than for acase–mounted part. However, certain lead–mounted partsare easily handled because the thermal resistance of bothleads is identical and quite low compared to the packageradiation and convection components which maybe

neglected. Examples of parts in which this simplifiedapproach is satisfactory are the MR750 series. Thermalresistance as a function of lead length is shown in Figure 32.Note that the thermal resistance is linearly proportional tolead length, indicating that the package heat transfercomponents play a negligible role in the total thermalresistance. If the package thermal resistance componentswere not negligible, the lines would curve as the lead lengthincreased.

Data is often given for the case where both leads haveidentical lengths. However, identical lead lengths will notresult in lowest thermal resistance to the mounting pointssince the net thermal resistance is composed of two parallelpaths. The lowest net value will always occur when one ofthe paths is made as short as possible. For example, supposea mounting situation is encountered where the leads musttake up a 1 inch span. If each lead were 1/2 inch long, thethermal resistance (from Figure 32) is l3C/W maximum.However, the device could be mounted with one lead 1/8inch long and the other 7/8 inch long. The thermal resistancefrom junction to the end of each lead is 4C/W for the 1/8inch lead and 23C/W for the 7/8 inch lead. The net thermalresistance of the parallel combination is 3.4C/W. Thereduction from 13C/W is quite significant but to takeadvantage of this reduction the mounting terminal must havea low thermal resistance to the ambient As the span becomesless, the advantages of asymmetrical mounting become lesssignificant.

Figure 32. Thermal Resistance as a Function of LeadLength for MR751 Series Axial–Lead Rectifiers

Lead Length (Inches)

Single Lead Heat Sink,Insignificant Heat FlowThrough Other Lead

Maximum

Typical

Both Leads to HeatSink, Equal Length

Rθ J

L, T

herm

al R

esis

tanc

e, J

unct

ion–

to–L

ead

(°C

/W)

15

30

10

25

5

20

0

35

40

0 1/2 5/83/81/4 3/41/8 7/8 1



As a design guide, when using lead–mounted pans,Figure 33 shows typical data for three popular case types.The data should not be taken as absolute becausejunction–to–ambient thermal resistance cannot be regardedas a design constant. The factors involved are discussed indepth in Chapter 13.

MOUNTING METHOD 1P.C. Board Where Available

Copper Surface area is small

MOUNTING METHOD 2Vector Push–In Terminals T–28

MOUNTING METHOD 3P.C. Board with

Copper Surface of Area A

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

L L


L L

ÉÉÉÉÉÉ

L = 1/2”

Board Ground Plane

Parts with asymmetrical lead conduction and/orsignificant convection and radiation from the case requite

use of a complete thermal model. Figure 34 shows asatisfactory approximation.

CASE # MOUNTINGLEAD LENGTH L

CASE # MOUNTINGMETHOD 1/8 1/4 1/2 3/4

591 65 72 82 92

59(DO–41) 2 74 81 91 101(DO 41)

3 40°C/W (L = 3/8, A = 2.25 2)

1 – 55 – 58

60 2 – 65 – 6860

3 25°C/W (L = 5/8, A = 6.252)

1 50 51 53 55

267 2 58 59 61 632673 28°C/W (L = 1/2, A = 6.252)

Data shown for the mountings shown is to be used as typical

guideline values for preliminary engineering or in case the tie point

temperature cannot be measured.

Figure 33. Typical Values for RJA in Still Air

Use of the above model permits calculation of average junction temperature for any mounting situation.Lowest values of thermal resistance will occur when the cathode lead is brought as close as possible to a

heat dissipator, as heat conduction through the anode lead is small. Terms in the model are defined as follows:

RθLA RθJAL RθJC

RθCA

RθCL RθLK

TAA TLA TJ PD TAK TA

25°C/W 2°C/W/in

70°C/W

RθSK

40°C/W/in

0.5°C/W 40°C/W/in

TEMPERATURES THERMAL RESISTANCESTA = Ambient RθCA = Case to AmbientTAA = Anode Heat Sink Ambient RθSA = Anode Lead Heat Sink to AmbientTAK = Cathode Heat Sink Ambient RθSK = Cathode Lead Heat Sink to AmbientTLA = Anode Lead RθLA = Anode LeadTLK = Cathode Lead RθLK = Cathode LeadTJ = Junction RθCL = Case to Cathode Lead

RθJC = Junction to Case*RθJAL = Junction to Anode Lead (S bend)

*Case temperature reference is at cathode end.

Figure 34. Approximate Thermal Circuit Model for a Case 60 Part



Use of the thermal model of Figure 34 to calculatejunction temperature is illustrated by the followingexample:

Cathode Lead Length 14 inch TA 60C

Anode Lead Length 12 inch TAA 70CRSA RSK 40CW (typical

for printed board wiring)TAK 80C

From the data in the figure, calculate:

RLA 40 x 12 20CW,RLK 40 x 14 10CW.

The model of Figure 34 may be successively simplified byusing Thevenin’s network theorem as illustrated byFigure 35. The resulting junction temperature is 117C.

Thus, the effective thermal resistance, junction–to–ambient,is (117–60)/2 = 28.5C/W; however, the number is notespecially meaningful because the tempera–tufts of theambient and the printed board wiring are not the same.

The concept of a single thermal resistance number todescribe the thermal properties of axial–lead parts must beused with caution, because the ambient temperature isgenerally not the same as the temperature of the points whichserve as a heat sink for the leads. Furthermore, in the case ofan asymmetrically mounted part, there is little likelihoodthat either mounting point would be at the same temperaturebecause more heat flows out through the low resistance lead.Thus, thermal resistance of a lead–mounted diode in termsof a single value is only useful when all the referencetemperature points involved have the same temperature.

Figure 35. Successive steps in the solution of the example in the text. Thermal problems may be solved byapplications of network theorems. (a) Model with example numbers inserted;

(b) Simplified thermal circuit obtained by applying Thevenin’s Theorem to each side of the model

85°C/W

70°C

2°C/W

2 W 50°C/W 70°C/W

80°C 60°C

TJ

(a)

(b)

85°C/W

240°

2°C/W

71.6°CTJ

29°C/W

Multiple Chip DevicesAssemblies having more than one die per package – for

example full–wave, bridge, or three–phaseconfigurations–have a considerably more complicatedthermal situation because of thermal coupling between thedie. To appreciate how the coupling problem can be handled,consider the thermal model of Figure 36. Coupling isrepresented by the resistances connecting all the dietogether. The coupling between adjacent die is primarily aresult of heat transfer through the lead frame, but thesurrounding encapsulate is also a thermal conductor. Inaddition, each die is also coupled to the diametricallyopposite one through the molding in the center of theassembly. The center coupling requires the addition of twoother resistance paths.

Since the model is so complex, it is easier to work in termsof a coupling factor. The general equation for thermallycoupled die can be written as follows:

TJ1 R1PD1 R2K2PD2(2.3)R3K3PD3 RnKnPDn

where:∆TJ1 = the rise in junction temperature of diode 1 with

respect to the reference temperatureRθn = the thermal resistance of diodes 1 through nPDn = the power dissipated in diodes 1 through nKθn = the thermal coupling between diode 1 and

diodes 2–4n = the die of interest



Figure 36. Sketch of Physical Construction and Thermal Model for a Bridge Assembly

P1 P2 P3 P4

Thermal Resistances

D3

D1

D2D4

Die Bond

Adjacent Die Coupling

Additional OppositeDie Coupling

Lead Frameand CaseMaterial

Case

Assuming equal thermal resistance for each die, Equation2.3 simplifies to

TJ1 R1(PD1 K2PD2 K3PD3(2.4) KnPDn)

For the condition where PD1 = PD2 = PD3 = PDn, the totaldissipation PDT = n PD1.

For this special case, Equation 2.4 can be furthersimplified to

(2.5)TJ1 R1(1 K2 Kn) PDTn

An effective package thermal resistance can be defined asfollows:

(2.6)R(eff) TJ1PDT

Combining Equations 2.5 and 2.6 yields:

(2.7)R(eff) R1 (1 K2 K3 Kn)n

Assume an assembly has a thermal coupling coefficientbetween opposite dice of 0.12 and between adjacent dice of0.20. If the individual die has a thermal resistance of6.0C/W, the effective bridge thermal resistance may becalculated from Equation 2.7 as

R(eff) 6.0(1 0.20 0.120 0.20) 4 2.28CW

This value is the one specified on the data sheet as theeffective bridge thermal resistance, junction–to–case.Satisfactory average, steady–state temperature calculationsmay be made by multiplying Rθ(eff), by the total powerdissipated in the package under a given load condition,provided the current in each diode is identical in wave–shapeand amplitude.

The coupling factor is particularly valuable when a bridgeassembly is operated in the split load circuit of Figure 37(b)instead of the more usual bridge circuit of Figure 37(a.) Thefollowing example illustrates the use of the data.

Assume that the previous assembly is used in the circuitof Figure 37(b) and operates such that

PD1 PD2 10 WPD3 PD4 5 W

Maximum temperature rise occurs in diodes 1 and 2. UsingEquation 2.4 and substituting values:

TJ1 6.0 [10 (0.02)(10) (0.12)(5) (0.12)(5)] 79.2

Figure 37. Basic Circuit Uses for Bridge Rectifiers (a) Standard Circuit; (b) Split Load Circuit

(a) (b)

Load 1

Load 2

IA

IB

D4

D2

D3

D1

IA

IB

D4

D2

D3

D1

Load

+

–



Transient Response of Semiconductors

Each component of thermal resistance in a semiconductoralso has a thermal capacitance associated with it, related tothe mass of the material. A high capacitance is desirable inorder to improve the transient and overload capability of thepart since it slows the response to a power pulse.

A mathematical analysis of one–dimensional heat flowindicates that the thermal response follows the relationshipTJ t . However, the various time constants associatedwith a semiconductor affixed to a package, and the fact thatheat flow is not usually one–dimensional, make the responseextremely difficult to calculate. The most practical methodof handling the transient thermal problem is to measure thethermal response of the semiconductor to a step of inputpower and to present the data in a graph. The thermalresistance as a function of time is called transient thermalimpedance and may he calculated by:

(2.8)ZJR(t) r(t) RJR

where:r(t) = fraction of steady state value at a given timeRθJR = thermal resistance, junction to a reference pointChoice of reference point depends on the type of part. For

case–mounted parts, the logical reference is the case. Forlead–mounted parts the leads are generally chosen;however, the ambient ins sometimes used.

Thermal ResponseThermal response of lead–mounted semiconductors is

difficult to present because of the effect of lead length.Figure 38 shows the thermal response of two lead–mountedparts. In general, the slope, between 10 and 100 ms, as onFigure 38(b), is followed until steady–state conditions areapproached. Figure 38(b) shows transient thermalimpedance, ZθJL(t). Where the effects of lead length areconsidered. Curves for other lead lengths can be sketchedusing the given curves as a guide and flattening the curve atthe appropriate value of steady–state thermal resistance.

(b) t, Time (ms)

(a) t, Time (ms)0.5 10 205.02.0 501.0 100 200 5000 10k20001000 20k500 50k

30

20

50

10

7.0

1.0

10070

5.0

3.0

2.0

Figure 38. Typical Thermal Response of Lead–Mounted Rectifiers (a) Case 59 with Fast Recovery Diode, Plotted Normalized;(b) Case 59 with Standard Diode, Plotted in Terms of C/W

Lead Length = 1/4 ”

L = 1”

L = 3/8 ”

L = 1/32”

ÉÉÉÉ

ÉÉÉÉ

LL

Heat Sink

Rθ J

L(t), J

unct

ion–

to–L

ead

Tran

sien

t The

rmal

Impe

danc

e (°

C/W

)

3.0 30 502010 1005.0 200 300 5000 10k20001000 20k500 30k

r (t

), T

rans

ient

The

rmal

Impe

danc

e(N

orm

aliz

ed)

0.3

0.2

0.5

0.10.07

0.01

1.00.7

0.05

0.03

0.02



Figure 39 shows response curves for typical powerrectifiers in stud–mount and press fit cases. Differences indies and manufacturing techniques make it difficult toquantitatively explain behavior, although it is evident thatthe more massive packages and larger die have slowerresponses.

Measurements of various rectifier diode arrays haverevealed that times well ever 10 seconds are required for

temperature changes of other die to become manifest at oneof the other die in the same package. As a result, transientcoupling can be neglected because of the relatively highfrequencies employed in electronic work.

When rectifiers are used in intermittent operation thethermal response of the heat sink may be used to advantage.Heat sink properties are discussed in Chapter 13.

(a) t, Time (ms)

(b) t, Time (ms)

(c) t, Time (ms)

Figure 39. Typical Thermal Response of Stud–Mounted and Press–fit Rectifiers (a) DO–4 Package;(b) DO–5 Package; (c) DO–21 Package

1.0

0.5

0.3

0.2

0.1

0.05

0.03

0.02

0.010.001 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 100 200 50050 1.0k 5.0k 10k

1.0

0.5

0.3

0.2

0.1

0.05

0.03

0.02

0.01

1.0

0.5

0.3

0.2

0.1

0.05

0.03

0.02

0.010.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0k 5.0k 10k2.0k

0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0k 5.0k 10k2.0k

r (t

), E

ffect

ive

Tran

sien

t Im

peda

nce

(Nor

mal

ized

)r

(t),

Effe

ctiv

e Tr

ansi

ent I

mpe

danc

e(N

orm

aliz

ed)

r (t

), E

ffect

ive

Tran

sien

t Im

peda

nce

(Nor

mal

ized

)



Use of Thermal Response DataA simple equation to permit calculation of temperature for

arbitrary pulse trains with random variations is impossibleto derive. However, since the heating and cooling responseof a semiconductor is essentially the same, the superpositionprinciple may be used to solve problems which otherwisedefy solution. Using the principle of superposition, eachpower interval is considered positive in value and eachcooling interval negative, lasting from time of application toinfinity. By multiplying the thermal resistance at a particulartime by the magnitude of the power pulse applied, themagnitude of the junction temperature change at a particulartime is obtained. The net junction temperature is thealgebraic sum of the terms.

The application of the superposition principle is easilyseen by studying Figure 40. Part (a) illustrates the appliedpower pulses. Part (b) shows these pulses transformed intopulses lasting from time of application arid extending toinfinity; at t0, P1 starts and extends to infinity; at t1, a pulse(–P1) is considered to be present and thereby cancels P1 fromtime t1, and so forth with the other pulses. The junctiontemperature changes, due to these imagined positive andnegative pulses., are shown in part (c). The actual junctiontemperature is the algebraic sum as shown in part (d).

Problems may be solved by applying the superpositionprinciple exactly as described; the technique is referred to asthe pulse–by–pulse method. It yields satisfactory resultswhen the total time of interest is much less than the timerequired to achieve steady–state conditions. This methodmust be used when an uncertainty exists in a random pulsetrain as to which pulse will cause the highest temperature.

–P4

P4P3

P2

P1

P4

P3

P2

Pin

Pin

Figure 40. Application of Superposition Principle (a) Input Power; (b) Power Pulses Separated into Components;

(c) TJ Change Caused by Components; (d) Composite TJ

(a)

(b)

(c)

(d)

Time

Time

Time

Time

P1

t0 t1 t2 t3 t4 t5 t6 t7

–P1

–P2

–P3

TJ



Where power surges or overloads occur with uniformtrains of repetitive pulses, more accurate answers with lesswork are obtained by using a model based on averaging thepower pulses. The basis of this method is shown inFigure 41. The average power pulse is followed by one pulseof the repetitive train and then the overload pulse. Thetemperature is calculated at the end of the surge or overload.

PO

pulse

t t

Pavg

n thPOV

Figure 41. Model for a Repetitive Equal Pulse TrainHaving an Overload Condition

Handling Nonrectangular PulsesThermal response curves, such as those shown in

Figure 38 and 39, are based on a step change of power; theresponse will not be the same for other waveforms. Thus farin this treatment a rectangular–shaped pulse has beenassumed. It would be desirable to be able to obtain theresponse for any arbitrary waveform, but the mathematicalsolution is extremely unwieldy. The simplest approach is tomake a suitable equivalent rectangular model of the actualpower pulse and to use the given thermal response curves;the primary rule to observe is that the energy of the actualpower pulse and the model are equal.

Experience with various modeling techniques has lead tothe following guidelines:

1. For a pulse that is nearly rectangular, a waveformhaving an amplitude equal to the peak of the actualpulse, with the width adjusted so the energies areequal, is a conservative model (see Figure 42(a)).

2. Sine wave and triangular power pulses model wellwith the amplitude reduced by a factor. FA, of 91%

and 71%. respectively, of the peak and the widthadjusted to 70% of the baseline width (as shown inFigure 42(b)). A power pulse having a sin2 shapemodels as a triangular waveform.

Rectifier diode forward power pulses are a combination ofsin and sin2 waveforms if the current is a sinewave. Ingeneral, suitable mudding results if the amplitude waveformfactor, FA, is about 0.91 when the peak current is low and0.71 when the peak current is high, that is, when the voltagedrop across the forward resistance (RF) is significant. (Atlow levels, diode voltage is fairly constant over the forwardcurrent cycle yielding a sine wave power waveform, whileat high power levels the diode voltage is more nearlyproportional to the instantaneous value of current resultingin a power waveform closer to a sin2 function. SeeChapter 4.)

Rectifiers used with SCRs in phase control circuits musthandle the current waveforms of part (c) of Figure 42.Empirically developed modeling rules for SCR powerlosses are indicated; the rules are slightly more conservativewhen used with rectifiers than with SCRs.

Power pulses having more complex waveforms aremodeled by using two or more pulses as shown inFigure 42(d).

Note: A point to remember is that a high–amplitude pulseof a given amount of energy will produce a higher rise injunction temperature than will a lower amplitude pulse oflonger duration having the same energy

The general equation for modeling is:

(2.9)TMP(AV)TWFAP(PK)

where: TM = pulse width of model

PAV = average power in the original waveform

TW = time duration of original waveform

(P(AV) TW = Area under the powerwaveform)

FA = amplitude waveform factor previouslydiscussed

P(PK) = peak power of original waveform



0.91 P(PK)0.95 P(PK)0.98 P(PK)

0.85 P(PK)0.75 P(PK)

0.7 P(PK)

0.71 P(PK)0.91 P(PK)

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

Figure 42. Models for Frequently Encountered Power Pulses(a) Model for Nearly Rectangular Waveform; (b) Models for Sine Wave and Triangular Pulses;

(c) Models of SCR Current Waveforms for Various Conduction Angles (). Pulses for >120 are centered withrespect to the sine wave. Pulses for > 90 start at the leading edge;

(d) Model for a Complex Waveform

30°22° 44°

60°67°

90°

180°

126°

150°

113°

120°

88°

(a)

(b)

(c)

(d)

P1

= AP1 T1

T1

A

A

0.7 TW0.7 TW

P1 (t1 –t0) + P2 (t2 – t1) = A

TW TW

t0 t1 t2

P1

P2

P(PK) P(PK)



Example Peak Temperature CalculationsThe following examples illustrate proper analysis

procedures for commonly encountered circuit applications.The first one is for a train of randomly spaced square pulses,and the second is for a single–phase circuit subjected to anoverload. The second example requires use of proper powerpulse modeling techniques to obtain a solution.

EXAMPLE 1Finding TJ at the end of the nth pulse in a train of unequal

amplitude, spacing, and duration:

General Equation:

TnPi[r(t2n1 t2i2) r(t2n1 t2i1)]RJC

(2.10)

n

i = 1

where n is the number of pulses and Pi is the peak value ofthe ith pulse.

To find temperature at the end of each of the three pulsesshown in Figure 43, Equation 2.10 becomes:

T2 [P1 r(t3) P1 r(t3 t1) P2r(t3 t2)]

(2.10b)RJC

T1 P1 r(t1) RJC (2.10a)

T3 [P1 r(t5) P1 r(t5 t1) P2r(t5 t2)

P2r(t5 t3) P3r(t5 t4)] RJC (2.10c)

Assume the following pulse conditions are applied to arectifier with a transient thermal response as shown inFigure 38(a) and RθJL = 31C/W for a lead length of 1/4inch.

P1 = 80 W t0 = 0 t3 = 1.3 msP2 = 40 W t1 = 0.1 ms t4 = 3.3 msP3 = 70 W t2 = 0.3 ms t5 = 3.5 ms

Therefore:t1 – t0 = 0.1 ms t3 – t1 = 1.2 mst2 – t1 = 0.2 ms t5 – t1 = 3.4 mst3 – t2 = 1 ms t5 – t2 = 3.2 mst4 – t3 = 2 ms t5 – t3 = 2.2 mst5 – t4 = 0.2 ms

t0 t1 t2 t3 t4 t5

Figure 43. Pulse Train Analyzed for PeakTemperatures in Example 1 Text

100

80

60

40

20

0

1.0 2.0 3.0 4.00

t, Time (ms)

P1

P2

P3

P(P

K),

Pea

k P

ower

(W

atts

)PROCEDURE:

Find r(tn – tk) for preceding time intervals fromFigure 31a; then substitute into the set of Equations 2.10.

T2 [P1 r(t3) P1 r(t3 t1) P2 r(t3 t2)] RJL

T1 P1 r(t1) RJL (80)(0.02) 31 50C

T3 [P1 r(t5) P1 r(t5 t1) P2 r(t5 t2)

P2 r(t5 t3) P3 r(t5 t4)] RJL

[80 (0.058) 80 (0.056) 40 (0.054)] 31

[4.64 4.48 2.16] 31 4.96 66.96 72C

[80 (0.074) 80 (0.073) 40 (0.072) 40 (0.066) 60 (0.027)] 31

[(5.91 5.83) (2.88 2.64) (1.62)] 31

2.48 7.44 50.22 60.14C

The calculations above are performed so that, precedingthe final answer, the residual temperature caused by thepreceding pulses is evident. Note that very little residualtemperature is left from the first pulse at the end of thesecond and third pulses. Also note that the second pulse gavethe highest value of junction temperature, a fact not soobvious from inspection of Figure 43. Because of the hightemperature caused by the second pulse, significant residualtemperature from the second pulse was present at the end ofthe third pulse.

EXAMPLE 2Find TJ at the end of an overload condition in a train of

pulses of equal amplitude, spacing, and duration.The overload–current condition shown in Figure 44 is

applied to the rectifier used in the previous example and ismodeled as shown in Figure 45. P1 is the average powerdissipation before the overload condition, P2 is the averagepower dissipation during the overload condition, and P3 isan equivalent peak power pulse resulting from the lastoverload pulse in the overload train. For the average currentof 0.4 A, before the overload condition, and the averagecurrent of 2.2 A during the overload, the average powerdissipation can be determined from rectifier powerdissipation data. The data shows P1 = 0.4 W and P2 3.0 Wfor a resistive load. P3 is a peak power and is obtained bynoting that an average current of 2.2 A has a peak value of6.9 A (3.14 x 2.2) causing a peak voltage of 1.45 V, obtainedfrom rectifier VF–IF data. Using the modeling rules, theequivalent rectangular pulse, P3, using a conservativewaveform factor of 0.91 yields:

P3 (0.91)(6.9)(1.45) 9.1 W



IF(AV) = 0.4 A

Figure 44. Overload Current Condition Used in Example 2 to Calculate Peak JunctionTemperature

For

war

d C

urre

nt

ForwardCurrent

Forward Current,

Overload Current, IF(AV) = 2.2 A

Figure 45. Model of Power Pulses Resulting from the Overload Current Conditions of Figure 44

AppliedVoltage

1 ms

t5P1

P2

P3

t0 t2 t3t4

t6

t1

VRVm2

The time t3 – t2 is found by adjusting the width TM of thepower pulse P3 for equivalent energy by using Equation 2.9to obtain

t3 t2 TMP2TW

P3

(t3 t2)(3)(16.667)

9.1 5.5 ms

thus,

(t2 t1) (t4 t3) 8.34 5.52

2.842 1.42 ms

t1 (9)(16.67) 150 ms

t2 t1 (t2 t1) 151.42

t3 t2 (t3 t2) 156.92

t5 t3 (t4 t3) 1 159.34

t3 t1 6.92

t5 t1 9.34

t5 t2 7.92

t5 t3 2.42

The general equations used to calculate the junctiontemperature rise above ambient at t3 and t5 are as follows:

(2.11a) P3 r(t3 t2)] RJL

T3 [P1 P1 r(t3) P2 r(t3) P2 r(t3 t1)

T5 [P1 P1 r(t5) P2 r(t5 P2 r(t5 t1)

P3 r(t5 t2) P3 r(t5 t3)] RJL (2.11b)

Solving,

9.1 (0.083)] 31 1.71 (31) 53C

T3 [0.4 0.4 (0.315) 3 (0.315) 3(0.088)

T5 [0.4 0.4 (0.317) 3(0.317) 3(0.096)

9.1 (0.091) 9.1 (0.068)] 1.15 (31) 36C

Thus, the junction temperature has cooled 17C from timet3 to time t5. Reverse power dissipation, due to reversevoltage and leakage current, has been assumed negligible inthe above example. If this is not the case, average reversepower dissipation is added to pulses P1 and P2; also a peakreverse power pulse is added between t4 and t5. Equations2.11a and 2.11b are accordingly modified.



Thermal RunawayRectifier circuits may operate the rectifying diode such

that thermal runaway is liable to occur and result indestruction of the diode. The problem arises because severalcharacteristics are a function of temperature. Reverserecovery, reverse leakage, and usually forward power lossesincrease with temperature. As power is applied, junctiontemperature increases, causing power losses to increase.The additional power causes a further increase intemperature. Thus, a regenerative process is operating.

In any thermal system, the conditions for thermal stabilityare such that as the ambient temperature rises. the systemmust be capable of dissipating more heat than is generated.That is, the heat generated in the semiconductor must be lessthan the thermal conductivity from junction–to–air.Mathematically, the conditions for stability are

(2.12)dPDdTJ 1RJA

where dPD/dTJ = change in power dissipation per unitchange in temperature

RθJA = thermal resistance, junction–to–ambient.A graphical approach [2] may be used to analyze the

problem and illustrate the principles involved. It alsopermits visualizing the influence of ambient temperatureand thermal resistance. Figure 46 shows how this is done;values are typical of those encountered with Schottky barrierpower rectifiers, which have a sufficiently high reverseleakage current to cause thermal runaway.

Curve A is a plot of the heat generated at the rectifierjunction versus junction temperature: The ordinate is simplyPR(AV) and may be found from IR vs. TJ and VR curves; it iseasy to do for dc conditions. The slope of curve A isdPD/dTJ.

Curve B represents the power–dissipation capability (rateof heat flow) of the equivalent thermal circuit as a functionof the junction temperature of the rectifier. The slope can beseen to be 1/RθJA, which corresponds to the thermalconductivity of the total thermal circuit from junction toambient air.

With no voltage applied, the unit dissipates no power andthe junction temperature is the same as the ambient. InFigure 46, this condition corresponds to the point TA. Whenvoltages are applied to the circuit, the heat generated by thesemiconductor (in the form of dissipation) is P1. Thisamount of internal heat generation in the semiconductorrequires that the junction temperature increase to T1.However, since the junction temperature has now beenincreased, the total power generated by the semiconductormust increase to P2. In this manner, the junction temperatureand resultant power generation increase until a stablecondition is reached at point 1, where the power–generationand thermal–conductance curves intersect. The temperatureat point 1 is labeled T2 and may be read from the abscissa asapproximately 48C; the ambient temperature is at theintersection of curve B with the abscissa, and is 30C for thisexample.

Figure 46. Graphical Analysis of Thermal Runaway

2.0

1.6

1.2

0.8

0.4

0 20 40 60 80 100T

°( C)T, Temperature

B

2

3

1A

C

B1 B2

Hea

t Gen

erat

ions

or

Rat

e of

Hea

t Flo

w (

Wat

ts)

T1 T2

P1

P2

It is now possible to predict the effect of changing theambient temperature. If the ambient temperature wereincreased. curve B would be translated to the right, resultingin a higher junction temperature because the intersection ofcurve A would be to the right of point 1. If the ambienttemperature increased to 49C (curve B1), the junctiontemperature would be about 85C. At values of ambienttemperature below 49C, for this particular thermalresistance (25C/W), the circuit always fulfills the thermalstability criterion, dPD/dTJ<RθJA and is therefore athermally stable circuit. At an ambient temperature 49C,curve B1 is tangent to curve A at point 2, where dPD/dTJ =1/RθJA. Under these conditions the circuit is conditionallystable, since a small incremental increase in junctiontemperature will cause an unstable condition. A further risein the ambient temperature will cause the thermalconductance curve B1 to fall below the power generationcurve as shown by B2. Under these conditions thesemiconductor junction temperature cannot stabilize. Thepower generated within the semiconductor continues toincrease in search of a stable condition until the junction isdestroyed.

From this representation, the effect of changing thethermal conductance can be determined. If the coolingfacility is changed (for instance, a better heat sink is used),the junction will run cooler for a given ambient temperature,since the slope will be increased. Curve B illustrates theresult. Curve C shows what happens if RθJA is increased to40C/W. Note that the maximum ambient temperatureallowed is 29C and that the junction temperature is at 75Cat the point of thermal runaway (point 3).



To aid the circuit designer in applying rectifiers havingreverse leakage high enough to require that thermal runawaybe considered in the design, a simplified approach has beendevised and is presented on applicable ON Semiconductordata sheets. It is based on the relationship

(2.13)

TA(max) TJ(max) RJA PF(AV) RJA PR(AV)

where TA(max) = maximum allowable ambienttemperature

TJ(max) = maximum allowable junctiontemperature (rated limit or thetemperature at which thermal runawayoccurs, whichever is lowest)

PF(AV) = average forward power dissipationPR(AV) = average reverse power dissipationRθJA = junction–to–ambient thermal

resistance.A reference temperature is defined by Equation 2.14:

(2.14)TR TJ(max) RJA PR(AV)

The reference temperature TR may be limited only byPR(AV) or may be limited by thermal runaway. TR is obtainedby a computer solution of the basic stability criteriaboundary given in Equation 2.12 as explained in thepreceding discussion. TR data is presented on graphs similarto that of Figure 47. With TR known. TA(max) is found from

(2.15)TA(max) TR RJA PF(AV)

Equation 2.15 is found by substituting Equation 2.14 intoEquation 2.13.

Figure 47 shows how TR is limited by both TJ(max)andthermal runaway. The transition between these twolimitations is evident on the curves of Figure 47 as adifference in the rate of change of the slope in the vicinity of115C. The data is based upon dc conditions. For use incommon rectifier circuits Table 4 indicates suggestedvoltage factors for an equivalent dc voltage to use forconservative design, i.e.

(2.16)VR(equiv) Vin(PK) FV

The factor FV is derived by considering the properties ofthe various rectifier circuits and the reverse characteristicsof the particular diode. At a fixed junction temperature. thereverse power waveform is determined for various peakreverse voltage levels and average power is calculated. FromIR – VR data, the value of VR is found which produces thesame power dissipation as in the circuit; it is VR(equiv).

Figure 47. Maximum Reference Temperature for aSchottky Rectifier

125

115

95

85

75

105

4.0 5.0 7.0 10 15 20 30 40

R JA (°C/W) = 50

3020

1510

7.0

5.0

2.53.5

TR

, Ref

eren

ce T

empe

ratu

re (

°C)

VR, DC Reverse Voltage (Volts)

EXAMPLE

Find TA(max) for the diode of Figure 47 operated in a 24 VDC supply using a bridge circuit with capacitive filter suchthat the load current IL(DC) = 10 A (IF(AV) = 5 A),IF(PK)/IF(AV) = 0, input voltage = 20 V(rms,) RθJA = 7C/W.

Step 1. Find VR(equiv). Read FV = 0.65 from Table 4.

VR(equiv) = (1.41)(20)(0.65) = 18.3

Step 2. Find TR from Figure 47. Read TR = 108C @VR = 18.3 and RθJA = 7C/W

Step 3. Find PF(AV) from rectifier data. PF(AV) = 10 W at IPK/I(AV) = 20 and IF(AV) = 5 A

Step 4. Find TA(max) from Equation 2.15.TA(max) = 108–(7)(10) = 38C.

References1. Bill Roehr and Bryce Shiner, Transient Thermal

Resistance General Data and Its Use,ON Semiconductor Application Note AN–569.ON Semiconductor Products Inc., Phoenix,Arizona.

2. Lloyd P. Hunter, et al., Handbook ofSemiconductor Electronics, Second Edition,Chapter 11. pp 11–80, 81. McGraw–Hill BookCo., Inc., New York, New York. 1962.

Table 4. Values for Factor FVÁÁÁÁÁÁÁÁÁÁÁÁ

CircuitÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Half WaveÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Full Wave, BridgeÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Full Wave, Center Tapped*ÁÁÁÁÁÁÁÁÁÁÁÁ

LoadÁÁÁÁÁÁÁÁÁÁÁÁ

ResistiveÁÁÁÁÁÁÁÁÁÁ

Capacitive*ÁÁÁÁÁÁÁÁÁÁÁÁ


CapacitiveÁÁÁÁÁÁÁÁÁÁÁÁ


CapacitiveÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sine WaveSquare Wave


0.50.75


1.51.5


0.50.75


0.650.75


1.01.5


1.31.5

*Note that Vrwm = 2 Vin(PK) *Use line to center tap voltage for Vin.



Chapter 3

The SPICE Diode Model



Special AcknowledgmentThis chapter was written by Howard T. Russell, Jr., PhD, OPALEngineering, Inc., August 4, 1991

IntroductionThis chapter presents a description of the SPICE diode

model and methods for the extraction of its parameters. Acomprehensive examination of this model will be givenalong with comparisons of the characteristics of a real diodeand those produced by the model. These comparisons willbe used to illustrate the model’s accuracy and limitations.Based on the nature of the model equations, mathematicalmethods for the extraction of the SPICE parameters (withthe exception of the noise parameters) will be presented.These methods are easily implemented on a hand–heldprogrammable calculator and will be used to extract theparameters for a ON Semiconductor MURHS4OCTrectifier as an example. Throughout this chapter, referencesare made to the characteristics and behavior of an ideal diodemodel. The development of this model may be found inseveral of the many well–known texts on the subjects ofsemiconductor device theory and pn junction diodes [1–4].

The SPICE model of a pn junction diode consists ofmathematical equations, parameters, and variables, all ofwhich are designed to work together to simulate asaccurately as possible the electrical characteristics of a realdevice. The equations and variables used for the model in theSPICE program are fixed and not easily modified [5, 6].Therefore, the accuracy resulting from a SPICE simulationof a diode depends on the precise extraction of its modelparameters. Fortunately, there are several parameterextraction methods which can be applied to this model, someof which yield more accurate results than others. The

inherent success of a particular method depends for the mostpart on how well device physics and theory are utilized in thedesign of the model, and upon the availability of data takenfrom a real device.

The SPICE Diode ModelThe parameters for the SPICE model of the diode are

given in Table 5 [5, 6]. The equations that use theseparameters are divided into four model groups which areresponsible for simulating various diode characteristics.These groups consists of the large–signal dc model, thesmall–signal ac model, temperature and area effects, and thenoise model.

The Large–Signal DC ModelThe large–signal behavior of the SPICE diode is

characterized by the relationship between the dc current andvoltage at its terminals. The parameters used to model thisbehavior are IS, RS, N, By, and 1EV. The parameter IS is thesame as the reverse saturation current IS for an ideal diode.The ohmic resistance RS is used to model the resistance ofthe metal contacts and the neutral regions under high–levelinjection. The emission coefficient N is used to modify theslope of the current versus voltage (I–V) characteristicscurve. Finally, the parameters BV and IBV model thereverse breakdown behavior.

Figure 48 shows the equivalent circuit of the SPICE diodefor large–signal dc analysis. This circuit contains an internaldiode D1, a series resistance having a value of RS, and ashunt conductance GMIN. The SPICE program adds thisconductance, which is transparent to the user, around everyinternal pn junction to aid convergence. The program defaultvalue for GMIN is 10–12 mhos but can be set to any othernon–zero value with a OPTIONS line in the circuit file [5].

Table 5. SPICE Diode Model Parameters


Name ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Parameter ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Default value ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Typical value ÁÁÁÁÁÁÁÁ

Units


IS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Saturation Current ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

10.0 f ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

50.0 f ÁÁÁÁÁÁÁÁ

A


RS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ohmic Resistance ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

2.0 ÁÁÁÁÁÁÁÁ

ohm


N ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Emission Coefficient ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

1.0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

1.1 ÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁTT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Forward Transit Time ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


10.0 n ÁÁÁÁÁÁÁÁ

sec


CJO ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Zero–bias Junction Capacitance ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


10.0 p ÁÁÁÁÁÁÁÁ

F


VJ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Contact Potential ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



V


M ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Junction Capacitance Grading Exponent ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



ÁÁÁÁÁEG ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Energy Gap ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



eV


XTI ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IS Temperature Exponent ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



ÁÁÁÁÁKF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Flicker Noise Coefficient ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


0.1f ÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁAF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Flicker Noise Exponent ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



ÁÁÁÁÁFC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CJ Forward–bias Coefficient ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



ÁÁÁÁÁBV ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reverse Breakdown ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

∞ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


V


IBV ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Current at BV ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

1.0 m ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

200.0 p ÁÁÁÁÁÁÁÁ

A



VF

ID

R5

D1

+VD–

Gmin

Figure 48. DC Large–signal SPICE Diode Model

+

–

The dc model variables consist of the voltage across theexternal diode terminals VF. The voltage across the internaldiode terminals VD and the terminal current ID. With theseparameters and variables, the large–signal dc characteristicsare modeled by the following equations

VF RS ID VD (3.1)

and

ID f(VD) (3.2)

where four regions of operation describe the functionalrelationship between the internal diode voltage and diodecurrent.

(a) For VD5 N Vt

ID IS exp VDN Vt 1GMIN VD (3.3)

(b) ForBV VD5 N Vt

IDISGMIN VD (3.4)

(c) For VDBV,

IDIBV (3.5)

(d) For VDBV,

IDIS exp(BV VD)Vt 1 BV

Vt (3.6)

For all of these equations, Vt is the thermal voltage which isdefined as

Vtk T

q (3.7)

To insure convergence between regions (c) and (d), it isnecessary that IBV is defined as

IBV IS BVVt

(3.8)

A typical plot of ID versus VD generated by these equationsis shown in Figure 49 where each of the regions (a) through(d) are indicated.

The Small–Signal AC ModelThe ac model of the SPICE diode is derived from the

linearized small–signal behavior of the internal diode D1shown in Figure 48. The circuit elements of this modelinclude the junction capacitance CJ, the dynamicconductance GD, and the diffusion capacitance CD, all ofwhich are bias dependent as are those correspondingelements of the ideal diode model.

VD

Figure 49. Large–scale I–V Characteristics of theSPICE Diode Model

–BV(d)

(c)

(b) (a)

IBV

IS

–5•N•Vt

ID

The junction capacitance is modeled by the parametersCJO, VJ, M, and FC. The parameters CJO and VY areidentical to the zero–bias junction capacitance Cj(0) and thecontact potential Vj described for an ideal diode. Theparameter M is a grading exponent that is used to change theslope of the junction capacitance versus voltage (C–V)characteristics curve. For abrupt or step junctions, M is 0.5while for linearly graded junctions, M is about 0.333. Theparameter FC is used to model the capacitance underforward bias conditions.



The variables for the model are the junction capacitanceCJ in farads and the internal diode voltage VD which arerelated by

CJ f(VD) (3.9)

where two regions of operation describe this function.

CJ CJO(1 FC)(M1)

1 FC (M 1)M VDVJ

(a) For VD FC VJ,

CJ CJO 1 VDVJM

(3.10)

(b) For VD FC VJ,

(3.11)

To insure that the last equation remains well behaved, PCis restricted to values between zero and one; that is,

0 FC 1 (3.12)

A typical C–V curve produced by these equations isshown in Figure 50 where each of the two regions areindicated.

The dynamic conductance is modeled by the slope of theI–V curve evaluated at a particular bias voltage. This slopeis found from the voltage derivative of the current describedin equations (3.3) through (3.6). The conductance GD inmhos of the internal diode D1 as a function of the voltage VDis derived from

GD f(VD) (3.13)

where three regions of operation describe this functionalrelationship which involve the parameters IS and N.

(a) For VD5 N Vt,

GD ISN Vt

exp VDN Vt (3.14)

(b) ForBV VD5 N Vt,

GD ISVD

(3.15)

(c) For VDBV,

GD 0 (3.16)

The diffusion capacitance CD is modeled by the forwardtransit time parameter TT, and the parameters IS and N.Similar to an ideal diode, this capacitance in farads is voltagedependent and is derived from

CD f(VD) (3.17)

VD

Figure 50. Junction C–V Characteristics of the SPICEDiode Model

(b)(a)

0 FC•VJ

CJO

CJ

where three regions of operation describe this functionalrelationship:

(a) For VD5 N Vt

CD TT ISN Vt exp VD

N Vt (3.18)

(b) ForBV VD5 N Vt

CDTT ISVD

(3.19)

(c) For VDBVCD 0 (3.20)

The complete small–signal ac model of the SPICE diodeis shown in Figure 51 where the resistance RS has beenincluded with the elements defined above.

Temperature and Area EffectsTemperature behavior of the SPICE diode is modeled

through certain temperature–dependent parameters. Theseparameters are IS, VJ, CJO, and EC. In the equations tofollow, TNOM is the nominal or reference temperaturehaving a default value of 27C. This value can also bechanged with the use of the .OPTIONS line. The variable Tis the analysis temperature (in C) which has a default valueof 27C if the TEMP line is omitted from the circuit file. Ifthe .TEMP line is used for temperature analysis, T takes onthe values given in this line. It is important to note thatSPICE assumes all input data and model parameters havebeen specified at 27C. Even though temperature isspecified in the circuit file and in the .OPTIONS line in C,it is converted by SPICE to K for use in the equations.



For the saturation current IS, the parameters N, EG, andXTI are used to model its temperature dependence with theequation:

IS(T) IS(TNOM) TTNOMXTI1N

(3.21) expq EGN K 1

TNOM 1

T

RS

Figure 51. AC Small–signal SPICE Diode Model

A

K

CJ CD

A

K

GminCG

where IS (TNOM) is the nominal value of the saturationcurrent and IS(T) is the value evaluated at the analysistemperature T.

The contact potential VJ has the temperature–dependentfunction given below

VJ(T) VJ(TNOM) TTNOM

(3.22) 2 k Tq 1nni(TNOM)

ni(T)

In this expression, VJ(TNOM) is the TNOM value of VJ,VJ(T) is the value evaluated at T, and ni(T) is the intrinsiccarrier concentration (in cm–3) of silicon which is also afunction of temperature. That is,

ni(T) 1.45 1010 TTNOM1.5

(3.23) exp q2 K Eg(TNOM)

TNOM

Eg(T)

T

where Eg(T) is the temperature–dependent function for theenergy gap (in eV) of silicon. From experimental results, thisfunction is found to be

(3.24)Eg(T) 1.16 7.02 104 T2T 1108.0

At 27C, Eg calculates to be about 1.115 eV.

For the zero–bias junction capacitance CJO, theparameters M and VJ are used to model its temperaturedependence with the equation:

(3.25)

CJO(T) CJO(TNOM)

1 4 104 M (T TNOM)m 1 VJ(T)VJ(TNOM)

The last temperature–dependent parameter is FC, thejunction capacitance forward–bias coefficient. Thisparameter has the simple function given as:

(3.26)FC(T) FC(TNOM) VJ(T)VJ(TNOM)

For the ideal diode, certain parameters are functions of thejunction area. The SPICE program also providesarea–dependency on these parameters through the use of theAREA factor in the diode description line in the circuit file.The parameters affected by the AREA factor are IS, RS, CJOand IBV which are modified by the following equations:

IS AREA IS (3.27)

RS RSAREA

(3.28)

CJO AREA CJO (3.29)

IBV AREA IBV (3.30)

where AREA has a default value of 1.

The Noise ModelSmall–signal noise behavior of the SPICE diode is

modeled by two noise current sources added to thesmall–signal ac circuit model as shown in Figure 52. Thecurrent source iRS is responsible for modeling thermal noisegenerated by the resistance RS. The mean–squared value ofthermal noise current (in A2) generated by this source isexpressed as

(3.31)iRS4 k T

RS f

2

where T is the temperature in K and ∆f is the noisebandwidth in Hz. The current source iD, is responsible formodeling both shot and flicker noise (1/f noise) generated inthe depletion region of the diode. The total mean–squaredvalue of noise current (in A2) generated by this source isexpressed as

(3.32)iD 2 q ID f KF ID

f f

2

where ID is the dc diode current, f is the frequency at whichthe noise is measured, and AF and KF are SPICE flickernoise parameters.



The Diode Model versus a Real DiodeTo see how well the equations for the SPICE diode model

simulate the behavior of both ideal and real diodes,comparisons are made among the terminal characteristics ofall three. These comparisons use standard characteristiccurves which illustrate the behavior of a typical real diode(shown with solid curves), and those produced by the idealand SPICE diode models (shown with dashed curves). Forclarity, all curves are labeled to indicate their origin.

The current (logarithmic scale) versus voltage (linear scale)for a diode driven by a forward–bias dc voltage is plotted andshown in Figure 53. From this I–V plot,three distinct regionsof operation are observed. In Region I, the device is operatingunder extreme low–level injection for bias voltages rangingfrom zero to about 100 mV, typically. For this mode ofoperation, the injected carriers passing through the depletionregion are largely affected by the many generation andrecombination (G–R) centers found near the metallurgicaljunction. The dominant effect of these G–R centers causes theincrease in the diode current with respect to the voltage to besmaller than ideally predicted. In Region II, the diode isoperating under low–level injection. The voltage range forthis region is from about 100 mV to a value determined byVF(max) which is derived from

(3.32)VF(max) Vt 1n N2low

10 n2i

where Nlow is the smaller of the impurity concentrations.Under this mode of operation, the G–R centers do not affectthe injected carriers as much as in Region I, and the currentincrease over this voltage range is found to be close to thatpredicted for an ideal diode. Beyond the voltage VF(max), thediode operates under high–level injection as illustrated byRegion III. Here the resistances of the neutral n and p–typeregions produce ohmic voltage drops which tend to reduce thecurrent increase. As these drops become more dominant, thediode current stops increasing exponentially and becomesmore proportional to the bias voltage.

RS

Figure 52. AC Small–signal SPICE Diode Model withNoise Sources

A

K

GD CJ CD

A

K

iD

iRS

Gmin

Figure 53. Forward–bias I–V Characteristics for Real,Ideal, and SPICE Diodes

(Ideal)

0

(Real)

(SPICE)

100 mV (max)VF VF

RegionI

RegionII

RegionIII

Superimposed on this plot is the dashed curverepresenting the I–V characteristics of an ideal diode. It isclear that this model is fairly accurate in Region II, but fallsshort of predicting the behavior of Regions I and III. Thesecond dashed curve is that of the SPICE diode which isgenerated by Equations 3.1 and 3.3. Compared to the realdiode, the characteristics produced by this model illustratesignificant accuracy in Regions II and III. However, like theideal diode, the characteristics are less accurate in Region I.

In Figure 54, the linear–scaled I–V characteristics of a realdiode are shown for both the forward and reverse–biasconditions. As the reverse–bias voltage increases toward thebreakdown voltage, the diode current in the reversedirection exhibits a slight increase due to surface leakageeffects. For real diodes, this current is referred to as thereverse leakage current IR. The current at which breakdownoccurs is called the breakdown current IBV. The first dashedcurve represents the I–V characteristics of an ideal diode.Under reverse–bias conditions, the reverse leakage currentis main–mined by the saturation current IS which is constantand not affected by the voltage. Even though the breakdownvoltage can be calculated, the true breakdown behavior isnot predicted by the ideal diode model equations.

The second dashed curve represents the I–Vcharacteristics of the SPICE diode as generated byEquations 3.3 through 3.6. For this model, the reverseleakage current is maintained by the saturation currentparameter IS, which is also constant and unaffected by thevoltage. However, the behavior of the model at thebreakdown voltage is fairly close to that of a real diode.



Figure 54. Forward and Reverse–bias I–V Characteristics for the Real, Ideal, and SPICE Diodes

(Ideal)

–BV

(Real)

(SPICE)

VF–IS–IBV

–5•N•Vt

ID

Junction capacitance versus voltage characteristic curvesare shown in Figure 55. Under forward–bias, the C–Vcharacteristics for a real diode are well behaved for voltagevalues close to the contact potential Vj. For an ideal diode,however, the capacitance calculated near Vj tends toapproach unrealistic values. In the reverse–bias region, theresults of this equation show close similarity to thecapacitance of a real diode.

The results of the SPICE diode junction capacitanceequations show a very accurate similarity to the capacitanceof a real diode, especially in the reverse–bias region. This isdue in part to the. parameter M in Equation 3.10 whichallows the slope of the C–V curve to vary, lathe forward–bias

region, the parameter PC is used in Equation 3.11 to producea straight–line approximation to the C–V curve for voltagesbeyond FCVJ.

A plot of diffusion capacitance as a function offorward–bias diode current is shown in Figure 56. Thediffusion capacitance behavior of an ideal diode illustratesa proportional increase in capacitance with current since theforward transit time T is assumed to be constant. This is thecase for the SPICE diode since the corresponding parameterTT is also constant. For a real diode, however, τT is knownto increase with current at high current levels due to currentcrowding effects. Thus, the diffusion capacitance typicallydeviates from predicted behavior as illustrated.

(Ideal)

(Real)

(SPICE)

VFFC•VF

CJ (0)

CJ

0 VJ

Figure 55. Forward and Reverse–bias Junction C–VCharacteristics for the Real, Ideal, and SPICE Diodes

(Real)

(Ideal & SPICE)

Figure 56. Diffusion Capacitance Characteristics forthe Real, Ideal, and SPICE Diodes

log CD

log ID



Figure 57 is a plot of the temperature coefficient (TCV) asa function of forward–bias current. The TCV for a real diodetypically has negative values over low current ranges butincreases to positive values at higher currents. This is duemainly to the positive temperature coefficient of the bulkresistance which dominates the diode voltage at these levels.The TCV of an ideal diode has negative values over a largerange of current as shown. This is also true for the SPICEdiode since the resistance parameter RS has no temperaturecoefficient.

Figure 57. Voltage Temperature Coefficient (TCV)Characteristics for the Real, Ideal, and SPICE Diodes

TCV

0

(+)

(–)

(Real)

(Ideal & SPICE)

log ID

SPICE Diode Model ParameterLimitations and Restrictions

Based on these comparisons, it is obvious that the SPICEdiode model is capable of performing a fairly accurate jobin simulating the behavior of a real pn junction diode. It isjust as obvious, however, that the model is also limited in itsrange of accurate simulation due in part to limitations of itsparameters. The following statements provide a review ofthe limitations on the model parameters and how they affectthe simulation results. For some of the parameters,suggested value restrictions are given in order to insureconvergence.(a) The saturation current IS is constant and not a function

of the reverse–bias voltage. Therefore, the simulatedreverse leakage current remains constant over thereverse–bias region up to the breakdown voltage.

(b) The ohmic resistance RS is constant and not a functionof current or voltage. The resistance of the bulk neutralsemiconductor regions of a real diode actually increasesas current increases for high–level injection.

(c) RS has no temperature coefficient. The temperaturecoefficient of the resistance of the bulk neutral

semiconductor regions of a real diode is actuallypositive, which produces a positive TCV at high–levelinjection.

(d) The emission coefficient N is constant, and cannotmodel the change in the slope of the I–V characteristicsbetween the extreme low–level and low–level injectionregions. For convergence purposes, N must be greaterthan 0.01.

(e) The forward transit time TT is constant and not afunction of current or voltage. As such, the diffusioncapacitance CD will increase proportionally withcurrent and the simulated reverse recovery time trr willbe constant over current.

(f) The temperature dependence of the zero–bias junctioncapacitance CJO is consistent with that of silicon only.In Equation 3.25, the coefficient of thermal expansionis that of silicon material.

(g) From Equations 3.22 to 3.24, the TNOM value of thecontact potential VJ must be greater than 0.4 V to insureconvergence for temperature analysis up to 200C. Fora larger value of the analysis temperature, theseequations can be used to determine the minimum valueof VJ.

(h) The temperature dependencies of the contact potentialVJ, the intrinsic cater concentration ni, and the energygap EG given in Equations 3.22 to 3.24, respectively,are consistent with that of silicon material only.

(i) For convergence, the forward bias coefficient PC isrestricted to values between zero and one as indicatedin Equation 3.12; that is,

0 FC 1.0

(j) The reverse breakdown voltage BV has a default valueof infinite. A specified value of zero for BV isinterpreted by SPICE to mean infinite.

(k) The reverse breakdown characteristics of a real diodetend to be “soft”; that is, the reverse leakage currentgradually increases toward the breakdown current asthe reverse–bias voltage increases. For the SPICEmodel, the reverse leakage current is modeled by theparameter IS which is constant out to the breakdownvoltage. This produces a “hard” breakdowncharacteristic for the model.

(l) The current at the breakdown voltage 1EV is dependentupon IS and BV. For convergence, IBV is restricted tovalues determined by

(3.34)IBVIS(T) BV

Vt(T)

where the saturation current IS and the thermal voltageVt must be calculated at the largest value of simulationtemperature by Equations 3.21 and 3.7, respectively.

(m) IBV is often not consistent with the breakdown currentIBV of a real diode at the specified breakdown voltage.



SPICE Diode Model ParameterExtraction Methods

The methods given in this section for the extraction of theSPICE diode model parameters are based on data acquiredfrom a real device, Table 6 lists the necessary data requiredfor the extraction of certain parameters. This data may betaken from actual measurements or from characteristic plotsavailable on most data sheets. For data sheet information, itis assumed that the plots represent a typical device and thatthe SPICE model is valid for these devices. The tools neededfor the extraction methods include a suitable scientificcalculator (programmable, if possible) which is capable ofperforming statistical calculations, and an understanding oflinear and nonlinear least–squares curve fitting methods.

Table 6. Diode Data Requirements for SPICE ModelParameter Extraction

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data RequiredÁÁÁÁÁÁÁÁÁÁ

Parameters Extracted

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Forward dc characteristics; forward diodecurrent (ID) versus forward diode voltage (VF).


IS, RS, N


Junction capacitance characteristics;reverse–bias junction capacitance (Cj) versusreverse bias voltage (VR).


CJO, VJ, M


Reverse recovery time (trr) versus forwarddiode current (IF).


TT


Forward voltage (VF) temperature coefficientversus forward current (ID), or reverse current(IR) versus temperature.


EG, XTI

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁBreakdown voltage characteristics.

ÁÁÁÁÁÁÁÁÁÁBV, IBVÁÁÁÁÁÁÁÁÁÁÁÁÁ


Noise measurements (parameters usually setto default values).


KF, AF


Other parameters for which the defaults areassumed: FC = 0.5 (typical)

ÁÁÁÁÁÁÁÁÁÁFC

For some parameters, more than one method of extractionmay be given. To determine which method is best inproviding a set of parameters yielding the most accuratesimulation, it is necessary to examine the differencesbetween actual device data and the results provided by themodel equations when using these parameters. By definingthese differences as errors, a single quantity can becalculated for each method that can be used as a basis ofcomparison. This quantity is called the error function E2which is the sum of the squares of the magnitudes of the perunit or normalized errors between actual device data and thecorresponding data generated by the model. This function isrepresented by the equation given below

(3.35)E2 |1|2 |2|2 . . . |n|2 |i|2

where εi, is the normalized error of the ith data point and nis the number of data points [7], For most modelingapplications, the method which produces the smallest valueof E2 is therefore judged the best method and the parametersextracted with this method provide the most accurate results.

Forward DC Characteristics (IS, RS, N)There are three methods for the extraction of the

parameters IS, RS, and N which model the large–signal dcbehavior in the forward–bias region. The first methodcomputes these parameters from three points taken from theforward–bias I–V curve and is appropriately called thethree–point I–V method. The second method uses a fixedvalue of RS (which can be taken from the results of thethree–point I–V method) and performs a linear regressiondata fit over the I–V curve to extract IS and N. The thirdmethod uses a fixed value of IS and performs a nonlineardata fit to extract N and RS, This method is useful if thereverse leakage current IR is specified and is to be modeledby IS.

1. Method 1 (Three–point 1–V method). To use thismethod, it is necessary to have a plot of the dcforward–bias I–V curve where the current axis islogarithmically scaled and the voltage axis islinearly scaled as shown in Figure 58. Estimatedvalues for the parameters can be found from thesteps outlined below.

(i) Select three data points from the I–V curve shown aspoints 1, 2, and 3.

(ii) Using the values of current and voltagecorresponding to these points as indicated, calculatevalues for the parameters RS, N, and IS from thefollowing equations

(3.36)

RS

(VF2 VF1) (VF1 VF3) 1nID1ID2

1nID1ID2

(lD2 ID1) (ID1 ID3) 1nID1ID2

1nID1ID2

(3.37)N(VF1 VF2) RS (ID2 ID1)

Vt 1nID1ID2

(3.38)ISID1

expVF1RSID1NVt

1



Figure 58. Forward–bias DC Data for the Three–pointI–V Method

1

2

i

3ID3

IDi

ID2

ID1

log ID

VF1 VFVF3VFiVF2

2. Method 2 (Linear regression with fixed RS). Withthis method, a linear regression data fit isperformed on the data covering the full range ofthe I–V curve to an equation of a straight linewhich represents the diode dc characteristics. Thisequation can be derived by combining Equations3.1 and 3.3 toproduce

(3.39)IDi IS expVFi RS IDiN Vt

1where IDi and VFi represent the ith data point takenfrom n data points on the I–V curve (shown inFigure 59), and RS is a known value of the ohmicresistance parameter. Assuming that theexponential term is sufficiently large, this equationcan be approximated by

(3.41)1n(IDi) 1n(IS) 1N VFi RS IDi

Vt

Taking the natural logarithm of both sides yields

(3.42)yi bm xi

which is the equation of a straight line expressedas

(3.40)IDi IS expVFi RS IDiN Vt

where:

(3.43)yi 1n(IDi)

(3.44)xi VFi RS IDiVt

(3.45)b 1n(IS)

and

(3.46)m 1N

The constants b and m are the y–axis intercept andslope, respectively, of the straight line representedby Equation 3.42, Values for these constants can befound by solving the matrix equation

n (xi) b (yi)

(xi) (xi)2 m (xi) (yi) (3.47)

where the summations are taken over the n datapoints. The calculated values of b and m are thenused to find IS and N from Equations 3.45 and 3.46where

(3.48)IS exp(b)

and

(3.49)N 1m

It is important to note that many scientificcalculators have built–in statistical functionscapable of performing linear regressioncalculations. For the type of equations used in thismethod, these functions can be used to extract theparameters IS and N directly. This, of course,eliminates the need to generate and solve Equation3.47. The steps involved in this method are outlinedbelow.

(i) Select a value of RS which maybe the valuecalculated from Equation 3.36 in Method 1.

(ii) Perform a linear regression data fit on n data pointstaken from the I–V curve to Equation 3.42 wherethe yi and xi data values are calculated fromEquations 3.43 and 3.44. This data fit will givevalues for b and m.

(iii) Calculate the values of IS and N from Equations 3.48and 3.49, respectively.

3. Method 3 (Nonlinear curve fit with fixed IS). Thetechniques used in this method are similar to thoseof Method 2 except that IS is held fixed, and RSand N are extracted. This method is particularlyuseful when IS must model a known value of thereverse leakage current. The equation for the curvefit is derived from Equation 3.39 where voltage isexpressed as the dependent variable; that is

(3.50)VFi N Vt1nIDiIS 1 RS IDi

where IDi and VFi again represent the ith data pointtaken from n data points on the I–V curve, and IS isa known value of the saturation current parameter.This equation may be expressed as a linearcombination of two functions of the current in theform of

(3.51)yi a1 f1(IDi) a2 f2(IDi)



where:

(3.52)yi VFi

(3.53)f1(IDi) Vt 1nIDiIS 1

(3.54)f2(IDi) IDi

(3.55)a1 N

and

(3.56)a2 RS

The constants a1 and a2 are found from the solutionof a matrix equation similar in appearance to that ofEquation 3.47 where

[f1(IDi)]2 [f1(IDi)f2(IDi)] a1

[f1(IDi)f2(IDi)] [f1(IDi)]2 a2

(3.57)[y1 f2(IDi)]

[y1 f1(IDi)]

The summations for the elements of this matrixequation are again taken over the n data points.Values of a1 and a2 found from this equation are thenused to calculate N and RS where:

(3.58)N a1

and

(3.59)RS a2

The details explaining more on the techniques ofthis method may be found in [8], The steps involvedin this method are outlined below.

(i) Select a value of IS which may be that of the reverseleakage current at a value of specified reverse–biasvoltage.

(ii) Generate the matrix Equation 3.57 where yi and thefunctions f1(IDi) and f2(IDi) are calculated fromEquations 3.52 through 3.54 for the n data pointstaken from the I–V curve.

(iii) Solve this matrix equation for the constants a1 anda2, and calculate the values of N and RS fromEquations 3.58 and 3.59, respectively.

Junction Capacitance Characteristics (CEO, VJ, M, FC)

There are two methods for the extraction of the parametersCJO, VJ, M and FC which model the behavior of thejunction capacitance. The first method computes theseparameters from three points taken from the reverse–biasC–V curve and is appropriately called the three–point C–Vmethod. The second method uses a fixed value of VJ (whichcan be taken from the results of the three–point C–Vmethod) and performs a linear regression data fit over the

C–V curve to extract CJO and M. In both methods, theparameter FC is set to the default value of 0.5 sinceforward–bias capacitance information is rarely presented onmost diode data sheets.

1. Method 1 (Three–point C–V method), To use thismethod, it is necessary to have a plot of thereverse–bias junction capacitance curve (Cj versusVR) where each axis is logarithmically scaled asshown in Figure 59.

(i) Select a data point at the lower end of the C–V curveshown as point 1. The voltage at this point should beless than the typical ideal value of VJ (that is, 0.8 voltto 1.0 volt).

(ii) Select two data points at the upper end of the curveshown as points 2 and 3. The voltages at these pointsshould be much greater than the typical ideal valueof VJ.

(iii) Using the values of capacitance and voltagecorresponding to these points as indicated, calculatevalues for the parameters M, VJ, CJO, and FC fromthe following equations

(3.60)M1nCj2

Cj3

1nVR3VR2

(3.61)k1 Cj1Cj21M (a constant)

(3.62)VJk1 VR1 VR2

1 k1

(3.63)CJO Cj1 1 VR1VJM

(3.64)FC 0.5

Figure 59. Reverse–bias Junction Capacitance Datafor the Three–point C–V Method

1

2

i

3

VR1 Log VRVF3VR2VRi

CJ1

log CJ

CJi

CJ2

CJ3



2. Method 2 (Linear regression with fixed VJ). Withthis method, a linear regression data fit isperformed on the data covering the full range ofthe reverse–bias C–V curve to an equation of astraight line representing the capacitancecharacteristics in this region. For reverse–biasvoltages, Equation 3.10 can be expressed as

(3.65)Cji CJO 1 VRiVJ M

where Cji and VRi represent the ith data point takenfrom n data points on the C–V curve (shown inFigure 59), and VJ is a known value of the contactpotential parameter. Taking the natural logarithm ofboth sides yields

(3.66)1n(Cji) 1n(CJO)M 1n 1 VRiVJ

which is the equation of a straight line expressed as

(3.67)Yi bm xi

where:

(3.68)yi 1n(Cji)

(3.69)xi 1n1 VRiVJ

(3.70)b 1n(CJO)

and

(3.71)mM

The constants b and m are the y–axis intercept andslope, respectively, of the straight line representedby Equation 3.67 Values for these constants can befound by solving a matrix equation similar to that ofequation 3.47 or by using the linear regressionfunction on the calculator. The parameters CJO andM are then calculated from

(3.72)CJO exp(b)

and

(3.73)Mm

The steps for this method are outlined below.(i) Select a value of VJ which may be the value

calculated from Equation 3.62 in Method 1.(ii) Perform a linear regression data fit on n data points

taken from the C–V curve to Equation 3.67 wherethe yi and xi data values are calculated fromEquations 3.68 and 3.69. This data fit will givevalues for b and m.

(iii) Calculate the values of CJO and M from Equations3.72 and 3.73, respectively, and the value of FC fromEquation 3.64.

Reverse Recovery Time Characteristics (TT)For the extraction of the forward transit time parameter

TT, the results of reverse recovery time (trr) measurementsderived by Leinfelder are employed [9]. The commonJEDEC test circuit for measuring trr shown in Figure 60while the idealized time–domain waveform of the diodecurrent resulting from this circuit is shown in Figure 61. Thereverse recovery time trr is commonly measured between thetime that the current (previously forward biased at IF) passesthrough zero going negatively and the time that the reversecurrent recovers to a value which is less than 10% of the peakreverse current IRM [10]. From Figure 61, trr is shown toconsist of ta, which is the time for the diffusion chargesupporting the reverse current to reduce to zero, and tb whichis the time for the depletion charge supporting the forwardvoltage to also reduce to zero. At the end of trr the diode isturned off and cannot sustain the reverse current. The totalcharge depleted from the diode during the reverse recoverytime is called the reverse recovery charge Qrr which is thesum of the charges Qa and Qb represented by the areas underthe waveform during times ta and tb, respectively. Byassuming that Qrr is dominated by the charge Qa so that thereverse recovery time trr, is approximately equal to ta, thefollowing equations can be generated from the informationshown on Figure 61. For the current fall–time tf:

(3.74)tf

IFdidt

where IF is the forward–bias diode current in amps and. di/dtis the slew–rate in amp/second of the current set by thecircuit. The expression for trr is:

(3.75)trr ta

IRMdidt

where IRM is the peak reverse current. Assuming that thereverse recovery charge Qrr is approximately equal to thecharge Qa, the area under the triangle corresponding to thischarge is computed from

(3.76)Qrr Qa

ta IRM2

t2a2 di

dt t2rr

2 di

dt

From Leinfelder’s work, an expression for Qrr was derivedfrom curve–fitting methods and was found to be accurate forsimulating trr. This expression is given as

(3.77) IF TT exp

n IFTT di

dt

Qrr IF TT exp tfTT



Figure 60. JEDEC Reverse Recovery Time Test Circuit

Figure 61. Idealized Time–domain Waveform for the Diode Current from the Test Circuit of Figure 60

CurrentViewingResistor

R2

Oscilloscope

Out

L1di/dt Adjust

+

_

C1

C2

D1

T1T2

SCR1T3

R1

1:1 D2

D3

0

0

didt

t

ID

IF

–IRM

Qa

ta

Qb

I(PK) Adjust

trr

tb

tf

where TT is, of course, the forward transit time parameter.By setting Equations 3.76 and 3.77 equal to each other, asingle expression involving TT is derived

(3.78)

t2rr2 di

dt IF TT exp

n IFTT di

dt

Thus, by knowing trr IF, and the current slew–rate di/dt,Equation 3.78 can be solved iteratively to find TT.Numerical algorithms such as Newton’s method can be usedon this equation which is easily implemented on aprogrammable calculator [7].

The steps for extracting the parameter TT are outlinedbelow.

(i) From the device data sheet, determine values for thereverse recovery time trr the forward–bias diodecurrent IF, and the slew–rate of the current waveformdi/dt.

(ii) Generate a function of the forward transit time TTwhere:

(3.79)

f(TT)t2rr2 di

dt IF TT exp

n IFTT di

dt

(iii) Use Newton’s method to solve Equation 3.79 for thevalue of TT that will set f(TT) to zero.



Temperature Characteristics (EG, XTI)There are three methods for the extraction of the

parameters EG and XTI. In each of these methods, only onetemperature–dependent expression is used where EG isselected and XTI is calculated. The first method uses thesmall–scale expression for the voltage temperaturecoefficient TCV found from the derivative of the voltage VFwith respect to temperature. The second method uses thelarge–scale expression for the TCV which is derived fromthe change of the diode forward voltage over largetemperature changes. The third method uses the expressionfor the temperature dependent saturation current IS given inEquation 3.21 to model the temperature behavior of thereverse leakage current IR. In all of the equations used inthese methods, temperature values must be convened todegrees Kelvin (K).

1. Method 1 (Small–scale TCV method). FromEquations 3.1 and 3.3, the expression for the diodeforward voltage as a function of temperature isderived as:

(3.80)VF(T) N Vt(T) 1n IDIS(T)

1 RS ID

Using the temperature–dependent expression forthe saturation current IS given in Equation 3.21, thesmall–scale or derivative form of the voltagetemperature coefficient TCV is derived and shownbelow

(3.81)

TCVdVF(T)

dT| ID, T

N Vt(T) 1n ID

IS(T) 1 (EG XTI Vt(T)T

where ID is the forward current and T is thetemperature at which the TCV is measured, usually27C. This equation is now used to find EG and XTIwith the steps outlined below.

(i) From the data sheet, determine the value of the TCV,and the values of the forward current ID, and thetemperature T corresponding to the TCV.

(ii) Select a suitable value for the energy gap EG whichshould correspond to the type of material used toprocess the diode (for example, 1.11 eV for silicon).

(iii) Solve for the value of the parameter XTI fromEquation 3.81 where

(3.82)

XTI 1Vt(T)

N Vt(T) 1n IDIS(T)

1 (EG T TCV)

T1 To

Figure 62. Typical Forward–bias Diode VoltageTemperature Characteristics

(27°C)

ID

VF (T1)

ID

VF (To) VF

2. Method 2 (Large–scale TCV method). Again fromEquation 3.80, the large–scale form of the voltagetemperature coefficient is derived and shownbelow

(3.83)

TCVVF(T)T

VF(T1) VF(T0)

T1 T0| ID

1T0

N Vt To 1n ID

ISTo [EG XTI Vt To T1 1nT1

To

T1 To ]where T1 is a temperature read from the data sheet,To is room temperature of 27C, VF(T1) and VF(To)are the diode voltages at these temperatures, and IDis the forward current, all of which are shown on thetypical I–V curve of Figure 62. This equation anddata are used to find EG and XTI with the stepsoutlined below.

(i) From the data sheet I–V curve plotted for at least twotemperatures, calculate the large–scale TCV at thecurrent ID from the expression

(3.84)TCVVF(T1) VF(To)

T1 To| ID

(ii) Select a suitable value for the energy gap EG whichshould correspond to the type of material used toprocess the diode (for example, 1.11 eV for silicon).

(iii) Solve for the value of the parameter XTI fromEquation 3.83where

(3.85)

CTIN Vt(To) 1n ID

IS(To) (EG To TCV)

Vt(To) T11nT1To

T1To



3. Method 3 (Reverse leakage current method).Assuming that the temperature behavior of thediode reverse leakage current IR can be modeledby that of the saturation current parameter IS,Equation 3.21 can be used directly to extract theparameters EG and XTI. From this equation, thetemperature–dependence of IR can be written as

(3.86)

IR(T1) IR(To) T1ToXTI1N

exp q EGN K 1

To 1

T1

where T1 is a temperature read from the data sheet,To is room temperature of 27C, and IR(T1) andIR(To) are the leakage currents at thesetemperatures, all of which are shown on the typicalIR versus temperature curve of Figure 63. Equation3.86 and this data are used to find EG and XTI withthe steps outlined below.

(i) From the data sheet reverse leakage current versustemperature (IR versus T) curve, select values of theleakage current at the temperatures To(27C) and T1that is, IR(To) and IR(T1).

(ii) Select a suitable value for the energy gap EG whichshould correspond to the type of material used toprocess the diode (for example 1.11 eV for silicon).

(iii) solve for the value of the parameter XTI fromEquation 3.86 where

(3.87)XTIN 1nIR(T1)

IR(To) qEG

k 1To 1

T1

1nT1To

Figure 63. Typical Reverse Leakage CurrentTemperature Characteristics

T

log IR

IR (T1)

IR (T0)

T027°C

T1

Reverse Breakdown Characteristics (BV, IBV)The steps for extracting the parameters BV and IBV are

outlined below.(i) From the device data sheet, determine the value of

the maximum dc blocking voltage VR(max).(ii) Multiply this voltage by a constant kBV having a

value ranging from about 1.3 to 2.0. This willaccount for the amount of manufacturersguard–band placed on the breakdown voltage inorder to insure the maximum voltage rating. Thisopera–don produces the value for the breakdownvoltage parameter BV where

(3.88)BV kBV VR(max)

(iii) Calculate the value IBV from

(3.89)IBV (1.1) IS(Tmax) BV

Vt(Tmax)

where the 1.1 multiplier insures the inequality inEquation 3.8 and Tmax is the maximum simulationtemperature.

Example Parameter Extractions for theMURHB4OCT Diode

As an example of the methods presented in the lastsection, the SPICE model parameters will be extracted forthe ON Semiconductor MURH84OCT rectifier with the aidof a programmable scientific calculator. Pertinentcharacteristic curves taken from the device data sheet will beused to provide the necessary data for the extraction. In theprocesses that are to follow, particular attention will beplaced not only on these curves but also on certain tabularinformation regarding maximum ratings and electricalcharacteristics. It is important that this data is included in thedetermination of the parameters since the model mustsimulate as closely as possible all characteristics of thediode.

It is industry practice to use 25C as room temperature.For the extraction process, the SPICE default of 27C willbe used instead and it will be assumed that the 2Cdifference will not produce any significant errors. At 27C,the value for the thermal voltage Vt which is used in severalof the extraction methods is calculated from Equation 3.7where

(3.90)Vt 25.85562 mV

For consistency, the order of parameter extraction willfollow that of the last section which begins with the forwarddc characteristics.



Forward DC Characteristics (IS, RS, N)The forward–bias I–V curve for the MURH840CT

rectifier is shown in Figure 64. Data from this curve will beused in each of the three methods for extracting theparameters IS, RS. and N.

1. Method 1(Three–point I–V method). As shown inFigure 64, three points are selected on the I–Vcurve at 25C as points 1 through 3. The currentand voltage values corresponding to these pointsare listed in Table 7. From Equations 3.36 through3.38, the following parameters are computed fromthis data for 27C:

(3.91)RS 40.20590 m

(3.92)N 2.854546

and

(3.93)IS 3.255398 A

2. Method 2 (Linear regression with fixed RS). FromFigure 64, the I–V data given in Table 8 isobtained. These 10 I–V data points aretransformed into x–y data points with Equations3.43 and 3.44 where

(3.94)yi 1n(IDi)

and

(3.95)xi VFi RS IDiVt

for i = 1 to 10. The value of RS used in Equation3.95 is that found from the results of Method 1 givenin Equation 3.91. For a linear regression data fitusing this transformed data, the matrix equationbelow is generated from Equation 3.47

(3.96)

390.3876 16911.02 m 528.9597

10 390.3876 b 2.420368 =

This equation is solved for b and m where

(3.97)b9.909661

and

(3.98)m 0.2600451

From Equations 3.48 and 3.49, values for theparameters IS and N are calculated, and presentedwith RS where

(3.99)IS exp(b) 49.69228 A

(3.100)N 1m 3.84554

and

(3.101)RS 40.20590 m

0.00

0.00

.00

00m

00m

00m0.00 500.00 m 1.00 1.500 2.00 2.50

3

2

1

25°C

100°C

VFM, Forward Voltage (V)

Figure 64. MURH840CT Forward–bias DC Datafor the Three–point I–V Method

Table 7. Data for the Three–Point I–V Method

ÁÁÁÁÁÁÁÁÁ

PointÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Diode Forward Current (ID) (A)


Diode ForwardVoltage (VF) (V)

ÁÁÁÁÁÁ

1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

1.0 m ÁÁÁÁÁÁÁÁÁÁÁÁ

0.423

ÁÁÁÁÁÁ


1.0 ÁÁÁÁÁÁÁÁÁÁÁÁ

0.973

ÁÁÁÁÁÁ



2.390

3. Method 3 (Nonlinear curve fit with fixed IS). Themaximum instantaneous reverse current (IR) at25C is specified on the data sheet as 10 µA.Since this current is modeled by IS, it is necessaryto keep its value less than 10 µA in order to satisfythe maximum IR specification. Thus, for thismethod, IS is set to 3.0 pA which is close to thevalue at 25C and 400 volts shown in the plot ofreverse current versus reverse voltage of Figure 69.From Table 8, the 10 I–V data points aretransformed into y data points with Equation 3.52,and the two current functions with Equations 3.53and 3.54 where

(3.102)Yi VFi

(3.103)f1(IDi) Vt 1nIDiIS 1

and

(3.104)f2(IDi) IDi

for i = to 10. The value of IS used in equation (103)is 3.0 A. For a nonlinear curve fit using thistransformed data, the matrix equation below isgenerated from Equation 3.57

(3.105)

43.00399 2276.01 a2 224.1998

1.202756 43.00399 a2 5.401513 =



This equation is solved for a1 and a2 where

(3.106)a1 2.986477

and

(3.107)a2 42.0777m

From Equations 3.58 and 3.59, values for theparameters N and RS are calculated, and presentedwith IS where

(3.108)N a1 2.986477

(3.109)RS a2 42.07777 m

and

(3.110)IS 3.0 A

Table 8. Forward Current Versus Forward Voltage forthe MURH840CTÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Diode Forward Current (ID) (A)


Diode Forward Voltage (VF) (V)


1.0 m ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.423



0.512



0.663


1.0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.973



1.408



1.706



1.925



2.104



2.256



2.390

To determine which of these three sets of extractedparameters best simulates this example device, the diodeforward voltage is calculated from the SPICE model andcompared to the data sheet value at the same current. Thesecalculations are performed for each set of the extractedparameters and listed in Table 9 where VFC is the voltagecalculated from

(3.111)VFC N VT 1nIDIS 1 RS ID

and ε is the error in percent between the data sheet voltageVF and VFC calculated as

(3.112)VFC VF

VF 100%

At the bottom of this table are the error functions (E2)calculated from the errors generated by the results of eachmethod in accordance with Equation 3.35. From anexamination of these values, it is clear that the parametersextracted with Method 1 produce the lowest value for E2.However, the forward voltage errors for currents beyond 1.0A (where the device is most likely to be used) aresignificantly larger than those produced by the parametersextracted with the other two methods. The parametersextracted by Method 2 yield lower errors in this range eventhough it has a larger error function. However, the value ofIS extracted by this method is too large to satisfy the datasheet specification for maximum IR. The parametersextracted by Method 3 produce the largest error function ofthe three while having errors above 1.0 A comparable tothose of Method 2. The value of IS used in this method does,however, meet the maximum IR specification. Plots of the dccharacteristics resulting from each of the three methods areshown in Figures 65(a) through 65(c). Both data sheet andcalculated voltages are plotted versus current to illustrate thecloseness of data fit.

At this point in the extraction process, a decision must bemade as to which of the three parameter sets should be usedto most accurately model the device in a practical andrealistic manner. If the maximum IR specification (at both25C and 150C) can be waived, then the parametersextracted with Method 2 should be used. If this waivercannot be exercised, which is often the case, then theparameters from Method 3 should be used in spite of theinaccuracy of the data fit for currents below 1.0 A. For thisexample, the maximum IR specification will be observedand the parameters extracted by Method 3 will be used.



Table 9. SPICE Diode Voltages and Percent Error for All Three Methods



Method 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Method 2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Method 3


MURH840CTData Sheet

Values


IS = 3.255398 µARS = 40.20590 m

N = 2.854546


IS = 49.69228 µARS = 40.20590 m

N = 3.845540


IS = 3.0 µARS = 42.07777 m

N = 2.986477ÁÁÁÁÁÁÁÁÁÁ

ID (A)ÁÁÁÁÁÁÁÁÁÁ

VF (V)ÁÁÁÁÁÁÁÁÁÁ

VFC (V)ÁÁÁÁÁÁÁÁÁÁ

(%)ÁÁÁÁÁÁÁÁÁÁ





1.0 mÁÁÁÁÁÁÁÁÁÁ





–28.2889ÁÁÁÁÁÁÁÁÁÁ


































































1–1729ÁÁÁÁÁÁÁÁÁÁ








4.8924ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

–ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

E2 = 0.0914765ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

E2 = 0.1155167ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

E2 = 0.1203895



IFM, Forward Current (A)



VF

M, F

orw

ard

Vol

tage

(V

)V

FM

, For

war

d V

olta

ge (

V)

VF

M, F

orw

ard

Vol

tage

(V

)

2.50

2.00

1.50

1.00

500.00m

0.001.00m 10.00m 100.00m 1.00 10.00 100.00

(a)

Figure 65. (a) MURH840CT DC Characteristics from Method 1; (b) MURH840CT DC Characteristics from Method 2; (c) MURH840CT DC Characteristics from Method 3

2.50

2.00

1.50

1.00

500.00m

0.00

3.00

1.00m 10.00m 100.00m 1.00 10.00 100.00

2.50

2.00

1.50

1.00

500.00m

0.00

3.00

1.00m 10.00m 100.00m 1.00 10.00 100.00

(b)

(c)

DataSheet

DataSheet

DataSheet

SPICE

SPICE

SPICE



Junction Capacitance Characteristics (CJO, VJ, M, FC)

The reverse–bias C–V curve for the MURH840CT isshown in Figure 66. Data from this curve will be used in eachof the two methods for extracting the parameters CJO, VJ,M and FC.

1. Method 1 (Three–point C–V method). FromFigure 66, a point is selected at the lower voltageend of the C–V curve as point 1. Points 2 and 3 areselected at the upper voltage end as indicated. Thecapacitance and reverse voltage valuescorresponding to these points are shown inTable 10.

From Equations 3.60 through 3.64, thefollowing junction capacitance parameters arecomputed from this data:

(3.113)M 0.4012080

(3.114)VJ 0.2159243 V

(3.115)CJO 152.7494 pF

and

(3.116)FC 0.5

Table 10. Data for the Three–Point C–V Method


ÁÁÁÁÁÁÁÁÁÁÁÁ

Diode ReverseÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Diode Junction


Point ÁÁÁÁÁÁÁÁÁÁÁÁ

Diode ReverseVoltage (VR) (V)ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Diode JunctionCapacitance (Cj) (pF)

ÁÁÁÁÁ1 ÁÁÁÁÁÁ0.01 ÁÁÁÁÁÁÁÁ150.0ÁÁÁÁÁÁÁÁÁÁ2

ÁÁÁÁÁÁÁÁÁÁÁÁ70.0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ15.0ÁÁÁÁÁ

ÁÁÁÁÁ3ÁÁÁÁÁÁÁÁÁÁÁÁ100.0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ13.0

2. Method 2 (Linear regression with fixed VJ). FromFigure 66, the C–V data presented in Table 11 isobtained. These 11 C–V data points aretransformed into x–y data points with Equations3.68 and 3.69 where

(3.117)yi 1n(Cji)

and

(3.118)xi 1n1 VRiVJ

C, C

apac

itanc

e (p

F)

Figure 66. MURH840CT Reverse–bias JunctionCapacitance Data for the Three–point C–V Method

1000

100

10

10.01 0.1 1 10 100

3

2

1

VR, Reverse Voltage

for i = 1 to 11. The value of VJ used in Equation 3.118 is thatfound from the results of Method 1 given in Equation 3.114.For a liner recession data fit using this transformed data, thematrix equation below is generated from Equation 3.47:

(3.119)

31.17795 133.9153 m –758.7108

11 31.17795 b –261.1229 =

Table 11. Junction Capacitance Versus

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reverse Voltage for the MURH840CT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Diode Reverse ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Diode Junction

ÁÁÁÁÁÁÁÁDiode ReverseVoltage (VR) (V) ÁÁÁÁÁÁÁÁÁ

Diode JunctionCapacitance (Cj) (pF)ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ0.01ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ150.0ÁÁÁÁÁÁÁÁ










ÁÁÁÁÁÁÁÁ100.00ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ13.0

This equation is solved for b and m where

(3.120)b22.58128

and(3.121)m0.4082637

From Equations 3.72 and 3.73, values for theparameters CJO and M are calculated, andpresented with VJ and EC where

(3.122)CJO exp(b) 155.9821 pF

(3.123)Mm 0.4082637

(3.124)VJ 0.2159243V

and

(3.125)FC 0.5

To determine which of these two sets of extractedparameters best simulates this example device, the diodejunction capacitance is calculated from the SPICE modeland compared to the data sheet value at the same voltage.These calculations are performed for each set of parametersand listed in Table 12 where CjC is the calculated capacitance

(3.126)CjC CJO 1 VRVJM

and ε is the error in percent between the data sheetcapacitance Cj and CjC calculated as

(3.127)CjC Cj

Cj 100%



At the bottom of this table are the error functions (E2)calculated from the errors generated by the results of eachmethod. From an examination of these values, it is clear thatthe parameters extracted with Method 2 produce the mostaccurate data fit to the actual device. Therefore, for this

example, the parameters extracted by Method 2 will be used.Plots of the junction capacitance characteristics resultingfrom both methods are shown in Figures 67(a) and 67(b).Both data sheet and calculated capacitance are plottedversus reverse voltage to illustrate the closeness of data fit.

Table 12. SPICE Diode Junction Capacitances and Percent Error for Both MethodsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁMethod 1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁMethod 2ÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

MURH840CTData Sheet

Values

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CJO = 152.7494 pFVJ = 0.2159243 V

M = 0.4012080FC = 0.5

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CJO = 155.9821 pFVJ = 0.2159243 V

M = 0.4082637FC = 0.5ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁVR (V)ÁÁÁÁÁÁÁÁÁÁÁÁCj (F)

ÁÁÁÁÁÁÁÁÁÁÁÁCjc (F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁε (%)

ÁÁÁÁÁÁÁÁÁÁÁÁCjc (F)

ÁÁÁÁÁÁÁÁÁÁÁÁε (%)ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ10.0 mÁÁÁÁÁÁÁÁÁÁÁÁ150.0 p

ÁÁÁÁÁÁÁÁÁÁÁÁ150.0000 p

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0.0000


ÁÁÁÁÁÁÁÁÁÁÁÁ2.0837ÁÁÁÁÁÁÁ













ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ–4.9492


ÁÁÁÁÁÁÁÁÁÁÁÁ–3.9222ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ1.0ÁÁÁÁÁÁÁÁÁÁÁÁ80.0 p

































ÁÁÁÁÁÁÁÁÁÁÁÁ127170 p

ÁÁÁÁÁÁÁÁÁÁÁÁ–2.1769ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁE2 = 0.021063, E2 = 0.018759

Cap

acita

nce

(pF

)

Cap

acita

nce

(pF

)

Reverse Voltage (V)

1000

100

10

10.01 0.1 1.0 10 100

Figure 67. (a) MURH840CT Junction Capacitance Characteristics from Method 1;(b) MURH840CT Junction Capacitance Characteristics from Method 2

SPICE

DataSheet

1000

100

10

10.01 0.1 1.0 10 100

SPICE

Reverse Voltage (V)

(a) (b)

DataSheet



Reverse Recovery Time Characteristics (TT)The typical value for the reverse recovery time trr for the

MURH840CT is 24.6 ns. This value is specified at aforward–bias current (IF) of 1.0 A and a current slew–rate(di/dt) of 50 A/s. The function equation for the forwardtransit time parameter TT generated from Equation 3.79 isshown below

(3.128)

f(TT) 15.129 109 TT exp

20 109

TT

0

From Newton’s method, the value of TT that satisfies thisequation is found to be

(3.129)TT 32.96688 nseconds

Temperature Characteristics (EG, XTI)The temperature characteristics of the MURH840CT are

illustrated in Figures 68 and 69. Even though only threetemperature points are given on these two plots, there issufficient data available to allow the parameters EG and XTIto be extracted with Methods 2 and 3. Since informationabout the small–scale voltage temperature coefficient is notknown, Method 1 will not be used.

1. Method 2 (Large–scale TCV method). Thelarge–scale TCV is obtained from theforward–bias I–V curve of Figure 68. At a forwardcurrent (ID) of 1.0 A, the diode voltages at 25C(To) and 100C (T1) are read as 0.973 V (VF(To))and 0.776V (VF(T1)), respectively. The value ofthe large–scale TCV is calculated from Equation3.84 where

(3.130)TCV2.62667 mVC

Selecting the value for the energy gap parameter EGas 1.1.1 eV which is typical for silicon, the value forthe parameter XTI is computed from equation (85)as

(3.131)XTI 23.702105

2. Method 3 (Reverse leakage current method). InFigure 69, the reverse leakage current (IR) versusreverse voltage at three temperatures is plotted. Ata reverse voltage of 400 V, the reverse currents at25C (To) and 150C (T1) are about 3.0 µA(IR(To)) and 300.0 µA (IR(T1)), respectively.Again for EG of 1.11 eV, the value for theparameter XTI is computed from Equation 3.87 as

(3.132)XTI 3.710244

In Table 13, the values of EG and XTI from each methodare listed along with the diode voltage calculated at a currentof 1.0 A for 27C and 100C, and the saturation currentparameter IS calculated at 150C. With the value of XTIobtained from Method 2, it is seen that the value of the TCVis close to that computed from the data sheet given inEquation 3.130. However, IS and, consequently, IRcalculated at 150C is found to be much larger than themaximum value of IR specified at this temperature which is500 µA. By using IR data over temperature to extract XTI aswas done with Method 3, IS at 150C is found to be veryclose to IR at the same temperature as shown in Figure 69.The value of the TCV computed with this XTI is. however,not as accurate that produced by the XTI of Method 2.Again, the specification for maximum IR will be observedand XTI computed by Method 3 given in Equation 3.132will be used.

Table 13. Comparison of Temperature Characteristics


ParameterÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Method


Parameteror VariableÁÁÁÁÁ

ÁÁÁÁÁ2 ÁÁÁÁÁÁÁÁÁÁ

3 ÁÁÁÁÁÁÁÁ

Units


EG ÁÁÁÁÁÁÁÁÁÁ

1.11 ÁÁÁÁÁÁÁÁÁÁ


eV


XTI ÁÁÁÁÁÁÁÁÁÁ



ÁÁÁÁÁVF (27C) ÁÁÁÁÁ

ÁÁÁÁÁ1.024041 ÁÁÁÁÁ

ÁÁÁÁÁ1.024041 ÁÁÁÁ

ÁÁÁÁV


VF (150C)ÁÁÁÁÁÁÁÁÁÁ



V


TCV ÁÁÁÁÁÁÁÁÁÁ

–2.698264 ÁÁÁÁÁÁÁÁÁÁ

–0.782152 ÁÁÁÁÁÁÁÁ

mV/C


IS (150C)ÁÁÁÁÁÁÁÁÁÁ

2.989445 m ÁÁÁÁÁÁÁÁÁÁ


A

100°C

25°C

100.00

10.00

1.00

100.00m

10.00m

1.00m0.00 500.00m 1.00 1.500 2.00 2.50

Figure 68. MURH840CT Forward–bias VoltageTemperature Characteristics

I FM

, For

war

d C

urre

nt (

R)

VFM, Forward Voltage (V) VR, Reverse Voltage (V)Figure 69. MURH840CT Reverse Leakage Current

Temperature Characteristics.

1000500

200100

502010

5

21

0.5

0.20.1

1 50 100 150 200 250 300 350 400

25°C

100°C

150°C

I R, R

ever

se C

urre

nt (

µA)



Reverse Breakdown Characteristics (BV, IBV)The maximum dc blocking voltage VR(max) for this

device is read from the data sheet as 400.0 V. Using aguard–band multiplier kBR of 1.3, the breakdown voltageparameter BV is calculated from Equation 3.88 to be

(3.133)BV 520.0 V

For a maximum simulation temperature of 150C, thecurrent at the breakdown voltage IBV is calculated fromEquation 3.89 as

(3.134)IBV 4.279703 A

SummaryTo summarize the extraction process, all SPICE parameters

for the MURH840CT are listed in Table 14. Characteristicplots generated by the SPICE diode model using theseparameters are shown in Figures 70a) through (d).

The SPICE diode model has been shown to consist of a setof equations and parameters derived from the theorydeveloped for an ideal diode. Certain modifications of theseequations allow the model added accuracy in the simulationof real diodes. Although the model has some limitations, itcan be used to realistically model the behavior of mostsemiconductor pn junction devices which includelow~current integrated circuit diodes, high–currentrectifiers, varactor diodes, Zener diodes, and Schottkybarrier diodes.

100

10

1

0.1

0.01

0.0010 0.5 1.0 1.5 2.0 2.5

27°C 100°C

VFM, Forward Voltage (V)

I FM

, For

war

d C

urre

nt (

R)

Figure 70. (a) MURH840CT SPICE Model Forward Voltage DC Characteristics at 27C and 100C;(b) MURH840CT SPICE Model Reverse–bias C–V Characteristics;

(c) MURH840CT SPICE Model Reverse Leakage Current Characteristics; (d) MURH840CT SPICE Model Reverse Breakdown Characteristics

1000

100

10

1

0.10 25 50 75 100 125 150

0

5

10

15

20600 500 400 300 200 100 0.00

(b)

(c) (d)

1000

100

10

1.01 0.1 1.0 10 100

VR, Reverse Voltage (V)

TJ, Junction Temperature (°C) VR, Reverse Voltage (V)

(a)

CJ,

Cap

acita

nce

(PF

)

I S, S

atur

atio

n C

urre

nt (A

)

I R, R

ever

se C

urre

nt (

A)



Table 14. SPICE Diode Model Parameters for the MURH840CT


Name ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Parameter ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

MURH840CT Value ÁÁÁÁÁÁÁÁÁÁ

Units


IS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Saturation current ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

3.0 µ ÁÁÁÁÁÁÁÁÁÁ

A


RS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ohmic resistance ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

42.07777 m ÁÁÁÁÁÁÁÁÁÁ

ohm


N ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Emission coefficient ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

2.986477 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁTT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Forward transit time ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

32.96688 n ÁÁÁÁÁÁÁÁÁÁ

sec


CJO ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Zero–bias junction capacitance ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

155.9821 p ÁÁÁÁÁÁÁÁÁÁ

F


VJ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Contact potential ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


V


M ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Junction capacitance grading exponent ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


ÁÁÁÁÁEG ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Energy gap ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


eV


XTI ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IS temperature exponent ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


ÁÁÁÁÁKF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Flicker noise coefficient ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁAF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Flicker noise exponent ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


ÁÁÁÁÁFC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CJ forward–bias coefficient ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


ÁÁÁÁÁBV ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reverse breakdown ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


V


IBV ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Current at BV ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


A

References1. A. S. Grove, Physics and Technology of

Semiconductor Devices, John Wiley and Sons,Inc., New York, NY, 1967.

2. A. Bar–Lev, Semiconductors and ElectronicDevices, Prentice–Hall International, Inc., LondonEngland, 1979.

3. U. S. Muller and T. I. Kamins, Device Electronicsfor Integrated Circuits, John Wiley and Sons, Inc.,New York, NY, 1977.

4. B. G. Streetman, Solid State Electronic Devices.Second Edition, Prentice–Hall Inc., EnglewoodCliffs, NJ, 1980.

5. SPICE 2 User s Guide. University of CaliforniaBerkeley, Electronics Research Labs, Berkeley,CA.

6. P. Antognetti and G. Massobrio, SemiconductorDevice Modeling With SPICE, McGraw–Hill BookCo., Inc., New York, NY, 1988.

7. C. F. Gerald, Applied Numerical Analysis,Addison–Wesley Publishing Co.. Reading, MA,1970.

8. B. Miller, “Curve Fitting Made Easy”, RF Design,Vol. 13, No. 6, June 1990, pp. 27 to 32.

9. B. A. Leinfelder, “Improving PN Junction ReverseRecovery Measurements”, PCIM, Part 1, January1988, pp. 41 to 44; Part 2, February 1988, Pp. 43to 45; Part 3, March 1988, pp. 52 to 54.

10. Rectifiers and Zener Diodes Data Book, TechnicalInformation Center, ON Semiconductor, Inc.,1987.



Chapter 4

Rectifier Diode Specifications and Ratings



Understanding the electrical and thermal characteristics

discussed earlier is helpful in design work. However, diodesare tested by the manufacturer and ratings are based oncompliance to given specifications. Therefore, a thoroughunderstanding of the meaning and significance ofspecifications and the development of ratings is mandatoryif devices are to be used reliably and economically.

Specification formats for rectifier diodes are establishedby the rectifier JEDEC1 committee for registered partnumbers, that is, 1NXXXX numbers. Althoughnon–registered house–numbered parts do not alwaysconform to the registration specification requirements, theJEDEC specifications generally are used as guidelines.Furthermore, adherence to letter symbols and definitions asdeveloped by JEDEC is widespread, although they havechanged in the past and will undoubtedly change in thefuture. The information presented is based on the presentstatus of the standard ANSI–EIA–282–A–19891, which isreferred to in this chapter as “The Standard.” The Standardwas developed by the JEDEC Committee on RectifierDiodes and Thyristors and approved by ANSI in September1989.

The Standard contains an extensive section on testing.Most of the tests described are not used for high volumeproduction, but are chosen to insure that a rectifier diode iscapable of meeting its ratings in a low–frequency, usually60 Hz powerline application. These tests are intended to beused to verify the specifications of JEDEC registered partnumbers and may be considered “referee” tests. In this

chapter, tests from the Standard are referred to as “StandardTests.”

Since the Standard has changed from previous issues, pastpractices are noted because many rectifiers used today wereregistered years ago. In addition, background information isgiven so that future changes may be understood.

Table 15 indicates the JEDEC symbols and terms used.The terms are also defined on the waveforms of Figure 71.The waveform sketches are typical of operation in ahalf–wave rectifier circuit driven from a sine wave source,which is the traditional basis of rating rectifier diodes. Twocycles of normal operation are shown followed by ahalf–cycle current surge of peak value ISFM. All values ofterms are referenced to the zero baseline. Instantaneousvalues of iF, vF and pF are shown at arbitrary times t1 and t2on the waveforms; the other terms apply at specific points.

In general, the subscripts carry a consistent meaningthroughout the waveforms. M stands for maximum or peak,S stands for surge, a nonrepetitive event, F stands forforward, and (AV) stands for an average value, sometimesreferred to as a dc value. R has a dual meaning: whenfollowing the primary symbol (i.e. I, V, P or T) such as in IRit stands for reverse; when preceding the subscript M, itstands for repetitive. A few exceptions occur to thenomenclature scheme and some terms can’t be shown on thewaveforms; these cases are described in Table 15.

1Joint Electron Device Engineering Council of the ElectronicIndustries Association (ETA) and National ElectricalManufacturers Association (NEMA).

Table 15. JEDEC Letter Symbols for Rectifier Specifications

Voltage Current Power Dissipation Junction

Forward Reverse Forward Reverse Forward Reverse Temperature

Total RMS VF(RMS) VF(RMS) IF(RMS) IR(RMS) – – –

Alternating Component RMS Vf Vr If Ir – – –

DC (No AC) VF VR IF IR PF PR TJ

DC (With AC) VF(AV) RV(AV) IF(AV)I0(1)

IR(AV) PF(AV) PR(AV) TJ(AV)

Instantaneous Total Value VF VR iF iR pF pR tJ

Maximum (Peak) VFM VRM IFM IRM PFM PRM TJM

Specific Maximum Peak Total2

Repetitive

Non–repetitiveSpecial cases3

–

–

VRRMVRWMVRSM

IFRMIFSM

IFM(OV)

IRRM

IRSM

–

–

–

–

TJRM

*TJSMTJFRMTJRWMTJFSM

1. Rectified Output Current, Average 180 Conduction Angle. 50 or 60Hz, Sine Wave Input2. Primarily used for ratings, see text3. Primarily used in developing current ratings, see Figure 71 and text.



Historically the major use of rectifiers is in the conversionof 60 Hz supply line voltage to direct current; consequently,the earliest JEDEC specifications consisted simply of acurrent rating, a voltage rating, and some measurement ofreverse current and forward voltage. Presently thermal andreverse recovery data is also required on all rectifier diodesbecause of their widespread use in power electronics.Graphs of the characteristics specified, showing the effect ofvoltage, current, and temperature, are frequently given onmanufacturers’ data sheets.

Various specifications (generally referred to as specs) incommon use are examined in this section. Their mainpurpose is to insure that the rectifier meets its current andvoltage ratings and to insure interchangeability of parts fromdifferent manufacturers.

TemperatureTemperature is the fundamental limiting factor of rectifier

diode power handling capability. Manufacturers establishcurrent and voltage ratings to insure long life using variouscriteria, but temperature is implicit in the ratings.

The maximum and minimum storage temperatures (Tstg)simply define the temperature range allowable duringstorage. Excessively hot temperatures can damage thedie–to–case bond or damage the package or alter electricalor thermal characteristics, which result in a field failurewhen the diode is placed into operation. Excessively coldtemperature can cause cracking of the chip with subsequentvoltage degradation or catastrophic failure. Minimumoperating temperatures are usually the same as minimumstorage temperatures.

The maximum repetitive peak temperature TJRRM is thetemperature used to establish VRRM. It usually is stated ondata sheets as TJ(MAX).

The maximum peak values TJSM and TJFRM, thoughgenerally not stated, are factors in determining the surgeratings and the average current ratings with capacitive orhigh form factor loads which cause high peak powerdissipation. The peak temperature limits are useful incalculating operating limits under unusual pulse or transientconditions; manufacturers usually provide these limits uponrequest. Temperature ratings during forward currentconduction are usually higher than those applicable when areverse voltage is present, because the combined stress oftemperature and voltage is the most sensitive chip failuremode.

Thermal ResistanceOlder rectifier diodes do not have thermal resistance

specified since the current rating alone as a function of diodereference temperature is a sufficient guide to operation in 60Hz rectifier currents. Diodes in power electronics circuits,however, experience a variety of waveforms not covered bycommonly published current derating curves. In order fordesigners to compute average junction temperature, thermalresistance is required and has been a JEDEC requirement fora number of years.

Peak junction temperature, particularly in applicationswhere the diode handles short duration pulses, can beconsiderably higher than the average temperature. Tocalculate peak temperature, the superposition technique iscommonly used with a curve of transient thermal impedanceor thermal response as described in Chapter 2. Not all classesof rectifier diodes are presently required by JEDEC tospecify transient thermal impedance, but manufacturersusually publish a thermal response curve on data sheets.

Some data sheets contain a specification called “apparentthermal resistance” which applies for a particular periodicwaveform of forward current. Apparent thermal resistanceis calculated such that the peak temperature is obtained bymultiplying the apparent thermal resistance by the averagepower produced by the waveform.

A typical thermal resistance or transient thermalimpedance test fixture uses the test diode’s forward voltageat a low “metering” current as an indicator of junctiontemperature. A switching circuit alternately applies a highcurrent pulse followed by the metering current. Forobtaining thermal resistance, the duty cycle of the highcurrent pulse is nearly 100%. A measurement of the diode“metering voltage” permits thermal resistance to becalculated. Two approaches find use in determining thermalresponse. The first uses high–power single–shot pulses ofvarying width followed by a measurement of the meteringvoltage. The second applies a pulse long enough to achievesteady state conditions; after the current drops to themetering level, the cooling curve is recorded by capturingthe change in forward voltage vs. time. Thermalcharacteristics tests require judgment regarding the mostappropriate technique and circuit to use as well as attentionto numerous details, which are discussed in “The Standard.”

Voltage RatingsVoltage ratings are not a characteristic; they cannot be

measured but are assigned by the device manufacturer andapply over the entire temperature operating range of thedevice. Ratings should not be exceeded under anycircumstances. All ‘repetitive ratings are referenced to ahalf–wave 60 Hz rectifier circuit using a resistive load.

The first three ratings to be discussed are generallyspecified with the same numbers for a particular rectifier.Although the theoretical basis of peak reverse voltageratings is the maximum reverse power generationpermissible before thermal runaway2 is reached, theseratings are frequently limited for other reasons, such as anabrupt change in slope of the V/I curve, surface effects, orinstability of the V/I curve. Voltage ratings are generallywell below avalanche breakdown voltage, but they may bea limiting factor at low temperatures.

2Voltage ratings generally apply when maximum rated forwardcurrent is flowing. Under this condition the thermal resistance,junction–to–ambient is necessarily rather low which preventsthermal runaway. However, thermal runaway can occur well belowrated voltage if RJA and TA are relatively high.



The equipment designer has the responsibility fordetermining that none of the reverse voltage ratings of thedevice are exceeded under any possible combination ofoperating or environmental conditions. If voltagesexceeding any of the reverse voltage ratings are applied to

the rectifier diode, a markedly increased probability offailure exists. The ratings do not imply any safety factor.Figure 71 illustrates the various voltages applicable torectifier diodes.

Figure 71. Illustration of JEDEC Letter Symbols. Sketches show Reverse and Forward Voltage and Current andJunction Temperature Excursion Resulting from the Developed Power

0

0

0

0

0

TJSM

TJRMTJFRM

TJ(AV)TJRRM

TJ

iFiF

VF

VF

VFM

VF(AV)

VFM

PF

PF

PF(AV)

PFM

VRVR(AV)

VRRMVRSM

iRiR(AV)

iRiRM

Peak Repetitive Reverse Voltage (VRRM)The rated peak repetitive reverse voltage (VRRM) is the

maximum allowable instantaneous value of the reversevoltage, including all repetitive transient voltages, butexcluding all nonrepetitive transient voltages that occursacross a rectifier diode. To verify the rating, a pulse of 100ms at a 60 Hz rate is used. The peak repetitive reverse voltagewhich occurs in a circuit is caused by rectifier diodeproperties in conjunction with circuit constants and is, tosome extent, under the control of the equipment designer.VRRM is a periodic voltage which includes commutationspikes and inductive kicks which occur each cycle.

Peak Working Reverse Voltage (VRWM)The rated peak working reverse voltage (VRWM) is the

maximum allowable instantaneous value of the reversevoltage that occurs across a rectifier diode, excluding allrepetitive and nonrepetitive transient voltages. The inputvoltage to the circuit must be such that the peak inversevoltage applied to the rectifier does not exceed rated VRWM.The rating is generally based upon operation in a half–wave

60 Hz rectifier circuit with resistive load and applies over theentire operating temperature range.

DC Reverse Blocking Voltage (VR)The rated maximum dc reverse blocking voltage is the

maximum allowable de reverse voltage, excluding allrepetitive and nonrepetitive transient voltages, across arectifier diode. The rating applies over the entire operatingtemperature range specified. Values for VR are usually thesame as VRWM. but VR may be restricted to operation at alower temperature than VRWM.

Peak Nonrepetitive Reverse Voltage (VRSM)The rated peak nonrepetitive reverse voltage (VRSM) is

the maximum allowable instantaneous value of reversevoltage across the rectifier, including all nonrepetitivetransient voltages but excluding all repetitive transientvoltages. The rating applies over the entire operatingtemperature range. The nonrepetitive peak reverse voltageoccurs as a random circuit transient, which may originatewithin the equipment or be externally generated. Transientvoltages may be minimized by transient voltagesurge–suppression components, as discussed in Chapter 9.



Reverse CurrentReverse leakage current is so low with the majority of

silicon p–n junction rectifier diodes that it plays no role indesign. In these cases, reverse leakage specifications areused to verify voltage ratings. However, the processing usedto reduce lifetime in the manufacturing of ultrafast diodescauses a marked increase in reverse leakage current.Schottky diodes also naturally exhibit high reverse leakage.Consequently, designs using fast diodes must include athermal runaway analysis and accurate reverse current datais essential. The following reverse current specifications arefound on manufacturer’s data sheets.

Maximum or Peak Reverse Current (IRRM)The maximum reverse current specified is the peak

reverse current through the rectifier with a half cycle of 60Hz sinusoidal rated reverse voltage (VRWM) applied atmaximum operating temperature – i.e., the case or leadtemperature at which the forward current is derated to zero,If reverse power is negligible, the maximum operatingtemperature is equivalent to TJRRM.

In production, IRRM is generally measured at roomtemperature using a pulse technique because it can be donequickly even though high–temperature leakage is notpredicted well by low–temperature measurements. Themanufacturer relies primarily on test data correlating high–and low–temperature leakage and on sample testing ofproduction lots to insure compliance to the registered hightemperature limits.

Average Reverse Current IR(AV)The average reverse current specified is the value of

reverse leakage current averaged over one complete 60 Hzcycle under the stated conditions of reverse voltage and casetemperature. Rated forward current may also be applied asan option. This specification serves as a comparison of therectifier to an ideal switch of zero leakage in the openposition.

Measurement of IR(AV) does not blend with a productionenvironment and is not specified on modem diodes. Olderregistered parts often specified IR(AV) usually with forwardcurrent applied. Its measurement requires use of a dynamicload test circuit which simulates operation in a half–waverectifier circuit at rated conditions, If accurate dynamic loadtest data is to be retrieved, the diode must be mounted on asubstantial heat sink having some external means of

controlling the case temperature to within a few degrees. Iftemperature control is not used, the inevitable differences inforward power dissipation between parts will causesignificant changes in case and junction temperature asdifferent parts are tested. The resulting data would be uselessbecause of the strong dependence of IR upon TJ.Consequently IRRM is the preferred reverse currentspecification.

DC Reverse Current (IR)The specified dc reverse current is the value of reverse

current through the rectifier under stated conditions of rateddc reverse voltage (VR) and case temperature. At one time,the temperature specified was required by JEDEC to be atthe maximum operating temperature, but, because ofthermal runaway problems, it may now be specified at alower temperature. Sometimes dc reverse current at roomtemperature is added to diode specifications bymanufacturers, but it is measured in production using apulse.

Reverse Breakdown Voltage V(BR)Breakdown voltage is not specified on rectifier diodes

unless the diode is a controlled avalanche type. For thenonavalanche diode, verification of reverse voltage ratingsis done by means of a reverse leakage current test

Controlled avalanche diodes have two values of“breakdown” voltage specified.

The first is a minimum breakdown specified at a lowcurrent chosen to place operation in the breakdown regionnear the “knee.” It may be performed using either a dc, ac,or pulsed signal source, but production testing favors use ofa short pulse at a low duty cycle. Normal circuit operatingvoltages should be below the minimum breakdown voltage.

The second breakdown test is designed to verify the peakreverse power dissipation specified for a controlledavalanche rectifier. The standard test consists ofsuperimposing a transient voltage to a diode which is biasedto rated VRWM. The series impedance and transient sourcevoltage are adjusted until the product of reverse voltage andreverse current equals the specified peak reverse powerdissipation of the diode. In production, a constant currentpulse is applied to all diodes even though the higher voltageunits will be stressed beyond their published ratings becauseadjustments are too labor intensive and fraught with chancesfor error.



Forward VoltageIn order to establish current ratings as a function of

reference temperature, a curve of forward voltage (VF) vs.forward current is required. To control VF a specification atone point is required for JEDEC registered part numbers.Manufacturers generally follow the JEDEC requirementsfor house–numbered parts and often provide supplementalinformation.

Maximum (Peak) Forward Voltage (VFM)The specified maximum forward voltage is the peak

forward voltage across the rectifier under the same statedconditions of current and case or lead temperature used forthe forward current rating (IO). VFM may be measured usingeither a 60 Hz half sine wave continuous current or a pulsetechnique to keep junction heating negligible. Using the halfsine wave, the temperature of the heat sink must becontrolled by external means so that variations in powerdissipation between parts do not influence case temperature,which is to be held to that specified for IO.

With the pulse method, no heat sink or complicatedtemperature control is necessary and, consequently, it ismore practical to use in production testing. A pulse widthunder 1 ms at a duty cycle under 2% is specified. Testing atthe peak current for which the rectifier is specified, i.e., πIOis required to insure that the power dissipation will alwaysbe below a certain limit, in order that temperature limits(TJFRM or TJRRM) will not be exceeded when operating atrated conditions.

The pulse test is performed at 25C (room temperature).The limit assigned to VFM when measured with the pulse testis different than that assigned with the 60 Hz test at elevatedcase temperature in order to account for the temperaturecoefficient of forward voltage, θV. Since parts from aparticular product line exhibit a consistent θV, a roomtemperature VFM test assures high temperature behavior.

Average Forward Voltage (VF(AV))The specified average forward voltage is the forward

voltage across the rectifier averaged over one completecycle under the same stated conditions of average forwardcurrent and temperature used for establishing the currentrating of the part. VF(AV) is measured in a circuit similar tothat used for VFM except that an average reading dc meteris used instead of a peak reading meter.

As previously discussed, temperature control is a problemwith the 60 Hz load test; furthermore, this measurement doesnot necessarily guarantee that the power dissipation will bebelow the limit necessary to keep temperature limits frombeing exceeded. This problem is illustrated by the sketch ofFigure 72. Two rectifiers having different forwardcharacteristics are shown by curves 1 and 2. Both have thesame VF(AV) but the rectifier of curve 2 has a higher VFM;it will have higher power dissipation than rectifier 1. As aresult, VF(AV) is no longer a required JEDEC spec and is seenonly on older data sheets.

VF(AV)

Figure 72. Two Rectifier Forward Voltage CurvesShowing Difficulty of Controlling Rectifier Power

Dissipation by Limiting Average Voltage

iF

IFM

IF(AV)

VFM2

VFM1

DC Forward Voltage (VF)The dc forward voltage is the forward voltage across the

rectifier for a given dc current and case temperature. Thisspec appears on older data sheets, but it does not adequatelycontrol VFM and requires case temperature control foraccuracy.

Forward Power DissipationFor convenience of the designer, data sheets usually show

a plot of average forward power dissipation versus averageforward current for various conduction angles. Data can beobtained by measurement or values may be obtained byusing one of several methods of calculation. The methodstrade off accuracy for simplicity and range from the watt peramp “rule of thumb”3 to integration techniques requiring theuse of a computer.

Power dissipation may be measured by utilizing thethermal resistance of the heat sink system. A thermocoupleis attached to a convenient place on the rectifier case or theheat sink, and the ac current is applied to the input of asuitable rectifier circuit, preferably the one intended for enduse. The temperature and average current levels are recordedafter thermal stability is achieved. Next, dc current is appliedand its level adjusted until the temperature equals thatobtained during the previous measurement. The forwarddrop is now easily measured and used to compute power.This measurement technique is particularly useful whenoperation is desired at frequencies where the transient powerlosses of the diode must be considered.3The watt per amp “rule of thumb” is based on the assumption thatfor any given value of average current, the average forwardvoltage is one volt. This approximation is conservative at smallforward currents and optimistic at the high values. it does,however, provide a reasonable guess of average power withoutknowing the forward voltage characteristic, providing theconduction angle is close to 1800.



Calculation of ac power losses is complicated by thenonlinear V–I characteristic of semiconductor diodes. Ifdiodes were to have a constant voltage drop with current, thepower waveform would naturally be a sine wave for sinewave currents. At low currents, the diode drop varies littlewith current; consequently, the power is nearly sinusoidal.At high currents, the resistance of the diode becomesdominant, producing a power waveform which approachesthe sine–squared waveshape, typical of a resistance. Toshow this behavior, Figure 73 compares actual diode powerwaveforms at a low and a high level to sine and sine squaredfunctions.

The most accurate way to solve for average powerdissipation is to use a computer in a piecewise integration.The computer is programmed to break the current sine waveinto a series of small equal increments. Power for eachincrement is found by programming the computer tomultiply VF – iF data obtained by interpolation of datapoints. The average power dissipation is the sum of theseincrements divided by the number of increments times theperiod of the waveform. Accuracy improves with thenumber of increments used. As a guide, average powerdissipation will be accurate to better than 1% if the wave isbroken into 20 equal increments and 25 data points are usedto define the forward voltage curve.

Conduction Angle in Degrees

Actual, IFM = 30 A

Sine

Actual, IFM = 4 A

1.0

0.8

0.6

0.4

0.2

020 60 80 100 120 140 160 1800 40

Sine2

Figure 73. Actual Diode Power WaveformsCompared to Sine Squared Waveforms for Half–Sine

Wave Currents

Rel

ativ

e V

alue

Another method of obtaining average power dissipation isto approximate the forward voltage curve with an offsetvoltage and a straight line as shown in Figure 74; thus,V = VO + mi, where m is the dynamic resistance of thediode.

Since

i IM sin t

(4.1)

PF(AV)1

2 ivd

O

π

12VOIM sin mI2 sin2 d

O

π

O

π

M

Integration and substitution yield

PF(AV)VOIM

mIM4

(4.2)

2

The offset voltage–straight line approximation is fairlyaccurate when the peak forward voltage is in the linearregion of the VF – iF curve. In the nonlinear or exponentialregion, this approach can be used if a different slope andoffset are determined for each value of forward current.Such a determination is an ideal task for a computer. Theresult is nearly as accurate as piecewise integration, but theprogram requires considerably less computer time thanpiecewise integration.

Figure 74. Approximation of a Diode ForwardCharacteristic for Accurate Calculation of Power

Loss when Handling a Sinusoidal Current Waveform

Slope = m

IFM

VO

I’F

V’F VFM

The computer is fed VF – iF data and programmed tolinearly interpolate between points as in the piecewisemethod. Based on the sine wave peak value and a percentageof peak value, the computer solves for two VF values, i.e.,for IFM and IF. VFM and VF are determined from the diodeforward voltage curve as shown in Figure 74. Using thesetwo values of forward voltage the slope and offset voltageare found from:

mVFM VFIFM IF

(4.3)

and

VO VFM IFMm (4.4)



Values calculated from Equations 4.3 and 4.4 are used inEquation 4.2 to find power at each current level. Bestaccuracy generally occurs when IF = 0.9 IFM since the majorportion of the sine wave’s energy is then between IF andIFM.

Of the methods used to calculate the power dissipation ina rectifier, the easiest and most conservative method makesthe assumption that the power dissipation waveform issinusoidal. Thus, the average power dissipation is found asfollows:

PF(AV)1

2PM sin d PM

(4.5)O

π

where PM IFM VFM.For convenience in calculating power dissipation,

Figures 75 and 76 permit form factor and peak to averagevalues to be found for a number of commonly usedwaveforms.

Figure 75. Form Factor for Various CurrentWaveforms

10

7.0

5.0

3.0

2.0

1.02.0 3.0 5.0 7.0 10 20 30 50 70 100 200

a, Conduction Angle (Degrees)

a

a

a

Full–Wave

Half–Wave

a

Figure 76. Peak to Average Ratios for VariousCurrent Waveforms

100

70

50

30

20

107.0

5.0

3.0

2.0

1.010 20 30 50 70 100 200

a, Conduction Angle (Degrees)

For

m F

acto

r, R

atio

of r

ms

to A

vera

ge V

alue

sR

atio

of P

eak

to A

vera

ge V

alue

s

a

aHalf–Wave

a

Current RatingsOf paramount importance are a rectifier diode’s current

ratings. Current ratings are conditional ratings – dependentupon the diode’s case or lead temperature and the waveformbeing handled.

Several temperature limits play roles in limiting thecurrent that a rectifier diode may handle. Some are indicatedon Figure 71, which shows the junction temperature of arectifier diode operating in a resistively loaded, half–wave,single–phase circuit under steady state conditions followedby a current surge. In addition, electro–migration may set alimit upon the current which a diode can conduct on acontinuous basis.

The repetitive peak junction temperature TJFRM sets onelimit upon rectifier current ratings. If exceeded, the die bondmay be weakened, resulting in an eventual field failure. Thelimit of TJFRM depends upon the manufacturers’ assemblytechnique. The temperature caused by the circuit dependsupon the amplitude and waveshape of the pulse train and thetransient thermal impedance of the rectifier.

Another limit is set by TJRRM (often called TJ(max)), whichis the temperature used for determining the voltage rating.Note that TJRRM is lower than TJ(AV) for sine waverectification shown in Figure 71. In practice the values ofTJRRM and TJ(AV) are close together.

A third limit on the rectifier diode’s current rating is thetemperature at which the lead material from the die to theterminal fuses or becomes excessively hot. Leadtemperature is a function of the lead material resistivity andthe rms value of forward current.

The junction temperatures, TJFRM and TJRRM, the leadfusing temperature and electro–migration must all beconsidered in determining a current rating. Since one or theother will limit current at different operating conditions,manufacturers often provide curves to aid in determiningsatisfactory operating limits.

A final temperature limit is the peak surge junctiontemperature, TJSM which is somewhat above the othertemperature limits. The surge is allowed only a few times(few being defined by JEDEC as less than 100) during arectifier diode’s life. The surge temperature is the basis forthe IFSM rating.



Average Forward Current (IO)It is customary, as well as a prior JEDEC requirement, to

rate rectifiers in terms of average current delivered to aresistive load at a specified case temperature in a 60 Hzhalf–wave circuit, unless another frequency is specified.(The 1989 version of Standard 282 indicates that the ratingsare to apply for input frequencies from 50 to 400 Hz). Therated current is defined as IO. The usual basis for this ratingis that tJ below TJRRM when VRWM is applied. The referencetemperature used for the IO rating is presently required byJEDEC to be chosen approximately 50C plus or minus25C lower than TJRRM.

It is safe to assume that IO is also an rms limit whenestimating current ratings for capacitive loads or other loadshaving a high form factor (ratio of tins to average current);however, such an assumption may unduly restrict theusefulness of a particular rectifier. Form factor andpeak–to–average ratio data are shown in Figures 75 and 76as functions of conduction angles for commonlyencountered rectifier waveforms. The data are useful inestablishing current ratings for conditions other than theones specified.

Figure 77 is an example of current derating data for a stud–or case–mounted rectifier. The dc (rms) limit is called out at39.3 A. A check of the curve data against the data of Figures75 and 76 reveals that the flat portion of the curves shows the

same rms limit; that is, for IFM/IF(AV) = 20, read a = 28 fromFigure 76. At this angle, read F ≈ 3.9 from Figure 75;therefore, IF(AV) = 39.3/3.9 ≈ 10 A, which agrees with curve6 on Figure 77. Consequently, derating curves forwaveforms other than the ones shown could easily bedetermined by using the data of Figures 75 and 76 to obtainthe rms limit and by using the given derating curves as aguide.

Sine wave derating data is based upon tJ = rated TJRRM ashort time after cessation of forward conduction. The dcderating curve, curve 1 on Figure 77 and the square wavederating curve, curve 2, are based upon TJRFM equalingrated TJRRM because the full reverse voltage may appearimmediately after forward conduction ceases. Note that thesquare wave curve, curve 2, is very close to the sine waveresistive load derating data; however, the average currentlimit is at 28 A rather than 25 A, since I(RMS)/I(AV) = 1.41 fora square wave.

Derating data for a lead–mounted rectifier is shown inFigure 78. Since no rms limit is indicated, it can be assumedthat it is greater than (3.9)(4.3) or 18.5 A by using data forIFM/I(AV) = 20 from Figures 75, 76 and 78. Therefore, otherwaveforms having a rms value below 18.5 A could be safelyhandled by the rectifier. For these other waveforms, it isappropriate to use the techniques outlined in Chapter 2 tocheck for TJFRM. It should be held to a reasonable limit.

Figure 77. Example of Current Derating Data whereRMS Limits are Evident as Flat Portions of the

Curves

28

24

20

16

12

8.0

4.0

075 85 95 105 115 125

3

4

5

2 1

6

dc, Continuous(Max IOC = 39.3 A

Sine WaveResistive Load

SquareWave

Curves Apply When Reverse Power is Negligible

Sine WaveCapacitiveLoads

20 10 5.0IFM =IF(AV)

TC, Case Temperature (°C)

I F(A

V), A

vera

ge F

orw

ard

Cur

rent

(A

mp)

75

3.0

6.0

115

2.0

5.0

12510595 135

1.0

4.0

085

7.0

145 155 165 175

Figure 78. Example of Current Data for a Rectifierwhich does not show an RMS Limit

Both LeadsTo Heat Sink

CapacitiveLoads

IFM IF(AV)

= π (Resistive/Inductive Loads

5

2010

TL, Lead Temperature (°C)

I F(A

V), A

vera

ge F

orw

ard

Cur

rent

(A

mp)



Peak Surge Forward Current (IFSM)The maximum allowable surge current (IFSM) is the peak

current that the rectifier can safely handle for a minimum of100 times in its lifetime. It is a nonrepetitive rating in thesense that the surge may not be repeated until thermalequilibrium conditions have been restored.

An illustration of the JEDEC specified conditions isshown in Figure 79. The rectifier is subjected to ratedvoltage and current until thermal equilibrium is establishedat the rated case temperature. One half–cycle of surgecurrent, IFSM. is applied, followed by one half–cycle ofnonrepetitive rated–voltage, VRSM. If the junctiontemperature is driven too high by the current, thermalrunaway will occur and the rectifier will be destroyed.

In some applications, such as motor control, severalcycles of surge current called overload current I(ov) must behandled. To illustrate overload capability, data similar tothat of Figure 80 are given on many data sheets. Duringeach cycle of overload, peak reverse voltage must notexceed VRWM. The intent of the JEDEC specification is tohave tJ at its rated repetitive limit prior to the nonrepetitivesurge. To provide additional information, surge andoverload data are often given for the situation when thediode is in a circuit that is turned on at room temperature(the 25C curves in Figure 80).

Multicycle surge data is used most often to selectproperly rated circuit breakers and/or to providesufficient series impedance to prevent diode damageshould a load fault occur. Another common use foroverload data is to check rectifier operation in a lineoperated circuit with a capacitive input filter, as shown bythe circuit of Figure 81(a). Worst–case current surgesoccur when the switch is closed as the input sine waveapproaches its positive peak (Figure 81(b)). Thewaveform should be compared to the overload ratingcurve. In many cases a visual comparison of the currentsurges is all that is necessary. For example, the rectifierhaving the surge ratings of Figure 80 will handle twosurges of 80 A each when TJ = 175C or 120 A when TJ =25C. The circuit current peaks of Figure 81(b) are 110 Afor the first pulse and 60 A for the second one; the otherpulses are so low by comparison that they need not beconsidered. Unless the rectifier is used near its uppertemperature limit of 175C, operation is safe and nofurther checking is necessary.

Figure 79. Conditions for the JEDEC Surge Current Specification

Rev

erse

Vol

tage

For

war

d C

urre

bt

Working Peak reverseRWMVoltage, V

Working Peak reverseRWMVoltage, V

1/2 Cycle Non–Repetitive PeakRSMReverse Voltage, V

Rated Forward Current, IO

Surge Current, IFSM

Rated Forward Current, IO

1/60 Sec.



40

100

30

80

20

60

15

150I F

SM

, Pea

k H

alf W

ave

Cur

rent

(A

mp) VRWM May Be Applied

Between Each Cycleof Surge, TJ Noted isTJ Prior to Surge

Non–RepetitiveRepetitive

TJ = 25°C

Number of Cycles at 60 Hz

Figure 80. Example of Surge Current Data (appliesfor MR850 Series)

1.0 7.0 105.03.0 202.0 30 50 70 100

25°C

175°C

175°C

When more precise information is needed, the simplestway to match the rectifier diode capability to the circuit’sdemands is to convert the overload surge data of Figure 80and the waveform produced by the circuit (Figure 81(b)) toequivalent rectangular waves using the thermal modelingtechniques discussed in Chapter 2. A satisfactory model isobtained if the amplitude is chosen to equal 70%4 of the peakvalue of the actual pulse and the width adjusted to contain thesame area. Therefore, the data of Figure 80 can beinterpreted as applying a rectangular pulse or a train ofpulses having an amplitude of 70% of the sine wave peakamplitude and a width of 5.83 ins.4 70% is chosen because the power pulse under surge conditionswill be cIose to a sin2 function (see Chapter 2).

40

100

80

20

60

0

120

0 40 503020 6010 70 80 90 100

Figure 81. Start up Transients in a Half–Wave Line Operated Rectifier Circuit: (a) Half Wave Circuit with Large Input Capacitor; (b) Worst–case Turn–on Waveform (IF(AV)=100 mA)

C

(b)

t, time (ms)

(a)

I F, F

orw

ard

Cur

rent

(A

mpe

res)

RS

RL



Using the methods of calculating instantaneous junctiontemperature presented in Chapter 2, the maximumtemperatures at the end of the power pulse and at the timewhen the reverse voltage reaches its peak may be calculatedfor the rectifier data and for the circuit. If the temperatureallowed during surge is higher than that produced by thecircuit, satisfactory operation can be assumed.

Rectifier diode data sheets sometimes show a subcyclesurge rating curve, so called because the time duration is lessthan the 8.33 ms time base of a 60 Hz wave. The rating isapplicable for events which occur while the diode isoperating at rated load current and working reverse voltage.However, the diode is not required to block immediatelyafter the subcycle surge current ceases. The rating is usefulwhen selecting a fast acting, current–limiting fuse forprotecting the diode during a load fault. Since fuses are ratedin terms of I2t (current squared seconds) an I2t rating for thediode is often given in place of a subcycle rating curve. Useof subcycle surge data is shown in Chapter 9.

SwitchingOriginally switching specifications were not required on

JEDEC registered rectifier diodes, since the principalapplications were at 60 Hz. Because of the widespread useof rectifier diodes in power electronic equipment, reverserecovery characteristics are presently required in order tobetter assure interchangeability in high–frequencyapplications. The terms used in switching specifications aredefined in Chapter 1.

Reverse RecoveryThe test circuit used to obtain data and specification limits

for reverse recovery usually conforms to one devised byJEDEC about 1970. As shown on Figure 82, the circuitconsists of a means of discharging the energy stored in acapacitor though a series inductor and the diode under test.By properly choosing circuit constants, a half–sine wavepulse of forward current is passed through the diode. Thecircuit can be modified to also store the charge involvedduring reverse recovery on a capacitor whose voltage willyield the reverse recovery charge, QRR.

R3

+_ D2

CURRENT

DUT

VIEWINGRESISTOR

SCR

60 HZLINE

L

C

R1

R2

D1

Figure 82. Standard JEDEC Reverse Recovery Test Circuit

The registration requirement states that ta, tb, IRM(REC),and QRR and are all to have maximum limits. The testconditions are also specified. Suggested conditions areTC = 25C, pulse repetition rate = 60 pulses per second anddi/dt = 25 A/µs. The peak forward current must be at leastthree times IO; the pulse width is required to be over fivetimes the diode’s reverse recovery time to ensure that dud:is fairly linear and nearly constant through zero crossingfrom IFM/4 to IRM(REC) and also to allow enough time forthe steady state charge gradient to be established in thediode. The pulse duty cycle is low to ensure negligibleheating of the diode.

The circuit of Figure 82 is difficult to adapt to thenecessary conditions required to measure ultrafast diodes,i.e., those with tRR under 100 ns. A fundamental limitationis caused by the inductor used to generate the forwardcurrent pulse. When the diode enters the high–impedancephase (tb) during turn–off, the circuit will ring at the resonantfrequency determined by the inductor and the diodecapacitance[2]. Therefore the circuit cannot measure tbunless it is longer than the period of the resonant circuit. Thelatest version of the Standard, therefore, shows an alternatemeans of driving the diode with square pulses derived froma power MOSFET circuit. The circuit shown in Figure 83,allows a higher di/dt; typical of modern power electroniccircuits, to be obtained and circuit inductance can be keptsmall.

Diode reverse recovery waveforms observed in the circuitof Figure 82 typically appear as shown by one of thesketches in Figure 84. Waveforms obtained in the circuit ofFigure 83 are similar, except the forward current pulse issquare. At the end of the period denoted as ta, the diodeimpedance begins to rise, allowing reverse current to decay.The nature of the decay during the tb interval depends uponthe impurity profile of the diode, the test or circuit electricalconditions and, unfortunately, the loop inductance andparasitic elements of the circuit.

If the waveform decays smoothly in a somewhatexponential manner, as shown by the waveform ofFigure 84(a), the diode is said to exhibit “soft recovery.” If,at some point during tb, the waveform exhibits a rapidchange in slope, as shown by the other waveforms, therecovery is described as abrupt. Abrupt recovery isundesirable because it often produces circuit ringing, whichcauses EMI problems in electronic equipment.



Figure 83. Test Circuit for Ultra–Fast Rectifier Diodes

DUT V

iV1

V2

V3

S1

S2

V4

RL

t1

t2

0.25 IR(Rec)

Figure 84. Test Current Waveforms for Various Types of Rectifier Diodes under Test in the Circuit of Figure 82

a) Soft Recovery b) Abrupt Recovery

Time Time

c) Abrupt Recovery d) Abrupt Recovery

0.25

IFMtff

tb

IR(Rec)

IR(Rec)to

ta

IR(Rec)to

tatb

tffIFM

ta tb tatb

tff tff

IR(Rec) IR(Rec)

To aid a designer in judging the nature of the tb waveform,a recovery softness factor (RSF) is sometimes stated. RSFis the ratio of tb to ta; therefore, larger numbers imply softerrecovery. Inspection of the waveforms of Figure 84,however, reveals that RSF is of limited value. It does providea valid comparison of waveforms (a) and (b), but waveforms(c) and (d) yield an RSF comparable to those of the softwaveform of (a), when in fact (c) and (d) are abrupt. If tb isnot accurately measured, a non–trivial task[2], then RSF isof no value at all.

The waveforms of Figure 84 show a long–standing andstill–preferred referee method of defining reverse recoverytime. The method of measuring ta is uniform but themeasurement of time tb differs depending upon the characterof the waveform. For waveforms which cross the axisbecause of circuit ringing, such as (b) and (c), tb is measuredfrom IRM(REC) to the zero crossing. For waveformsapproaching the axis asymptotically as shown by (a) and (d),the zero crossing is determined by a straight line drawn fromIRM(REC) through the point where iRR has decayed by 75%.

The preferred measurement technique must be donemanually using an oscilloscope and consequently is not usedin a production test environment. It is much more commonto see recovery time measurements referenced to 10% ofIRM(REC) or to a specified reverse current level.

The difficulty of performing accurate recovery timemeasurement increases with the speed of the diode.Consequently, a method of measuring the “recoveredcharge” QRR without measuring the reverse recoverywaveform has been proposed [2] and equipment is availableto perform the test electronically. In addition, calculation ofrecovery time has shown good agreement with carefullymeasured data for most diodes. The recovered charge is theamount of charge delivered to an external circuit by thediode during turn–off. It is the area under the reverserecovery waveform (see Figure 84). The electronictechnique uses a means of transferring the recovered chargeto a capacitor where it is stored and whose voltage is easilymeasured by a voltmeter. The method is described in theStandard and also in MIL–STD–750 C, method 4061.1.



Forward RecoveryForward switching characteristics are seldom specified on

rectifier data sheets even though a diode’s turn–on behavioris important in a number of power electronic applicationsoperating at high frequencies. The reason for the absence offorward recovery data is that manufacturers are reluctant toadd tests not demanded by design engineers. The importanceof having fast turn–on and low dynamic impedance isevidently not fully appreciated.

Although a forward switching test is not required onJEDEC registered diodes, the Standard shows a procedurefor measurement and has defined terms. The test circuit isvery simple; it is a series loop consisting of a pulsed current

source, the diode and a means of measuring current. Thecurrent source is usually obtained by adding a seriesresistance to a voltage generator. The open circuit voltage ofthe source is required to be 50 V or 3VFM, whichever isgreater. The rise time of the input wave should be fastenough so that it does not affect the diode’s performance.

The turn–on voltage wave, with pertinent terms noted, isshown on Figure 85. VFRM, tfr, and the steady state pulsevoltage, VF, are specified. The measurement point VFR fortfr is 1.1 VF when VFRM between 1.3 V and 10 V WhenVFRM exceeds 10 V, VFR is specified at 3VF. Should VFRMbe below 1.3 V, VFR = VF + 1/2 (VFRM – VF).

0.1 VF

tfr

VF

Figure 85. Turn–on Waveform Showing JEDEC Defined Terms.

V

B

VFRM

VFR(1.1 VF UNLESS OTHERWISE SPECIFIED)

References1. “Standard for Silicon Rectifier Diodes,”

ANSI/EAI–282–A–1989, Electronic IndustriesAssociation, 2001 Pennsylvania Aye, N.W. Washington,D.C. 20006

2. “B. Leinfelder, “Improving PN Junction ReverseRecovery Measurements,” Pans 1, 2, and 3,“Powerconversion and Intelligent Motion,” Jan., Feb.,March, 1988.



Chapter 5

Basic Single–Phase Rectifying Circuits



In this chapter, basic characteristics of single–phasecircuits with resistive loads are discussed. Polyphasecircuits are treated in Chapter 6; filter design follows inChapter 7. Results of all the calculations in this chapter arepresented in Table 16.

Basic OperationWhen considering any rectifying circuit, a designer

desires to know the magnitude of the direct voltage andcurrent, the regulation of the load voltage, and the efficiencyto be expected from the rectifying process. All these valuesdepend upon a number of variables–such as the type ofcircuit, the constants of the supply, the characteristics of therectifying unit, and the nature of the load–which complicatethe analytical solution. However, certain simplifyingassumptions idealize the circuit so that a useful analysis canbe made.

The simplest circuit for rectifying single–phasealternating torrent gives half–wave rectification. Such acircuit is indicated in Figure 86(a), where the bold–facedarrow represents the rectifying unit and the direction ofconventional current flow. Assume (1) an ideal AC sourcewithout resistance, (2) the impressed emf is a pure sinewave, (3) the rectifying unit has zero resistance in theforward direction of current and infinite resistance in thereverse direction, and (4) the load is purely resistive. Withthese assumptions, let a sine wave alternating voltage asshown in Figure 86(b) be impressed across the input to therectifying circuit. The output is a rectified half–wave ofcurrent as indicated in Figure 86(c), which is of a sine form,since i = (VM/RL) sin ωt. During the second half of the cyclethe rectifier blocks current. The current flowing through theload resistance RL produces an iRL voltage drop which hasa half sine waveform. The voltage waveform across therectifier is shown by Figure 86(e).

Table 16. Characteristics of Basic Single–Phase Rectifier Circuit with Resistive LoadsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Rectifier Circuit Connection

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Half–Wave

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Full–WaveCenter–Tap

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Full–WaveBridge


Load Voltage and Current WaveshapeCharacteristic

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÉÉÉÉÉÉ

ÉÉÉÉÉÉ


ÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉ


ÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁDiode Average Current

lF(AV)/IL(DC)


ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0.50

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0.50ÁÁÁÁÁÁÁÁÁÁÁÁÁ


Diode Peak CurrentIFM/IF(AV)


3.14


3.14


3.14ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Form Factor of DiodeIF(RMS)/I(DC)


1.57


1.57


1.57


Diode RMS CurrentIF(RMS)/IL(DC)


1.57ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


0.785


RMS Input Voltage Per Transformer LegVi/VL(DC)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

2.22ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


1.11ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Peak Inverse VoltageVRRM/VL(DC)


3.14


3.14


1.57


Transformer Primary RatingVA/PDC




1.23


Transformer Secondary RatingVA/PDC




1.23ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Total RMS Ripple, %ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

121ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


48.2ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Lowest Ripple Frequency, fr/fiÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



2ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Rectification Ratio (Conversion Efficiency), %ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



81.2

1. P I2L RL VL ILRL



Current RelationshipsSince the function of rectification is to convert alternating

current to direct current, the equivalent value of the directcurrent output is of primary interest. Its value is measured bythe dc ammeter placed in the circuit of Figure 86(a).

This dc value is the average value of th6 instantaneousrectified current over one cycle or a period corresponding to2π radians. Average values can be determined by a graphicaland arithmetic process by measuring the instantaneous valueof current at a series of equally spaced points along the timeaxis and then dividing the sum of these values by the totalnumber of points in a cycle. A more accurate solution maybe obtained by measuring the area under the rectified currentpulse and dividing by 2π. The more direct solution is toapply calculus to the problem, thus:

IDC IAV1

2 IM sintd(t) (5.1)

0

π

Solving,

IDC2IM2 0.318 IM (5.2)

An ac ammeter inserted in the rectifying circuit ofFigure 86(a) gives a different reading from the dc meter firstconsidered. This difference arises because the ac meterregisters effective or root–mean–square (rms) values [1]rather than average values. The heating or effective value ofa current varies as the square of the instantaneous current.Hence, to determine the effective value of the rectifiedcurrent graphically, it is first necessary to plot squaredvalues of the instantaneous current as suggested by thedotted i2 curve on Figure 86(c). The effective area under thedotted i2 curve may be obtained by the graphical pointmethod, or by calculus:

Effective area = I2 sin2td(t)0

π

M

(5.3) I2Mt

2 sin 2t

4 I2

M

20

π

and the effective or rms current,

effective area

2

0.5 IM(5.4)

IAV = 0.318 IM

Figure 86. Circuit and Wave Shapes for Half–Wave Rectification: (a) Half–Wave Circuit;(b) Input Waveform; (c) Current Waveform; (d) Current Waveform with Pertinent Points Indicated;

(e) Rectifier Voltage Waveform

A

(a)

i

ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ

ÉÉÉÉÉ1 cycle

π

(c)

(b)

(d)

(e)

0

+

–

0

+

0

+

i = –VMR L

π

IM= VMR Lsin ωt

RL

V = VM sin ωt

VRRM = VM

IM

IRMS = 0.5 IM

V = VM sin ωt

i2



The average and effective values of rectified current forthe half–wave circuit are indicated in Figure 86. Theintegration of Equations 5.1 and 5.3 follow the standardprocedures for obtaining the average and effective, values ofperiodic functions.:

Half–wave circuits are not used with transformers unlesscurrent requirements are small, because the dc component ofoutput current must flow through the transformer. The dccomponent causes core magnetization and high core lossesresult. However, the half–wave circuit finds limited use inlow–current, direct–line rectification.

Two types of circuits are used for full–wave, single–phaserectification. One circuit uses a transformer with a mid–tapin the secondary winding, as shown in Figure 87(a). Theother uses a bridge configuration, shown in Figure 87(b),which requires two extra rectifier diodes, but the secondaryrequires only half as much winding. Performance is similarexcept that the bridge diodes are subjected to only half thepeak inverse voltage of the center–tap circuit (to bediscussed later). Since both half–waves of current passthrough the transformer (dividing in the secondary of thecenter–tap circuit), there is no dc component of flux in thetransformer core to increase core losses.

Using the same assumptions made for the precedinghalf–wave rectifier circuit, the relation between the inputand output sides of either full–wave rectifier circuit may bereadily calculated. Since both halves of the cycle are

rectified, the current and voltage on the input side are normaleffective values; rms values on the output side are the sameas for a sine wave while the dc or average values are twicethat of a half–wave circuit. The relationships are shown inFigure 87(d).

Form FactorRectifier circuit efficiencies can be related to a quantity

termed form factor (fl. It is the ratio of the heatingcomponent of a wave to the dc component:

FI(RMS)I(AV)

(5.5)

Substituting the values from Equations 5.2 and 5.4 intoEquation 5.5, the form factor for a half–wave circuit is 1.57.The form factor is the same for each rectifier element in thefull–wave systems because each side conducts on oppositehalf cycles. However, the form factor of the output currentof a full–wave circuit is much better. It is found from thevalues shown on Figure 87; i.e., F = (0.707)1(6.636) = 1.11.

Form factor takes on significance when rectifiers musthandle high peak currents at low duty cycles, since the powerlosses in the diodes and transformers are much higher thanencountered with sine wave pulses. Applications where highform factors are the rule occur when capacitive input filtersare used, when batteries are being charged, and whenrectifiers are used with SCRs in phase control circuitry.

RLVac

Vac

RL

IRMS = 0.707 IMIAV = 0.636 IM

V = VM sin ωtVM

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

Figure 87. Circuit and Waveshapes for Full–Wave Rectification: (a) Center–Tap Circuit;(b) Bridge Circuit; (c) Input Waveform; (d) Output Waveform

(a)

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ1 cycle

(c) (d)

+

–+

– +

(b)

– +

π2π2

IM = VM /RL

Ri



Utilization FactorBecause of the waveforms involved in rectifier circuits,

transformers are not used as efficiently as when they handlepure sinusoidal waveforms. A measure of rectifier circuitmerit is the utilization factor (UP), defined as the ratio of thedc output power to the transformer volt–ampere ratingrequired by the primary and/or the secondary. Forsingle–phase circuits with resistive loads, the UF can befound by using the relationships between rms and averagecurrent. As defined,

UFIAVVAV

IRMSVRMS(5.6)

For the half–wave circuit:

UF (0.318 IM) VDC(0.51 IM)(2.22 VDC)

(5.7) 0.286

For a full–wave circuit, transformer utilization is muchimproved because conduction is continuous. In thecenter–tap circuit, although both the secondary windings arepresent, only one is used at a time. The utilization factor forthe secondary is found as

VF(0.318 IM)(2)VDC

2(0.5 IM)(1.11)VDC 0.572

In the primary, the whole winding is naturally incontinuous use; the input power is, assuming a 1:1 windingfor simplicity, (√2/2)IMVi(RMS).

Therefore,

VF(0.318 IM)(2)VDC

( 2 2)IM(1.11)VDC 0.812

The bridge rectifier circuit has the same utilization factoras the primary of the full–wave center–tap circuit. The UPof the single–phase bridge is quite high and is only exceededby certain polyphase circuits.

However, utilization factor does not tell the whole story inthe case of a half–wave circuit since only one half of the sinewave of current is passed, and the windings carry a dccomponent of current which magnetizes the iron core andincreases the core losses. As a result, half–wave rectifiers areonly practical for use with a transformer when the currentrequirement is very small.

HarmonicsWhen the current in a transformer winding does not have

a sinusoidal waveform, harmonic currents are present. Theharmonic content can be found by a Fourier analysis of thewaveform or a spectrum analysis of current in an operatingcircuit. For half sine waves the percentage of each harmonicwith respect to the fundamental is given in Table 17:

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Table 17. Harmonic Percentages of a Half Sine Wave


Harmonic ÁÁÁÁÁÁ

2ndÁÁÁÁÁÁ

3rd ÁÁÁÁ

4thÁÁÁÁÁÁ

5thÁÁÁÁÁÁ

6th


% ÁÁÁÁÁÁ

21.2ÁÁÁÁÁÁ

0 ÁÁÁÁ

4.2ÁÁÁÁÁÁ

0ÁÁÁÁÁÁ

1.8

Harmonics cause transformer core loss and hysteresis lossto be higher than with single–frequency operation becausethese lasses increase with frequency. The extra loss causedby the second harmonic in the resistive loaded rectifiercircuit is not high compared to other losses in thetransformer and is usually neglected. ‘With other loads,losses caused by harmonics can be appreciable and not onlycomplicate transformer design but also cause trouble withthe electrical distribution system.

Ripple FactorThe rectified voltage and current output consists of a

series of unidirectional waves or ripples. For someapplications these variations are not objectionable, but forothers they must be smoothed out by filters. For all cases, therelative magnitude of the ripple is important in thecomparison of rectifying circuits. The comparison is madein terms of ripple factor. Ripple factor is the ratio of effectivevalue of the alternating components of the rectified voltageor current to the average value. In equation form ripplefactor is

rfeffective rectified ac load component Irms

average load current (IDC)(5.7)

Percent ripple is a term used interchangeably with ripplefactor and is simply the ripple factor expressed in percent (rfX 100).

The various components of current associated with ripplefactor are illustrated in Figure 88. Figure 88(a) shows thesingle current pulse of half–wave rectification, andFigure 88(b) shows the splitting of the pulse into a dccomponent and a ripple component. Figures 88(c) and 88(d)give an actual separation of the components, andFigure 88(e) illustrates the components for full–waverectification.

In accordance with the preceding definition, the ripplefactor is the ratio of the effective current represented by I’ ofFigure 88(c) to the dc component shown in Figure 88(d).This ratio may be computed by following the precedingform of calculation. Thus, the instantaneous ac ripplecomponent i may be represented as

i i IDC, (5.8)

and the total rms value of the ripple component Irms is

Irms1

2 (i IDC)2 d

(5.9)

2

0

Irms1

2 (i2 2IDCi2DC) d 2

0



0.318 IM

I(AV)

Figure 88. Illustration of Ripple Factors forHalf–Wave and Full–Wave Circuits

ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ


ÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÉÉÉÉ

(a)

(b)

(c)

(d)

(e)

i

i’

Ripple factor 1.21

Ripple component

dc component

Ripple factor0.48

0.318 IM

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ0.636 IM

The first term in this expression is the rms value of the totalcurrent I(RMS). The integral of the idθ part of the secondterm integrates to the average value I(DC), and the last termis simply I2

(DC) after the limits are applied. Thus:

Irms I2RMS 2I2DC I2DC (5.10)

By combining Equations 5.10 and 5.5, the ripple factormay be expressed as

rf F2 1 (5.11)

(F is the form factor of the output current, not the diodecurrent.) Substitution of values from Figures 86 and 87 intoEquation 5.11 gives

0.5IM

0.318IM 1.57Half–wave F

0.707IM0.636IM

1.11Full–wave F

rf 1.572 1 1.21

rf 1.112 1 0.482

Rectification RatiosThe preceding discussion of ripple factor leads to the idea

that the heating losses (I2R) which occur in the various partsof the complete rectifier circuit are increased by the irregularwaveforms of current that are inherent in the rectifyingprocess. This loss may be illustrated by comparing theheating loss caused by an ideal direct current to that resultingfrom the actual current waves of Figures 88(a), 88(b), and88(c). The ratio of dc power in the load to ac rms power inthe load is termed the rectification ratio, Ó and is written as

I(DC)RL

I(RMS)RL(5.12)

2

2

Substitution of the appropriate current values in terms ofIm yields:

.406 (half–wave),

.812 (full–wave),

ÓÓ

The rectification ratio is sometimes called the conversionefficiency. This term is somewhat misleading since theoverall power efficiency for the assumed conditions (zerolosses) must be 100%. The real significance of therectification ratio is that it gives a qualitative indication ofthe increased heat losses that occur wherever a pulsatingcurrent flows through resistance elements. A second methodof expressing the increased heat losses is by the current formfactor, discussed earlier, which is the ratio of theroot–mean–square to the average value.

Voltage RelationshipsThe input voltage required to achieve a given dc output

voltage (VDC) is a necessary piece of design information.The output voltage (VDC) is IDC RL and Equation 5.2 statesthat IDC = 0.318 IM for the half–wave circuit. The peakcurrent (IM) is VM/RL and the rms input voltage

Vi Vm 2

Combining these relationships yields:

Vi 2.22 VDC (half–wave)

The full–wave circuit produces twice the dc level as thehalf–wave circuit for a given input voltage per transformerleg. Consequently,

Vi 1.11 VDC (full–wave)

Another voltage of importance is the maximum voltagewhich the rectifier must block when it is not conducting. Itis called the peak inverse voltage, or, in rectifier parlance,VRRM. VRRM is the sum of the peak input voltage and therectifier peak output voltage at the same instant in time.

In the half–wave circuit of Figure 86, the output voltageis zero when the input voltage reaches its negative peak;therefore,

VRRM VM ( 2) (2.22 VDC) 3.14 VDC.(half–wave)



In the full–wave center–tap circuit, the output voltage ismaximum at VM, because of rectifier conduction on oneside, when the other side must block VM. Therefore, VRRM= 2 VM, but now the rms input voltage, VM is 1.11 VDC,consequently

VRRM ( 2) (2)(1.11) VDC 3.14 VDC.(full–wave center–tap)

For the bridge, the blocking rectifiers are across the outputvoltage; therefore, the maximum reverse voltage is VM. Inthis case,

VRMM ( 2) (1.11) VDC 1.57 VDC.(full–wave bridge)

Circuit VariationsMany applications require equal positive and negative

power supply voltages. Circuits shown in Figure 89 arecommonly used to provide dual output voltages. Thesecircuits are simply combinations of the standard half–waveand center–tapped full–wave circuits previously discussed.

Chapter 2 illustrates how a rectifier bridge assembly may beproperly handled thermally in the circuit of Figure 89(b). Ifthe loads are balanced, the circuit of Figure 89(a) does nothave a dc component in the transformer core, therebyovercoming the major objection to the half–wave circuit.

The standard rectifier diode, being just a two terminaldevice, has no internal means of regulating current. It isoften used, however, in conjunction with controllablerectifiers such as SCRs in circuits similar to the hybridbridge rectifier shown in Figure 90.

Similar circuits have a multitude of applications but aremost often used with fixed input voltages to vary the averagepower to the load. A change in gate pulse delay to the 5CRserves to vary the conduction angle, α, as desired. Thehybrid bridge may also be used to regulate the load powerover a range of input voltages or perform a combination ofthese functions. In such circuits the form factor can be quitehigh. For this reason, additional derating must be applied tothe rectifier diodes current rating when operation is confinedto small angles of conduction.

RL

iF

RL1

RL2

RL1

RL2

ÎÎÎ

ÎÎÎ

ÉÉÉÉ

Figure 89. Single–Phase Supplies with Dual Output Voltages: (a) Dual Half–Wave Supply;(b) Dual Full–Wave Supply (a bridge assembly is convenient to use in this application)

+

–

+–

+

–

+–

(a) (b)

Figure 90. Typical Hybrid Bridge Rectifier with Resulting Diode Current Waveform

Pulse

α Conduction Angle

ÉÉÉÉÉÉ

ÉÉÉÉÉÉ



SummaryAll the commonly used characteristics of low–frequency

single–phase rectifier circuits with resistive loads have beendiscussed in this chapter. Results are summarized inTable 16. From the standpoint of maximum utilization of thetransformer and reverse voltage rating of the rectifierdiodes, the bridge circuit is superior to the other two.Although it requires more diodes, overall cost is generallysimilar because of simpler transformer construction andlower diode VRRM requirements. At voltages of 12 VDC andbelow, the power efficiency of the bridge becomesunacceptable because the output current must pass through

two diodes in series. Furthermore, the diode VRRM rating isof little concern. The full wave center–tap circuit is thereforepreferable at low voltages. For economy reasons, thehalf–wave circuit finds use when current requirements aresmall, particularly if direct connection to the power line isallowable.

Filters are generally used on the output of single phaserectifying circuits. Circuit characteristics are similar to thoseshown in Table 16 when inductive loads or choke inputfilters are used, but characteristics change drastically withcapacitive loads or filters. Chapter 7 discusses filtering andits effect upon rectifier circuit performance.



Chapter 6

Polyphase Rectifier Circuits



A multiplicity of polyphase circuits have been devised,but only a few are of relative importance. This chapterdevelops some of the basic relationships to show thedemands placed upon the rectifier diode by some of the morepopularly used circuits. More exhaustive studies are givenin the references [1] [2].

Polyphase transformer windings may be wye (Y) (alsocalled “star”) or delta (∆) connected. When Y connected asin Figure 91(a), voltages from any terminal (i.e.. A, B, or C)to the neutral (N) are called phase voltages and appear on avector diagram as shown in Figure 91(b). The voltages VAB,VBC, and VCA are called line voltages. The line voltages arealso 120 out of phase, but because they are the vector sumof two phase voltages they are √3 times larger and aredisplaced 30 from the phase voltages as shown inFigure 91(c). A common method of transformer connectionis the delta connection indicated in Figure 91(d). The voltageacross the delta terminal is the same as the line voltage, andconsequently bears the same relationship to the phasevoltage as the line voltage.

By summing voltages from two phases in a transformer,a voltage bearing any desired amplitude and phase shift froma phase voltage may be obtained. Thus, there is no inherentlimit to the number of phases which may be generated.

When a three–phase system is driving a balanced load, thepower is given by

P 3 VI, (6.1)

where P = total power

V = rms phase or line voltage

I = corresponding rms phase or line current.

VOBB

VOC

VCA

VOA

VBC

VOA

VOB

VOC

Figure 91. Y and Connections and AppropriatePhase Relationships:

(a) Wye–Connected Transformer Windings;(b) Phase Voltage Relationships;

(c) Complete Voltage Vector;(d) Delta–Connected Transformer Windings

B

A

A b

C C ca B

(a) (b)

(c) (d)

°30

°30

°30

°120

°120

°120

C C

c

B

b Aa

N

B

General Relationships in Polyphase Rectifiers

The analysis of polyphase rectifier circuits may be greatlysimplified if the transformers and rectifiers are idealized;that is, they are assumed to possess no resistance or leakagereactance. Furthermore, the diode is assumed to have a zeroforward voltage drop and a zero reverse current. Byidealizing the components, simple general expressions canbe derived for polyphase rectifiers.

Figure 92 shows the rectified voltage waveform for thegeneral case of a polyphase rectifier circuit (See Figure 93for the simplest polyphase rectifier circuit). Conductiontakes place through the rectifier with the highest voltageacross it. Note that neither the voltage nor the current is everzero in the load. The instantaneous load voltage VL ofFigure 92 is equal to the voltage of the conducting phase, andis given by

vL VM sin (6.2)

where VM = the peak phase–to–neutral voltage.

VM

Figure 92. Rectified Voltage Waveforms forMultiphase Rectifier Circuit. The number of output

pulses per cycle is designated

π2m

Current RelationshipsAs with single–phase circuits, the average or dc value of

output current is of prime interest. It is the average value ofthe instantaneous rectified current over one cycle or a periodof 2π/m radians (see Figure 92). Using integral calculus, theaverage current per phase equals the rectifier diode currentand is given by

IF(AV)IM2 sin d (6.3)

(π / 2)+(π / m)

(π / 2)+(π / m)

Solving,

IF(AV)IMsinm (6.4)

The total load current (IL) is in times the current perconducting phase or

IL(DC) IMm sin m (6.5)



The rms current (If) is also of interest as it determinesheating in the transformer winding resistance and in thediode. The rms value varies as the square of theinstantaneous current and may be obtained by integration.

If IF(RMS) 12 IM sin d12 (6.6)

(π / 2)+(π / m)

(π / 2)+(π / m)

2 2

Solving:

If IF(RMS) IM 12 m 12

sin 2m

12

(6.7)

It is convenient to have the diode rms current in terms ofaverage current rather than the peak value so that the formfactor of rectifier current may be determined. Equation 6.4may be combined with Equation 6.7 to obtain

FIF(RMS)IF(AV)

2m

12 sin 2

m

sin m

(6.8)

For m greater than or equal to three, Equation 6.8 may beapproximated as

F m (6.9)

The simplification is done by using the small angleapproximation, sin θ = θ. Ordinarily, the error caused by theapproximation would be too large for θ = 60, but becauseof the nature of Equation 6.8, the overall error is small. Forexample, for m = 3 Equation 6.8 yields F= 1.76 whileEquation 6.9 yields F= 1.73.

Voltage RelationshipsIn order to design the transformer, the required input

voltage from each transformer secondary leg (Vi) for a givenoutput voltage must be known. Since VM = RLIM andVL(DC) = RLIL(DC), substituting these relationships intoEquation 6.5 results in

VL(DC) VMm sin m (6.10)

The rms value of Vi is VM√2/2. Substituted andrearranging Equation 6.10 yields

ViVL(DC)2 m sin

m (6.11)

The peak repetitive reverse voltage or peak inversevoltage applied to the rectifier, VRRM, is also of vitalinterest. In full–wave center–tapped circuits, it is the sum ofthe instantaneous load voltage and peak input voltage.

To obtain exact values, the precise output waveform mustbe considered. However, VRRM cannot exceed 2 VM and inmany polyphase circuits VL(DC) approaches VM. To beconservative, let VL = VM; since Vi(PK) = VL√2, usingEquation 6.11 above, VRRM can be put in terms of voltageas

VRRM 2VL(DC)m sin

m (6.12)

For bridge connections, VRRM is simply the peak outputvoltage, which is one half of that given by Equation 6.12.

Transformer UtilizationHigh transformer utilization is one of the chief benefits of

polyphase rectifier systems. The utilization factor (UF) isthe ratio of do power in the load to the volt ampere or powerrating of the transformer and is commonly used incomparing rectifier circuits. As defined,

UFI(AV)V(AV)(OUTPUT)

I(RMS)V(RMS)(INPUT)(6.13)

Values for the terms depend upon whether primary orsecondary UF is desired. The utilization factor of theprimary is found by considering the total volt–ampererequirement of the transformer and the total do load power.The secondary utilization factor generally considers only aparticular winding’s contribution to the load and thevolt–ampere requirement of the winding.

Utilization factors can only be computed by studying thevoltage and current relationships in a particular circuitconfiguration. It can be shown [1] that the highest obtainableutilization factor occurs when in = 3, i.e., conduction occursin a winding for 120. In this case, the winding is idle fortwo–thirds of the cycle. The larger the number of phases, thelonger is the idle time and the less effectively the transformeris being used. To achieve high utilization factors and also theadvantages of 6– or 12–phase operation, bridge circuits areused and special secondary winding arrangements havebeen devised which permit m to be three for the secondarywindings; however, in is effectively six or twelve for theoutput voltage waveform.

RippleThe same relationships for ripple hold true for polyphase

circuits as with single–phase circuits. In Chapter 5, it isshown that the ripple factor of the output voltage may beexpressed as

rfVmn

2 VL(DC) 2

(nm)2 1 (6.14)

An expression for the various ripple harmonics is obtainedfor the general polyphase rectifier system by applyingFourier analysis to the waveform. The resulting expressionis given by

rfVmn

2 VL(DC) 2

(nm)2 1 (6.15)

whererf = ripple factor due to the nth harmonic,Vmn = peak voltage of the nth harmonic,VL(DC) = dc output voltagem = number of output pulses per cycle,n = order of the harmonic.In Equation 6.15, the only harmonics involved are

multiples of in. Thus, for m = 3, only the third, sixth, ninth,etc., harmonics of the input voltage contribute to the ripplevoltage.



Rectification RatioThe last general item of interest is the rectification ratio Ó.

sometimes referred to as waveform or conversionefficiency. It is the ratio of dc power in the load (I2

L(DC)RL)to rms power in the load (I2

L(RMS)RL). In the ratio of terms,the load resistance cancels and IL(RMS)/IL(DC) is the loadcurrent form factor. Consequently, the rectification ratiomay be expressed as

1[F(load)]2 (6.16)

To find the load current form factor, the total rmscomponent of load current must be known. It may be foundfrom Equation 6.6 by recognizing that the total current willbe m times the phase current. Therefore.

IL(RMS) m2 IM sin d12 (6.17)

(π / 2)+(π / m)

(π / 2)+(π / m)

2 2

Solving,

IL(RMS) IMm2 m 12

sin 2m

12

(6.18)

By comparing Equation 6.1810 Equation 6.7, it can beseen that rms load current is simply √m times rectifier legcurrent and the load current is in times the rectifier legcurrent. Therefore, the form factor of the load is simply 1/√mtimes the rectifier leg form factor as given by Equation 6.8.Accordingly:

F(load)

2mm

12 sin 2

m

sinm(6.19)

An attempt to simplify Equation 6.19 as done withEquation 6.8 yields unity. Therefore, it must be used withoutapproximation to yield meaningful results. SubstitutingEquation 6.19 into Equation 6.16 yields

2m sin2(m)

m

12 sin 2

m (6.20)

OverlapIn practice current does not switch instantaneously from

one diode to another Overlap is observed, that is, a period oftime where current flows in two diodes, each in differentbranches. Overlap is caused because leakage inductance andthe stored charge in diodes will not allow current in theindividual phases to change instantaneously.

One effect of overlap is to reduce the output of the rectifiercircuit. This reduction, along with the voltage drop in the

rectifier and transformer should be calculated and used tocorrect the output voltage predicted ideally. The overlapproblem is discussed more fully in Chapter 7 and in thereferences.

Common Polyphase Rectifier CircuitsA discussion of the basic and more popular rectifier circuit

configurations follows. Pertinent characteristics of eachcircuit are listed in Table 18.

Three–Phase Half–Wave Star Rectifier CircuitThe three–phase star rectifier circuit, often referred to as

the three–phase half–wave rectifier, is illustrated inFigure 93(a). The associated voltage waveforms are shownin Figure 93(b). Because the circuit is economical, it findslimited use where dc output voltage requirements arerelatively low and current requirements are too large forpractical single–phase systems. The circuit is worthstudying mainly because it is a building block of morecomplicated systems. By using the equations developed inthe preceding section, the various items of interest may becalculated as given in Table 18.

The dc output voltage is approximately equal to the phasevoltage. However, the diodes must block approximately theline–to–line voltage, which is √3 times the phase voltage. Inaddition, the transformer design and utilization aresomewhat complicated in order to avoid transformer coresaturation caused by the do component of current flow ineach secondary winding.

Figure 93. Circuit (a) and Waveform (b) for theThree–Phase Star or Half–Wave Rectifier Circuit

(a)

(b)

CB

A

N

0

RL

VAN VCNVBN

VL



Three–Phase lnter–Star Rectifier CircuitThe three–phase inter–star or zig–zag rectifier circuit

shown in Figure 94 overcomes some of the transformerlimitations of the three–phase half–wave star circuit. Theprimary and secondary windings each consist of two coils,with pairs of coils forming a phase, located on differentbranches of the transformer core. The windings on the samecore branch are connected such that the instantaneousmagnetomotive force is zero. Although this connectioneliminates the effects of core saturation and reduces theprimary rating to the minimum of 1.05, it does so at theexpense of economy, since it does not utilize the voltage ofeach winding to yield the highest possible out put voltage.The two secondary windings in series give a voltage of√3VS1 instead of 2VS1. This results from the addition of twosinor voltages that are 600 apart. Consequently. thesecondary volt ampere rating increases to 1.71 from the 1.48value shown in Table 18. Otherwise, circuit constants are thesame as the three–phase star circuit and therefore are notlisted in Table 18.

Figure 94. Three–Phase Inter–Star or Zig–Zag Circuit

A

B

C

A’B’C’

AC’

C

B

B’

A’

VS

VS1

VS

RL

Table 18. Summary of Significant Three–Phase Rectifier Circuit Characteristics for Resistive LoadsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁHalf–wave

ÁÁÁÁÁÁÁÁ


Double Wyewith Interphase

ÁÁÁÁÁÁÁÁF ll–wave


Wye–Delta ConnectionsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Half–waveStarÁÁÁÁÁÁÁÁBridge


with InterphaseTransformer

ÁÁÁÁÁÁÁÁ

Full–waveStarÁÁÁÁÁÁÁÁ

ParallelÁÁÁÁÁÁÁÁÁÁ

SeriesÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Average Current through DiodelF(AV)/IL(DC)


0.333


0.333


0.167


0.167


0.167


0.333


Peak Current through DiodeIFM/IF(AV)


3.63


3.14


3.15


6.30


6.30


6.30


Form Factor of Current through DiodeIF(RMS)/I(DC)

ÁÁÁÁÁÁÁÁ1.76





ÁÁÁÁÁÁÁÁÁÁ2.46ÁÁÁÁÁÁÁÁÁÁÁÁ


RMS Current through DiodeIF(RMS)/IL(DC)


0.587


0.579


0.293


0.409


0.409


0.818ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RMS Input Voltage Per Transformer LegVi/VL(DC)


0.855


0.428


0.855


0.741


0.715


0.37


Diode Peak Inverse VoltageVRRM/VL(DC)


2.09ÁÁÁÁÁÁÁÁÁÁÁÁ




1.05ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

1.05


Transformer Primary RatingVA/PDC

ÁÁÁÁÁÁÁÁ

1.23ÁÁÁÁÁÁÁÁ






Transformer Secondary RatingVA/PDC


1.50


1.05


1.49


1.81


1.05


1.05


Total RMS Ripple, % ÁÁÁÁÁÁÁÁ






1.0


Lowest Ripple Frequency, fr/fi ÁÁÁÁÁÁÁÁ

3 ÁÁÁÁÁÁÁÁ

6 ÁÁÁÁÁÁÁÁÁÁÁÁ

6 ÁÁÁÁÁÁÁÁ

6 ÁÁÁÁÁÁÁÁ

12 ÁÁÁÁÁÁÁÁÁÁ

12


Rectification Ratio (ConversionEfficiency), %






100ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

100

1. See Table 19 in Chapter 7 for inductive load data.



Three–Phase Full–Wave Bridge CircuitA three–phase full–wave bridge connection is commonly

used whenever high dc power is required, as it exhibits anumber of excellent attributes. It has a low ripple factor, lowdiode PIV, and the highest possible transformer utilizationfactor for a three–phase system. Because of the full–waverectification associated with each secondary winding, it ispermissible to use any combination of wye or delta primaryand secondary windings or three single–phase transformersin place of one three–phase transformer. A schematic of apopular circuit is shown in Figure 95(a). The voltagewaveforms are shown in Figure 95(b).

Each conduction path through the transformer and loadpasses through two rectifiers in series; a total of six rectifierelements are required. Commutation in the circuit takes placeevery 60, or six limes per cycle. Such action is referred to asa six pulse rectifier which reduces the ripple to 4.2% andincreases the fundamental frequency of ripple to six times theinput frequency. No additional filtering is required in manyapplications. Thus, with this circuit the low ripple factor of asix–phase system is achieved while still obtaining the highutilization factor of a three–phase system. The dc outputvoltage is approximately equal to the peak line voltage or 2.4times the rms phase voltage; each diode must block only theoutput voltage. Three–phase bridge connections are popularand are recommended wherever both dc voltage and currentrequirements are high.

The circuit characteristics are obtained by substitutingm = 6 in the general equations. Results are shown in Table 18.

Figure 95. Three–Phases Full Bridge Circuit andAssociated Waveforms.

(a) Three–Phases Full–Wave Bridge Circuit; (b) Voltage Waveforms, Solid Line is Output Voltage

and the Dashed Lines are the Phase Voltages

(a)

(b)

O

RL

Three–Phase Double–Wye Rectifier withInterphase Transformer

The three–phase double–wye rectifier circuit is frequentlyused instead of a bridge circuit because each rectifier diodecontributes only 1/6 instead of 1/3 of the load current.However, the peak inverse voltage for this circuit is higherthan the three–phase star system due to the interphasereactor.

The circuit (Figure 96) consists essentially of twothree–phase star circuits with their neutral pointsinterconnected through an interphase transformer or reactor(also called a balance coil). The polarities of thecorresponding secondary windings in the two parallelsystems are reversed with respect to each other, so that therectifier output voltage of one three–phase unit is at aminimum when the rectifier output voltage of the other unitis at a maximum, as shown. The action of the balance coil isto cause the actual voltage at the output terminals to be theaverage of the rectified voltages developed by the individualthree–phase systems. The output voltage of the combinationis therefore more nearly constant than that of a three–phasehalf–wave system; moreover, the ripple frequency of theoutput wave is now six times that of the supply frequency,instead of three times.

Figure 96. Circuit and Waveforms for theThree–Phase Double Wye Circuit: (a) Circuit; (b)

Waveforms

(a)

(b)

InterphaseReactor

(Balance Coil)

One Cycleof Supply

Voltage of second Y

Voltage across load

C1

A1

B1

B2 C2

A2

RL



In order that the individual three–phase half–wavesystems may operate independently with current flowingthrough each diode one third of the time, the inter–phasereactor must have sufficient inductance so that thealternating current flowing in it as a result of the voltageexisting across the coil has a peak value less than one–halfthe dc load current. That is, the peak alternating current inthe interphase reactor must be less than the direct currentflowing through one leg of the coil. Since the direct currentflows in opposite directions in the two halves of theinterphase reactor, no dc saturation is present in this reactor.

Six–Phase Star Rectifier CircuitThe six–phase star rectifier circuit shown in Figure 97 is

often referred to as the three–phase diametric or full–waverectifying circuit because it has a center–tapped transformer.The characteristics are obtained from the general rectifierequations where m is equal to six. Fields of applicationinclude requirements for very high dc load currents inlow–to–medium voltage ranges. Voltage is usuallyrestricted because the peak inverse voltage applied to thediodes is twice the peak phase voltage and transformersecondary utilization is poor. Current flows in only onerectifying element at a time, resulting in a low averagecurrent, but a high peak to average current ratio in the diodes.

The six–phase star circuit is attractive in applicationswhich require a low ripple factor and a common cathode oranode connection for the rectifiers. The primary winding isgenerally delta–connected, although a wye connection issometimes used with a tertiary winding. An additionaladvantage of the six–phase star is that the dc currents cancelin the secondary and, therefore, core saturation is notencountered.

Figure 97. The Six–Phase Star Circuit

RL

Six–Phase Full–Wave Bridge CircuitsIn many applications, it is necessary to reduce ripple below

the 4.2% level characteristics of tree–phase, full–wave andsix–phase, half–wave connections. A reduction toapproximately 1.0% at a ripple frequency twelve times theinput frequency can be achieved by using wye–deltasecondaries which result in 300 phase shift betweenwindings. Either parallel or series bridge connections may beused for the output as shown in Figure 98.

When an equalizing reactor is used to couple the twobridge sections as in Figure 98(a), the system behaves as twoparallel three–phase bridge circuits, with each sectionsupplying one–half the load current. The parallel connectionof the two groups is preferable to avoid having current passthrough four diodes in series, but for high–voltageapplications the series connection (as in part b) may resultin a more economical design.

Figure 98. Six–Phase Full–Wave Bridge Circuits

(a)

(b)

RL

RL



Comparison of CircuitsAs discussed, the three–phase and six–phase star circuits

have limited applications because of a number ofdisadvantages. The most popular circuits by far are thethree–phase full–wave bridge and the three–phasedouble–wye with interphase transformer. Both are alike inmany respects.

Comparing the double–wye connection with interphasetransformer with its rival, the three–phase bridgeconnection, it is found:

1. The diodes of one leg of an interphase transformerconnection have to handle twice the voltage butonly half the current of the diodes in one leg of abridge connection with the same values of directvoltage and current. This is because thecommutating groups operate in parallel in theinterphase transformer connection and in series inthe bridge connection. The high voltage rating isusually no problem and does not, in general,proportionally increase the price of the diodes(very high voltage excepted), but the lower currentvalue reduces the rating of the diodes and allassociated components such as fuses, bus bars, andcooling equipment, and is therefore a greatadvantage.

2. The total power losses are smaller in an interphasetransformer connection because of the lowercurrent carried by the diodes.

3. The reactive voltage drop caused by the bus barscan be made smaller in an inter–phase transformerconnection since the current to be commutated isonly half of the current commutated in a bridgeconnection, and the commutating voltage is twiceas high.

For these reasons, the interphase transformer connectionis competitive with the three–phase bridge connection in acertain voltage–current range, despite the relatively hightransformer rating and the problem of avoiding saturation ofthe inter–phase transformer core due to current unbalance.

In special cases where low ripple is required and largepower must be handled, a six–phase bridge or otherhigh–order system may prove attractive. Other usefulsystems are covered in the literature [2].

High–Current Parallel–ConnectedDiodes

In some applications in chemical, metal, andtransportation industries, the required dc output currentcannot be achieved by using a single cell diode. In suchinstances, it is necessary to operate diodes in parallel. Caremust be taken in the design to achieve a reasonable degreeof current balance. The three main causes of unbalance are:• differences in diode forward voltage drop

• self and mutual inductances of the diode and busconnection (referred to as the ladder effect in literature [3])

• magnetic coupling between legs.Diode differences can be minimized by purchasing the

diodes in closely matched sets but matched diodes aredifficult to obtain from manufacturers at a cost–effectiveprice. The resistance of the fuses used in series with eachdiode also improves balance. Some resistance will beencountered in the busing and connections. It should be verylow in the main busses as compared to that in each individualdiode leg.

Use of balancing transformers is a very effective means offorcing proper current balance and may be less expensivethan purchasing factory matched units. The transformersconsist of laminated iron cores usually with single–turnprimary and secondary windings. The current from twodiodes in parallel passes around the core in oppositedirections so that any unbalance will induce a voltage whichserves to correct the unbalance. The basic technique isshown in Figure 99. Its extension to larger numbers ofrectifiers is illustrated and briefly discussed in Figure 100.

Figure 99. Parallel Operation of Rectifier DiodesUsing Balancing Transformers

+

+



Computer simulation of the busing used in a stack ofparallel diodes has led to the following design guidelines [4]:

1. The ac and dc buses of each leg should be as closeas possible. Mutual inductance between thesebuses is beneficial.

2. The distance between the parallel diodes should beincreased. The coupling of the mutual inductanceof these paths acts as an improperly phasedbalance reactor.

3. The length of the diode path should be as short aspossible. Although the resistance of the pathincreases as the path length increases, theself–inductance and mutual–inductance effectspredominate, which increases the unbalance.

T4

T3

T2

T1

+

+

+

+

+

+

+

+

(a) (b)

Figure 100. Schemes for Balancing the Current When More than Two Diodes are Required.(a) Balancing Reactors Used with Diodes in an Extension of the Basic Circuit. Transformer T3 must handle

twice the current of T1 or T2; T4 must handle twice the current of T3, etc.; (b) Balancing Reactors in a Closed–Chain System. Each winding carries only the current of one diode

References1. Jacob Millman and Samuel Seely, Electronics,

Second Edition, Chapter 14, McGraw–Hill BookCompany, Inc., New York, New York, 1951.

2. Johannes Schaefer, Rectifier Circuits: Theory andDesign, John Wiley and Sons, Inc., New York,New York, 1965.

3. D.A. Paice, Multiple Paralleling of Power Diodes,IEEE Trans. TECI, Vol. IECI22, pp. 151–158,May, 1975.

4. S.M. Peeran, A. Kusko, W.R. Hodgson & E.G.Fellendort, Current Balance in Parallel PowerDiodes in Three–Phase Rectifiers, IEEETransactions on Industry Applications, Vol. IA–23,No 3., May/June, 1987.



Chapter 7

Rectifiers Filter Systems



!

Rectifiers without output filters, especially single–phasecircuits, find limited application owing to their high rippleand relatively low rectification ratio. A Fourier analysis ofthe rectifier output waveform yields a constant term (the dcvoltage) and a series of harmonic terms. Filters are usuallyadded to extract the constant term and attenuate all harmonicterms. The input impedance of the filter dramaticallyinfluences the current and voltage relations of thetransformer–rectifier combination; therefore, filters arebroadly classified by the type of input element used.

Inductor–input filters are preferred in higher–powerapplications in order to avoid excessive turn–on andrepetitive surge currents. Choke–input filters also offergreatly reduced electromagnetic interference, which isfrequently caused by rectifier repetitive surge currents.More efficient transformer operation is also obtainedbecause of the reduction in form factor of the rectifiercurrent.

An inductor attempts to hold the load current constant andis thus more effective at heavy loads or small values of loadresistance. Use of an inductor alone is generally impractical,particularly when variable loads must be handled becausethe attenuation is not sufficient with reasonable values ofinductance. Analysis of a single L–R network shows that theripple is reduced by the factor:

1

1 XLRL2 (7.1)

whereXL is the reactance of the filter chokeRL is the resistance of the load.Unless XL » RL, filter action is ineffective. The basic

inductor–input filter is therefore an L section employingboth inductance and capacitance so that the complementarycharacteristics of the filter elements are used to advantage.It should also be noted that inductive loads, or filters, are notgood practice in half–wave single–phase rectifiers owing tothe large rectifier inverse–voltage transient which occurswhen conduction inevitably ceases.

Demands for smaller and lighter equipment have forceddesigners to use capacitor–input filters in lower–powersystems operating from single–phase ac lines. Whencapacitor–input filters are used, diodes whose average ratingmore nearly matches the load requirement can be used if asource–to–load resistance ratio of about 0.03 and voltageregulation of about 10% are acceptable. Close regulationfrom the rectifier is seldom needed in electronic equipment

because the rectifier is followed by an electronic regulatoror switch mode dc–to–dc converter.

Behavior of Rectifiers with Choke–Input Filters

The voltage and current relations existing in rectifiersystems having a series–inductance (choke–input) filter areillustrated by the sketches of Figures 101 and 102. Whilethese apply to specific rectifier circuits, the same generalbehavior occurs in all rectifier systems of the choke–inputtype.

When the input inductance is assumed infinite, the currentthrough the inductance is constant and is carried at anymoment by the rectifier diode which has the most positivevoltage applied to its anode at that instant. As the alternatingvoltage being rectified passes through zero or when anotheranode becomes most positive, the current suddenly transfersfrom one diode to another, giving square current wavesthrough the individual rectifier diodes, as shown by thedotted lines in the lower sketches of Figure 101. When theinput inductance is finite and large, the situation is as shownby the solid lines. The current through the input chokeincreases when the output voltage of the rectifier exceeds theaverage or dc value and decreases when the rectifier outputvoltage is less than the dc value, causing the current throughthe individual diodes to be modified as shown. If the inputinductance is too small, the current decreases to zero duringa portion of the time between the peaks of the rectifier outputvoltage, and the conditions are similar to a capacitor–inputfilter system, as discussed later in this chapter.

The ratio of peak current per individual diode to the dccurrent developed by the overall rectifier system dependsupon the rectifier connection and the size of the inputinductance. When the input inductance is infinite, the anodeof each rectifier diode must at some time during the cyclecarry the entire load current, except in the case of thethree–phase half–wave double–wye system, where eachdiode is called upon to carry only half of the load current.These and other useful current relations for differentrectifier connections are presented in Table 19. When theinput inductance is not infinite, the current through the inputinductance will vary around the value for the infiniteinductance case, as illustrated in Figure 101. In the leastfavorable case, corresponding to an input inductance barelysufficient to obtain choke–input type of operation, the peakvalue of diode current is twice the value corresponding toinfinite input inductance.



L1 L1D2

D3

D1

D1

Figure 101. Voltage and Current Waveforms Existing in Rectifier Systems Operating with Choke–Input Filters:(a) Circuit of Rectifier and Filter, Single–Phase Full–Wave Case;

(b) Circuit of Rectifier and Filter, Three–Phase Case

LOAD

Transformer

Rectifier

Rectifier Filter

Output

LOAD

RectifierOutput

Voltage Relations

Voltage

Rectifier Output Voltage

Across Load

Voltage Relations

Voltage AppliedTo Filter Input

Voltage Applied ToLoad (SubstantiallyConstant)

Finite Inductance

Current in Inductance

Infinite Inductance Finite Inductance

Current in Inductance

Infinite Inductance

Finite Input Infinite InputInductance

Current in Individual Diodes

Inductance

D1

D2

Current in D1

Current in D2

Current in D3

D2

(a) (b)

Figure 102. Typical Current Waves in Primary and Secondary Windings of Transformer for Ideal Choke–InputSystems: (a) Single–Phase Full–Wave System; (b) Three–Phase Half–Wave

D2

D3

D1

LOAD

+

LOAD

Rectifier Circuit

(a) (b)

–

Current in One Half of Secondary

Current in Other Half of Secondary

Current in Primary

No. 1

No. 2

No. 3

Current in Primary No. 1



Table 19. Characteristics of Typical Rectifiers Operated with Inductance–Input Filter Systems


RectifierCircuit

Connection


Single–PhaseFull–WaveCenter Tap


Single–PhaseFull–Wave

Bridge


Three PhaseHall–Wave

Star


Three–PhaseFull–Wave

Bridge


Three–PhaseDouble Wye

WithInterphaseÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁCharacteristicÁÁÁÁÁÁÁÁÁÁ

Center–TapÁÁÁÁÁÁÁÁÁÁÁÁ

Bridge ÁÁÁÁÁÁÁÁÁÁ

Star ÁÁÁÁÁÁÁÁÁÁ

Bridge ÁÁÁÁÁÁÁÁÁÁ

InterphaseTransformerÁÁÁÁÁÁÁÁÁÁÁÁ


‡Average Current Through DiodeIF(AV)/IL(DC)


0.500


0.500


0.333


0.333


0.167


‡Peak Current Through Diode IFM/IF(AV)ÁÁÁÁÁÁÁÁÁÁ





3.00


Form Factor of Current Through DiodeIF(RMS)/IF(AV)


1.41


1.41


1.73


1.73


1.76


RMS Input Voltage Per Transformer LegVI/VL(DC)


1.11*ÁÁÁÁÁÁÁÁÁÁÁÁ





Diode Peak Inverse Voltage(PIV) VRRM VL(DC)


3.14


1.57


2.09


1.05


2.42


Transformer Primary Rating VA/PDC

ÁÁÁÁÁÁÁÁÁÁ1.11




ÁÁÁÁÁÁÁÁÁÁ1.05ÁÁÁÁÁÁÁÁÁÁÁÁ


Transformer Secondary Rating VA/PDC


1.57


1.11


1.48


1.05


1.48


Ripple (VF/VL(DC) Lowest frequency inrectifier output (fr/f1) Peak Value of Ripple


2


2


3


6


6

Components:Ripple frequency (fundamental)Second harmonicThird harmonic

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.6670.1330.057


0.6670.1330.057


0.2500.0570.025


0.0570.0140.006


0.057†0.0140.006

Ripple peaks with reference to dc axis:Positive peakNegative peak


0.3630.837


0.3630.637


0.2090.395


0.04720.0930


0.04720.0930

1. This table assumes that the input inductance is sufficiently large to maintain the output current of the rectifier substantially constant, andneglects the effects of voltage drop in the rectifier and the transformers. PDC = 12

LRL, VL = ILRL*Secondary voltage on one side of center–tap.†The principal component of voltage across the balance coil has a frequency of 3 fi and a peak amplitude of 0.500. The peak balance coil voltage,

including the smaller, higher harmonics, is 0.605.‡Assumes infinite input inductance.

The output voltage from the rectifier diodes applied to achoke input filter can, for nearly all practical purposes, beconsidered the same as if applied to a resistive load. Theoutput voltage wave of the rectifier can be considered asconsisting of a dc component upon which are superimposedac voltages, termed ripple voltages. In the case of theidealized full–wave single–phase rectifier, Fourier analysisshows that the output wave vL has the equation

VL2VM1 2

3cos 2t 2

15cos 4t 2

35cos 6t

(7.1)

whereVM represents the peak value of the ac voltage applied to

the rectifier diodeω is the angular velocity (2 πf) of the supply frequency.

(A full derivation of this equation is given at the end of thischapter.)

Note that the dc component of the output wave is 2/π timesthe crest value of the ac wave, and the lowest frequencycomponent of ripple in the output is twice the supplyfrequency and has a magnitude that is two–thirds the dc

component of the output voltage. The remaining ripplecomponents are harmonics of this lowest frequencycomponent and diminish in amplitude with the order of theharmonic involved in accordance with Equation 7.1. Themore significant components of ripple are shown in Table20. The ripple frequencies in the table are presented inrelation to the fundamental frequency of ripple, not to theinput frequency. For the full–wave circuit, the fundamentalripple component for a 60 Hz input is 120 Hz; the secondharmonic is 240 Hz, and the third harmonic is 360 Hz.

Table 19 also gives the results of the analyses [1] for theoutput waves delivered by several popular polyphaserectifier connections. The ripple voltages are much less forthe three–phase half–wave rectifier than for thesingle–phase connection, and are still less for the six–phasearrangements. In all cases, the amplitude of the ripplecomponents diminishes rapidly as the order of theharmonics is increased. Not only are the ripple amplitudeslower but the ripple frequencies are higher for polyphasethan for single–phase rectifiers, attributes which allowchoke size to be greatly reduced. For example, thethree–phase full–wave connections used with a 60 Hz input



have a lowest ripple frequency component of 360 Hz withan amplitude of 5.7% of the dc level. The second harmonicis 720 Hz with a level of only 1.4% and the third harmonicis 1080 Hz with an amplitude of only 0.6%. Consequently,a relatively small choke and capacitor can reduce thefundamental ripple frequency to a very low level and theharmonics to an insignificant level.

Input Inductance RequirementsTo achieve normal choke–input operation, it is necessary

to maintain continuous flow of current through the inputinductance. The peak value of the alternating currentcomponent flowing through the input inductance must,hence, be less than the dc output current of the rectifier. Thevalue for minimum inductance, called critical inductance(LC) is derived from the following argument.

The average or dc current is VL(DC)/RL. The peakalternating current is very nearly the peak value of thefundamental–frequency component, since thehigher–frequency components of the ripple current arerelatively small. The current ripple harmonics are smallerthan those given by Table 19, because of the higher reactanceof the inductor at the harmonic frequencies. The inductor isnormally followed by a capacitor having a low reactance atthe fundamental ripple frequency, so that the peak ripplecomponent is very close to VM1/ω1L. The ratio ofpeak–to–average current therefore closely approximates(VM1/VDC)/ωLC/RL, which must not be less than unity.

For a single–phase, full–wave circuit, the fundamentalripple component ωi is twice the input frequency ωi; also, theratio VM1/VDC is the coefficient (2/3) of the fundamentalripple frequency term (cos 2ωt) in Equation 7.1. Aftersubstituting 2ωi, for ω1 and 2/3 for VM1/VDC into theprevious expression, the following equation for criticalinductance is found:

LCRL3i

(7.2)

Using a similar procedure for polyphase rectifiers, thecritical inductance is found to be

L2RL

m(m2 1)i(7.3)

In Equations 7.2 and 7.3LC = the critical inductance in HenriesRL = the load resistance in ohmsωi = the input or line frequency in rad/secm = the effective phase number for the output wave.(If the resistance of the choke, diode, or transformer is

significant, the values should be added to RL).For convenience, Equations 7.2 and 7.3 are put in the form

LCRLA (7.4)

where A is a constant determined from Figure 103.

Figure 103. Values for the Constant A Used toCompute Critical Inductance

500 k

200 k

100 k

50 k

20 k

10 k

5 k

2 k

1 k

50 100 200 500 1 k 2 k 5 k500

A

Input Frequency (Hz)

Single–Phase, Full–Wave

Three–Phase, Half–Wave (m=3)

Three–Phase, Full–WaveSix–Phase, Half–Wave (m = 3)

Values for other frequencies can easily be obtained byextrapolation, since A is inversely proportional tofrequency. The value of A for a single–phase full–wavecircuit operating at 20 kHz, for example, is 400,000 (10times the 2 kHz value). The critical inductance required inpolyphase systems is considerably less than that required ina single–phase system. The higher the load resistance (i.e.,the lower the dc load current) the more difficult it is tomaintain a continuous flow current. Also, with a given L,continuous flow will not occur when the load current dropsbelow a critical value.

When the inductance is less than the critical value, thesystem acts similar to a capacitor–input system, describedlater. When the load current varies from time to time, it isnecessary to satisfy the equations at all times if properoperation and, in particular, good voltage regulation are tobe maintained. In order that this requirement may besatisfied at very small load currents without excessiveinductance, it is usually necessary to place a resistance(commonly termed a bleeder resistance) across the output ofthe rectifier–filter system. The bleeder current is acompromise between having excessive dissipation in thebleeder resistor and excessively large Lc.

It is important to keep in mind that the effectiveinductance LC is the incremental inductance, that is, theinductance to the alternating current superimposed upon thedc magnetization. Incremental inductance always increasesas the dc magnetization decreases. This fact is of assistancein satisfying the equations at low load currents where RL islarge and can be put to advantage by the use of a “swinging”choke in which the inductance is varied by the load currentusing a controlled approach to saturation that lowersinductance as current increases.



It is essential to avoid series resonance between the inputchoke and first filter capacitor because at resonance veryhigh circulating currents flow. Since at resonance,1/ω1L = ω1C, to avoid resonance it is sufficient to insure that

2 LC 2 (7.5)1

where is the lowest frequency component of the ripple.The output ripple magnitude depends upon the values of

the choke and the capacitor used. It is calculated as shownin the subsequent sections.

Voltage Regulation in Choke Input SystemsGiven ideal components, the load regulation of a rectifier–

filter system employing input inductance greater than thecritical value would be perfect–i.e., voltage output would beindependent of load current. In practice, the output voltagefalls off with increasing load as a result of resistance in thediodes, filter, and transformer and as a result of the leakagereactance of the supply transformer. The various resistancesin the circuit reduce the output voltage without affecting thewaveshapes in the system. The leakage reactance of thetransformer, however, distorts the waveshape of the outputvoltage by preventing the current from shifting instantlyfrom one transformer winding to another, as in the idealcases of Figure 101. The situation in a typical case is shownin Figure 104 where represents the time interval requiredto transfer the current. During this transition period, theoutput voltage assumes a value intermediate between theopen–circuit voltages of the two windings that aresimultaneously carrying current, instead of following theopen–circuit potential of the more positive anode. As aresult, the average voltage of the output is less than if noleakage inductance were present by the amount indicated bythe shaded areas in Figure 104(c). The quantitative relations,which are quite complicated, depend upon both the rectifierand the transformer connections.

When the input inductance is less than the critical value,the output voltage rises, and when the load resistance is verylarge, the output voltage will approach the peak value of therectifier output waveform causing the system to have poorvoltage regulation. When the load current is small, theenergy stored in the inductor is also small and the inductoris essentially out of the circuit.

Figure 104. Effect of Transformer LeakageInductance on the Behavior of a Polyphase Rectifier:

(a) Three–Phase Half–Wave Rectifier Circuit;(b) Current of Individual Diodes;

(c) Voltage Wave

LOAD

Rectifier

+

–

Output

ÉÉÉÉ

ÉÉ

ÉÉÉÉ

ÉÉÉÉ

(a)

(b)

(c)

Behavior of Rectifiers Used withCapacitor–Input Filters

The rectifier–filter system illustrated in Figure 105 differsfrom that of Figure 101 in that a shunt capacitor is presentedto the rectifier output. Each time the positive peakalternating voltage is applied to one of the rectifier anodes,the input capacitor charges up to just slightly less than thispeak voltage. No current is delivered to the filter untilanother anode approaches its peak positive potential. Whenthe capacitor is not being charged, its voltage drops offnearly linearly with time because the load draws asubstantially constant current. A typical set of voltage andcurrent waveforms is shown in Figures 105(c) and 105(d).Use of an input capacitor increases the avenge voltage acrossthe output terminals of the rectifier and reduces theamplitude of the ripple in the rectifier output voltage.



Analysis of Rectifiers withCapacitor–Input Systems

The detailed action that takes place in a capacitor–inputsystem depends in a relatively complicated way upon theload resistance in the rectifier output, the input filtercapacitance, the leakage reactance and resistance of thetransformer, and the characteristics of the rectifier diode. Forpurposes of analysis, the actual rectifier circuit, such as thatof Figure 105(a), is replaced by the equivalent circuit ofFigure 105(b). The diode is replaced by switch S, whichcloses only when one of the diodes conducts current. Thetransformer is replaced by an equivalent generator having avoltage equal to the open–circuit line to center–tapsecondary voltage and having equivalent internalimpedance elements LS and RS. The inductance LS is theleakage inductance of the transformer, measured acrossone–half the secondary winding with the primaryshort–circuited. The source resistance RS the correspondingtransformer’s resistance plus a resistance to account for theresistance of the diode. In very low–voltage systems, a smallpotential φ may be needed to more accurately account for thediode voltage drop. The input capacitor of the filter systemis C1, and the first inductance L1 (if used) and the load areassumed to draw a constant current I1 equal to the dc voltagedeveloped across the input capacitor divided by the sum ofthe actual load resistance plus the resistance of the filterinductance.

By utilizing the equivalent circuit of Figure 105(b), theeffects that result from changes in individual circuitelements may be deduced. Thus, a decrease in the loadresistance–i.e., an increase in the dc output current–reducesthe average or dc output voltage, increases the ripplevoltage, and increases the length of time during which thediode is conducting, as illustrated in Figure 106(a).Increasing the input capacitance has as its principal effect adecrease in the ripple voltage and also causes the averagevoltage to be increased slightly; these effects are shown inFigure 106(b). Increasing the leakage inductance (orresistance) of the transformer, reduces the average outputvoltage as illustrated in Figure 106(c), and likewisedecreases the ratio of peak–to–average current flowingthrough the rectifier diode. In the case of a source and diodehaving very low impedance, the situation is as illustrated inFigure 106(d), and the peak current becomes quite high.

L1

C1 C2

I1

VC C1

RSLS

former Rectifier Filter

Figure 105. Actual and Equivalent Circuits ofCapacitor–Input Rectifier System, Together with

Oscillograms for Voltage and Current for a TypicalOperating Condition:

(a) Actual Circuit; (b) Equivalent Circuit; (c) Voltage Across Input Capacitor C1;

(d) Current Through Diode

R

Trans–

a

a

i

VM sin ωt

(a)

(c)

(b)

(d)



Figure 106. Effects of Circuit Constants and Operating Conditions on Behavior of Rectifier Having aCapacitor–Input Filter: (a) Effect of Load Resistance; (b) Effect of Capacitance;

(c) Effect of Transformer Leakage Inductance; (d) Effect of Very Low Diode and Transformer Impedance

Normal CapacitanceNormal Load Resistance

Low LoadResistance

Normal Leakage Inductance

IncreasedLeakageInductance

Low Impedance

Very LargeCapacitance

Cur

rent

Vol

tage

Cur

rent

Vol

tage

Cur

rent

Vol

tage

Cur

rent

Vol

tage

(a) (b)

(d)(c)

NormalImpedance

Design of Capacitor–Input FiltersThe best practical procedure for the design of

single–phase capacitor–input filters still remains based onthe graphical data presented by Schade [2] in 1943. Thecurves shown in Figures 107 through 10 give all the requireddesign information for half–wave and full–wave rectifiercircuits. Whereas Schade originally also gave curves for theimpedance of vacuum–tube rectifiers, the equivalent valuesfor semiconductor diodes must be substituted. However, therectifier forward voltage offset often assumes more

significance than its dynamic resistance in low–voltagesupply applications, as the dynamic resistance can generallybe neglected when compared with the sum of thetransformer secondary–winding resistance plus thereflected primary–winding resistance. The forward offsetmay be of considerable importance, however, since it isabout 0.8 V for conventional silicon junction diodes andabout 0.4 V for Schottky diodes, which clearly cannot beignored in supplies for 12 V or less.



RL

RS

VM

VC(DC)

Figure 107. Relation of Applied Alternating Peak Voltage to Direct Output Voltage in Half–WaveCapacitor–Input Circuits (From O.H. Schade, Proc. IRE, Vol. 31, 1943, p. 356)

CRL, (C in farads, RL in ohms)

70

60

50

40

30

20

10

00.1 1 10 100 1,000

0.050.5

1

2

4

6

8

1012.515

2025303540

5060708090100

(%) (%)

80

90

100

C VC RL

RL

VM

RL

RS

VM

VC(DC)(%) (%)

Figure 108. Relation of Applied Alternating Peak Voltage to Direct Output Voltage in Full–WaveCapacitor–Input Circuits (From O.H. Schade, Proc. IRE, Vol. 31, 1943, p. 356)

CRL, (C in farads, RL in ohms)

70

60

50

40

300.1 1 10 100 1,000

0.05

0.51

2

4

6

81012.515

20

25

303540

50

60708090100

80

90

1000.1

CRS

RSRLVC

VM

VM



Figure 108 shows that a full–wave circuit must operatewith ωCRL ≥ 10 in order to hold the voltage reduction to lessthan 10 percent and ωCRL ≥ 40 to obtain less than 2%reduction. However, these voltage–reduction figuresrequire RS/RL, where RS is now the total series resistance,to be about 0.1%. Such a low source resistance, if attainable,causes repetitive peak–to–average current ratios of 10 to 17respectively, as can be seen from Figure 109. Rectifierdiodes can handle high repetitive peak currents but theirrated average current must be derated. To aid designers,manufacturers often provide capacitive load derating data.

The turn–on surge current generated when the input–filtercapacitor is discharged and the transformer primary isenergized at the peak of the input waveform causes a surgecurrent determined by the peak secondary voltage less therectifier forward drop limited only by the series resistance

RS. In order to control this turn–on surge, additionalresistance must often be provided in series with eachrectifier. It becomes evident that a compromise must bemade between voltage reduction on the one hand, and diodesurge rating and hence average current–carrying capacity onthe other hand. If small voltage reduction–that is, goodvoltage regulation–is required, a much larger diode isnecessary than that demanded by the average current rating.An obvious solution to this problem is to avoid the use of acapacitor–input filter. The alternative of a choke–inputfilter, as discussed previously, may be more costly than thecost of increased rectifier surge capacity.

A design example showing the use of Schade’s curve isgiven at the end of this chapter. For comparative purposes,Table 21 shows rectifier circuit values when ωCRL = 100and RS/RL= 2%.

Figure 109. Relation of RMS and Peak to Average Diode Current in Capacitor–Input Circuits(From O.H. Schade, Proc. IRE, Vol. 31, 1943, p. 356)

1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500 700 1000

40

30

20

10

7

5

3

0.02

0.10.20.51251030100

0.05

0.02

0.05

0.10.2

0.5

1.02.05.010

30100

nCRL

nCRL

3.0

2

7

201

5

30107.0 50

3

5.0

10

70 200 300 1000

F=

I F(R

MS

)/IF

(AV

) (P

er D

iode

)

1.0 2.0 100

I FM

/ I F

(AV

) (P

er D

iode

)

% R

S /

nRL

% R

S /

nRL

n = 1 For Half–Wave Single–Phase Rectifier Circuits2 For Full–Wave Single–Phase Rectifier Circuits

= 2 f, where f = Line Frequency

C in FaradsRl in OhmsRS = RMD Equivalent Source Resistance



Diode Peak Inverse VoltageThe peak inverse voltage applied to the diodes in a

rectifier system operating in conjunction with aseries–inductance input depends upon the topology. Itranges from as high as π times the dc component of theoutput voltage, in the case of the single–phase center–tappedconnection, to barely more than the dc voltage in thethree–phase full–wave bridge. Results in typical cases aregiven in Tables 19 and 21 and are the same as thosedetermined for the resistive load circuits in Chapters 5 and6.

The peak inverse voltage applied to the rectifiers incapacitor–input systems is generally based upon thecapacitor charging to VM which is the case when the load islight and the capacitor large. However, the peak of thereverse voltage sine wave occurs sometime after thecapacitor has been charged. The peak voltage the capacitorattains is a function of the RS/RL ratio; the voltage on thecapacitor when a diode’s reverse voltage reaches its peak isdependent upon the load time constant. The relationship hasbeen worked out for two cases as shown in Figure 111.

Figure 110. Root–Mean–Square Ripple Voltage for Capacitor–Input Circuits(From O.H. Schade, Proc. IRE, Vol. 31, 1943, p. 356)

100

CRL (C in farads, RL in ohms)

7050

3020

107.05.0

3.02.0

1.00.70.5

0.3

0.2

0.11.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500 1000

Circuit Parameter

Half–Wave

Full–Wave

A

A

0.11.01030

RS/RL (%)

0.11.01030

A

A

rf, R

ippl

e F

acto

r (%

)

Figure 111. Ratio of Operating Peak Inverse Voltage to Peak Applied 60 Hz AC for Rectifiers Usedin Capacitor–Input, Single–Phase, Filter Circuits

2.0

RS/RL

1.8

1.6

1.4

1.2

1.00.01 0.02 0.04 0.07 0.1 0.2 0.4 0.7 1.0

CRL 100

CRL = 10

PIV

/VM



Transformer ConsiderationsThe ratio of the actual dc rectified power output to the

volt–ampere capacity of the windings on the basis ofsinusoidal waves, for the same heat loss due to windingresistance, is termed the transformer utilization factor (UF).Its value depends upon the rectifier connections and is, ingeneral, not the same for the primary and secondarywindings, since the waveshapes in these windings willgenerally be different. Table 19 shows the reciprocal of theUF of the primary and secondary windings for some of themore commonly used rectifier connections. Derivation ofthe values is handled as shown for the resistive load circuitsin Chapters 5 and 6.

The wave shapes of the currents that flow through thewindings of the transformer in the idealized case of arectifier system operating with an infinite input inductanceare shown in Figure 102 for two typical cases. Because thesewaves are not sinusoidal, the heating of the transformerwindings is greater for a given dc power output from therectifier than would be the case if the same amount of acpower were delivered by the transformer to a resistance load.It is accordingly necessary to design the transformerwindings more generously for rectifier applications than forcases where sinusoidal currents are involved.

Since transformer volt–ampere ratings vary with the rmscontent of the rectified circuit, they must be calculated foreach capacitive–input filter design. Higher RS/RL ratioshelp reduce transformer requirements. Also, the effects oftransformer saturation and finite bandwidth cannot beignored. The former tends to limit the peak current while thelatter allows the capacitor to charge over a longer time andhence reduces the peak charging current i = C dv/dt. Coresaturation generally occurs on the recurrent charging peaks,and this will cause a lower output voltage than thatcalculated from the rated transformer secondary voltage.That saturation is occurring and that flattening is not due tothe secondary–winding resistance can be determined byobserving the voltage waveform induced in an unloadedwinding on the same core.

HarmonicsBecause the currents which flow in a rectifier circuit using

a choke or capacitor input filter are not sinusoidal, highvalues of harmonic currents are present. These harmoniccurrents complicate the design of the transformer and, insingle–phase circuits, the harmonic currents flow into thepower line where they can cause a number of difficultieswith the power distribution system. In a polyphase rectifier,the third harmonic can be kept from the powerline by havingthe primary windings arranged in a delta configuration. Thecirculating third harmonic component of primary current, ofcourse, causes additional power loss in the transformer.

The choke input filter causes a square wave of current toflow in a single phase circuit. A Fourier analysis indicatesthat only odd harmonics are present and they decrease as 1/n,where n is the harmonic number. Thus, the amplitude of the

third harmonic is 1/3, the fifth is 1/5, etc., that of thefundamental frequency.

Capacitive input filters cause a much higher currentharmonic content than choke input filters cause. Theharmonic content is particularly severe in transformer–lesssingle phase supplies because transformer leakageinductance is not present. Inductance in series in the rectifierwidens the diode conduction angle and lowers the currentpeak. A computer simulation of a single–phase bridgerectifier with a capacitor input filter yielded the resultsshown in Table 20 [3]. The value of the filter capacitor isnormally so large that small changes in its value do not alterthe results.

Table 20. Harmonic Currents In a Single–phaseFull–wave Capacitor–Input RectifierÁÁÁÁÁÁÁÁ


ZR*ÁÁÁÁÁÁÁÁHarmonic

ÁÁÁÁÁÁÁÁ

1%ÁÁÁÁÁÁÁÁ

2%ÁÁÁÁÁÁÁÁ

5%ÁÁÁÁÁÁÁÁ

10%ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

3rd5th7th9th11th


83.0%56.2%29.2%11.7%8.6%


76.3%42.4%15.4%8.7%7.1%


63.5%22.0%8.1%6.1%3.5%


49.8%10.2%7.3%3.8%2.5%

*ZR = Ratio of source inductive reactance to load impedance at thefundamental frequency.

The bridge is used without a transformer when its outputis used by a switch mode dc–dc converter. In this case, theharmonic problems are transferred to the transformer in theelectrical power distribution system feeding the equipment.

For a single–phase circuit, it is possible to significantlyreduce harmonics fed into the power line by adding anoptimally chosen inductor in series with the line to widen theconduction angle of diode forward current [4]. The inductoris much smaller than would be required for the typicalcontinuous conduction choke–input filter. An optimallychosen capacitor added across the line raises the powerfactor to approximately 0.9, which is the same as obtainedwith a typical choke input filter.

Polyphase circuits behave differently. The larger thechoke, the lower the harmonics and the higher the powerfactor. Increasing the inductor above a threshold does notoffer any significant improvement in harmonics or powerfactor.

Surge CurrentBecause semiconductor junctions are limited in the

amount of transient power that they can safely handle,attention must be given to the surge current occurring whenthe circuit is energized. The expected behavior can bededuced by studying the equivalent circuit of the rectifiersystem shown in Figure 105(b).

For analyzing a choke input filter, a choke is insertedbetween the switch and the capacitor C1. Before voltage isapplied, C1 may be regarded as a short. Current buildup willbe governed by the L/RS time constant of the circuit. (L is thesum of the filter and transformer leakage inductance). Thecurrent surge is not significantly different than encountered



in normal operation, even if the input voltage is applied at atime when the voltage has reached its positive peaks,because the inductor has high reactance to fast risingtransients.

The capacitor–input filter, however, allows a large surgeto develop, because the reactance of the transformer leakageinductance is rather small. The maximum instantaneoussurge current is approximately VM/RS and the capacitorcharges with a time constant τ=RSC1. As a rough–butconservative–check, the surge will not damage the diode ifVM/RS is less than the diode IFSM rating and τ is less than thetime of one–half cycle. It is wise to make RS as large aspossible and not pursue tight voltage regulation; therefore,not only will the surge be reduced but rectifier andtransformer ratings will more nearly approach the dc powerrequirements of the rectifier load.

Comparison of Capacitor–Input andInductance–Input Systems

The basis for distinguishing between inductance–inputand capacitor–input systems is that in the former the currentflows continuously from the rectifier output into the filtersystems, while in the latter the current flows intermittentlyfrom the rectifier into the filter. Intermittent action is alsopresent with inductance–input systems when the inputinductance is less than the critical value. When this is thecase, the system is classified as a capacitor–inputarrangement even though it possesses a series inductance.

A comparison of the performance of inductance–inputand capacitor–input systems shows that, in the latterarrangement, the dc voltage is higher, the ripple voltagemore, the surge current higher, and the voltage regulationpoorer than when inductance input is used with the samediode, transformer, load resistance, and capacitance. Also,with capacitor–input the ripple voltage increases withincreasing load current, unlike the inductance–input systemwhere the ripple voltage is independent of load current. Theutilization factor of the power transformer is much poorerwith the capacitor–input system because of the higher ratio

of peak–to–average current flowing through the rectifierdiode, and likewise the diode is less efficiently utilized. Thecharacteristics of several popular rectifier systems areshown in Table 21.

Shunt capacitor–input arrangements are generallyemployed in most consumer equipment such as personalcomputers, radio and television receivers, high–fidelitysound systems, or small public–address systems, when theamount of dc power required is small. They must be usedwith half–wave rectifiers and are attractive when the inputpower is taken directly from the ac line without a powertransformer. In contrast, inductance–input arrangements areused when the amount of power required is large, since thenthe higher utilization factor and lower peak currents result inimportant savings in rectifier and transformer costs.Inductance input is often employed when good regulation ofthe dc voltage is important but the precision of an electronicregulator circuit is not needed. Inductance–input systemsare normal in polyphase rectifier systems.

Filter SectionsFigure 114 gives typical examples of filters that are placed

between the rectifier output and the load to make the currentdelivered to the load substantially pure direct current. Thesefilters are made up of series impedances (either inductancesor. resistances) that oppose the flow of alternating currentfrom the rectifier output to the load and shunt capacitors thatbypass the alternating currents that succeed in flowingthrough the series impedances.

For purposes of discussion and analysis, filters areordinarily divided into sections, each consisting of a seriesimpedance followed by a shunt capacitor, as indicated inFigure 114. In this classification, the inductance in aninductance–input system is considered to be part of the firstsection of the filter. However, a shunt capacitance across therectifier output is not included as part of a filter section, butrather is considered to be part of the rectifier system, whichdelivers to the first filter section a voltage corresponding tothe voltage developed by the rectifier across the inputcapacitor.



Table 21. Summary of Significant Rectifier Circuit Characteristics. Capacitive Data is for WCRL= 100 and RS/RL = 2.0%


RectifierCircuit

Connection


Single–Phase






Three–PhaseHalf–Wave


Three–Phase


Three–PhaseDouble–Wye

With


Three–PhaseFull–Wave


CharacteristicÁÁÁÁÁÁ

LoadÁÁÁÁÁÁÁÁÁÁ

Single–PhaseHalf–WaveÁÁÁÁÁ

ÁÁÁÁÁ

Full–WaveCenter–Tap ÁÁÁÁ

ÁÁÁÁ

Full–WaveBridgeÁÁÁÁÁÁÁÁÁÁ

Half–WaveStar ÁÁÁÁÁÁÁÁÁÁ

Three–PhaseBridge ÁÁÁÁ

ÁÁÁÁ

WithInterphaseÁÁÁÁÁ

ÁÁÁÁÁ

Full–WaveStar


Average CurrentThrough diodeIF(AV)/IL(DC)

ÁÁÁÁÁÁÁÁÁ

RL&C*


1.00


0.50


0.50


0.333


0.333


0.167



Peak CurrentÁÁÁÁÁÁ

RÁÁÁÁÁÁÁÁÁÁ








Through DiodeÁÁÁÁÁÁ

L*ÁÁÁÁÁÁÁÁÁÁ

– ÁÁÁÁÁÁÁÁÁÁ






6.00


IFM/IF(AV) ÁÁÁÁÁÁ

CÁÁÁÁÁÁÁÁÁÁ



8.0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DATA NOT AVAILABLE


Form Factor of ÁÁÁÁÁÁ








2.46


Current ThroughÁÁÁÁÁÁ








2.45


DiodeIF(RMS)/IF(AV)

ÁÁÁÁÁÁ





DATA NOT AVAILABLE


RMS Current ÁÁÁÁÁÁ








0.409


Through DiodeÁÁÁÁÁÁ








0.408


IF(RMS)/IL(DC) ÁÁÁÁÁÁ





DATA NOT AVAILABLE


RMS Input VoltageÁÁÁÁÁÁ

R&LÁÁÁÁÁÁÁÁÁÁ







0.741


per TransformerLeg Vi/VL(DC)

ÁÁÁÁÁÁ









Diode Peak InverseÁÁÁÁÁÁ

R&LÁÁÁÁÁÁÁÁÁÁ







2.09


Voltage PIVVRRM/VL(DC)

ÁÁÁÁÁÁÁÁÁ

C


2.00


2.00


1.00


2.00


1.00


2.00


2.00


TransformerPrimary ÁÁÁ

ÁÁÁRÁÁÁÁÁÁÁÁÁÁ







1.28


Rating VA/PDCÁÁÁÁÁÁ

LÁÁÁÁÁÁÁÁÁÁ







1.28


TransformerSecondary

ÁÁÁÁÁÁ








1.81

ÁÁÁÁÁÁÁÁÁÁÁÁRating VA/PDC

ÁÁÁÁÁÁL

ÁÁÁÁÁÁÁÁÁÁ–






ÁÁÁÁÁÁÁÁÁÁ1.81ÁÁÁÁÁÁ

ÁÁÁÁÁÁTotal RMS Ripple %

ÁÁÁÁÁÁ


121ÁÁÁÁÁÁÁÁÁÁ




4.2ÁÁÁÁÁÁÁÁ



Lowest RippleFrequency fr/fs

ÁÁÁÁÁÁÁÁÁ


1


2


2


3


6


6


6


Rectification RatioÁÁÁÁÁÁ








99.8


(ConversionEfficiency) %

ÁÁÁÁÁÁ



100ÁÁÁÁÁÁÁÁ



100ÁÁÁÁÁÁÁÁ


100

*Inductive data valid when the circuit input voltage is a square wave, resistive or inductive load. PDC = I2LRL (RS neglected) VL = ILRL

Voltage and Current Relations in FiltersThe input voltage to the filter is whatever output voltage

is developed by the rectifier connection in the case ofinductance–input systems (it is the same as with a resistiveload), or is the voltage developed across the shunt capacitorin the case of capacitor–input systems. The ripple voltage inthe output of the rectifier–filter system is then the alternatingcomponent of this input voltage reduced by the action of thefilter sections.

Most filter sections are composed of a series inductanceand a shunt capacitance. In practical filters of this type, thereactance of the shunt capacitance at the lowest ripplefrequency is much smaller than the resistance of the load (orthe reactance of the series inductance of the followingsection). Substantially all ripple current entering theinductance L of the section flows through the capacitance C

of the filter section. The current in the section is thenVi/(ωL– 1/ωC), where Vi is the alternating voltage appliedacross the input to the filter section. The voltage that thiscurrent develops in flowing through the capacitor C is(1/ωC)Vi/ωL – 1/ωC) = Vi /ω2LC – 1). Dividing by Viresults in the following relationship for the voltage reductionthrough an L–C section:

VoVi 1

2LC 1) (7.6)

whereL = series inductance of filter sectionC = shunt capacitance of sectionω = angular frequency of ripple voltage involved.Results of Equation 7.6 are given in Figure 113 for the

usual case where the ripple components are harmonics of



60 Hz. Figure 115 indicates the actual ripple output of afull–wave single–phase rectifier circuit.

When the current drawn by the load impedance is small,the series inductance of the LC filter may be replaced by a series resistance as shown in Figures 114(e) and 114(f). Thisarrangement is widely used in low–current applications suchas resistance–coupled amplifiers, tuned radio–frequencyamplifiers, and so forth, and has the advantage that aresistance is much less expensive than an inductance ofcorresponding effectiveness. The disadvantage is the dcvoltage drop and power loss that occur in the resistance;these losses limit the resistance–capacitance type of filter tocases where the current is small and where a moderate dcvoltage drop is permissible.

In practical resistance capacitance filters, the reactance ofthe shunting capacitor is always made small compared to theseries resistance of the filter and to the impedance to whichthe output of the filter section is connected. The ripplecurrent flowing in R is Vi!R2 + (1/ωC)2 ≈ Vi/R, where Vi isthe ripple voltage applied to the section. The ripple outputvoltage of the section results from the current Vi/R flowingthrough the reactance 1/ωC of the capacitance C of thesection, and hence is Vi/RωC. Therefore, a section of

resistance–capacitance filter reduces each frequencycomponent of voltage applied to the input side according tothe approximate relation:

VoVi 1

RC (7.7)

whereR is the series resistanceC is the shunt capacitance.(See Figure 114(e)).When a large amount of ripple reduction is required, more

than one section is used because the total capacitance andinductance is less than that required for just one section. Thetotal reduction in ripple voltage produced by the severalsections is very nearly the product of the voltage–reductionfactors of the individual sections. The effectiveness of thefiltering accordingly increases rapidly with the number ofsections. For many applications, a single section is entirelyadequate, particularly with polyphase rectifiers. Only inspecial cases, such as audio–frequency amplifiers with veryhigh gain, will the number of sections required exceed two,and then only for those parts of the amplifier that operate atvery low signal–power levels.

Figure 112. Typical L and Section Filters: (a) and (b) L–C Filters, Choke Input; (c) and (d) L–C Filters, CapacitorInput; (e) and (f) Filters with Series Resistances

L1

C1 Load

(a)

(c)

(b)

(d)

Section

L2

C2 Load

Section

L1

C1

Section

L1

C1 Load

Section

C

Rectifier

Rectifier Rectifier

(e)

R1

C1

Section

C

Rectifier

L2

C2 Load

Section

L1

C1

Section

Rectifier

C

L2

C2

Section

L1

C1

Section

Rectifier

C

(f)



Figure 113. Reduction in Ripple Voltage Produced by a Single–Section Inductance–Capacitance Filter at Various Ripple Frequencies

L (Henries) X C (µfds)

0.5

0.2

0.1

0.05

0.02

0.01

0.0051.0 2.0 5.0 7.0 10 20 30 50 70 100 200 500

6.0

14

20

26

34

40

46

240

360

120

180

f = 60 Hz

Filt

er R

educ

tion

Fac

tor

=O

utpu

t Vol

tage

Inpu

t Vol

tage

Filt

er R

educ

tion

Fac

tor

(dB

)101

Figure 114. Ripple Factor for Single–Section LC Filter for Full–Wave Input

1005

210

5

21.0

5

20.1

5

20.01

2 5 1 2 5 2 5 2 5 2 5

i2 LC

Minimum Value of i2 LCto avoid resonance

r f, R

ippl

e F

acto

r (%

)

10–1 102 103 104

Graded FiltersWhen the output of a rectifier–filter system is called upon

to supply voltages for several stages of an amplifier system,ordinarily the amount of ripple or hum voltage that can betolerated is least for those stages that operate at the lowestsignal–power levels. This makes it desirable to arrange thefilter system so that the voltages applied to different circuitsoperated from the rectifier–filter system undergo differentamounts of filtering.

For example, the output stage of an audio amplifierobtains its collector voltage directly from the inputcapacitor, which is permissible because of the high powerlevel at which the output stage operates, combined with thehum–suppressing action of the usually used push–pullconnection. Progressively increased filtering, is providedfor the lower level stages, care being taken to design thesystem so that the reduction in ripple voltage introduced bythe filter between stages is at least as great as theamplification of the stages.

A graded filter reduces to the lowest possible value themagnitude of the currents that must be carried by the seriesimpedance arms of the filter and often makes it practical touse resistance–capacitance filter stages in parts of thesystem, as illustrated in Figure 114. This results insubstantial economy in cost, weight, and size compared toan arrangement in which the entire rectifier output is subjectto the maximum amount of filtering. A graded filter alsoprovides isolation or decoupling between amplifier stages,thereby reducing regeneration.

Filter Component SelectionThe inductors used in a low–frequency filter must have

laminated iron cores with an air gap that is sufficient toprevent the dc magnetization from saturating the core. Theinductance that is effective in the filter is the incrementalinductance, which depends both upon the dc and the acmagnetizations of the core. In estimating the acmagnetization that can be expected, it is normally assumed



that the alternating current flowing in the inductance is equalto the voltage of the lowest ripple frequency applied acrossthe input of the filter section, divided by the reactance of theinductance of the section. The alternating magnetization inthe inductance of the first section may be relatively large,whereas the alternating magnetization for the inductances ofthe other filter sections will be very small if the first sectionis at all effective.

The capacitors used in filters must be capable ofcontinuously withstanding a dc voltage equal to the peakvoltage applied to the rectifier. Electrolytic capacitors areordinarily used where the peak voltages do not exceed 400to 500 V. Such capacitors have very low cost in proportionto capacitance, but they possess the disadvantage of alimited life. Various types of plastic capacitors are usuallyused at higher voltages and also find use at lower voltageswhere long life is more important than low cost.

Example of Power Supply DesignInformation given in this chapter is used to design a power

supply for an audio amplifier in a home entertainmentcenter. The dc supply voltage will be obtained from a 120 V,single–phase line. Electronic regulation is not necessary,economically feasible, or particularly desirable for suchapplications. The supply will consist of a step–downtransformer, rectifier diodes, and a capacitive–input filter asshown in Figure 116.

Design Constraints

For this example, a supply is to be designed to meet thepower requirements of a 20 W stereo amplifier (operating ina maximum ambient temperature of 55C) which must drive8–Ω speaker loads. The output power transistors are in atotem–pole configuration and operate from a single dcsupply. Theoretically, a 36 V supply would be adequate, buta full load voltage of 40 V is required to make up fortransistor and resistive losses. The average current drawnfrom both channels at rated power out (20 W per channel) is1.43 A. To minimize distortion, idle current is 50 mA perchannel. At zero signal, the ripple is critical and must be heldto 400 mV maximum so that no hum is detectable.Regulation is not critical, but it is desirable to keep theno–load voltage below 50 V to ease the voltage requirementsof the output transistors.

Figure 115. Bridge Circuit Used for Example Design

+

–

C

RS

VL

From the previous discussion, the power supplyspecifications are summarized in terms of the constantsrequired:

1. = 2 f = 377 rad/sec2. RL = VL(DC)/IL(DC)

= 40/1.43 = 28 at full load= 50/0.1 = 500 at idle

3. VL(DC)(full load)/VL(DC)(idle) = 80%4. rf = 400 mV/50 V = 0.8%

Passive Component SelectionThe choice of circuit is between a single–phase

full–wave center–tap or a full–wave bridge circuit asoutlined in Table 16 in Chapter 5. The center–tap requiresonly two diodes, but it has the disadvantages of requiringan additional winding, causing a poorer transformerutilization factor, and doubling the required voltage ratingsof the diodes. The deciding factor in favor of using thebridge rectifier circuit is its higher secondary utilizationfactor. This is an important consideration when using acapacitive input filter because high rms currents arerequired from the transformer to obtain good outputvoltage regulation (i.e., a low RS/RL ratio is required).

The curves shown in Figure 110 are used to find a valuefor C to meet the ripple specification. To use the curves, itis necessary to estimate a value for the RS/RL ratio. This canbe done by referring to Figure 108 and assuming that the idledc voltage equals the peak of the input voltage and that theωCRL product is large enough to place operation in the righthand plateau of Figure 108. Based on these assumptions,note that to hold VL(DC)/VM above 80%, RS/RL < 7%. If itis desired to minimize1 C, then operation may move into theknee region and RS/RL may need to be made considerablyless than 7% to hold VL(DC)/VM to 80%.

From Figure 110, at ωf = 0.8%, RS/RL = 1% (beingconservative), read ωCRL = 90. Therefore, C = 90/(377)(500) = 496 µF and a standard value of 500 µF can be used.

A suitable value for RS to maintain the required voltageregulation can be obtained by using Figure 108. Under fullload with C = 500 µF, ωCRL = 5.2. Again assuming that theoutput voltage at idle equals the peak input voltage, whichmakes VL(DC)/VM = 80%, read RS/RL ≈ 3.5% atωCRL = 5.2. Therefore, RS = (0.035) (28) ≈ 1.0 Ω. Thisvalue may be largely composed of the sum of thetransformer secondary resistance, the reflected primaryresistance, and the diode dynamic resistance.

At idle, RS/RL = 1.0/500 = 0.2% and, as previously found,ωCRL = 90. From Figure 108, VL(DC)/VM is read as 97%,which verifies the validity of the assumption that at idleVL(DC) = VM.

1In many cases, minimizing C will result in lower cost. However,by choosing a larger value of C, RS may be increased to obtainthe same voltage regulation, with the beneficial effects of lowerruts and peak surge currents. The lower rms values may result inlower cost for the transformer and diodes, so that the overallpower supply cost is less.



Transformer SelectionThe peak output voltage developed across the capacitive

filter has been specified as 50 V, which requires atransformer secondary rms voltage of 35 V. However,because of the forward voltage drops across the diodes, astandard 36 V transformer may be used. The transformervolt–ampere rating is dependent on rms current, which canbe obtained from Figure 109. At full load RS/RL = 3.5% andωCRL = 5.2. In full–wave circuits, n = 2, the value ofnωCRL = 10.4, and RS/RL = 3.5%, yielding a diode currentform factor of approximately 2.1. The load and secondaryform factor, being full–wave, is l/√2 times the diode formfactor. Consequently, the transformer rating is

VA (36) (1.43) (2.1) 2 77.

Diode SelectionA diode bridge assembly is chosen for ease of installation.

Since each diode’s reverse voltage is clamped by the filtercapacitor, the bridge voltage rating need only be sufficientto handle a high line condition, typically 130% of nominal.In this application, 100 V diodes are adequate.

In choosing a bridge, the total output current of 1.43 A isused as a selection guide rather than average current perdiode. A series of bridges with 2.0 A current ratings will beevaluated for this application. It is necessary to determinewhether these bridges can handle the repetitive peakcurrents into the filter and the initial surge current requiredto charge the filter capacitor.

The steady–state peak–to–average current ratio can beobtained from Figure 109. With RS/RL = 3.5% andnωCR = 10.4, a peak–to–average ratio per leg of 7 isinterpolated. Consulting Figure 116, taken from the diode’sdata sheet, a peak–to–average ratio of 7 per leg yields amaximum full–wave average current capability of about 1.7A at 55C, which exceeds the requirement comfortably.

I L(D

C),

DC

Out

put C

urre

nt (

Am

p)

Figure 116. Derating Data for the Example

2.0

1.6

1.2

0.8

0.4

020 60 80 100 120 140 160 1800 20040

TA, Ambient Temperature (°C)

(Per Leg)

Capacitive LoadsIFM/IF(AV) = 5.0IFM/IF(AV) = 10IFM/IF(AV) = 20

Resistive InductiveLoads

Full–Wave Bridge Operation

The diode bridge assembly has a surge current rating of 60A for one cycle; i.e., it will handle two 60 A, half–cycle (8.3ms) surges. The worst–case peak surge current in thisapplication is

VMRS 501.0 50 A

The time of the surge is the time it will take to charge thecapacitor, roughly the time constant of the series resistor andthe filter capacitance, or

t RSC (1.0) (500) F 0.5 ms.

Since the surge current is less than the rating and the timeis much less than one cycle, the bridge will be satisfactory.

References1. 1. J. Schaefer, Rectifier Circuits, John Wiley and

Sons, Inc., New York, 1965, p. 258.2. 2. 0. H. Schade, Analysis of Rectifier Operation,

Proc. IRE, Vol. 31, No. 7, July, 1943, pp. 343–344,346–347.

3. 3. Robert H. Lee, Origin and Characteristics ofHarmonic Currents, Part I, Power Quality,Volume 1, No. 5, 1990, pp. 349–351.

4. 4. Arthur W. Kelley and William F. Yadusky,Rectifier Design for Minimum Line CurrentHarmonics and Maximum Power Factor,Conference Proceedings of the Fourth AnnualPower Electronics Conference and Exposition,Baltimore, 1989, IEEE Document number:89Ch2719–3.

EQUATION 7. 1

is derived as follows:

DC componentVM

t

t0

sint d(t) 2VM

Ripple component of

2VM

t

t0

cos nt sin t d(t)

2VMcos (n 1)t

2 (n 1)

cos (n 1) t2 (n 1)

2VM 2n2 1

frequency n2

t 0t

In these equations n may have values 2, 4, etc.



Chapter 8

Rectifier Voltage Multiplier Circuits



"

Voltage–multiplying power supply circuits are oftenemployed when high–voltage sources are required, currentdemand is small, and regulation from the rectifier system isnot too important. Voltage doublers are widely used in“universal input” line–operated equipment.

The principle of operation for all multiplying circuits isessentially the same. Capacitors are charged and dischargedon alternate half–cycles of the ac supply voltage. Thevoltage at the output terminals is the sum of these voltagesin series. Thus, the rectifier loading is necessarily capacitive,and high peak currents flow through the rectifier, much likerectifier circuits with capacitor input filters.

Voltage–Doubling CircuitsThe conventional full–wave voltage doubler is shown in

Figure 117. It is the most commonly used voltage–doubling,circuit. The circuit operates as follows: C2 is charged to VMthrough D2 and RS2 during the negative half–cycle of thesupply voltage. During the positive half–cycle, the supplyvoltage charges C1 trough D1 and RS1. A voltage of 2 VMappears across the output terminals. The capacitors’ voltageratings must be greater than VM, and the peak voltage ratingof the rectifiers, VRRM must be greater than 2 VM. The ripplefrequency is twice that of the input supply.

Figure 117. Conventional Full–Wave Doubling Circuit

D1

RS1

D2

C2C1

RS2

RS1 RS2

=

=

VMsin t

2 VM

Conventional voltage–doubler circuits may be designedfrom curves similar to those used for capacitor input filters.(See Figures 118 through 121.) Voltage doublers exhibit thehigh inrush and peak repetitive currents encountered withcapacitive input filters. The source resistance, RS, must bechosen to limit the inrush current to a safe level.

As an example, suppose approximately 200 V dc isrequired from the ac line to supply a l kΩ load. A rectifier isselected whose surge rating is 10 A. Ripple is not critical andit is desired to minimize capacitor size.

RS is selected from:

RS VM(max)IFSM (1.41)(130)10 (High line is taken as 130 V)

19 (use 20 ).

Capacitor size is determined by using Figure 118, whichrequires that VL(DC)/VM and RS/RL be calculated.

VL(DC)VM 200(1.41)(117) 1.21

(Normal line is taken as 117 V)

RSRL 201000 2%

Read CRL 7.0,

"C 7.0RL 7.0(377)(103)

18.6 F (Use 20 F).

With C = 20 µF ωCRL = 7.54 and the remaining circuitinformation may be found:

From Figure 119, IFM/IF(AV) = 5.5From Figure 120, If/IF(AV) = 2.2From Figure 121, rf = 13%.



Figure 118. Output Voltage as a Function of Filter Constraints for Full–Wave Voltage Doubler

2.0

1.8

1.6

1.4

1.2

10

0.8

0.61.0 4.0 10 40 100

0

0.25

0.50.751.0

1.5

2.0

4.0

6.0

10

12

15

0.1

2.0 6.0 20 60 200 400

20

CRL, (C in Farads. RL in Ohms)

%

VL(

DC

)/VM

RSRL

l f/I F

(AV

)

Figure 119. Peak Rectifier Current as a Function of Filter Constants for Full–Wave Voltage Doubler

108.06.0

4.03.0

2.0

1.0

20

40

60

100

0.010.025

0.050.10.250.51.02.55.01550

0.2 0.4 1.0 2.0 4.0 10 20 40 100 200 400 1000 2000

ωCRL (C in Farads, RL in Ohms)

%RSRL



Figure 120. rms Rectifier Current as a Function of Filter Constants for Full–Wave Voltage Doubler

10

8.0

6.0

4.0

3.0

2.0

1.0

0.01

0.0250.050.10.250.51.02.551550

0.2 0.4 1.0 2.0 4.0 10 20 40 100 200 400 1000 2000


I f/ I

F(A

V)

RSRL

r F, R

ippl

e F

acto

r (%

)

Figure 121. Ripple as a Function of Filter Constants for Full–Wave Voltage Doubler


10050

20

10

5.0

2.0

1.0

0.5

0.2

0.11.0 2.0 5.0 10 20 50 100 200 500 1000

0.1%RS/RL = 10%

In the cascade circuit (Figure 122), C1 is charged throughD2 during the negative half–cycle. In the positivehalf–cycle, C1 in series with the input voltage charges C2to a voltage of 2 VM, when RL is very large. The capacitorC1 should be rated greater than VM, C2 greater than 2 VM,and the rectifier should have a peak inverse voltage ratingexceeding 2VM. The ripple frequency is that of the input.

The cascade voltage doubler has poorer voltageregulation because the charge on C1 must supply the chargeto C2; however, it has the advantage of a common connectionbetween the output and the input. To compare the twovoltage–doubling circuits, the circuits may be evaluatedusing similar components. The resulting characteristics aregiven in Table 22. Design curves have not been worked outfor the cascade circuit. It performs better when C1 is muchlarger than C2.

Table 22. Voltage Doubling Circuit Characteristics


CircuitConfiguration


VinVolts(rms)


RsOhms


RLOhms

ÁÁÁÁÁÁÁÁÁ

CF


VL(DC)Volts


IL(DC)mA


rf%


Conventional ÁÁÁÁÁÁÁÁ



1k ÁÁÁÁÁÁ



205 ÁÁÁÁÁÁÁÁ

12.0


Cascade ÁÁÁÁÁÁÁÁ



1k ÁÁÁÁÁÁ




16.0



“Universal” Input CircuitSwitchmode power supplies normally rectify the ac

power line mains directly without using a low–frequencytransformer. Isolation from the line is provided by thehigh–frequency transformer in the power supply. Mostmanufacturers supply to the worldwide market place whoseac mains voltages and tolerances fall into two broad ranges:90 to 130 V ac, and 180 to 270 V ac.

RL

C1

C1 = C2

Figure 122. Cascade (Half–Wave) Voltage DoublingCircuit Full–Wave Voltage Tripler Circuit

C2

D1

D2

RS2 VM

VM sin ωt

A popular means of accommodating both ranges is shownby the circuit of Figure 123. When the switch is open, thecircuit operates as a full bridge rectifier. With 230 V ac input,the dc output is approximately 320 V. When the switch isclosed, the circuit is configured as a full–wave voltagedoubler, producing about the same output with a 115 V acinput. The switching power supply is designed to provide aregulated output despite variations in the dc level caused byoperation over either ac input range.

Switching can be made automatic [1] in response to theapplied line voltage in order to eliminate power supplyfailure caused by having the switch or terminal straps in thewrong position. For automatic switching, a triac is used forthe switch. It is turned on by a circuit which senses when theac line peaks are below that produced by 130 V rms. Tosimplify the design, integrated circuits such as the MC3423P overvoltage sensing circuit are available.

The ripple is highest when the circuit is operating in thevoltage–doubling mode. To conserve space and lower cost,small capacitors are desirable. Therefore, high ripple on theorder of 10 to 20% is often allowed; the switching supplyreduces the ripple to a low value in its outputs. On the otherhand, in high–quality equipment designed to ride through ahalf or full cycle line voltage dropout, the filter capacitorsmay be somewhat oversized in order to provide the desiredhold–up time.

The preceding example illustrated the use of the curveswhen maximum output voltage was not a design goal butit was desired to minimize the capacitor size. In most cases,

particularly for the universal input, ωCRL is chosen on theorder of 50 or more and RS/RL is as small as practical inorder to obtain a high output voltage. For example, withωCRL = 100 and RS/RL = 1%, VL(DC)/VM is only 1.7 (fromFigure 118). To more nearly approach 2, RS/RL ratios arechosen on the order 0.25%. With RS/RL = 0.25% andωCRL = 100, VL(DC)/VM is a much more acceptable ratio of1.85. However, the rectifier peak–to–avenge current ratiois now about 11. (See Figure 119) When switched to fullbridge operation, the filter capacitors are placed in seriesdropping ωCRL to 50. The curves in Chapter 7 reveal thatVL(DC)/VM = 0.96 and IFM/IF(AV) = 15, worse than duringoperation as a doubler.

C1

C2

Figure 123. Dual Input Voltage Range Circuit

Z

AC

During turn–on, the low value of RS needed for gooddoubler operation results in enormously high inrush current.Consequently, universal rectifier circuits must use somemethod of having RS high at turn–on and low duringsteady–state operation. Two schemes are presently used;one uses a negative temperature coefficient thermistor andthe other uses a triac.

The thermistor is used in place of RS on Figure 123 and ischosen to have a room temperature resistance to limit inrushcurrent to a safe value. As charging current flows, thethermistor heats; its temperature rise causes a correspondingdrop in its resistance value. The time constant of thethermistor must be longer than that of the rectifier filter forthis scheme to work. The disadvantage of the thermistor isthat it cannot respond to momentary interruptions on the acline which allows a high surge current to flow when the linevoltage reappears.

A more foolproof and commonly used scheme parallelsRS – which is large – with a triac. A control circuit fires thetriac when certain circuit conditions are met which insuresthat the capacitors are fully charged.



Voltage Tripling CircuitsThe full–wave voltage tripler shown in Figure 124

operates as follows. On the negative half–cycle of thesupply voltage, C1 and C3 (in parallel) charge to VM. On thepositive half–cycle C1 (in series with the supply voltage)charges to 2VM. Thus a voltage of 3VM will appear at theoutput terminals of the circuit. The voltage rating of C1 andC3 must be greater than VM, and the rating of C2 must begreater than 2VM. The diodes should be able to block atleast twice the maximum peak value of the input supplyvoltage. The ripple frequency of the output is twice that ofthe input. The output characteristics for the full–wavetripler are shown in Figure 125.

The cascade principle may be extended to obtain a voltagetripler as shown in Figure 126. The operation of the cascadevoltage tripler is quite similar to that of the cascade voltagedoubler circuit. The voltage rating of C1 should be greaterthan VM and the voltage ratings of C2 and C3 should begreater than 2VM. The peak inverse voltage ratings of the

diodes should also exceed 2VM. The ripple frequency of theoutput voltage will be the same as the frequency of theapplied voltage.

As might be anticipated, the regulation and ripple of thecascade voltage tripler is inferior to that of the full–wavevoltage tripler. For a comparison of the two circuits, refer toTable 23.

Figure 124. Full–Wave Voltage Tripler Circuit

D1

D2

3 VM

RS

C2

R L

C3

C1

D3

VM sin ωt

Figure 125. Output Characteristics for the Full–WaveVoltage Tripler Circuit of Figure 124.

500

400

300

200

100

00 40 80 120 160 200

40

36

32

28

24

20

16

12

8.0

4.0

0

VL(

DC

)Out

put V

olta

ge (

Vol

ts)

Rip

ple

Vol

tage

(V

olts

rm

s)

IL(DC), Load Current (mA)

VL(DC)

Ripple

C1 = C2 = C3 = 20 µFVin = 117 V (rms)RS = 20 Ω

Figure 126. Cascade (Half–Wave) Voltage Tripler

D1D2

3 VM

RS C2

R L

C3

C1

D3VM sin ωt

Table 23. Voltage Tripling Circuit CharacteristicsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CircuitConfiguration

ÁÁÁÁÁÁÁÁÁ

RLOhms


VL(DC)Volts


IL(DC)mA

ÁÁÁÁÁÁÁÁÁ

rf


RLOhms


VL(DC)Volts


IL(DC)mA

ÁÁÁÁÁÁÁÁÁ

rf%


Full–Wave ÁÁÁÁÁÁ

5.0 kÁÁÁÁÁÁÁÁ


77 ÁÁÁÁÁÁ

2.4ÁÁÁÁÁÁÁÁ



170 ÁÁÁÁÁÁ

8.0


Half–Wave ÁÁÁÁÁÁ



66 ÁÁÁÁÁÁ




112 ÁÁÁÁÁÁ

37.0



Voltage QuadruplesThe full–wave voltage quadrupler circuit of Figure 127

operates in the following way: Assume that the input supplyvoltage is positive. This causes capacitor C1 to chargethrough D2 to VM. Also, capacitors C4 and C2 in series withD4 charge to VM/2 (assuming the capacitors are equal invalue). The charging voltage polarities of C1, C2 and C4 atthis point are shown in Figure 127. On the negativehalf–cycle, C1 in series with the supply voltage charges C3through D1 to 2 VM. Also, capacitor C2 charges to VMthrough D3 with the opposite polarity than that shown inFigure 127. On the next positive half–cycle, capacitor C4 ischarged to 2 VM since the voltage across C2 and the supplyvoltage are in series. In addition, the charge on C1 isreplenished. At this point, the output voltage across C3 andC4 is 4VM. The next negative cycle replenishes the chargeon C2 and C3 and the next positive cycle replenishes thecharge on C1 and C4.

The ripple on the output has a frequency twice that of theinput. The voltage rating of C1 and C2 must be greater thanVM while that of C3 and C4 must be greater than 2 VM. Allof the diodes must have a voltage rating greater than 2 VM.Output characteristics are shown in Figure 128.

The cascade half–wave voltage quadrupling circuit isshown in Figure 129. The operation of this circuit isbasically the same as the other cascade networks. Thecapacitance of C1 should be high and its voltage rated aboveVM while the remaining capacitors and the diodes should berated above 2 VM. The ripple frequency of the output is thesame as that of the supply.

The regulation of the half–wave voltage quadrupler isinferior to the full–wave as might be expected. (CompareFigure 128 to Figure 130.) To improve regulation, the valuesof capacitors C1 and C2 are increased. To illustrate thisimprovement, the output characteristics of the circuit ofFigure 129 were obtained when all capacitors equal 20 µFand 40 µF The results are shown in Figure 130.

D1

D2

4 VM

RS

C2

R L

C3

Figure 127. Full–Wave Voltage Quadrupler*Voltage Polarity is opposite to that shown when fully

charged. See text.

C1 D3

C4

D4

– +

+

–

+–

+–

+–VM sin ωt

*

Figure 128. Output Characteristics of a Full–Wave Voltage Quadrupler Circuit.

600

500

400

300

200

100

010 20 40 60 80 100

24

20

16

12

8

4

0

VL(

DC

)Out

put V

olta

ge (

Vol

ts)

Rip

ple

Vol

tage

(V

olts

rm

s)


C1 = C2 = C3 = C4 = 20 µFRS = 20 OhmsDiodes: 1N4003VS = 117 Volts (Line)

Ripple

Output Voltage



D1 D2

RS C2

R L

C3

C1

D3

C4

D4

Figure 129. Cascade (Half–Wave) Voltage Quadrupler Circuit

Figure 130. Output Characteristics of the Half–Wave Voltage Quadrupler Circuits

600

500

400

300

200

100

00 20 40 60 80 100

60

50

40

30

20

10VL(

DC

)

Rip

ple

Vol

tage

(V

olts

rm

s)

Out

put V

olta

ge (

Vol

ts)

40 µF

20 µF

OutputVoltage

C1 = C2

Ripple

40 µF

20 µF


VM sin ωt

Figure 131. n–Section Voltage Multiplier Circuit

RS

C2

R L

C3C1

C4 C n2 C n

C5 C n1

2VM 2VM

2VM 2VM

VM sin ωt

High–Order Cascade Voltage MultipliersIn theory, the number of sections which can be added to

the basic cascade circuit is unlimited, as illustrated inFigure 131. In practice, the number of sections is limitedbecause the regulation becomes progressively worse asadditional sections are added.

Both even and odd multiples of VM can be obtained. Thecapacitor connected to the supply charges to VM. Theremaining capacitors on that side of the circuit charge to 2 VM.

Thus, odd multiples of VM from the upper branch and evenmultiples from the lower branch can be obtained with respectto ground.

References1. S.K. Tong and K.T. Cheng, External–Sync Power

Supply with Universal Input Voltage Range forMonitors, ON Semiconductor Application Note,AN1080.



Chapter 9

Transient Protection of Rectifier Diodes



In order to achieve the high degree of reliability alreadyassociated with silicon rectifier diodes, it is imperative tounderstand that the ratings are based on the absolutemaximum rating system. With this system, ratings applywithin a certain defined set of operating, test, orenvironmental conditions, and degradation or failure may becaused by a combination of electrical or environmentalstresses, even though application of any one rating will notimpair the performance of the device. Ratings areestablished by extensive tests, including life–testsconducted by the manufacturer, and are typically checkedduring production by quality control sampling. The usershould be aware that there is no safety factor implied aboveeach maximum rating, although manufacturers generallyemploy one.

Because of the intolerance of silicon rectifier diodes tovoltage transients in excess of their ratings, a proper circuitdesign generally requires some built–in means to afford safeoperation. Therefore, it is imperative to discuss some of thecauses of voltage transients and means of limiting them.Unwanted transient voltages, commonly referred to assurges, are present in all electrical and electronic systems.The origin of surges may be external to the electronicequipment or surges may be internally generated by theequipment’s electronic circuits. Surges are randomlycreated on the utility distribution system by lightning,capacitor bank switching, start–up and shut down ofelectrical and electronic equipment, and fault clearing.These surges often have high energy and must be consideredin the design of rectifier circuits operating from the utilitymains. Internally generated surge voltages are usuallycaused by rapid switching of current. The surge voltageproduced is a result of energy stored in circuit and wiringinductance.

Overcurrent can also lead to failure of semiconductordiodes. The small thermal mass associated with silicondevices allows the junction temperature to rise and fall veryrapidly during a current surge and remain undetected by anexternal thermocouple. If, during this event, the junctiontemperature exceeds the maximum rated value, the devicemay fail destructively (short) as a result of thermalbreakdown.

Consequently, silicon diodes are specified so that theexcursion of the junction temperature during expectedoverloads can be calculated and thus held within properlimits through circuit design and thermal management.Fuses, circuit breakers, or protective circuitry are used toprotect rectifier diodes from excessive current.

Externally Generated Voltage SurgesSeveral years of work by many people in IEEE

committees culminated in the publication of IEEE standard587–1980, which describes “typical” transient conditionsoccurring in unprotected power circuits. It addressestransient voltages that exceed twice the peak operatingvoltage, with durations ranging from a fraction of amicrosecond to a millisecond, and originating primarilyfrom system switching and lightning effects. Transientsshorter than 100 ns and long–duration surges that sometimesexist on power lines are not covered by the standard. Thestandard also proposes tests which approximate thereal–world transient conditions for the purpose ofevaluating the survival capability of equipment connected toac mains. The IEEE standard was later adopted by ANSI andgiven the document number C62.41.

A major revision of the standard was issued in 1991,upgrading it to a “recommended practice.” [1] Designers ofpower–line operated equipment should familiarizethemselves with its contents. The revised document, whileretaining most of the original information, provides updatedand expanded information relevant to “typical” surgeenvironments based upon location within a building.Additional guidance is given on suggested specifications tobe used for equipment, based upon exposure level. Thematerial which follows is based upon the main points of therecommended practice, applicable to the design of aline–operated rectifier system.

Three location categories are defined: “A” and “B” forindoor applications, and “C” for outdoor applications. Thelocation categories are further defined in Figure 132. Theytake into consideration the increase in power–lineimpedance to high–frequency surges from the outside tolocations well within the building. Most consumerelectronic equipment can be expected to find use in locationcategory A while industrial commercial equipment is oftenlikely to be used in category B locations.



Outbuilding

Outbuilding

Meter

Meter

Meter

Transformer

ServiceEntrance

ServiceEntrance

Underground Service

(a)

(b)

(c)

AOutlets and long branch circuits.All outlets at more than 10 m (30 ft)from Category EAll outlets and more than 20 m (60 ft)from Category C

BFeeders and short branch circuitsDistribution panel devicesBus and feeder in industrial plantsHeavy appliance outlets with “short”connections to service entranceLighting systems in large buildings

COutside and service entranceService drop from pole to buildingRun between meter and panelOverhead line to detached buildingUnderground line to well pump

Demarcation between Location Categories B and C is arbitrarily taken to be at the meter or at the mains disconnect (NECArt. 230–70 [B2]) for low–voltage service, or at the secondary of the service transformer if the service is provided to the userat a higher voltage.

Figure 132. Location Categories



A summary of data taken on the rate and magnitude oftransient voltage occurrence is provided. Transientoccurrence varies over wide limits depending upon thepower system, its loading, and the amount of lightningactivity. Data collected from many sources have led to theplot shown in Figure 133. This prediction shows only therelative frequency of occurrence, while the number ofoccurrences can be described only in terms of low, medium,or high exposure. These exposure levels are defined ingeneral terms as follows:

1. Low Exposure. Systems with little load switchingactivity, that are in geographical areas known forlow lightning activity.

2. Medium Exposure. Systems in geographical areasknown for medium–to–high lightning activityand/or significant switching transients.

3. High Exposure. Rare but real systems subject tosevere switching transients and/or extensivelightning activity.

Figure 133. Annual Rate of Occurrencesat Unprotected Locations

1

Num

ber

of S

urge

s P

er Y

ear

Exc

eedi

ng

Sur

ge C

rest

of A

bsci

ssa

0.3 0.5

10

2 5 10 20

3

10 2

10 1

1

10 –2

10 –1

LowExposure

*ClearanceSparkover

MediumExposure

HighExposure

*In some locations sparkover of clearances may limit the overvoltages to lower levels

Two recommended standard test waveforms are definedas shown in Figure 134. The first test wave is called acombination impulse wave; its open circuit voltage andshort circuit current are shown in Figure 134(a) andFigure 134(b) respectively. The second test wave is a ringwave as shown in Figure 134(c).

Impulse waves have been in use for many years to testlightning arrestors and high–power surge suppressiondevices, because impulses are characteristic of thewaveform produced by lightning strikes to power lines. The

short form nomenclature for an impulse wave is tr/td wheretr denotes the rise time and td denotes the pulse width,defined at the point where the amplitude has decayed to 50%of its peak value. Thus the combination wave has a 1.2/50 µsopen–circuit voltage and an 8/20 µs short–circuit current.The impulse wave deposits substantial energy in asurge–protective device and is usually chosen to specifyprotector performance. For example, UnderwritersLaboratories (UL) has chosen the standard’s combinationwave to test portable power taps (i.e., power strips) havingsurge–protective devices.

Figure 134. Standard Test Waveforms Defined

50 s

0.5 Vpeak0.3 Vpeak

0.9 Vpeak

VV peak

T1

20 s

0.9 I peak

0.1 I peak

T2

T x 1.25 = 8 s2

T x 1.67 = 1.2s1

I peak

0.5 I peak

0.9 Vpeak

0.1 Vpeak

0.5s

60% of V peak

V peak

(a) 1.2 x 50 sec Impulse

(b) 8 x 20 sec Impulse

(c) 0.5 s – 100 kHz Ring Wave

T = 10 s (f = 100 kHz)



Based upon a consensus of engineering experts, theamplitudes expected for various combinations of locationcategories and exposure levels are shown in Table 24. Theinformation is taken from the updated version of C62.41; inthe original version, only the high exposure levels weresuggested. The revision recognizes the significance ofsystem exposure as well as equipment location categories.

The ring wave is typical of most disturbances within abuilding because transient energy excites the naturalresonant frequency of the wiring system. In practice, thefrequency can vary from a few kilohertz to a few hundredkilohertz. The fast rise time is used because equipment usingthyristors is prone to false triggering with high dv/dt, and fastrising wavefronts can cause a nonuniform voltagedistribution in windings. The 0.5 µs/l00 kHz ring wave istherefore primarily aimed at evaluating equipmentimmunity to fast wavefronts and high–frequencydisturbances. Since the ring wave is not intended to checkenergy capability, its effective source impedance is chosenmuch higher than that of the combination wave.

Fast–rising surges are produced on power lines byopening airgap switches such as relays and contactors.Although fast transients are attenuated rapidly with distanceby the impedance of the power line, equipment in closeproximity may be affected. A common situation occurswhen two pieces of equipment are powered from the sameduplex receptacle. Switching off the power to one willcouple a high–frequency transient to the other, possiblycausing a malfunction. The waveform chosen to representthe fast transient is a 5/50 ns impulse applied in a bursthaving a duration of 15 ms. It is delivered by a generatorhaving a 50 Ω source impedance with a peak amplitude of

1 kV, 2 kV, or 4 kV depending upon the severity leveldesired.

High–energy surges have been added to the menu ofwaveforms. The 10/1000 µs impulse is suggested as typicalof lightning–induced pulses traveling in long undergroundcables, surges generated by fuse blowing in long cables, andthe envelope of the oscillation caused by capacitor bankswitching. A 5 kHz ring wave is also suggested as typical forthe oscillation caused by capacitor bank switching.

The levels and impedance values chosen for testing withthe high–energy surges are shown in Table 25. Buildinglocation categories do not apply because the building wiringdoes not significantly attenuate the low–frequency surges.Levels of test voltages and source impedance of the surgesare based upon system exposure and the system voltage. Forexample, the peak total voltage developed by fuse clearingoccurring near the peak of the power line voltage, for a 120V rms line in an industrial environment, is the sum of peakline voltage and peak transient voltage. That is:

Vtotal 120 2 (1.3)(120) 2 390 V

In reviewing the data presented, it is obvious that thetransient voltage levels are highly site dependent. Thedilemma a designer faces is to provide sufficient transientprotection to equipment to insure a reasonable survival ratewithout adding excessive cost, although the location wherethe equipment will be used and the severity of the exposurelevel is not known. A reasonable solution to the dilemma isto design for a category B, medium exposure level. Userslocated in high exposure sites have no doubt experiencedtroubles with all electronic equipment and have installedsurge protective devices throughout the facility.

Table 24. Suggested Levels of Standard Voltage and Current SurgesÁÁÁÁÁÁÁÁÁÁ



ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ring WaveÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CombinationÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

LocationCategory


SystemExposure


PeakVoltage


PeakCurrent


EffectiveImpedance


PeakCurrent


EffectiveImpedance


A ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

LowMedHigh


2 kV4 kV6 kV


67 A133 A200 A


300300300


–––


–––


B ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

LowMedHigh


2 kv4 kv6 kV


167 A333 A500 A


120120120


1 kA2 kA3 kA



CÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

LowMedHigh


6 kV10 kV20 kV


–––

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

–––


3 kA5 kAl0 kA


Table 25. Suggested Levels for High Energy SurgesÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ10/1000 s Impulse

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1.5 s/5 kHz Ring WaveÁÁÁÁÁÁ


SystemExposure


ExposureDefinition


PeakVoltage


SurgeImpedance


ExposureDefinition


PeakVoltage


SurgeImpedance


Low ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Residential ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

– ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

– ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Far fromSwitched Bank


– ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

–


Medium ÁÁÁÁÁÁÁÁÁÁ

Commercial ÁÁÁÁÁÁÁÁÁÁ

1.0 Vpk ÁÁÁÁÁÁÁÁÁÁÁÁ

1 Ω ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Typical ÁÁÁÁÁÁÁÁ

1.0 VpkÁÁÁÁÁÁÁÁÁÁÁÁ

1–5 Ω


High ÁÁÁÁÁÁÁÁÁÁ

Industrial ÁÁÁÁÁÁÁÁÁÁ

1.3 Vpk ÁÁÁÁÁÁÁÁÁÁÁÁ

0.25 Ω ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Near LargeSwitched Banks

ÁÁÁÁÁÁÁÁ

1.8 VpkÁÁÁÁÁÁÁÁÁÁÁÁ

0.5–1.0 Ω



Internally Generated Voltage SurgesNormal equipment operation generates surge voltages. In

practice, the possibilities are almost endless; the circuitdesigner must astutely analyze the transient–generatingpotential of a particular system in their electricalenvironment. A few situations, however, are quite common.

When transformers feed rectifiers from the ac power line,several mechanisms for generating transients exist. Ageneralized lumped circuit model for a transformer is shownin Figure 135. It should not be taken too literally because theelements shown are actually distributed in nature. However,the model allows several effects to be visualized.

Figure 135. Broadband Circuit Model of a Transformer

L P R S

R CL

R P

ZLL M

CPS

C P

L S

RCL = core loss representationLm : primary magnetizing inductanceRp : primary winding resistanceLp : primary winding leakage inductanceT : ideal transformerLs : secondary winding leakage inductanceR : secondary winding capacitanceZL’ : secondary load impedanceCPS : primary to secondary interwinding capacitanceCP : primary winding capacitanceCS : secondary winding capacitance

C S

Note that the interwinding capacitance (CPS) and thesecondary winding capacitance (CS) form a capacitivedivider. Depending upon transformer construction, theirratio may vary widely. The winding techniques commonlyused for 60 Hz applications allow CPS to exceed CS.Consequently, if a voltage step is applied at the input, suchas with a switch closure occurring at the peak of the ac line,it is possible for a voltage surge almost equal in amplitudeto the peak ac primary voltage to appear across thesecondary terminals. Since the surge is not directly relatedto the turns ratio, the rectifier reverse voltage may be manytimes the normal peak inverse voltage when a stepdowntransformer is used. It should be evident that any line voltagesurge with a fast rise time will also be coupled through theinterwinding capacitance and appear at the secondarywithout much attenuation.

In addition, because of system resonance the input voltagestep usually generates a damped oscillatory transient with apeak amplitude possibly as high as twice the normalsecondary voltage. The frequencies of oscillation aredetermined by the values of the parasitic reactances in thetransformer and its load. The effects just described areillustrated in Figure 136.

Figure 136. Situation where TransformerInterwinding Capacitance Couples a Transient to the

Secondary

Switch

Load

A

B

PS

May Have StrayInductance orCapacitance

+

–+

–SwitchClosed

VLine

VAB

VAB

Opening the primary circuit may generate even moreextreme voltage transients resulting from the collapse of themagnetic flux in the core, represented by LM in Figure 135.A worst–case situation is shown in Figure 137 where switchopening occurs at the time of zero voltage crossing of the acline. At this time, the magnetizing flux is at its maximum andits collapse may produce a transient, an order of magnitudehigher than the normal secondary voltage. In practice, thegenerated surge voltage is not as clean as shown because ofswitch arcing.

Figure 137. Typical Situation Showing PossibleTransient when Interrupting Transformer

Magnetizing Current

Load

SwitchOpened

LineVoltage

MagnetizingCurrent and

SecondaryVoltage

Flux

ACLine

I M

Switch

A

B



Switching of loads on the output of a rectifier can causetransients to be developed across the diodes, as shown inFigure 138. The inductance LEQ represents the equivalentinductance of the power source, consisting of wiringinductance plus leakage inductance if a transformer ispresent. A short across Load 2 causes a very high current tobe drawn which stores a large amount of energy in LEQ.When the fuse blows causing a rapid decrease in current, theinductance generates a voltage of Ldidt having an energy ofLI2/2. A similar but less severe effect occurs when normalloads are intentionally switched off.

LEQ

Figure 138. Transients Caused by Load Switching

A

B

+

–

VAB

Shortacross Load 2Load

2Load

1

ACSupply

Fuse

+

–

0

Surge Protection CircuitsEffective control of transient voltage surges in equipment

used on ac power lines invariably uses a metal oxide varistor(MOV). It can handle a large amount of transient energy forits weight, size, and cost. Service life is long, if properlyapplied. MOV characteristics are shown in Figure 139 for apart suitable for use across a 120 V ac power line. It isbi–directional and exhibits a fairly sharp breakdown, whichhelps limit voltage surges.

Figure 139. Typical V–I Characteristic of an MOV

I 0

+

–

– +

0

V

Transients from lightning and many other sources enterthe power system as a current source. The high surgevoltages observed across power lines are the result of highsurge currents flowing through the loads across the line. Inorder to prevent generation of high voltages, it is generallydesirable to use an MOV directly across the line to divert thesurge current back to its source, as shown in Figure 140. Ifthe voltage across the varistor is too high for the downstreamelectronics, an inductor is used to restrict the current flowinginto the rest of the circuit. A second MOV or othervoltage–limiting device is used to hold the voltage at thecircuit to the desired level. When a rectifier circuit with acapacitor input filter is in a medium exposure environment,it may perform the function of the second clipper.

Figure 140. Functions of Elements Used in aProtection Network

V I

FusingOptions

VO

Clip(Clamp)

Restrict

Divert

MOVs are well suited to handle the l00 kHz ring wave andthe 8/20 µs impulse associated with the majority of transientactivity. But they cannot handle the high energy of the lessfrequent long waves typical of fuse blowing, capacitor bankswitching, and line voltage swells. If the downstreamcircuits can be designed to handle these long durationsurges, which may approach twice nominal line voltage,MOVs which break down at twice the line voltage peak canbe used. This approach has a long history of success in thedesign of semiconductor based systems used in electricutility applications.

In cases where the downstream circuits cannot bedesigned to be cost–effective with a twofold voltagemargin, MOVs which clamp at lower levels may be used;however, the MOV is likely to become a sacrificial elementwhen a long–duration surge is encountered. The designeris faced with trading off the cost advantages of using lowervoltage downstream components against the increasingprobability of protective device failure as the clampingvoltage is lowered. [2] The breakdown voltage of thevaristor, as an absolute minimum, must be above the peaksof a high line voltage. For example, a l40 V(rms) rated MOVis the minimum suitable for a 120 V nominal power line inthe U.S.

Fusing the equipment is important because when an MOVfails, it fails as a short. However, the resulting fault currentwill open the device, possibly violently.



Two fusing options are shown in Figure 140. Placing thefuse in series with the input line insures that the equipmentis never operated without protection. If the line fuse is sizedto handle high power equipment or equipment having asubstantial inrush current, the varistor may rupture whenshorted before the fuse has time to open. To avoid thissituation, a rugged varistor should be selected which canhandle the line fault current for enough time to cause the linefuse to blow.

Placing the fuse in series with the MOV permits theequipment to continue operating but without protection.This approach is risky, but has merit when the downstreamcircuits are able to handle some transient voltages withoutdegradation. An additional risk introduced when the fuse isused in series with the varistor, is that of the surge caused byfuse blowing. During the time the varistor is shorted,sufficient energy may be stored in the upstream lineinductance to cause a damaging voltage surge at the inputterminals to the rectifier circuit. To minimize the surge atfuse blowing, a fast–acting or current–limiting fuse shouldbe used.

An example of applying surge suppression to athree–phase circuit is shown in Figure 141. The MOVsacross the input lines serve as the diverters. The filter chokeprovides the restrict function, and the filter capacitor alsoserves as the clipper. Since these filter components are large,the surge voltage limited by the MOVs is greatly attenuatedat the dc output. Consequently, it is usually possible to selectthe MOV breakdown voltage to exceed twice that of thenominal line voltage peaks. The inductor must be effectivefor the 8/20 µs pulse. It will need to be wound to minimize

feed–through capacitance, or else a small high–frequencyinductor can be placed in series with the low–frequencyfilter inductor. The circuit should be tested to determine howmuch surge voltage is coupled through the transformer; thesurge may not follow the turns ratio.

The popular “universal input” single–phase rectifieradapted to include transient protection is shown inFigure 142. Tests have shown the importance of matchingthe varistor voltage to the incoming line voltage and haveindicated typical performance when a 2000 A, category B,8/20 µs current surge is applied [3]. With R1 = 0.5, L1 = 100µH, and C1 = C2 = 540 µF, the 2000 A surge caused the 320V dc output voltage to rise by 74 V. In many cases, thefollowing circuits can be designed to handle this extravoltage.

The inductor may be used as part of the EMI filtercommonly required on equipment. It is also possible to usea second section of suppression to make the circuit almostimmune to transients, while the inductors also serve as thenormal mode and common mode EMI filters [4]. Such acircuit is shown in Figure 143. With a 3000 A 8/20 µs surge,the transient voltage on the output filter capacitors is a mere10 V. The peak inverse voltage across the rectifier isdetermined by the peak limiting voltage of the MOV TheEMI filter provided over 100 dB of attenuation from 6 kHzto 50 MHz, differential mode, and from 6 kHz to 12 MHzcommon mode. Good filter and surge suppressionperformance is dependent upon the coils. They need high Qover a broad frequency band and must be wound to minimizeshunt capacitance.

Figure 141. Transient Suppression in a Three–Phase Rectifier

R 1L 1

D1

D2

S1

C1

C2

S2

Figure 142. MOV Protection for a Universal Input Rectifier

Figure 143. A Transient Suppression and EMI Filter Integrated with the Rectifier Circuit

R 1L 1

M1

M2

M3

M4 L 2

L 3

L 4

R 2

R 3

R 4

C1

C2

C3

C4

TZ 1

TZ 2

LCM

C F1

C F2



Surge Current ProtectionHigh current surges cause rapid heating of the

semiconductor die. If reverse voltage is applied while therectifier junction is above its rated temperature limit, a shortmay result from the combined stresses. Furthermore, evenwhen little or no reverse voltage is present, excessivetemperature can weaken the bond of the die to its package,causing thermal resistance to increase with time in service.A long term thermally regenerative process occurs, leadingto diode destruction. In some cases, excessive current maycause the lead material between the rectifier terminal and thedie to fuse.

The type and extent of protection needed is determined bythe circuit characteristics and performance required. Circuitcharacteristics are roughly divided into two main types, andthe extremes are:• Type 1: Circuits with current limiting impedance

• Type 2: Circuits without current limiting impedanceThese types are subdivided according to circuit

performance requirements as to whether or not service maybe interrupted upon failure of a diode. Since all circuitscontain a certain amount of impedance, how a given circuitis classified depends on both circuit impedance and rectifierdiode ratings. In general, a circuit is classified as Type 1 ifthe circuit impedance will keep fault currents below thesingle–cycle surge current rating of the rectifier diodes(IFSM), and as Type 2 if the circuit impedance allows faultcurrents to go over the diode surge rating. Type 1 circuitsmay be protected with conventional fuses or circuit breakerschosen to open at currents below the surge current ratings ofthe rectifier diodes. Type 2 circuits, low impedances, aredesirable from the standpoint of efficiency but requirespecial fast–acting protective elements.

Current surges in rectifier circuits result from thefollowing factors:

1. Capacitor in–rush2. Direct current overload3. Direct current short (fault)4. Failure of a single rectifier diode

Capacitor in–rush is easy to observe and calculate and isdiscussed in Chapter 7; the other problems require someheroism in order to observe circuit conditions. Simulation ofthe fault may often be accomplished by using an SCR as a

crowbar; the scope may be triggered by the same signalwhich fires the SCR.

Fusing ConsiderationsBasic operation of a fuse is as follows. When a current

larger than normal is applied to a fuse, it starts to heat upsignificantly because power dissipation is proportional tothe square of current. If this current continues, the fusibleelement or link eventually reaches its melting point. As thelink melts, voltage builds up across the fusible materialwhich causes arcing. Arcing continues until enough of thelink has melted so that the applied voltage can no longerjump the gap. At this time current flow through the fusestops. This basic operation is shown in Figure 144. The solidline shows the actual fault current due to the limiting actionof the fuse and circuit impedance. The dashed line shows theavailable fault current that would flow without the fuse. Asshown, melting of the fuse starts at point A. Typically, thecurrent rises to a peak let–through current as shown at pointB and then decays through the impedance of the arcing fuseto zero at point C. The time from point B to point C is thearcing time of the fuse. The melting time and the arcing timetogether make up the total clearing time of the fuse. Clearingtime is often called blowing time.

Figure 144. Action of a Fuse in a Circuit Subjected toa Current Surge

0

Cur

rent

Peak AvailableLet–ThroughCurrent

AB

Peak Let–ThroughCurrent

Time

C

MeltingTime

ArcingTime

Clearing Time



Three basic types of fuses are available: normal–acting ormedium–acting, fast–acting, and slow–acting (oftenreferred to as “slo–blo”). The different behavior of thefast–acting and the normal–acting fuse is caused by thematerial used for the link (this is the part of the fuse thatmelts) that results in the fast–acting fuse having a smallerthermal inertia. Similarly, the “slo–blo” fuse has a largerthermal inertia than the normal–acting fuse which resultsfrom use of a low–temperature melting point alloy and a heatsink. Figure 145 shows the general blowing timerelationship for the three types at various overloadconditions. Note the large blowing time required for the“slo–blo” compared to the other two. It is because of thisdifference that only medium–acting and preferablyfast–acting fuses are used to protect rectifiers. Thefast–acting fuses are sometimes called current–limitingfuses because of their fast blow times, although all fusescould be regarded as current limiters.

Figure 145. Chart Showing the Relation of Percent ofRated Current to Blowing Time for Typical Fuses

800

700

600

500

400

300

200

100

00.001 0.01 0.1 1.0 10 100 1 k 10 k 100 k

Per

cent

of R

ated

RM

S C

urre

nt

Blowing Time (Seconds)

“Slo–Blo”

Fast Acting

MediumActing

The best type of fuse in the fast–acting category is thesilver–sand or semiconductor fuse. As the link (usuallymade of silver) melts, the arcing caused by the voltagedeveloped across the fusible material is quenched by sandcrystals placed around the silver link. The sand effectivelylengthens the arc path. The particular size of the sandcrystals is selected on the basis of the voltage and currentratings of the fuse. Fuses are available which limit faultcurrent to as low as four times normal rated current.

Fuses are sensitive to changes in current and temperaturenot voltage. Figure 146 shows the effect changes in ambienttemperature have on the current rating and blowing time. Afuse may be used at any voltage up to its maximum ratingwithout any influence on the fuse’s performance. Only afterthe link melting temperature is reached and arcing occurs inthe circuit, are voltage and available power an influence onthe fuse performance. It has been shown [5] that the clearing

time I2t (the effective energy that the fuse will let through)decreases as a fuse is used below its rated voltage.

Figure 146. Action of a Fuse in a Circuit Subjected toa Current Surge

150140

130

120

110

100

90

80

70

60

50

40

30–40 –20–60 0 20 40 60 80 100

Ambient Temperature (°C)

Per

cent

of R

atin

g or

Blo

win

g Ti

me

“Slo–Blo”Medium & Fast Acting

Effect on CarryingCapacity Rating

Effect on Blowing Time

There are two common ways to select a fuse. One way isto compare the fuse and rectifier on the basis of surgecurrentthat is compare peak let–through current and rectifiersurge current for a given fault current. Another way is to basethe analysis on thermal energy, I2t. It has been shown [6] thatessentially equivalent heating occurs in a fuse and in arectifier for a unit of I2t where the I2t of the fuse is based ona triangular surge current waveform and the I2t of therectifier is based on a sinusoid waveform. Based on thissecond approach, the following steps can be used as a guidefor fuse selection:

1. Select a fuse with a current rating which is slightlyhigher than the current flowing through therectifier under normal conditions. (Remember, thisis an ac rms current rating.)

2. Check the voltage rating on the fuse to insure thatit is equal to or greater than the maximum circuitvoltage.

3. Estimate or measure the available fault current.Since it is circuit dependent, it can be foundanalytically by dividing the source voltage by thesystem impedance with the fault placed in thesystem.

4. With this information, the fuse tables are used tofind the worst–case peak let–through current, IPLT,and the total clearing energy, I2t, for the selectedfuse. A word of caution: fuse ratings are somewhatdependent upon mounting hardware. If anonstandard mounting is used, consult the fusemanufacturer to see if there is any change in thefuse ratings.

5. Using the latter two parameters and assuming atriangular model for fuse current, find the totalclearing time by using the formula:

tc 3I2tI2PLT (9.1)



6. Obtain rectifier data required for this comparison(a plot of I2t versus pulse base width). If surgecurrent ratings, IFSM, have been given instead, I2t:can be calculated using the formula:

I2t I2FSM(t2) (9.2)

The rectifier sub cycle I2t ratings versus pulse width plotlinearly on log–log paper.

7. Compare: With time as the independent variable,and knowing the I2t for both the fuse and rectifier,it is now possible to determine if the rectifier isactually protected.

8. Put the fuse in the circuit, short the load orsimulate the fault, and see if the rectifier isprotected. Surge current should be examined on anoscilloscope.

EXAMPLEFault current = 3000 ARectifier I2t = 27,0000 A2s from 1 to 8.3 msLoad fuse rating = 150 A (TYPE KAX)For the 3000 A fault current, the total clearing I2t and peak

let–through current are found from Figures 147 and 148 tobe 9500 A2s and 2000 A. Using Equation 9.1, the clearingtime is found as follows:

tc 3I2tI2PLT (3)(9500)(20002) 7.1 ms

Thus, the fuse will blow before the rectifier at a peak faultcurrent of 2000 A. If the I2t of the rectifier had not beengiven, it could have been found using the IFSM rating.

IFSM at 1 cycle is specified at 3600 A. Using Equation 9.2,

I2t I2FSM(t2) (3600)2(8.3 ms)(103)2 54 103A2s

This value is twice the value of 27,000 given on the datasheet, thus showing that I2t decreases by a factor of twogoing from a pulse width of 8.3 ms to 1 ms, a not unusualsituation.

When circuit requirements are such that service is not tobe interrupted in case of failure of a rectifier diode, thegeneral approach is to use a number of diodes in parallel,each with its own fuse. Additional fuses or circuit breakersare used in the ac line and in series with the load forprotection against dc load faults. Fuse values should becoordinated so that a diode fuse will open in the event ofdiode failure before the line fuses, the load fuses, or circuitbreakers open. In the event of load faults, line or loadelements should open before any of the diode fuses open.Such a system is illustrated in Figure 149.

Fuses are typically rated for use in ac circuits. When usedin dc circuits, the voltage ratings are typically half of the acrating. Some manufacturers offer fuses specificallydesigned for use in dc circuits, which are much moredifficult to interrupt than ac circuits. There are subtle factorsaffecting fuse operation in dc circuits [9].

Redundant systems often need additional transientprotection because fuse blowing causes a transient in thecircuit upstream from the fuse. In the circuit of Figure 149,an MOV across all six rectifier banks is normally required.

Figure 147. Total Cleaning Ampere Squared Seconds versus Available Fault Current, Type KAX Fuse

700 k

RMS Symmetrical Current in Amperes

500 k

300 k

200 k

100 k

70 k

50 k

30 k

20 k

10 k

7000

5000

30001000 5000 10 k 20 k 50 k 100 k

800700

600

500

400

300

250

200

150

100

50

Fus

e R

MS

Am

pere

Rat

ing

Tota

l Cle

arin

g I2

t (R

MS

Val

ue)

(Am

pere

s S

quar

ed–S

econ

ds)



Figure 148. Peak Let–Through Current versus Available Fault Current, Type KAX Fuse

RMS Symmetrical Current in Amperes

Type: KAX Voltage Rating: 250 V

30 50 100 500 1000 5000 10 k 50 k 100 k

30 k

20 k

10 k

7000

5000

3000

2000

1000

700

500

300

200

100

70

50

30

800600500400300250225200150

80

50

100

Fuse RMSAmpere Rating

403015

10

5.0

2.0

60

I PLT

, Ins

tant

aneo

us P

eak

Let–

Thr

ough

Cur

rent

(A

mps

)

Figure 149. Fuse Placements in a Redundant System

CC C

BB B

CC C

BB BBB B BB B

BB B BB B BB B

A

A

A

E

E

E

E E

E



References1. IEEE Surge Protective Devices Committee,

Recommended Practice on Surge Voltages InLow–Voltage ac Power Circuits, Institute ofElectrical and Electronic Engineers.

2. Francois D. Martzloff and Thomas F. Leedy,Selecting Varistor Clamping Voltage: Lower Is NotBetter, Proceedings of the 1989 ZurichInternational EMC Symposium, pp. 137–142.

3. Bill Roehr, Hardening Power Supplies to LineVoltage Transients, PCIM, June, 1986.

4. Bill Roehr, An Effective Transient and NoiseBarrier for Switching Power Supplies, PCIM,Sept. 1986.

5. Martin Smith, Some Considerations ofCoordinating Fuses and Semiconductors, BussmanMFG. Co., Publication E–60–A–15.

6. Emil T. Schnoholzer, Fuse Protection for PowerThyristors, IEEE Transactions on IndustryApplications. Vol. lA–B, #3, May/June 1972.

7. Bob Botos and Bob Haver, A Fuse–ThyristorCoordination Primer, ON SemiconductorApplication Note AN568, ON Semiconductor,Phoenix, Arizona.

8. F. B. Golden, Take the Guesswork out of FuseSelection, The Electronic Engineer, July 1969. pp.71–75.

9. A. F. Howe, P. G. Newberry, N.P.M Nurse, DCFusing in Semiconductor Circuits, IEEETransactions on Industry Applications, Vol 1A–22,No. 3, 1986.



Chapter 10

Basic Diode Functions in Power Electronics



!

The buck and boost converters are generally regarded asthe basic building blocks for power conversion [1]. Bycombining these basic building blocks with some kind oftransformation function, many new complex and all knownconverters are derived.

The basic topologies of buck and boost converters areshown in Figures 150 and 151. In operation, the transistorswitch, often referred to as the power switch, is alternatelyturned on or off. When the power switch is on, the amountof energy stored in the inductor is determined. When thepower switch is off, some or all of the stored energy flowsto the load and the filter capacitor, CF. These four essentialelements–power switch, diode, inductor or choke, andcapacitor–play key roles in all power conversion circuits.Despite its essential role, the diode has received far lessattention in the literature than its more glamorous associate,the power switch.

Buck and boost converters are designed to operate in oneof two modes. In “continuous mode” operation, the inductoror choke current never becomes zero during the switchingcycle. In “discontinuous mode” operation, the choke currentdecays to zero, often called “drying out,” before the powerswitch turns on again. The overall characteristics of theconverter and the requirements placed upon the fouressential elements differ greatly depending upon whetheroperation is confined to the continuous or discontinuousmode.• Naturally commutated or soft switching circuits

• Forced commutated or hard switching circuitsIn naturally commutated circuits, diode turn off is

primarily by internal recombination and no appreciablereverse current flows. Basic circuit functions that arenormally naturally commutated include:• Rectification, discontinuous mode

• Catching

• Clipping

• ClampingTo maintain soft switching operation after forward current

ceases, sufficient time for stored charge to recombine mustelapse before the circuit requires the diode to be a highimpedance. Diodes must be chosen so that their “timeconstant” (lifetime, *TS) is less than 20% of the time

allocated during the pulse repetition period. Duty cyclesvary over a wide range in pulse–width–modulated (PWM)circuits so that the time for diode turn off may be below 10%of the pulse repetition period in some designs.

Forced commutation occurs in circuits where appreciableforward current is flowing when a change in circuit stateforces the diode to turn off. Usually a high reverse currentoccurs during turn–off which must be handled by othercircuit elements.

Basic circuit functions that commonly use forcedcommutation include:• Freewheeling

• Rectification, continuous modeIn hard switching circuits, the closer the diode is to the

ideal one with no stored charge, the better the circuitperforms. As will be shown later in a detailed analysis, thelow–impedance state which the diode maintains during theta portion of reverse recovery time causes high stress onother circuit elements which can be mitigated by using a fastrecovery diode.

Circuits used in power electronics generally can be placedin one of two categories as far as the demands imposed uponthe diode are concerned. They are:

In many circuits, the element that suffers the highest stressis a power transistor switch which normally is the mosthighly stressed and failure–prone component in a powerelectronics system. Consequently, any means to reducestress on the power switch is helpful to overall systemreliability and efficiency. Choosing a fast diode is onemeans, and using a transistor snubber is another. Snubbercircuits, discussed in the next chapter, usually employdiodes which also need to be selected for proper operation.

This chapter examines the basic diode functionsseparately with the objective of identifying the requirementsof the diodes. Used in conjunction with additional active andpassive components, the basic functions are embedded in anumber of widely used sub–circuits that play important rolesin power electronic systems. Some practical concerns suchas power switch drive circuit problems, parasitic inductancecaused by layout, and use of a diode snubber are discussednear the end of this chapter. The next chapter shows somecommonly used power electronic circuits to illustrate theprinciples of diode selection developed in this chapter.



Rectification, Discontinuous ModeThe discontinuous mode boost converter shown in

Figure 150 is a common example of rectification where theswitching is soft. Waveforms are shown in Figure 152 foran idealized case where resistance in the circuit is zero.However, since resistance causes power loss and heating,considerable effort is spent in power conversion circuits tominimize resistance and waveforms in practice are notsignificantly different from those shown.

When the power switch QS is turned on, current ramps upin QS and the choke stores energy in its core. During thistime, shown from t0 to t1, the circuit voltages are fixed. Thetransistor on–state level is nearly zero, the inductor has VIimpressed across it and the diode must block the outputvoltage. When the transistor turns off, the voltage across thetransistor reverses and the “flys back” according to therelationship, v = –L di/dt. When the voltage across the powerswitch starts to exceed the output voltage V0,the diodeconducts allowing the choke energy to flow into the load andthe capacitor.

The output voltage is a complex function of the switchduty cycle, the load current, and the output filter capacitorbut it must exceed the input voltage. An attempt to have V0< V1 would cause dc current to flow from V1 and the circuit

would not function. Because of the flyback action of thechoke voltage, the converter’s sometimes called a flybackconverter, but this term is more properly reserved for apopular transformer–coupled converter that can be shown tobe a cascade connection of a buck and a boost converter. Theboost circuit is also called a ringing choke or step–upconverter.

The diode requirements are not stringent in thisapplication. For low loss, the forward voltage drop anddynamic impedance during turn–on should be low. Thediode only needs to block V0. The carrier lifetime *TSshould be no more than 20% of the charging time of thecapacitor for the boundary condition where the time from t3to t4 is zero. Otherwise its conduction would extend into thetime when the switch turns on, resulting in reverse recoverylosses.

When the input voltage is first applied, the transistor is off.An inrush current flows to charge the filter capacitor, limitedonly by the characteristics of the LC network and any seriesresistance in the wiring and components. The current waveis a one–half cycle of a damped sinusoid and its peak valuecan be several times the steady state value that thecomponents normally experience. Either the componentsmust be sized to handle the inrush or means must be takento limit its magnitude.

QS

iLVD

iS

QS

Figure 150. Output Section of a Boost Converter; the Diode Performs Rectification

LOAD

+

–

VL

–+

–+

+

–

Figure 151. Output Section of a Buck Converter; the Diode Performs a Catch Function

LOAD

L–+

VD

A

+

–

+

–

VS

VO

COVI

DR

VI

iS

DFiD VO

CO

VS iL



V

VI

IO

iS

VL

iL

VD

VS

Figure 152. Idealized Waveforms for Boost Converter Operating in the Discontinuous Mode

0

0

0

0

0

id

(VO–VS)

TS

t2t1t

VO

IO

IS

VO

VO VO

TSt3

iS iP

II

VI



CatchingThe discontinuous mode buck converter is sometimes

used at low power levels. The diode performs a catchfunction rather than a rectification function. Waveforms areshown in Figure 153, idealized to the extent that resistancesin the components are neglected.

When the power switch is turned on, current ramps up inthe inductor; charging the output capacitor and deliveringcurrent to the load. During transistor turn–off, which beginsat time t1, the inductor causes the voltage at point A to go

negative. It is prevented from dropping below the referencelevel by the diode. The waveform is sometimes said to be“caught.”

Without the catch diode, the voltage across the switchcould reach destructive levels. The transistor current nowflows through the diode which permits the choke to continuesupplying current to the load. Since the diode maintainscurrent flow during pan of the cycle, it is often called a“freewheeling” diode. By maintaining current flow whenthe transistor is off, circuit efficiency is improved.

VI–VO

TS

id

iS

VL

iL

VD

VS

Figure 153. Idealized Waveforms for Buck Converter Operating in the Discontinuous Mode

0

0

0

0

0

VI

IS

t2

t1

VO

VO

IO

t

TS

iS id

VD–VO



Mitigating inductive kick is a common problem in powerelectronics. The push–pull circuit of Figure 154 suppliespower to a resistive load via a transformer. The inductanceLP represents the sum of parasitic wiring inductance plustransformer leakage inductance.

D2

Figure 154. A Push–Pull Full Bridge Circuit UsingCatch Diodes

+

A B

V

LP

RL

D1

Q1

Q2

D3

D4

Q3

Q4

Assuming very fast switching, when Q2 and Q3 turn on attime t1, V+ appears at point B and point A is pulled to ground.Current builds up at a rate determined by the circuit timeconstant. When the signal to turn off the transistors isreceived, they will not turn off at the same time because oftheir storage delay time. Suppose Q2 turns off first. It willneed to block V+ plus the inductive kick generated by LP, ifthe catch diodes are not in the circuit. A similar situationoccurs when transistors Q1 and Q2 are switched.

The inductive kick is given by Faraday’s law asVL = –LP di/dt. It is instructive to calculate the inductive kickfor the typical values in a high–frequency power electroniccircuit. Assume that V+ = 400 V. RL = 20 Ω (current = 20 Α)and LP = 0.2 µH. If the switch opens in 20 ns,

VL (0.2)(106)(20)(0.02)(1106)200 V

Raising the transistor switch blocking voltagerequirement imposes penalties in terms of cost andperformance. Consequently, it is common practice to usecatch diodes to confine the voltage across the switches tovalues between the rail voltage and ground. The diodes also

prevent the current in the inductor from changing quickly.The current is commutated from an off–going switch to adiode and decays according to the relationship, ∆t = IL/V.

The diode forward recovery characteristic is of utmostimportance in this application since it determines how farabove the rail or below ground the inductive kick can drivethe voltage. Since the diode is on only briefly, othercharacteristics are relatively unimportant except, of course,the diode must block the voltage V+. As with other softswitching circuits, when used at high frequencies the diodelifetime should be less than a fifth of the time betweenpulses. Otherwise, a reverse current will flow through thediode, which must be handled by the power switch atturn–on.

ClippingIn clipping, a portion of a wave is flattened off or limited tosome arbitrary level, irrespective of the amplitude of theoriginal signal. Peak clippers find use in power electronicsto protect semiconductors from overvoltage.

A peak clipper, also called a peak limiter, prevents thepositive (or negative) amplitude of the wave fromsignificantly exceeding a value set by the clipper. A simpleexample of such a clipper is illustrated in Figure 155. Whenthe instantaneous value of the input voltage wave liesbetween VA and VB, neither of the diodes conduct, and theinput wave is transmitted directly to the output terminalswithout change. On the other hand, when the input voltageis more positive than VA, diode DA will conduct and thusprevent the output voltage from rising appreciably aboveVA. Similarly, when the input Voltage becomes morenegative than VB, diode DB will conduct and clip thenegative peaks of the output voltage at a level approximatelyequal to VB. In circuits of this nature, the output is often saidto be “clamped” to VA or VB. However, a clamping circuitdoes not change the waveshape or limit its amplitude, asdescribed in the next section. For the diode clippers to beeffective, the series resistance RS must be considerablygreater than the forward resistance RF of the diodes, since RSand RF form a voltage divider. In addition, the turn–onimpedance should be low to minimize overshoot and thediode lifetime fast enough to follow the input waveform.



If the batteries in Figure 155(a) are replaced by largecapacitors, the circuit functions as a dynamic clipper whendriven by a repetitive ac wave. The left capacitor is chargedto the positive peak of the ac wave and the right capacitor ischarged to the negative peak. Should a transient exist on thewave in excess of the normal peak value of the wave, it willbe clipped. The action is essentially the same as whenvoltage sources are used, except the sources adjust to thepeak of the ac wave. To permit the voltage level to drop inresponse to a change in the amplitude of the wave, a bleederresistor across each capacitor is needed. The RC timeconstant is usually chosen to be about five times the periodof the input wave.

V2

V1

VB

VB

VA

VA

V2

D2D1

Figure 155. Diode Clipping Circuit and Waveformswhen Peak Clipping a Sine Wave:

(a) Circuit; (b) Waveforms

0

0t

D1 D2Conducts Conducts

(a)

(b)

t

VBVA

V1

RS

ClampingMany asymmetrical waveforms possess a dc reference

component which remains fixed–it is not a function of thewaveform. When such a waveform is passed through atransformer or a capacitor, the dc component is nottransmitted. Loss of the dc reference is often a problembecause the absolute value of the positive and negativeportion of the wave is dependent upon the duty cycle which

usually varies over a wide range in a power converter. Inorder to properly drive a power stage when the drivewaveform is coupled through a transformer, the positive andnegative peaks must remain at fixed levels. To regain theoriginal waveform it becomes necessary to reinsert a dccomponent of appropriate amplitude. This process is termeddc restoration. It is a special example of a more generalprocess known as clamping, in which a reference level isintroduced that has some desired relationship to the wave.

The simplest form of a clamping circuit consists of a diodeassociated with a resistance–capacitance network, asillustrated in Figure 156. The resistance R in these circuitsis relatively large, and the time constant RC is considerablygreater than the time of one cycle of the applied wave. Ifcircuits are used that insert a dc component of suchamplitude and polarity that the negative peaks of the originalwave are at zero level, as shown in Figure 156(a), then it issaid that the negative peaks of this wave are clamped to zero.The same wave with its positive peaks clamped to zero voltsand to +V volts is shown in parts (b) and (c), respectively.

The detailed action of the diode clamp of Figure 156(b)can be understood by considering Figure 157. If RC is solarge that it can be considered infinite, then the diode chargescapacitance C to a voltage V that just barely prevents theoutput voltage V0 from going positive; thus, V is thereinserted dc voltage. However, if RC is high but not infinite,then some of the charge on the capacitor leaks off during thetime interval t3 – t2. This causes the output wave to decaywith a time constant RC during the time interval t3 – t2;however, if RC is very much greater than the time t3 – t2, thechange ∆V0 in the amplitude of the output voltage will besmall. At t3 the voltage at the output terminals increasessuddenly in amplitude by the peak–to–peak amplitude V ofthe applied wave and makes the output voltage go ∆V0 voltspositive at time t3. This causes current to flow into thecapacitor to replace the charge that leaked off during theprevious period, as shown. The time constant associatedwith this current flow corresponds to C being chargedthrough the diode and source resistance.

In common with the diode requirements of other softcommutated circuits, diode forward recovery should be fastand the lifetime fast enough to not have any stored chargeleft in the diode when the next cycle of the input waveoccurs. The proper value for the time constant RC is acompromise between two conflicting requirements. Thelarger this time constant, the smaller will be the variation∆V0 of the clamping voltage during the cycle, and, hence,the smaller will be the positive spike at t1 and t3. On the otherhand, the larger the RC product, the more slowly is theclamping voltage able to adjust itself to reductions in dutycycle or amplitude of the wave that is to be clamped.



Figure 156. Clamping Circuits and Waveforms; (a) Negative Peaks Clamped to Zero;(b) Positive Peaks Clamped to Zero; (c) Positive Peaks Clamped to V

V

(a)

(b)

(c)

0R

C

0R

C

0R

C

+

V

V

V′

V′

Figure 157. Detailed Waveforms for the Clamping Circuit of Figure 156(b): (a) Applied Wave; (b) Output Wave–RC Infinite; (c) Output Wave–Moderate RC;

(d) Current through Diode Corresponding to (c)

V

Decay with Time Constant RC(d) Current Through Diode Corresponding to (c)

VO

t 1 t2t 3

(a) (b)

(c) (d)

V′

VO

VO



FreewheelingAn important use of diodes is to keep current flowing in

an inductor when the source of energy is pulsed off. Whenused in this manner, the diode is called a freewheeling diode.Action is similar to the catch diode used in the discontinuousmode buck converter, but the diode is carrying forwardcurrent when the power switch turns on. A commonapplication is the buck converter of Figure 151 operating inthe continuous mode. In this case, inductor LF is chosenlarge enough so that its current never goes to zero.

Waveforms for the buck converter operating in thecontinuous mode are shown in Figure 158 They are drawnto the same scale as those shown in Figure 153, which applyto the discontinuous mode. It is quite apparent thatcontinuous mode operation places much less peak currentdemand upon the switch, diode, and inductor. Although notshown, the ripple current through the filter capacitor is alsomuch less. Consequently, the current capabilities of the keypower components can be downsized from those required bythe discontinuous mode.

VD

iS

VL

iL

Figure 158. Idealized Waveforms for a Buck Converter Operating in the Continuous Mode

0

0

0

0

0

0

id

VS VS

VS

VS–VO

TS TS

t2t1

t0

VO

VO

IO

IS

There are two disadvantages of continuous modeoperation. The inductance of the choke must be much largerand the diode must experience forced commutation whenthe power switch turns on. The resulting reverse recoverycurrent adds a current spike to the turn–on waveform whichreduces circuit efficiency.

Waveforms for the boost converter operating in thecontinuous conduction mode are shown in Figure 159.Continuous mode operation offers the same reduction ofpeak currents in the components of the boost converter asoccurs in the buck converter and it introduces the sameproblem, forced commutation. Accordingly, low storedcharge is a desirable diode attribute.



VI

Figure 159. Idealized Waveforms for a Buck Converter Operating in the Continuous Mode

0

0

0

0

0

0

VS

VD

iL

VL

iS

id

VO

VO

IO

II

VI

VI

(V–VS)

tt2t1

The rectifier diode (DR) has a dual role. It is a rectifiersince it passes intermittent pulses of current to the filtercapacitor, C0. It also is a freewheeling diode since itmaintains the flow of choke current when the transistorswitch is off.

To provide high efficiency, the diode DF must meetstringent requirements. Since it supports the full load currentpossibly up to 90% of the time, it should have a low forwarddrop. When the switch turns off, a low dynamic VF isrequired for low loss and to minimize the switch voltagestress. (At this instant the freewheeling diode also acts as acatch diode; therefore, the terms “freewheeling” and “catch”are often used interchangeably.) When the switch turns on,both the switch and the diode are subjected to a high current,limited only by the circuit parasitic inductance and diodereverse recovery time. Consequently, low diode storedcharge is a very important asset, not only for high diodeefficiency, but also for high switch efficiency and low stress.

Rectification, Continuous ModeIn the basic buck and boost converters, both the power

switch and the diode participate in producing a dc outputfrom a dc input. A rectifier function as classically viewed–that is, changing an ac wave to a unidirectional wave–doesnot exist. However, when a transformer is present, the diodethat functions as a rectifier becomes obvious.

Countless numbers of converters [2] can be derived bycombining buck and/or boost topologies with transformersand chokes. One of the more popular topologies is theforward converter shown in Figure 160. It normally operatesin the continuous mode. A more detailed analysis of theforward converter is given in the next chapter; at this pointthe rectification function is the focus of the discussion.When the power switch is on, the dotted end of the secondarywiring is positive; the rectifier diode DR conducts,permitting current to be transmitted from the input source to



the choke and the load. When the power switch is off, thetransformer polarities reverse and output current iscommutated to the freewheeling diode while DR blocks.When the switch turns on again, current is commutated from

the freewheeling diode to the rectifier diode. Both changesof state occur under forced commutation conditions andtherefore efficiency is improved as the diode stored chargeapproaches the ideal of zero.

DO DF

Figure 160. Output Section of a Forward Converter

Q

L

NP CO VO

NO

NS

DR

VI

Forced Commutation AnalysisThe previous material has pointed out several power

supply circuits where a power transistor must clear diodestored charge while turning on. The equivalent circuit ofFigure 161. is useful for analyzing the commutating intervalfor any of these hard switching circuits. The essentialcommon features are that during the switching interval thetransistor must conduct the current formerly flowing in thediode, and the voltage across the transistor must drop froma relatively high off–state level to an on–state level thatapproaches zero. To show the major impact of diode stored

charge, an in–depth analysis of the switching processfollows. The analysis reveals numerous advantages of usingdiodes having a low stored charge–which is synonymouswith fast reverse recovery–in forced commutation circuits.

The current remains constant as current is switchedbetween the transistor and diode. At any instant of time, thesum of transistor current and diode current equals theinductor current, modeled as a current source. The pertinentwaveforms are shown in Figure 162. The solid lines applyfor a practical diode, while the dotted lines show behaviorfor an ideal diode having no switching losses.

iD

Figure 161. Equivalent Circuit Used for Analyzing Losses in Forced Commutated Circuits

(+)

IO

iS

VS

VD

VI



IRM(REC)

t3t′2t2t1t0

tri

–VI

VD

tatb

PD

VF

iO

iD

PS

VS

IO

Figure 162. Forced Commutation Waveforms: (a) Power Switch Voltage and Current;(b) Power Switch Dissipation; (c) Diode Voltage and Current; (d) Diode Dissipation.

Diode Forward Drop and Switch On–State Levels Are Exaggerated

V(on)

iS

0

0

0

0

t

(a)

(b)

(c)

(d)

VI

At the start of the cycle at time t0, the diode is conductingand the transistor is off. As the transistor turns on at t1,current is diverted from the diode. However, the diode is stilla low impedance and therefore the transistor must withstandthe full input voltage as its current builds up. At t2, all theinductor current is assumed by the transistor. If the diodewere ideal, it would turn off and the commutation would becomplete. The dashed lines indicate what the waveformswould be if the diode were ideal, that is, if it did not havestored charge or junction capacitance. With a real diode, thelow–impedance state is maintained during the ta interval ofdiode reverse recovery. Thus, the transistor currentovershoots because of the reverse recovery current. Duringthe diode ta time, shown on Figure 162. as the interval fromt2 to t2, the transistor is subjected to high stress. During thediode tb time, shown on Figure 162. as time interval t2 to t3,both the transistor and the diode are subjected to high stress.During the diode tb interval, diode current decays to zero andthe transistor current mirrors it, dropping to its on–state

value. Also, the transistor voltage drops to its saturationlevel while the diode voltage rises to the supply voltage.

The power dissipation waveforms for both the transistorand diode are also shown in Figure 162. The shaded area onthe transistor waveform indicates the dissipation caused bythe diode stored charge and capacitance. Note that thedissipation during ta is almost as much as the dissipationduring the switching of inductor current to the transistor inthe time interval t1 to t2. This situation is not uncommonwhen the diode reverse recovery time is approximatelyequal to the transistor rise time. Reverse recovery currentraises transistor dissipation appreciably because it occurswhen the transistor is sustaining its full off–state voltage.



By approximating the voltage and current change withstraight lines, the transistor dissipation during turn–on canbe found from the waveforms using geometry. It is given by:

PT VIIO2 tri

TS VIIO IRM(REC)

2 ta

TS

(10.1)VIIO

2 trv

TS VIIRM(REC)

4 tb

TS

The first term is the dissipation in the transistor duringcurrent rise time if the diode were ideal. The second term hastwo parts: the first part is caused by the lengthening oftransistor turn–on by the diode ta interval and the second partaccounts for the overshoot current caused by ta. The thirdterm is the dissipation during transistor voltage fall time ifthe diode were ideal. The last term is dissipation producedduring the tb portion of diode recovery. It assumes that tb =trv, which is not necessarily true; however, it is often true thatthe tb contribution to transistor dissipation is comparablysmall.

Nearly all the diode dissipation occurs during time tb. It isdifficult to quantify since the voltage during the tb intervalis also affected by the transistor and circuit inductance.Additionally, the tb interval is a function of the diodecapacitance which produces reactive power notcontributing to its power dissipation. For a slow diode,where tb is much longer than trv, the diode dissipation maybe approximated by assuming that the full reverse voltage isacross the diode during tb. In this case the transistordissipation during tb is zero, and the diode dissipation is:

(10.2)PD VIIRM(REC)

2 tb

* TS

Regardless of how power is shared during the tb interval,Equation 10.2 is an accurate expression for the sum of thetransistor and diode dissipation. When the diode is fast, tbwill be much less than trv and dissipation in the diode will bevery small since the voltage across it will not have time torise appreciably. Consequently, when fast diodes are used,the contribution of tb, to dissipation in both the transistor anddiode is small.

The first two terms in Equation 10.1 quantify the powerdissipation during the current rise time interval. The effectof the diode recovery current during the ta interval is foundby expressing the first two terms with IRM(REC) as a variableinstead of ta. From the waveforms of Figure 162, observethat the current waves have a constant slope from t1 to t2,therefore, ta/tri = IRM(REC)/IO. Substituting for ta in Equation10.1 and after some manipulation, the following expressionfor the dissipation PI, during the tri and ta intervals is derived:

(10.3)PI

VIIO2 tri

TS1 2IRM(REC)

IO

I2RM(REC)I2O

The expression outside the brackets in Equation 10.3 is thetransistor dissipation when the diode is ideal–that is,IRM(REC) is zero. The term in brackets is a multiplying factor(PR) which shows the ratio of PI with an ideal diode to PI

with a real diode during the current commutation interval.Because of the squared term, the ratio increases very rapidlywith increasing IRM(REC). Figure 163. illustrates the heavypenalty that IRM(REC) imposes upon the power transistor.When IRM(REC) = IO, PI is four times that occurring with anideal diode.

It is important to recognize that Equation 10.3 is valid forall types of diodes. It does not matter whether the source ofIRM(REC) is stored charge in a junction diode or capacitancein a Schottky diode; high IRM(REC) causes a severe increasein the transistor dissipation during turn–on.

Equation 10.3 can be stated in terms of tri to show theeffect of changing the transistor current rise time. FromFigure 162. the recovered charge (Qa) during time intervalta is found by geometry to be:

Qa ta IRM(REC)2

Figure 163. Increase in Switch Dissipation duringCurrent Commutation Caused by

Diode Recovery Current

00.0

2

4

6

8

10

0.5 1.0 1.5 2.0

IRM/IO

PR

/PI

Solving for ta and substituting into Equation 10.3, thefollowing expression is derived after some algebraicmanipulation:

(10.4)PI VIIOTri

2TS VI

QaTS2VI

TS QatriIO

The first term is a dissipation component that isproportional to transistor rise time. It is the dissipation thatoccurs when the diode is ideal: that is, Qa = 0. The secondcomponent is fixed by the diode charge while the third termis affected by both diode charge and transistor rise time. Itis evident that a point of diminishing returns is reachedwhere improvements in rise time cause negligible reductionin power dissipation. The primary reason is that as tri isreduced, IRM(REC) increases. Secondarily, as tri (diode di/dt)is reduced, Qa increases somewhat in a practical diode.

Equation 10.4 can be put into another form to access thepoint of diminishing returns by malting some simpleapproximations. For a fast pn junction diode, the charge (Qa)which appears during time interval ta is approximately equalto the stored charge QS when di/dt is rapid. Also the forward



diode current equals the transistor current which equals theload current. Therefore,

Qa# QS# IF TS# IC TS# IO TS

Substituting into Equation 10.4 and performing somealgebraic manipulations, the following expression isformed:

(10.5)PT VIIO2 tri

TS12 * TS

tri 16 * TS

tri

The term outside the bracket is by now the familiarexpression for transistor dissipation when an ideal diode isused (*TS = 0). The bracketed term shows the factor causingincreased dissipation in terms of the ratio of the diodelifetime to the transistor current rise time. This term PR isplotted in Figure 164 and offers insight for choosing anappropriate diode for use in a particular application.

Figure 164. Effect of Diode Lifetime on PowerDissipation during Current Commutation

20

16

12

8.0

4.0

00.1 2.01.00.50.2 5.0

Pow

er R

atio

tS/tri

The curve asymptotes to a little over two when *TS ismuch less than tri, which is approaching the condition whenthe diode is ideal. However, the ratio is only four when *TS≈ 0.4 tri. This choice may be more cost effective because theextra dissipation during other parts of commutation maymask the increase caused by a slower diode. Note, however,as the diode lifetime becomes larger than the transistor’s risetime, the power ratio increases rapidly.

Speeding the transistor rise time when using a slow diodemay appear to improve matters, but it is not always wise.Assume that a circuit is operating with components such that*TS/tri = 2. The power ratio is approximately 11. If the risetime is cut in half, the ideal power dissipation (the termoutside the brackets in Equation 10.5) is cut in half, but thepower ratio from Figure 164 is now 20. Clearly, little hasbeen gained. In practice, much has been lost. The fasterswitching will produce a higher peak switch current becauseIRM(REC) will be higher; consequently, the power switchdrive circuit will need to produce much higher peak currentsand will consume more power.

In most designs, the power switch rise time is chosen toprovide low loss at the frequency of operation. Lossescaused by the diode recovery process are tolerable and a costeffective design is achieved if diode lifetime (*TS) is chosento be 20% to 50% of the transistor current rise time.

Practical Drive Circuit ProblemsIn the preceding idealized analysis circuit parasitic

inductances were ignored. When switching at very fast rates,their effects cannot be ignored and may even dominate theswitching process. During the ta interval, dt/dt is determinedby the transistor’s characteristics, its drive and parasiticinductance common to the output current loop and the drivecurrent loop. Voltage induced in the common inductanceplays a significant role in switching at high speeds.

Consider the circuit of Figure 164. As current builds up inthe common inductance, the developed positive voltageeffectively reduces the drive voltage (negative feedback),placing a practical limit upon the ultimate switching speedduring the ta portion of diode recovery. At the end of time ta,switch current drops to IO. The di/dt during the tb interval isnot directly controlled by the transistor but is a function ofthe diode stored charge recovery characteristics as well asthe diode’s capacitance resonating with parasitic loopinductance. With ultrafast diodes, the recovery interval tb isshort and the transition abrupt. The resulting high di/dtcauses a negative voltage across the common inductancewhich serves to increase the on–drive voltage. This inducedvoltage generates positive feedback and at highcommutation speeds will greatly increase the diodesabruptness.

VI

Figure 165. Inductance Common to Drive and OutputCurrent Loops Slows di/dt

IO

Another source of feedback is the capacitance from outputto input of the power switch. When the voltage drops acrossthe switch, a current is coupled into the switch input circuit.The coupled currents direction is opposite to that of thedrive, which slows the voltage transition. The effect is



normally not noticeable when the switch is a bipolartransistor because the collector–base capacitance is smalland the base current has a relatively high value; the rate ofchange of voltage is determined primarily by thecomponents in the output circuit. However, the feedbackcapacitance of a MOSFET is large and, because of MillerEffect, constitutes the major portion of the FET’s inputcapacitance. Because of the positive feedback noted above,a drive scheme selected for a suitably fast initial di/dt maycause the rectifier to snap off very abruptly. If the drive isreduced to slow di/dt to an acceptable speed, the drive maynot provide a fast enough dv/dt to keep losses low during thetb interval.

Thus, diode QRR and common inductance between theinput and output current loops team up to compound theproblems of obtaining a low–loss, low–noise turn–on of thepower switch. Current and voltage snubbers, as discussed inthe next chapter, can mitigate these effects. However, usinga diode with low QRR and, if possible, a soft recoveryreduces the magnitude of the problems.

Layout ConsiderationsHigh–speed forced commutation causes high di/dts and

dv/dts in circuit wiring, which places stringent requirementson layout. A poor layout makes a high–speed rectifier looksluggish. For example, parasitic circuit inductance is oftenthe underlying cause of what appears to be poor forwardrecovery characteristics. A high duck flowing throughexcessive stray inductance produces a large induced voltage.In a catch diode application where the purpose of the diodeis to clamp voltage to a power rail, the inductance diminishesits effectiveness.

The layout contribution to parasitic inductance caused bywiring can be estimated from the length of the wiring loop.The self inductance of one of two parallel wires may becalculated from

(10.6)L (2 1n dr 0.5)l

where L = self–inductance of a cylindrical wire (nH)

d = distance between axis of wires

r = radius of wires

l = length of wires (cm)The wires must be conducting equal current in opposite

directions and d must be small compared to I for the equationto be valid. The minimum value occurs in the case of twoenameled wires that are touching, making d = 2r. Lcalculates to be about 1.9 nH/cm. If d= l00r, the calculationyields approximately 10 nH/cm or 25 nH/inch, commonlyused “rules of thumb.” As the examples show, however,lower inductance is achieved by minimizing the distancebetween wires in a loop. If a transformer is in the circuit loop,its leakage inductance will be the dominant parasitic and isnormally found by measurement.

Another aspect of the problem caused by parasitic seriesinductance is a forced decrease in the maximum allowablecommutation speed. As the transistor turns off in a hardswitching circuit, such as a continuous conduction modebuck or boost converter, current in the diode increasesbecause current in the output inductor is constant. If the di/dtand the parasitic inductance are high, the voltage across thepower switch will be abnormally high. Therefore, if thetransistor voltage is to be held in check, either its turn offmust be slowed, which causes increased turn off losses, ora larger snubber is required, as discussed in the next chapter.Both of these remedies become increasingly difficult toimplement as switching frequency is raised.

Parasitic capacitance across the diode is usually smallrelative to the rectifier’s junction capacitance, so its effectsare rarely seen. Capacitance from the diode’s case to the heatsink must be addressed because the case is usually tied to thecathode.

Output rectifiers often experience high dv/dt, whichinjects noise into the heatsink when the output filter inductorlies between the rectifiers and the dc output as shown inFigure 166(a). By placing the choke in the return loop asshown in Figure 166(b), circuit operation remainsunchanged since the choke is still in series with the parallelcombination of the load and the output capacitors. Theadvantage of this rearrangement is that the cathodes of therectifier diodes are not on a node that has rapid voltageswings and noise is not injected into the heatsink. Thedisadvantage of this arrangement is that the transformerreturn is now no longer at a dc node and radiation from thetransformer must be addressed.

VOUT

VOUT

Figure 166. Output Rectifier Configurations: (a) Conventional Arrangement for Minimizing

Transformer Radiation; (b) Alternate Arrangement for Low Noise injection

into Heatsink

(a)

(b)



The Diode SnubberAny of the forced commutation circuits usually produce

high–frequency ringing in the circuit loop that has beenswitched off. The ringing occurs because the abrupt changeof current excites the resonant tank composed on theeffective circuit inductance (LEF) and the diode junctioncapacitance (CJ). The Q of this network is high because loopresistance is purposely kept low to avoid power losses.Ringing may not appear in circuits using a diode which hassoft recovery because its impedance while in the tb phasedamps the resonant circuit. However circuits using fast pndiodes with abrupt recovery or Schottky diodes usuallyexhibit severe ringing.

In circuits using Schottky diodes, the ringing energy canbe high enough to generate a voltage higher than the diodebreakdown voltage. Operation in breakdown is undesirablebecause of the increased power dissipation generated andthe possibility of diode failure if its avalanche energycapability is exceeded. In addition, the EMI produced by theringing usually causes malfunction in nearby electroniccircuits.

To eliminate the ringing, the resonant circuit is criticallydamped by placing a series R–C network across the diode asshown in Figure 167. The capacitor serves to block dc andit is normally chosen to be about 10 times the capacitance ofthe diode (Cj). The resistor is chosen to provide criticaldamping; that is, the Q of the resonant tank is set to 0.5. Fora parallel damping resistor (RP) in the resonant tank:

(10.7)RP QLEF

When LEF is determined, the resonant frequency can befound from the usual relationship

1 LEF CJ

and RP determined from Equation 10.7. The capacitance CJis voltage dependent, so that the ringing frequency is not apure sine wave. A value of CJ picked from the diode’scapacitance curve at about 1/3 of VRRM usually providessuitable results.

Choice of the snubber capacitor (CS) is a compromisebetween snubber effectiveness and snubber loss (PR) that isdissipated in the resistor, RP. The power loss is given by

(10.8)PR 12 CS V2RRMfs

In order that the snubber capacitor is fully discharged eachcycle, the time constant (RP CS) must be less than one–tenthof the minimum off–time of the diode. If RP is made too low,it will feed significant signal around the diode. Therefore,efficiency is best when CS is as small as possible and RP aslarge as possible within the constraints given.

In a full–wave center–tap rectification scheme, onesnubber across the secondary may be used when the outputcurrent is low. At high currents, the preferred method of onesnubber across each diode is required to suppress thehigh–voltage spikes induced in the output wiring.

Figure 167. Equivalent Circuit Used to Analyze theDiode Snubber Circuit

V

+

–

T

Df

iDfVD

+

–

RS IO

CS

LEf

The previous approach of using a large capacitor in thesnubber network and choosing the resistor for criticaldamping prevents the voltage peak from exceeding thenormal off–state level. Although satisfactory forlow–voltage circuits, in higher–voltage circuits the powerloss rn the snubber resistor is unacceptable. An approachwhich allows CS to be reduced and shows the trade off inpeak diode voltage has been devised [3] [4]. The peakvoltage and resistor dissipation is obtained by analyzing thecircuit of Figure 167, which is an equivalent circuit fornearly any hard commutation circuit.

A baseline capacitance Cb and a baseline resistance Rb aredefined as

(10.9)Cb LEFIRM(REC)VO 2

(10.10)Rb VOIRM(REC)

The analysis neglects the diode junction capacitance andconsequently the oscillations occur at a frequencydetermined by LEF and DS. The oscillatory wave is dampedby RS and the peak value is determined by RS and CS. Fora given value of CS, an optimum value of RS can be foundthat minimizes peak voltage. Figure 167 shows behavior forCS = Cb, which is ordinarily a good choice. Note that a broadnull occurs when RS = Rb, which yields a peak voltage of 1.5VO.



Figure 168. Maximum Overvoltage across the Diode as a Function of Snubber Resistance for a Fixed Value ofSnubber Capacitance CS. (Courtesy Bill Robbins, University of Minnesota)

0 1 2

3

2

1

0

RSIRR(REC)

VO

CS = Cb

VRRM/VO

RS / Rb

The energy loss in the resistor at diode turn–off consistsof two components:

(10.11)WR (12)LEF I2RM(REC) 12 CSV2O

At the end of the current oscillations, energy (WC) isstored in CS, which must be dissipated in RS and the diodewhen the diode turns on. This third component is:

(10.12)WC (12) CS V2O

The total energy dissipation WT is the sum of the terms inEquations 10.11 and 10.12

(10.13)

WTWRWC (12) LEF I2RM(REC) CSV2O

(12) LEFI2RM(REC) 1 2 CSCb

Figure 169 shows the results of an extensive analysis ofthe circuit. All values are normalized, including the scales.Note that VRRM/VO decreases rather slowly from 1.5 to 1 asCS becomes larger than Cb. However, the total energydissipated increases linearly with CS; therefore, it iscommon to choose CS = Cb. When CS has been selected, theoptimum value for RS is read directly from Figure 169.



Figure 169. Snubber Energy Loss and the Maximum Overvoltage for the the Optimum Value of SnubberResistance RS and a Function of the Snubber Capacitance CS (Courtesy Bill Robbins, University of Minnesota)

0 1 2 30

3

2

1

CS / Cb

WTLEF IRR(REC)/2

VRRM/VO forRS = RS(opt)

WRLEFI2RRM/2

RS(opt)Rb

References1. Rudolph P. Severans and Gordon E. Bloom,

Modern DC to DC Switchmode Power ConverterCircuits, Van Nostrand Reinhold Company, NewYork, N.Y.,

2. Ibid, 5, 6, & 7.3. Ned Mohan, Tore M. Undeland, William P.

Robbins, Power Electronics, Converters,Applications, and Design, John Wiley and Sons,New York, N.Y., pp. 470–478.

4. William McMurray, “Optimum Snubbers forPower Semiconductors,” IEEE Transactions onIndustry Applications, Volume IA–8, No. 5,Sept/Oct 1972, pp. 593–600.



Chapter 11

Power Electronic Circuits



In the previous chapter, several important functions thatdiodes fulfill are described. An analysis shows theadvantages of using diodes with low stored charge,particularly in forced commutation circuits. In this chapterseveral circuits in common use are presented, emphasizingthe role that diodes play and offering guidance indetermining the characteristics of importance. Topicscovered include drive circuits, snubbers, and rectification inswitch–mode power supplies. By treating topics in the listedorder, the interaction between circuit functions is moreclearly perceived.

Drive Circuits for Power MOSFETsIn most cases, drive circuits for power MOSFETs are

simple. A drive stage only needs to develop the requiredsteady–state voltage between gate and source (usually 10 V)and provide sufficient peak current to the FET’s inputcapacitance to achieve the desired switching speed. Fornoise immunity, the drive circuit should be a low impedancewhen the PET is in the off–state. The drive source returnshould be directly connected to the source terminal of thePET to minimize the effects of source inductance.

In some cases, electrical isolation is needed between theMOSFET and the drive stage. One way to do this is with atransformer. When the duty cycle of the drive signal variesover a wide range, dc restoration is needed to maintainproper voltage levels between the MOSFET gate and itssource. A drive circuit with dc restoration is shown inFigure 170. In some circuits, a Zener diode may be requiredto prevent transient voltage spikes from damaging theMOSFET.

Figure 170. MOSFET Drive Circuit Using dcRestoration to Handle Large Changes in Pulse Duty

Cycle

Drive Circuits for Bipolar PowerTransistors

The design of a drive circuit for a bipolar junctiontransistor (BJT) operating in a power converter proves to bea challenging assignment. Criteria which generally applyare:

1. The on–drive (IBI) should have a fast rise time andprovide adequate drive at the leading edge toreduce turn–on losses.

2. After the initial peak, the amount of base currentshould drop to a level just sufficient to produce asatisfactory on–state (VCE(SAT)) voltage. KeepingIBI low during the major portion of on–time helpsreduce the storage time. Since the collector currentvaries over a wide range in most converters, aproportional drive scheme or Baker Clamp helpsachieve this condition.

3. A negative base drive (IB2) is mandatory in orderto keep turn–off switching losses to an acceptablevalue. The drive needs to be tailored to the needsof the particular transistor type used for the powerswitch. Most third and fourth generation BJTsperform well if the change from IBI to IB2 is rapidand IB2 is high throughout the turn–off interval.

4. When the power transistor is off, the drivecircuitry should present a low impedance to thetransistor base in order to have good noiseimmunity.

Rectifier diodes play important roles in many of thecommonly used drive schemes. It is easy to generate therequired negative base current if a bias supply having areverse polarity with respect to the emitter of the powerswitch is available. However, such a bias supply is seldomavailable, especially in a switch–mode power supply.Designers are loathe to create one because it complicates thedesign, particularly if the supply is to operate on worldwidepowerline voltages. Consequently, the circuits presented inthis chapter provide the means to generate the reverse basecurrent without an external supply.

Baker ClampThe storage time associated with the turn–off of bipolar

transistors has always been a problem for circuit designers.Allowance must be made for worst–case storage time ordisastrous events may occur. Such allowance lowersefficiency because it shortens the time available to deliverpower pulses, which in turn raises the peak current.Unfortunately, storage time varies considerably with thevalues of IC and IBI prior to turn–off and with the amplitudeand waveshape of IB2. A technique developed many yearsago by R.H. Baker is shown in Figure 171. It reduces andstabilizes storage time as operating conditions vary.

Circuit operation is as follows. When a positive pulse isapplied to an initially off transistor, forward current flowsthrough DB into the base of the transistor, turning it on. Thevoltage at the input is set at two diode drops, approximately1.5 V. As collector current builds up and collector voltagedrops, diode DF starts to conduct and keeps VCE from fallingbelow about 0.8 V. This action prevents the bipolar operatingpoint from entering the hard saturation region andtheoretically eliminates storage time since thecollector–base junction is not reverse biased. Diode DF actsas a current–regulating feedback element, setting the basecurrent to the amount required by the transistor at a



particular collector current and on–state voltage. Current atthe input which exceeds this base current (i.e., excesscurrent) is shunted into the collector circuit by diode DF.When the input pulse goes negative, reverse current is drawnfrom the base through diode DR in parallel with diode DBuntil its stored charge is depleted. Resistor R is presentmainly for noise immunity; it also establishes a small reverseoff–state voltage at the base if the input level remainsnegative.

Figure 171. Baker Clamp Configuration

R

II

VI DR

DB

DF

The Baker Clamp provides the expected results forlow–voltage bipolar transistors – that is, storage timebecomes negligible and fall time is not affected. However,high voltage power transistors exhibit a quasi–saturationregion caused by stored charge in their wide, high resistivitycollector region. When operated in quasi–saturation, somestorage time still occurs. It is possible to move operation outof the quasi–saturation region by stacking additional diodes

in series with DB, but the on–state loss becomesunacceptably high.

It might seem that the Baker Clamp is not particularlyeffective with high–voltage transistors; however, operationin hard saturation causes anomalous fall time behavior,while fall time behavior is more theoretical if operationextends only into the quasi–saturation region. To show theeffectiveness of a Baker Clamp [1] the test circuit ofFigure 172(a) was used. Transistors Q1 and Q2 arealternately turned on to provide IB1 and IB2 to the powerswitch. The load inductor, diode, and capacitor simulate aflyback converter load. A sketch of the waveforms observedare shown in Figure 172(b). When II is first applied, it isdelivered solely to the transistor base. Current builds upslowly in the inductor but its high impedance allowscollector voltage to drop quickly. Diode DF conducts,shunting the excess base current into the collector of thepower switch. As collector current (ICT) rises, base current(IB1) drops and maintains the value IC/hFE as collectorcurrent ramps toward its peak, which is established by thepulse width of II.

The most interesting results occur with a fixed base driveand a variable collector current, a common situation in aswitching power supply. The effect upon storage time isshown in Figure 173. Note that use of the Baker Clamp hasachieved a remarkable reduction in storage time at lowcollector currents and its value is somewhat independent ofcollector current. Improvement in fall time is even morespectacular as shown in Figure 174. The trade–off made forthe improved switching performance is an increasedon–state voltage. It is typically 0.3 V in hard saturation and0.9 V with the Baker clamp.

ROFF

Figure 172. Baker Clamp Circuit for Evaluating High–Voltage Transistors:(a) Test Circuit; (b) Waveforms

+7.5

Q1

Q2

–6.5 V

20 V

OUTPUTCURRENT

ICTMJE16004 250 V

INPUTCURRENT

I I

(a) (b)

DF

DB

DR

IC

VOFF

S1

IDF

IB1

II

ICT

IT



Figure 173. Storage Time with Fixed Drive ina Baker Clamp Circuit

0

2.0

4.0

6.0MJE16004Iin = 800 mAVCEM = 250 VROFF = 2 ΩVOFF = 6.5 VTC = 25°CDF: IN4937

Baker Clamp

Hard Saturation

t Si,

Cur

rent

Sto

rage

Tim

e (µ

sec)

40

200

400

600MJE16004IS = 800 mAVCEM = 250 VROFF = 2 ΩVOFF = 6.5 VTC = 25°CDF: IN4937

Baker Clamp

Hard Saturation

0.4 1 2 3 4

Figure 174. Fall Time with Fixed Drive ina Baker Clamp Circuit

t fi, C

urre

nt F

all T

ime

(nse

c)

Not all transistors will exhibit the behavior illustrated inFigures 173 and 174, and data of this nature rarely appearson manufacturer’s data sheets. Consequently, it is advisableto test transistors in a circuit similar to Figure 172 todetermine if the improvement in switching losses more thanoffsets the additional on–state losses associated with theBaker Clamp.

Selection of the diodes deserves critical attention. Thecollector feedback diode DF needs to be able to block thevoltage applied to the collector of the transistor. Its storedcharge should be low enough that the diode recovers duringthe storage time of the transistor. Otherwise, it will play arole in the turn–off process, affecting both storage and falltime. Finding the right diode may not be easy since storedcharge is not often specified and conditions for reverserecovery specifications do not approximate those in a BakerClamp circuit. As a rough rule of thumb, the specifiedreverse recovery time should be under a quarter of thespecified storage time of the transistor. Testing a number ofsamples with a current probe in series with diode DF willnormally be necessary to be sure that an adequate marginexists between diode recovery time and transistor storagetime. A slow forward recovery time is actually beneficial.The delay allows the spike of current from II to persistlonger, thus reducing turn–on loss. Fortunately, slowforward recovery is a characteristic of high–voltage diodes,regardless of their stored–charge behavior.

On the other hand, fast forward recovery is important fordiode DB, unless a peaking capacitor is placed in parallelwith it. A low–voltage diode provides fast forward recovery.A large area diode also may provide sufficient peakingcapacitance. Slow reverse recovery is an advantage. Thestored charge will hold the anode positive during theturn–off phase, thereby increasing the current availablefrom the negative voltage source. Often diode DR is omitted;the circuit then depends upon the stored charge in diode DBto exceed the stored charge in the transistor, therebyproviding a current path for IB2 until the transistor turns off.Diode DR also has non–critical requirements. It is used

simply to apply reverse current (IB2) when VI is derivedfrom a scheme which drives VI negative.

Fixed Drive CircuitThe circuit of Figure 175 is commonly used with circuits

such as the half bridge in which the power switch cannot beconnected to “ground” [2]. It generates a negative pulsewithout the need for a separate supply voltage. Furthermore,the rise time of the reverse current is not limited bytransformer leakage inductance.

Figure 175. Popular Fixed Base Drive Circuit Usingan Isolation Transformer

D C

RB2

RB1VB

QD

QP

The circuit operates as follows. When a positive pulse isapplied, a high peak forward current flows through thecapacitor and diode into the base of QP, turning it on. As Cbecomes charged, IB1 drops to the value determined byresistor RBI. IB1 is given by:

IB1 (VS VBE)RB1 (11.1)

and the voltage on C is:

VC VS VBE VD (11.2)

where VS = amplitude of transformer secondary pulse

VBE = base–emitter voltage of transistor QP

VD= forward voltage drop of diode D.When the pulse voltage drops to zero, the voltage on

capacitor C forward biases the driver transistor, QD. As QDturns on, the negative voltage on C causes a high reversecurrent (IB2) to flow out of the base of QP.



The circuit can generate a fast–rising, high–current IB2pulse. It is important that parasitic wiring inductance be keptto a minimum. The drive transistor QD should be ahigh–speed switching type and capacitor C must have a lowESL and ESR. Diode D does not affect the turn–off drive, butit should have a fast forward recovery time and low VFRMin order to apply a high IB1 to the transistor during turn–on.Care must be taken to ensure that C is fully charged duringthe minimum pulse width, which the transistor is expectedto handle.

Proportional Drive CircuitAnother method of minimizing the increase of storage

time with a decrease of collector current involves arrangingthe base drive current to be proportional to the collectorcurrent. Not all bipolar transistors respond favorably withproportional drive, but most do. In addition, high–voltagetransistors usually exhibit an improvement in fall time,which lowers switching losses. The improvement inturn–off time is similar to that achieved with the BakerClamp, but the transistor remains in the “hard” saturationregion of operation when in the on–state, which achieveslowest on–state losses.

The circuit of Figure 176 has been used [3] to drive bipolartransistors in a power converter operating up to 1 kW ofoutput power. The scheme is often called a regenerativedrive circuit because the secondary windings of the drivetransformer are in phase, allowing the power transistor tosupply its drive signal. During steady–state conditions whenthe power transistor QP is on, the driver transistor QD is off,causing the primary winding to be inactive. The base currentis derived from the collector current and its magnitude isdetermined by the turns ratio of the secondary windings.Consequently, no drive circuit power is required to hold thepower transistor on, which results in an efficient drivescheme. The Baker Clamp diode DF may or may not be usedto improve overall losses, depending upon circumstances.

The circuit operates as follow: Assume the power switchQP is on and QD is off.

Figure 176. Efficient Proportional Base Drive CircuitWhich Easily Adapts to Using a Baker Clamp

+24 V

CBRB

QPDB1 DB2

DF

QD

DPRP

DC

The primary winding has a large voltage drop across itcaused by the current flow in the secondary base drivewinding which produces a drop of about 2.5 V across theseries diodes and the base–emitter junction of QP. Inaddition, CB is charged to about 1.6 V. The phasing of thewindings is such that the dotted ends are positive. When QDis turned on into hard saturation, the dotted end of theprimary is pulled close to ground. The other end of theprimary winding would go negative but cannot because ofthe presence of clamp diode DP which turns on and clampsthe winding to ground. The net effect is one of a short beingplaced across the primary which stops the regenerativeaction in the secondary. The secondary windings now appearas a short. Therefore, a reverse base current is supplied to thepower switch as CI discharges and the stored charge indiodes DBI and DB2 exits. During turn–off of QP, primarycurrent flow is composed of the reflected currents in thesecondary windings which flow through DP and QD. Thebase drive to QD must be sufficient to keep it in hardsaturation while handling the relatively high reflectedsecondary currents.

After QP is off, the drive transformer primary currentdecays to zero and diode DP turns off. Current flows throughRP and the primary winding which places a reverse bias onQP, holding it off. Since the only current flow is in theprimary, energy is stored in the core. When the systemrequires QP to turn on, QD is turned off and the stored energyin the core develops a flyback voltage of a polarity to turn onthe power switch, QP. The resulting build–up of collectorcurrent causes a proportional regenerative build–up ofbase–drive current (IB1). which maintains the power switchin the on–state after the flyback energy has dissipated.

Switching performance is highly dependent upon thechoice of components in the drive circuit as well as thechoice of the power switch. The transformer leakageinductance must be small to permit a rapid change of basedrive from IBI to 1B2. The windings are usually trifilarwound on a toroidal core. Naturally, leads and wiring tracesmust be short to minimize inductance. The return lead to thebase winding should be connected directly to the emitter ofthe power sWitch to prevent the relatively large voltagedeveloped across the emitter lead inductance from beingintroduced into the base circuit. Diode DP should have a lowturn–on impedance since its reflected impedance is part ofthe base circuit during the turn–off interval of the powerswitch. A low–voltage pn or Schottky diode serves very wellin this application.

Diodes DB1 and DB2 are basically level shifters so theirswitching characteristics are unimportant. Their function,however, is very important because they established thevoltage across the drive transformer windings when thepower switch is on. A resistor cannot take their placebecause its drop would vary with changes in load current.



The circuit easily adapts to Baker Clamp operation bymerely adding diode DF. The improvement in switchingperformance is not as dramatic as achieved in fixed basedrive circuits; with many transistors, lower overall losses areachieved by letting the transistor saturate. The higher theswitching frequency, the more likely is the Baker Clamp tobe an effective scheme to lower losses. If the Baker Clampis used, diode DF should be selected for low stored charge,as previously discussed.

Transistor Snubber CircuitsNetworks are frequently added to power electronic

circuits to control the load line and thereby reduce the energywhich a power switch must handle during switching. Thesenetworks are called snubbers, and diodes usually play a keyrole. Snubbers are commonly classified into three typesbased upon their function:

1. Turn–on snubbers2. Turn–off snubbers3. Overvoltage snubbers

Additionally, these functions can be accomplished byusing either dissipative or nondissipative techniques forhandling snubber energy. In a dissipative scheme, energythat would cause transistor dissipation is, in effect,transferred from the power switch to a resistor. In anondissipative or “lossless scheme,” resistors are avoidedand transistor switching losses are transferred to the sourceor the load using some combination of diodes, capacitorsinductors or transformers.

Power Circuit Load LinesThe usual load line of a power circuit is inductive.

Furthermore, a diode typically is added to catch inductivespikes and it may also perform the freewheeling functionwhen operation is in the continuous conduction mode. To thetransistor, a load of this nature is referred to as a clampedinductive load.

The buck converter previously discussed in Chapter 10shows the need for snubbers. An equivalent circuit is shown

in Figure 177, where the filter inductor is replaced by acurrent source (continuous mode operation) and strayinductances are shown as separate circuit elements.Transistor switch waveforms for a complete switching cyclecommencing with the transistor in the on–state are shown inFigure 178.

At time t0, the transistor voltage begins to rise but itscurrent remains essentially constant. At t1, the freewheelingdiode starts conducting, which diverts current away from thetransistor. The voltage across the transistor overshoots VIbecause of diode forward recovery time and circuitinductance. In a high–voltage circuit, transistor turn–on isfaster than diode forward recovery time so that ic reacheszero at t2 and the transistor collector–emitter voltage settlesto its steady state value at t3. The turn–off switching path onthe V–I plane is seen from Figure 179 to cause the transistorto experience high instantaneous power dissipation.Depending upon the switching speed and frequency, theaverage power dissipation could also be significant. Forbipolar transistors, the high power dissipation may beoutside of the transistor’s safe operating area, posing dangerof failure. The bipolar transistor is particularly sensitive tovoltage spikes during turn–off; thus the stray inductivespikes and the forward recovery overshoot voltage of thefreewheeling diode (VOS) critical to transistor survival.

LE

Figure 177. Equivalent Circuit of a Buck ConverterOperating in the Continuous Conduction Mode

–+

DF

LD

VI

iS

LCVS

IO

Figure 178. Power Switch Waveforms for the Buck Converter

I O

VOSV ST

IO

VI

iS

VS

t0

t2

t1

t3

t4

t5

t6

0



The transistor’s turn–on period commences at time t4. Ascurrent rises, the stray inductances generate a voltage step,VST. As described previously in some detail, the reverserecovery current of the diode causes the switch current is toexceed IO. At t5 the diode impedance begins to increasewhich allows the collector voltage to drop towards theon–state level, which it reaches at time t6. The turn–on pathshown on Figure 179 is also seen to produce highinstantaneous dissipation. The situation is not as stressful tothe power switch because semiconductors are moreforgiving of current peaks than voltage peaks.

Snubbers reduce these power peaks by pushing theswitching paths toward the origin. If the paths shown onFigure 179 protrude beyond the safe operating area of thepower switch, a snubber is essential in order to insurereliable operation. Even if not required to protect the powerswitch, snubbers are often used to reduce switching losses inorder to allow the power switch to run cooler or lessen heatsink requirements. Snubbers, when carefully chosen, resultin a higher power efficiency for the system than if they areomitted, even if the dissipative type is used [4].

Figure 179. Switching Load Loci for the Buck Converter

i

Turn–off

Turn–on

idealized inductiveturn–off path

path

rate

VI

t4t3 t2

t1

t5

t6

t0

Turn–On SnubbersTurn–on snubbers are used more frequently with

thyristors than transistors because thyristors have a finiteturn–on di/dt limitation, whereas transistors have largeturn–on (forward biased) safe operating areas. However, theturn–on snubber lowers stress and peak power dissipation inthe power switch. It is particularly effective withhigh–voltage bipolar transistors and thyristors which exhibita significant dynamic saturation voltage. The turn–onsnubber makes use of an inductor to slow current rise timeand allow a rapid drop in voltage across the switch to occurprior to current build–up. Figure 180 shows how a turn–onsnubber is implemented in the buck converter. The keyrequirement is that the inductor is placed in the current pathbetween the power switch and the freewheeling diode.

Two modes of operation are possible. The first mode

occurs with a small inductance such thatVS Ldisdt VI. The second mode occurs whenV VI.

In the first mode, dis/dt is determined by thecharacteristics of the power switch and its drive circuit. Thevoltage step, VST on Figure 178, becomes progressivelylarger as LS is increased, but the current waveforms of thetransistor and freewheeling diode are virtually unchanged.The turn–on path from t4 to t5 is moved toward the left onFigure 179 as LS increases.

In the second mode, di/dt is controlled by the inductor LS.The current switching time is relatively slow but switchdissipation is nearly zero because the voltage drops almostimmediately to the off–state level as current starts to rise.With adequate drive to the switch, dynamic saturation is notnoticeable.



Figure 180. Buck Converter with Dissipative Turn–on Snubber

VI

LSRS

DS

DF

IO

The current overshoot caused by the reverse recovery ofthe freewheeling diode can be reduced to any value desiredby the choice of LS. The turn–on path from t4 to t5 is avertical line originating close to the origin. When thetransistor is turned off, the energy stored in LS during theswitch on–state must be controlled. The diode DS is used asa catch diode to clamp the inductive spike generated atswitch turn–off. Unfortunately, the diode cannot be usedwithout a series (RS). The reason is that the inductor currentmust decay nearly to zero during the switch off–state inorder for the snubber to be effective. Accordingly, thesnubber circuit values are bound by the followinginequality:

t(off state)$ 3 LSRS (11.3)

The resistance of the diode alone is ordinarily too low toallow proper circuit operation at the high frequencies usedin power electronic circuits. Unfortunately, an overshootvoltage equal to RSIO is developed across the resistor RS.Thus, the design of the turn–on snubber involves a numberof compromises. The snubber’s maximum time constant(LS/RS) is limited by the frequency of operation. Making LSlarger results in lower turn–on losses, but since RS must alsobecome larger, the overshoot will increase proportionally.

The inductor used for LS is not physically large becauseit is allowed to saturate at t5 since its function is required onlyduring the interval from t4 to t5. The diode DS performs acatch function; therefore its forward recovery overshootvoltage is important because it adds to the overshoot voltagedeveloped across the resistor RS.

A nondissipative or “lossless” turn–on snubber isoccasionally used. One approach, based on the work ofMeares [5], is shown in Figure 181. The snubber inductanceis the transformer’s magnetizing inductance which performsthe same functions as the discrete inductor in Figure 180 andis subject to the same design constraints. When the currentreverses through the freewheeling diode, the current iscoupled through the transformer whose secondary deliversthe reverse recovery current to the input through the snubberdiode DS. In this manner, the current demand from the powersource is reduced.

The scheme is not truly “lossless” because losses in thetransformer and diode DS cannot be avoided. The forwardrecovery of DS is more important than its forward dropbecause it only conducts current for a short period of time.Its specification requirements are similar to that of a catchdiode.

IO

Figure 181. Buck Converter with “Lossless” Turn–on Snubber

DS DF

QS

CF

V1



Turn–Off SnubbersThe turn–off snubber is designed to slow the rise in

voltage across the power switch while allowing the currentto drop rapidly. The most common approach uses an R–C–Dnetwork as shown in Figure 182. When the power switch ison, its current equals IO and the voltage drop across theswitch is nearly zero. Since IO is constant during turn–off,as collector current drops, a current IO–iC flows into thecapacitor through the snubber diode DS. The capacitor ischosen to achieve the desired rate of rise of the transistorcollector–emitter voltage. The resistor is used to charge thecapacitor when the switch is on, and therefore it must bebound by the following inequality:

t(on state)$ 3 RSCS (11.4)

To arrive at a suitable design, the peak current to dischargethe capacitor must be considered. It may be approximatedsimply as VCE(off)/RS. Thus, for a given frequency ofoperation the RSCS product has an upper bound. As CS ismade larger to reduce the turn–off energy consumed in thepower switch, RS must be smaller which increases theturn–on energy. For a given set of conditions, an optimumvalue of CS exists which minimizes the total losses in thepower switch and snubber over a complete cycle [4]. Usingthe optimum value makes the load line appear resistive.

The snubber diode’s forward recovery characteristic is ofmajor interest since the diode appears as a time variableresistance (rF) in series with the capacitor during powerswitch turn–off. Therefore, in addition to the capacitorvoltage, a voltage of (IO–iC) rF appears across the transistor,increasing its dissipation.

Turn–off snubbers can also be designed to be “lossless.”They make use of a resonant circuit; the complete analysis[6] is complex and beyond the scope of this treatment.However, a qualitative description of a popularimplementation shows the importance of diodecharacteristics, which is the focus of this chapter. A practicalcircuit arrangement is shown in Figure 183(a) where thelossless snubber is applied to a flyback converter. The

snubber could be applied as well to other transformercoupled topologies.

The snubber components are DS1, DS2, LS, and CS. Thetransformer leakage inductance reflected to the primary isshown as an external component, LL. The turns ratio of thetransformer is n:1 and its magnetizing inductance is verylarge compared to its leakage inductance, so that themagnetizing inductance does not affect snubber operation.

A qualitative view of basic circuit operation is easilyobtained by assuming that the power switch QS is initiallyin the on–state. The capacitor is charged to some positivevoltage between zero and VI. When the drive signal changesto initiate turn–off, after a short delay switch current startsto fall. The inductive load keeps the load current constantcausing current to switch from QS into CS and DS1 since thecurrent in LS cannot change rapidly. Depending upon theinitial charge on CS, the switch voltage may exhibit an initialjump until diode DS1 becomes forward biased. Once DS1 isconducting, the rate of rise of voltage across the switch iscontrolled by CS in a manner similar to that of the moreconventional R–C–D snubber. With a properly chosencapacitor having a sufficient initial charge, the switchvoltage rises only to a chosen small portion of the off–statevoltage before the switch current reaches zero. The forwardrecovery characteristics of the diode are important since itstransient voltage is reflected to the switch voltagewaveform.

When QS is turned on, it completes the series resonantcircuit composed of QS, CS, DS2, and LS. The charge on CSand its voltage polarity is such that current flows through thenetwork, and the voltage at point A drops to -VCP, thevoltage across the capacitor prior to the turn–on of QS. Ascurrent rises in the resonant loop, the voltage at point A risestoward +VCP but DS1 conducts when VA exceeds VI. At thattime, the energy stored in LS flows into the input source.Thus, the energy stored in the capacitor during switchturn–off is transferred to the inductance and then to the inputsource when the power switch again turns on.

IO

Figure 182. Buck Converter with Dissipative Turn–off Snubber

DF

LL

RS

CS

DS

QS

CFV1



Figure 183. Application of a “Lossless” Snubber of the Resonant Type: (a) circuit;(b) current in DS2

L L

A –+

t 1

t 2

E = 1/2 LI 2RRM

(a)

(b)

DS1

DS2

LSCS

QS

CFV1

The mode of operation described is based upon one of theearlier papers on the subject [7]. A later paper [6] explainsthat four different modes of operation exist depending uponthe choice of snubber constants, the transformer design andfrequency of operation. While differing in details, all modesallow proper operation of a power converter if suitablydesigned.

Resonant snubbers are difficult to implement inconverters operating under current mode control because asignificant amplitude of half–sine wave current at thesnubber resonant frequency appears on the power switchwaveform during turn–on. The problem must be addressedor converter operation will be erratic.

In descriptions of circuit operation, diode requirementsare seldom explained in detail. For the circuit beingconsidered, abrupt current changes only occur when thepower switch changes state or when the diode turns on.Consequently, a fast diode turn–on characteristic reduceslosses. Diode reverse recovery is usually important in DS2but not DS1. The current waveform of DS2 is shown inFigure 183(b). The turnoff di/dt is controlled by LS.Normally the di/dt is high enough that significant reverserecovery stress occurs. The diode lifetime (*TS) should beat least three times less than the resonant period of thesnubber to avoid significant diode reverse recovery losses.

Overvoltage SnubbersIn most power electronic circuits, even when the load is

clamped, parasitic inductances cause overvoltage spikes.These parasitics are introduced because of transformerleakage inductance, capacitor effective series inductance(ESL), and wiring inductance. A turn–off snubber does notalways eliminate the overvoltage spike because of theparasitic inductances in the snubber circuit. Furthermore,many circuits have no need of a turn–off snubber because ofthe load characteristics in relation to the power switch SOA

and because operation is at a frequency where the switchingpower loss is not important. In these cases, an overvoltagesnubber may prove useful.

Overvoltage spikes can be clipped with the circuit ofFigure 184. In operation, while the power switch is off, thevoltage on the overvoltage capacitor CV is pulled up to thesupply voltage, VI, by diode DV. When the switch turns off,the diode DV is activated whenever the energy in the smallleakage and stray inductance, lumped as LL, causes theswitch voltage to exceed VI. The switch voltage is clippedto VI plus the diode forward recovery voltage plus thevoltage increase on the capacitor as it absorbs the inductiveenergy. The time constant RVCV is chosen small enough toallow the capacitor voltage to decay back to the normaloff–state level before the next turn–off cycle of the powerswitch.

Figure 184. An Overvoltage Snubber

QS

DV

IO

RV

CFV1

CV

LL

With some loads, the switch voltage during the off–statewill exceed VI under normal operation. For instance, aforward converter is typically designed to allow an off–statevoltage of 2VI. The overvoltage snubber will work in manyof these situations because after a few cycles of circuitoperation, the capacitor CV will be charged to the normal



off–state voltage. Any short spikes which exceed this levelare clipped.

While clipping, the energy from the net circuit inductanceis delivered to the capacitor (CV). The voltage increaseacross the switch (∆V) is found by equating energy to obtain:

V I0 LLCV

To calculate the switch voltage, the forward recoveryvoltage of diode DV is added to ∆V from the equation. Tominimize the spike, it is very important to keep inductancelow in the loop consisting of QS, CV, and DV. Use of ahigh–quality capacitor having a low ESL is beneficial.

An alternate method of clipping spikes is to use a transientvoltage–suppression type of Zener diode. (The MOV,discussed in Chapter 9, has too wide a voltage tolerance andtoo high a dynamic impedance to function well in powerelectronic circuits.) However, the Zener may dissipate moreenergy than the resistor because it must operate at a voltagelevel greater than VI. Using the overvoltage snubber, theenergy is dissipated in RV. It only needs to handle the changein voltage as given by the above equation.

Snubber Diode RequirementsFrom the descriptions of snubber diode requirements

presented in the circuit examples, it is clear that the diode’sforward recovery behavior is of most importance in snubberoperation. Specifically, a low dynamic resistance is requiredat turn–on. Unfortunately, forward recovery is not a requiredspecification on JEDEC registered devices and it is rarelyspecified on manufacturer’s data sheets.

As explained in Chapter 1, the diode dynamic resistancerF at turn–on is determined by the resistivity of the materialsin the diode structure and its area. The breakdown voltage isroughly proportional to resistivity. Therefore, the turn–onperformance of diodes improves as voltage breakdowndecreases. Little improvement is seen as breakdown dropsbelow 100 V, however, because other sources of bulk dioderesistance begin to dominate.

Diode selection for low dynamic turn–on resistance on thebasis of voltage break–down is not straightforward. Thespecified voltage rating is not a reliable guide to the actualbreakdown voltage of a rectifier diode because of along–standing industry practice of sourcing both high andlow–voltage devices from the same product family.

The exception is the Schottky diode, which has alow–voltage rating because of the difficulty in makinghigh–voltage parts. Consequently, the actual breakdownvoltage of a Schottky is only slightly in excess of ratedvoltage. Using Schottkys for applications requiring voltageratings below 100 V yields best performance. For highervoltage applications, the choice is less obvious. Some

ultrafast diode families have limited voltage capabilitywhich might provide low dynamic impedance. To be safe,the manufacturer should be consulted. Other sources for lowdynamic impedance diodes having breakdown voltages upto 200 V include zener or transient voltage suppressordiodes. These diodes have well controlled voltagebreakdown levels but are not processed for fast reverserecovery and therefore cannot operate at as high a frequencyas an ultrafast device. From 400 to 1000 V, tests [8] haveshown that a MEGAHERTZ rectifier provides improvedperformance.

Power Conversion CircuitsThe output rectification section of a switch mode power

supply (SMPS) commonly uses a full–wave single–phasecircuit (as described in Chapter 5) only when the input is analternating wave – that is, a wave having both positive andnegative half cycles of equal amplitude and duration. Thesewaves are produced by various kinds of push–pull powerconverter arrangements. However, a number of populartopologies are single–ended; therefore, the rectifier circuitis fed with unidirectional power pulses. In these cases, ahalf–wave rectifier is satisfactory, and means are employedto reset the transformer core to prevent saturation.

The major use of SMPSs is to power digital equipmentwhose logic circuits commonly operate from a 5 V bus.Linear circuits and disk drives usually require othervoltages, with 12, 15, 24, and 28 V being in common use.SMPSs are cost effective at power levels as low as 25 W andare also used to provide power up to several thousand watts.Obtaining efficient high–frequency rectification at highpower and low voltage is a design challenge. For example,the rectifiers in a 5 V, 1 kW supply must handle 200 A, whichdictates use of low forward drop Schottky diodes.Additionally the equivalent series resistance (ESR) ofcapacitors usually determines ripple which forces use ofcapacitors of much larger value than indicated by the designcurves in Chapter 7. Attention must also be given to bussingand connections in order to minimize losses.

In this section, rectifier circuits commonly used withpopular topologies are discussed with the purpose ofunderstanding rectifier diode requirements and penaltiesimposed by using diodes having various types of nonidealbehavior. In addition, other information helpful in the designof high–frequency rectifier circuits is offered. Thistreatment assumes the reader is familiar with operation ofthe various topologies commonly used in switch–modepower supplies and therefore descriptions and equations arepresented without qualification. Necessary background isprovided by the books listed in the bibliography.



The following material shows how rectifier diodes arematched to the requirements of some popular convertertopologies used in switching power supplies. The treatmentis not exhaustive to keep it within the scope and spaceallocated within this book. However, the issues involved indiode selection are felt to be sufficiently discussed so that theprinciples used can be applied to other topologies in additionto the ones shown.

Flyback ConverterThe output section for the flyback converter in Figure 185

shows the power switch QS, snubber network (RS, CS, andDS), the output rectifier diode DR, and filter capacitor DF.The circuit can be operated in either the continuous ordiscontinuous mode, defined with reference to the current inthe transformer primary, which also doubles as an energystorage inductor.

The transformer winding polarity is such that no diodecurrent flows when the transistor switches on. During thistime energy is stored in the core. When the transistorswitches off, the stored inductor energy causes the top of thesecondary to develop a positive voltage which turns on thediode to charge the capacitor. During diode conduction, thetransformer secondary appears as an inductor as shown inChapter 10 for the boost circuit. Its stored energy keepscurrent flowing until the required amount of inductiveenergy is transferred to the capacitor. The control loop in thepower supply adjusts the duty cycle of the power switch,such that the stored inductive energy matches that requiredby the load, thus keeping the average voltage on capacitorCO constant.

Pertinent waveforms for each mode of operation areshown in Figure 186. The waveform set in part b is shown

for the boundary condition; any further increase oftransformer current will move operation into the continuousmode. Under idealized conditions, the peak diode current isgiven by:

IFM2I0

1 D(MAX) IO(MIN) (11.5)

where: IO = the dc output current

D(MAX) = the maximum transistor duty factor.

IO(MIN) = the minimum load current.For a typical design in either mode, the boundary

condition is the worst case. If IO(MIN) = 0 and the maximumswitch duty factor is 0.5 (a typical condition), IFM = 4 IO. Alow diode forward voltage is required for high efficiency.

As the transistor turns off, two steps of currentcommutation take place. First the collector current iscommutated to the snubber capacitor CS via snubber diodeDS. As the primary voltage continues to rise, it reaches apoint where the rectifier diode DR starts to conduct andcurrent is commutated to DR. During this secondcommutation interval, fast reverse recovery of DS and lowforward recovery of DR are important to obtain efficientrectification. These effects not only cause losses, but theyalso produce a negative spike in the output voltage whichincreases ripple.

For the discontinuous mode, the decay of diode storedcharge must be faster than the decay of current in theinductor. Selecting a diode whose *TS is under 20% of thetime from t1 to t2 usually yields satisfactory results. Shouldany charge be left in the diode when the transistor turns on,the circuit functions but the power switch experiences areverse recovery current spike which lowers circuitefficiency.

VCE

Figure 185. Output Section of a Flyback Converter Having a Transistor Snubber

Load

+

–

+

–

+

–

n:1

+

iDR

VOCO

DR

V2

IO

VF

iC

QS

CS

DSRS

VI



V1/nV1/nV2

VCE

Figure 186. Flyback Converter Waveforms: (a) Continuous Mode; (b) Discontinuous Mode (Boundary Case)

TS TS

t 0 t 1 t 2 t 0 t 1 t 2

I O

I O

(a) (b)

iL

iL =

niC + iDR

iLmin

iLmax

iL

DTS DTS

V1 + n (V0 + VF) V1 + n (V0 + VF)

V0 + VF V0 + VF

iDR

niC

In the continuous mode, significant diode current iscommutated to the transistor when it turns on. The problemscaused by hard switching – transistor turn–on loss andringing – are reduced by using a fast diode. Nevertheless, adiode snubber is usually required (not shown on Figure 185).

The reverse voltage is the sum of the secondary voltageand the output voltage, plus any circuit ringing. Thetransformer is normally designed to produce the minimumrequired secondary voltage (VFM + VO) with a duty cycle of0.5. At this point, the diode peak inverse voltage will only

be a little over 2 VO (transformer turns ratios never come outexactly as calculated and voltage drops must be considered).The worst case occurs when the converter operates at a highline condition. A 1.5:1 input voltage range is common; forthis case, the minimum PIV will be three times the outputvoltage. Diodes selected for prototype work should havehigh voltage ratings, at least 1.5 times that predicted until theexact operating voltage conditions and parasitic transientvoltages are determined in laboratory testing.



Forward ConverterThe forward converter normally operates in the

continuous mode and the diodes are subjected to forcedcommutation. A circuit diagram of the forward converterand associated waveforms are shown in Figures 187 and188. Although a transistor snubber circuit is usually added,it is not shown because it does not influence diode behavior.The converter bears a superficial resemblance to the flybackconverter just described but operation is entirely different.The transformer does not serve as a choke.

The winding phasing is such that when power switch QSis on, rectifier diode DR is also on; current flow stores energyin the inductor LO and feeds the load. When QS is turned off,the voltages on all windings reverse. In the secondary, DRbecomes reverse biased and the choke current is now carriedby the freewheeling diode DF. The center winding is used toreset the core by allowing the magnetizing currentdeveloped when QS was on to flow through thedemagnetizing diode DD to the supply voltage VI. When QSis turned on, the winding polarities reverse to their formerstate and power is transferred to the load through DR whichcommutates off the freewheeling diode DF.

Transistor QS is turned on rapidly to reduce switchinglosses; consequently DR turns on rapidly which causes asimilarly rapid decrease of current in DF and a potentiallyhigh reverse recovery current, which passes through DR tothe transistor. The peak current, whose rate of rise is limitedonly by transformer leakage inductance and transistorcapability, could be significantly higher than the normalcurrent at the end of the transistor conduction interval, if thediode is not suitably chosen. The current spike may cause asignificant increase in turn–on dissipation in the transistorby raising its on–state voltage; the drive circuit could bedesigned to accommodate this current spike, but thissolution lowers efficiency. In addition, the overcurrentprotection scheme must be designed to ignore the spike. Thelower the stored charge in the diode, the less difficulty isexperienced with reducing turn–on losses and designingprotection circuitry.

When the transistor turns off, several changes of stateoccur simultaneously. The end result is that the rectifierdiode is cut off and the choke current flows through thefreewheeling diode. When turn–off is initiated, the transistorcurrent decreases rapidly compared to the current changesin the other components. Reset of the core through thedemagnetizing winding and its series diode DD commences.The demagnetizing current is a small fraction of thecollector current. Also the rectifier diode current is

commutated to the freewheeling diode. The reverserecovery current of DR flows through the freewheelingdiode causing a current spike during its forward recoverywhich increases its power dissipation. The recovery currentof DR also flows through the transformer and appears –modified by the turns ratio – as a reverse current through thedemagnetizing diode DD. The resulting reduction of currentin DD increases its impedance which in turn reduces thereverse recovery current. Thus the reverse recovery currentis lower than might be expected, thereby prolonging thecommutation interval in the secondary circuit.

Using ultrafast or Schottky diodes for the output diodesreduces the numerous problems associated with storedcharge. The speed requirements for DD are not severe; itoperates in a soft recovery mode. It must, however, have avoltage rating over twice the maximum input voltage to theprimary. The peak inverse voltage across the output diodesis equal to the secondary voltage minus the forward voltageacross the conducting diode, which can be neglected whenselecting diodes. The converter is usually designed such thatthe secondary voltage delivers that required to provide theoutput voltage when the input voltage is at its minimumlevel. At this point the peak inverse voltage is a little overtwice the output voltage. The input voltage range is typically1.5:1 and, allowing some margin for transient spikes, thevoltage rating of the output diodes typically needs to be atleast four times the output voltage. Since the output circuitswitches by forced commutation, diode snubbers should beused.

Push–Pull DC–DC ConvertersPopular push–pull configurations are shown in

Figure 189. Although the stresses on the power switchesdiffer, the voltage generated at the secondary of thetransformer and the behavior of the rectifier diodes isidentical for all three configurations. Push–pull converterscan be viewed as two forward converters operating 180 outof phase and using a common transformer. Since the powerswitches alternately magnetize the core in oppositedirections, no reset winding is required.

Because the secondary voltage waveform is alternating, afull–wave rectifier circuit is most efficient. Operation of therectifier circuit is similar to the single–phase full–wavechoke input circuit described in Chapter 7 where theinductor current is continuous. In a PWM power converter,a “dead time” occurs when both power switches are offcausing secondary voltage to be zero. During this interval,each diode ideally carries half the choke current, whilefunctioning as freewheel diodes.



Figure 187. Output Section of a Forward Converter (Transistor Snubber not shown)

Load

+

–

+

–

+

–

n : n : 1

++

–

–+

–+

DFVF

iDF

iDR DR

VF

iC

DD

VI

VL

VOCO

LO

QS

V2

t1 t2t0

TSDTS

iLmin

V0 + VF

Figure 188. Forward Converter Waveforms for Continuous Mode Operation

n

iDR, niC

iDR + iDF iLmax

iDF

V2

iL

VL

niC

V1/n

V1/n

– V0 – VF

V1



D2

Q1

Q2

D1

Figure 189. Output Sections of Popular Push–Pull Converters: (a) Center–Tap; (b) Full–Bridge; (c)Half–Bridge

n : 1

+

–

L

+

–

L

i D1

+

–

LI L

n : 1

n : 1

(a)

(b)

iD1

D1iD1

V2 iD2VO

IL

VI

D2

Q1

Q2

Q1 Q2

IL

iD2

D2

Q’1Q’2

VO

VOiD2

V2

V2

VI

D1

(c)



It is important that the diodes carry equal currents in orderto develop equal but opposing flux in the transformer, thusavoiding core saturation. To aid in maintaining equalcurrents, the wiring runs to the diodes should be identical.Purchasing diodes in matched pairs is beneficial but oftennot worth the additional cost and complexity added toproduction.

The secondary voltage and resulting current in each diodeare shown in Figure 190. The commutation intervals are

indicated by the steep slopes on the diode currentwaveforms. Note that each diode experiences two distinctcommutation intervals:

1. Current in one diode falls from full current to halfcurrent while the current rises from zero to halfcurrent in the other.

2. Current in one diode falls from half current to zerowhile current in the other rises from half current tofull current.

V1/n

iL

Figure 190. Secondary Waveforms for Push–Pull Converters

on on on on

V2

iD1

iD2

TSTSDTS DTS DTS

Q1 Q1 Q1 Q1

V1/n

In interval 1, no reverse recovery spike occurs since thediode does not cut off. However, during interval 2, reverserecovery current occurs in the diode turning off; the reverserecovery current spike also appears in the current of thediode and the transistor, which are turning on. Becausereverse recovery occurs when a diode is carrying only halfthe output current, the stored charge requirement is not assevere as for a forward converter operating at the sameoutput level and diode switching frequency. Rectifier diodecurrent handling requirements and voltage ratings areidentical to the forward converter.

The MOSFETs in the circuits of Figure 189 show diodesconnected between drain and source. These are part of theMOSFET, often called intrinsic or body–drain diodes. Thearea of the diode is large and its current handling capabilitygenerally exceeds that of the MOSFET, especially forhigh–voltage devices. Industry practice is to assign the diode

a continuous current rating equal to the MOSFET’s and apeak current rating three to five times greater.

Darlington transistors also have a built–in diode fromcollector to emitter. The Darlington’s diode is the result ofthe emitter metallization partly overlaying the base toproduce the monolithic base–emitter resistor of the outputstage. Consequently, the contact and the collector basejunction form a current path from the emitter to the collector.The total area of this structure and its current capacity neednot be large to construct a properly functioning transistor,but they are purposefully enlarged to increase thecollector–emitter diode’s current handling capability. Ingeneral, low–voltage Darlingtons have diode current ratingsequal to the collector current ratings, but in high–voltageDarlingtons, the diode current rating is typically half that ofthe collector current rating.



The utility of an intrinsic rectifier depends on theapplication in which it is used as well as the rectifier’scharacteristics. Circuits that use only one transistor rarelyexercise internal diodes. Therefore, intrinsic diodecharacteristics are unimportant in “single–ended” buck,boost, flyback, and forward converters. On the other hand,in bridge circuits for power supplies or motor controls, thediodes are often used as circuit elements, where theyfunction as catch or freewheeling diodes. As discussed, thecatch function requires good forward recoverycharacteristics, while freewheeling requires good reverserecovery as well. Intrinsic diodes can fulfill necessary circuitrequirements in many applications.

Off–Line AC–DC ConvertersThe proliferation of electronic equipment powered by

switch–mode power supplies has created a great deal ofdifficulty for building electrical distribution systems [9].The difficulties arise because of the narrow pulses of linecurrent drawn by the capacitor input filters used to providethe dc power to the power switching stages. The currentpulses have high rms values and a high harmonic content,which is fed into the electrical distribution system.

Among the problems caused are:1. Circuit breaker life is short and improper operation

occurs.2. Excessive current flows in the neutral of the three

phase power distribution system. The neutral is not

supposed to carry current, so it is not protected bybreakers; consequently, fires have occurred.

Recognizing the need to control harmonic currents,organizations such as IEC and IEEE are developingstandards. When implemented, the stringent requirementsof IEC standard 555–2 [10] will force manufacturers sellingin Europe to develop new methods [11] of rectification andfiltering for single–phase circuits rather than use the classictechniques described in Chapter 7.

One of the more popular schemes uses acontinuous–mode boost converter operating at a highfrequency (100 kHz, typically) under current mode control[11]. A simplified circuit is shown in Figure 191. The controlcircuit receives three inputs. A sample of the full–waverectified sine–wave voltage is applied where it serves as acurrent waveform reference. A current transformer, asshown, or a resistor in series with the power switch providesa sample of the input line current. The third input isproportional to the dc output voltage. The controller usesthese inputs to provide a PWM drive to the power switch.The drive achieves two objectives:

1. The dc output voltage is regulated by varying theratio for switch on time to off time.

2. The average inductor current over one ac cycle (50or 60 Hz) is forced to be sinusoidal by varying theon–time pulse width during the cycle such that theaverage of the pulses is sinusoidal.

Figure 191. Popular High–Power Factor Rectification Circuit Using a Boost Converter

+

–

AC INPUTBRIDGE

RECTIFIER

CONTROLCIRCUIT

Vout



The inductor and switch waveforms are sketched inFigure 192. Of course, in practice the repetition rate of thehigh–frequency switching pulses are much higher thanshown and the pulses cannot be drawn to scale on a sketchof this kind.

The choke is usually operated in the continuousconduction mode over most of the ac cycle. At some point,typically around 30 V with a 120 V input, the inductor isallowed to “run dry” in order to keep it small. This createsa little step in the input current wave which raises itsharmonic content. Thus a tradeoff between choke size andperformance occurs.

The high–frequency rectifier diode DR must meet stringentrequirements. It operates in a forced commutated mode overmost of the ac cycle so low stored charge is important. Inaddition, it must block the dc output voltage, which, for aboost converter, must exceed the highest line voltage peaksanticipated. For a “universal input” circuit, the boosted outputvoltage is typically around 400 V, dictating use of diodes withat least a 500 V rating. Fortunately, the current requirementsare not severe since the current pulses have the sameamplitude as would occur with a resistive load.

Figure 192. Inductor and Transistor Currents in the Boost Converter Rectifier

Inductor CurrentSwitch Current

Synchronous RectificationThree demands placed upon the power supply industry

highlight the need for improved rectifiers:1. Three–volt dc levels for the next generation of

VSLI2. Improved efficiency3. Smaller size.

These demands are interrelated; without improvements inrectification efficiency, the efficiency of the 5 V supply islikely to remain about 80% and efficiency in a 3 V supplywill be intolerable. Improvements in power density demandless internally generated heat.

A well–publicized method of improving rectificationefficiency is to use a “synchronous rectifier.” Althoughsome innovative drive schemes have been developed whichdo not require additional windings on the power transformer[12], the most common embodiment consists of alow–voltage power MOSFET driven by an auxiliarywinding on a power transformer as shown in Figure 193. Thewinding polarity is such that each MOSFET receives drivewhen it is to conduct current. Current flows from theMOSFET’s source to its drain, which is opposite to that ofconventional use. When the MOSFET turns off, it blocksdrain–to–source voltage as it would in a standardapplication.

Figure 193. Rectification by Using Power MOSFETs as Synchronous Rectifiers

G

S D

GS D

L

VO



Synchronous rectification is possible because theMOSFET can conduct current in either direction when itschannel is enhanced. Figure 194 illustrates the first and thirdquadrant operating characteristics of a 28 mΩ 60 VMOSFET. If the MOSFET’s on–voltage is lower than theforward voltage of a comparable Schottky, rectificationefficiency is improved. Designing a synchronous rectifierrequires sequencing the MOSFET’s turn–on. Some deadtime is needed; otherwise, both transistors may be onsimultaneously and shoot–through losses will be high.However, if the dead time is large relative to the carrierlifetime, the intrinsic diode will begin to conduct current,charge will be stored in its junction, and high reverserecovery losses will occur during commutation. A solutionto the cross conduction problem is to use a Schottky inparallel with the MOSFET to conduct current duringcommutation, but the added cost and complexity makes thissolution unappealing. Unique MOSFETs developedspecifically for synchronous rectification have the bestchance of challenging traditional rectification methods.

I A

200mV

500mV

2

Figure 194. Power MOSFET Output Characteristics inthe 1st and 3rd Quadrant

Synchronous rectification is not in widespread use at thistime primarily because it is difficult to achieve lower lossthan a Schottky provides. Simplicity of use is also stronglyin favor of the Schottky. A major advantage of the Schottkyis that its forward voltage decreases at elevated temperature,whereas the MOSFET’s on–voltage increases. With presentSchottky and MOSFET technologies, the Schottky is lessexpensive because its die size is smaller.

In spite of the Schottky’s strengths, there are severalapplications where cost is of secondary interest that canbenefit from the use of synchronous rectification.Sometimes the highest possible efficiency is requiredsimply to save power, as in a battery–operated laptopcomputer where the operating ambient temperature is low[12]. In other situations, minimizing heat generation isessential because there is no outlet for it, as in someaerospace or military applications. Using a large MOSFETor a group of paralleled MOSFETs might be the only way toachieve the performance goals. Using synchronousrectifiers also provides new options for secondary sidecontrol and can help improve post regulation. The ability tocontrol conduction time has enabled designers to omitORing diodes in a system of paralleled converters [13].



References1. Warren Schultz, “Baker Clamps–Traditional

Concepts Updated for Third Generation PowerTransistors,” Powerconversion International,July/August 1984. (Reprints available from ONSemiconductor Products Inc. Request AR 131.)

2. George Chryssis, High Frequency SwitchingPower Supplies: Theory and Design,McGraw–Hill Book Co., New York, N.Y. 1984.

3. Frank Cathell and Bill Roehr, “A Return from theExotic–A Simple 1KW Off–Line Converter UsingTwo Power Switches and a Half–BridgeTopology,” Official Proceedings of the TwelfthInternational SATECH Conference, Boston, MA,October 25–31, 1986.

4. W. McMurray, “Selection of Snubbers and Clampsto Optimize the Design of Transistor SwitchingConverters,” IEEE Transactions on IndustryApplications, Vol. IA–16, No.4, pp. 513–523,July/Aug 1980.

5. L.G. Meares, “Improved Non–Dissipative SnubberDesign For Buck Regulators and Current–FedInverters,” Proceedings of Powercon 9, PowerConcepts, Inc., 1982, B–2, pp.1–8.

6. Moshe Domb, “Nondissipative Snubber AlleviatesSwitching Power Dissipation, Second–BreakdownStress, and VCE Overshoot: Analysis, Design,Procedure and Experimental Verification,”Conference Record of 1982 IEEE PowerElectronic Specialists Conference, pp. 445–454.

7. William J. Shaughnessey, “Modelling and Designof Non–dissipative LC Snubber Networks,”Proceedings of Powercon 7, March 24–27, 1980,San Diego, CA, pp. G4–1 to 04–9.

8. Sam Anderson, Kim Gauen, and William C.Roman, “Low Loss, Low Noise, MEGAHERTZ

Rectifiers for High Frequency Applications,”PCIM, Oct. 1991.

9. “The Case for Power Factor Correction,” PCIM,December 1989, pp. 23, 24.

10. Hill Roehr, “A Synopsis of the Proposed IECHarmonic Standard 555–2,” PCIM, June 1990, pp.31.

11. Recent conferences have devoted entire sessions tothe subject of power factor correction of lineoperated rectifiers. See: (a) ConferenceProceedings of 1990 and 1991 IEEE AppliedPower Electronics Conference, IEEE, New York,NY. (b) The Proceeding of the NineteenthInternational Power Conversion Conference,1989, Intertec Communications, Ventura, CA.

12. Bijan Mohandes, “Achieving 90% Efficient PowerConversion Using Synchronous Rectification,”Proceedings of the Twentieth International PowerConversion Conference, June 25–29, 1990,Munich, West Germany.

13. Ray On, “An Implementation of SynchronousRectifiers in a Power Converter Designed for Usein Parallel Operation,” Proceedings of PowerConversion and Intelligent Motion ‘90,Philadelphia, PA, Intertec Communications,Ventura, CA.

General ReferencesJohn 0. Kassakian, Martin F. Schlect, and George C.

Verghese, Principles of Power Electronics,Addison–Wesley Publishing Company., New York, NY

Ned Mohan, Tore M. Undeland, William P. Robbins,Power Electronics: Converters, Applications, and Design,John Wiley and Sons, New York, NY.

Rudy Severans and Ed Bloom, Modern DC–to–DCSwitchmode Power Converter Circuits,” Van NostrandReinhold Company, New York, N.Y., 1985.



Chapter 12

Reliability Considerations



#

Reliability is a discipline that combines engineeringdesign, manufacture, and test. An efficient reliabilityprogram emphasizes early investment in reliabilityengineering tasks to avoid subsequent cost and scheduledelays. The reliability tasks focus on prevention, detection,and correction of design deficiencies, weak pans, andworkmanship defects with the goal of influencing theproduct development process and producing products whichoperate successfully over the required life.

The reliability of a product can only be established ifreliability is designed in, proper quality–controlledinspection and manufacturing assured; and maintenanceprocedures carried out. Improvement in reliability occurswhen reliability information, obtained from test and fielddata, is analyzed and then, through an iterative feedbackprogram, is used to improve the design.

This chapter discusses the fundamental reliabilityconcepts and methods. The focus is on understanding thecauses of failures in order to address them in design,manufacture, and test.

ConceptsReliability is the probability that for a given confidence

level, the product will perform as intended (i.e., withoutfailure and within specified performance limits), for aspecified mission time, when used in the manner and for thepurposes intended under specified applicationenvironmental and operational conditions. Reliability isthus a quantitative metric used to assess performance overtime, and can be considered to be a characteristic of aproduct in the sense that reliability can be estimated indesign, controlled in manufacturing, measured duringtesting, and sustained in the field.

Quality describes the reduction of variability, so thatconformance to customer requirements/expectations can beachieved in a cost–effective way. Quality improvement fora task or a process is described in terms of the target field,current status with respect to target (variability), reductionof variability (commitment to continuous improvement),customer requirements (who receives output, what areperson’s requirements/expectations), and economics (costof nonconformance, loss function, etc.). While quality is ameasure of variability (extending to potentialnonconformances–rejects) for the product population,reliability is a measure of variability (extending to potentialnonconformances–failures) for the product population,time, and environmental conditions.

Reliability serves as an aid to determine feasibility andrisk when utilized early in the concept development stage ofa product’s development. In the design stage of productdevelopment, reliability analysis involves methods toenhance performance over time through the selection ofmaterials, design of structures, choice of design tolerances,manufacturing processes and tolerances, assemblytechniques, shipping and handling methods, andmaintenance and maintainability guidelines. Engineeringconcepts such as strength, fatigue, fracture, creep,tolerances, corrosion, and aging play a role in these designanalyses. The use of physics of failure concepts coupledwith mechanistic as well as probabilistic techniques is oftenrequired to understand the potential problems and tradeoffs,and to take corrective actions when effective. The use offactors of safety and worst–case analysis are often part of theanalysis. In the manufacturing and operations stage of aproduct, reliability analysis is useful in determining stressscreening procedures, reliability growth, maintenancemodifications, field testing procedures, and various logisticsrequirements such as the number of spare pans.

The reliability of electronic devices can be represented byan idealized graph called the bathtub curve. There are threeimportant regions identified on this curve. In Region A, thefailure rate decreases with time and it is generally calledinfant mortality or early life failure region. In Region B, thefailure rate has reached a relatively constant level and iscalled the useful life region. Many modem semiconductorshave been improved to the point where infant mortality anduseful region failure rates are so near zero that the namebathtub curve is used as reference rather than expressing thetrue shape of the failure rate curve. Furthermore, the resultof continuous reliability improvement is that manysemiconductor products no longer require environmentalstress screening such as bum–in.

In the third region, Region C, the failure rate increasesagain and is called the wearout region. Modemsemiconductors should not reach the wearout portion of thecurve when operated under normal use conditions (i.e.,within the maximum rated value) and within reasonablelifetimes. In fact, the wearout portion of the curve, for manyfailure mechanisms, has been delayed beyond the useful lifeof much equipment. This is accomplished by physics offailure studies based on highly accelerated tests from whichdesign rules are obtained which help to produce productswith improved lifetimes.



Design for ReliabilityReliability in electronics design hinges on the recognition

that an organized, disciplined, and time–phased approach todesign, development, qualification, manufacture, andin–service management of a product is required to achievemission performance over time, safety, support ability, andcost–effectiveness. The foundation of the approach consistsof tasks, each having total engineering and managementcommitment and enforcement. The tasks are:

1. Define realistic system requirements.2. Define the design usage environment

(temperature, humidity, cycling ranges, vibration,etc., including all stress and loading conditions).

3. Characterize the materials, and the manufacturingand assembly processes (use design of experimentsto determine and/or validate materials andprocesses).

4. Identify the potential failure sites and failuremechanisms (parts and part details, potentialfailure mechanisms and modes, architectural andstress interactions, measures for control).

5. Design to the usage and process capability (lifecycle usage requirements, quality levelscontrollable in manufacturing and assembly).

6. Qualify the product manufacturing and assemblyprocesses. (If all the processes are in control andthe design is proper, then could move fromproduct test, analysis, and screening, to processtest, analysis, and screening.)

7. Control the manufacturing and assemblyprocesses. (Processes must be monitored andcontrolled to avoid inappropriate shifts; this mayinvolve screens and tests to assess statisticalprocess control.)

8. Manage the life cycle usage of the product usingclosed–loop management procedures (realisticinspection and maintenance procedures, trackingprocedures, deficiency reporting, and updates inprocedures based on actual usage).

The reliability tasks which are utilized to design forreliability include system architecture and devicespecification, stress analysis, derating, stress control, stressscreening, failure data collection and analysis, and failuremodes, effects, and criticality analysis (FMECA). These arebriefly discussed below.

System Architecture and Device SpecificationAs the physical design begins, reliability analysis can

affect the system architecture and part selection, althoughfunctional and performance characteristics play thedominant role. Individual components must not beconsidered to be the only, or necessarily the major, source offailures. Interconnections and structures must also beproperly selected. Furthermore, the interactions of stressesare important. Another aspect of system architecture is theuse of redundant circuits. Redundancy may be deemed

necessary for mission completion when the reliabilityestimates indicate improbable success or unacceptable risk.

Stress AnalysisGiven the system architecture and pans, reliability

prediction models are used to assess the influence of themagnitude and duration of the stresses on the reliability ofthe parts and systems, so that stress– andenvironment–controlling systems (i.e., vibration, coolingsystems) and derating techniques can be implemented.Temperature, humidity, electrical fields, vibration, andradiation are major stress variables affecting reliability.

There are various ways in which both the operating andenvironmental stresses can be controlled to improvereliability. Methods can be applied to keep harmful stresses(i.e., high temperatures, high shock loads, high humidity,high radiation etc.) away from sensitive devices andstructures, or to manage the system environment to obtaincontrolled stress conditions. Lowering the harmful stressesis often a first choice of designers for reliabilityimprovement. However, the cost and complexity of loweredstresses must be balanced against the cost and complexity ofelectronic complications to improve reliability by improvedarchitectures and pans.

DeratingDerating is based on the concept that operating electrical,

thermal–mechanical, and chemical stresses acceleratefailures in a predictable manner which, if controlled, willimprove reliability. Using the mathematical expressions ofreliability prediction, one can often derive a derate schedule.Such schedules must be based on the dominant failuremechanisms for the particular electronics and must includeinterconnects and device interactions, as well as the devicesthemselves.

Stress ScreeningScreening is the process by which defective parts,

resulting from improper or out–of–control manufacture andassembly processes are detected and eliminated from aproduction batch. The principle involves observing orinducing latent defect failures only in a population of partsthat already has “weak” parts without reducing thereliability in the population of “strong” parts. Theassumption is that, through the application of short–termstresses, the weak population can be discovered andeliminated, leaving a highly reliable population. Stressscreening methods and the associated acceleration stresslevels must be based on the failure mechanisms due toproblems in quality.

One type of screen is called bum–in, whereby the parts areoperated for a period of time at high temperatures in orderto precipitate defects in the weak population of pans. Forparts with low failure rates (below ten failures per milliondevice hours) ON Semiconductor believes bum–in prior tousage does not remove many failures. On the contrary, itmay cause failures due to handling.



Failure Modes, Effects, and Criticality Analysis(FMECA)

FMECA is a method to assess the interoperability of thepans, subassemblies, assemblies, and subsystemscomprising the system. The objective is to determine theeffect of failures on system operation, identify the failurescritical to operational success and personnel safety, and rankeach potential failure according to the effects on otherportions of the system, the probability of the failureoccurring, and the impact of the failure mode. Reliabilitypredictions are often used for each element in the system foreach potential failure mode.

Failure Data Collection and AnalysisFailure data comes from life tests, accelerated life tests,

any environmental stress screens that may have beenperformed, and, if available, field characterization andmalfunction data. Users of this data must be aware of thesource of data, the specific failure modes uncovered infailure analysis, the manufacturing and handling conditions,the application of the parts in the field, and the applied stresshistory. Test data often neglect the kinds of stresses thatactually arise in the field, while field data collection isnotoriously inadequate, in the sense that a failure is oftenassociated with a removal rather than with a well–identifiedfailure mechanism. In other cases, the cause of failure iseither not reported or inaccurately reported if it was causedfrom being installed incorrectly, mishandled, or misused.Users of data must be especially cautious when using modelsextrapolated from field– and test–based models for newtechnology–type pans having very little, if any, applicationdata. Failures should be classified by the failure location orfailure site, the consequence or mode by which the failure isobserved (i.e., open, short, parameter drift) and the failuremechanism (i.e., electronic overstress, corrosion,electromigration, fatigue).

Practical Aspects of SemiconductorReliability

An understanding of semiconductor reliability requiresknowledge of the potential failure mechanisms and thestresses that accelerate failures. What follows is a briefoverview of each of the various failure mechanismsaffecting semiconductor devices. A focus is placed ontemperature dependency because traditionally steady–statetemperature has incorrectly been considered to be a criticalparameter to reliability. This section shows that below ratedtemperatures, steady–state temperature is not a majorcontributor to failures and that more attention should be paidto temperature cycling and temperature gradients. Not allmechanisms described are present in all power rectifierdiodes, but for complete coverage of the topic, are includedhere.

Electrical OverstressElectrical overstress occurs when a higher–than–rated

voltage or current induces a hot–spot temperature beyondspecifications for short periods of time. Hot–spotdevelopment typically occurs at a semiconductor junctiondue to an increase in the current flow to accommodate theadditional stress in the device. As the junction heats up, theincreased temperature encourages increased current flowdue to the lowering of the silicon resistance at highertemperature which in turn further heats up the junction. If thesituation continues, the hot–spot temperature may exceedthe intrinsic temperature of silicon, beyond which theresistivity of silicon decreases greatly. This allows morecurrent to pass through the hot spot, further increasing thetemperature, and resulting in thermal runaway. Failureoccurs when the silicon in the hot spot melts, destroying thesilicon crystal structure. If the electrical transient continues,the interconnects are expected to melt as well.

Second BreakdownWhen reduced to basics, excessive temperature causes

most failures in semiconductor chips. High uniformtemperature within the chip is responsible for a gradual driftof characteristics that becomes more noticeable astemperature is raised, but this rarely causes catastrophicfailure, such as opens or shorts.

Catastrophic failures result from extreme temperature ina lead wire causing it to open, or from a hot spot in the chipcausing it to short. In most circuits, the latter also causes theformer. A reverse voltage is always required in order toproduce a sufficient amount of current crowding to cause ahot spot, and high hot–spot temperatures cause an extremereduction in the voltage capability of a semiconductor. Athermally induced breakdown, observable on a V–I plot,occurs as shown in Figure 195.

Figure 195. Typical V–I Plot of SemiconductorMaterial Exhibiting Thermal Breakdown

Voltage

Cur

rent



Thermal breakdown – a switch back of voltage from ahigh to low level – has been shown to be a fundamentalproperty of any semiconductor material. It occurs at thetemperature at which the material becomes intrinsic. Thetemperature of intrinsic conduction is inversely related toresistivity, varying from 200C to 400C for resistivityvalues in common use.

The most thermally rugged devices are silicon,diffused–junction, or Schottky barrier semiconductors oflow resistivity. Silicon is better than germanium because itbecomes intrinsic at higher temperatures; a diffused junctionresults in more even current distribution than does analloyed junction, and the lower the resistivity of the material,the higher the temperature at which it becomes intrinsic.

Ionic ContaminationIonic contamination causes reversible degradation such as

a threshold voltage shift and gain reduction in MOS devicesdue to the presence of mobile charge ions within the oxideor at the device–oxide interface. Ionic contamination iscaused by mobile ions in semiconductor devices.Contamination can arise during packaging and interconnectprocessing, assembly, testing, screening, and duringoperation. Alkali ions, such as sodium, chloride, andpotassium, are the most common contaminants. The amountand distribution of the alkali ions in or near the gatedielectric region will influence the device threshold voltageby superposition of these ionic charges on externally applieddevice voltage. Extra positive charge at the Si/SiO2 interfaceinduces extra negative voltage resulting in a decrease in thethreshold voltage of the device. The mobility of the ions istemperature dependent. For this reason, a high–temperaturestorage bake and exposure to high temperature duringbum–in are found to screen out the ionic contaminationfailures. A common characteristic of contamination failuresis the reversibility under high temperatures in theneighborhood of 150 to 200C which partially or fullyrestores device characteristics, reflecting a disordering ofcharge accumulations resulting from ion mobility andapplied bias.

The problem of ionic contamination is solved by use ofhigh–purity materials and chemicals for processing, use ofHCl during oxidation, and use of phosphosilicate glass(PSG) or borophosphosilicate glass (BPSG) over thepolysilicon to getter the ions. Passivation layers can provideadditional protection against ingress of alkali ioncontamination in completed devices.

ElectromigrationElectromigration is the result of high current density,

typically of the order of 106 A/cm2, in metallization trackswhich produces a continuous impact on the metal grainscausing the metal to pile up in the direction of the currentflow and produce voids in an upstream direction withrespect to the current flow. In thin–film conductors,electromigration–induced damage usually appears in theform of voids and hillocks. Voids can grow and link together

to cause electrical discontinuity in conductor lines whichleads to open circuit failure. Hillocks can also grow andextrude out materials to cause short–circuit failure betweenadjacent conductor lines in the same level or in adjacentlevels in multilevel interconnecting structure. Alternatively,it can break through the passivation or the protective coatinglayers and lead to subsequent corrosion–induced failures.Void–induced open–circuit failures usually occur at anearlier time than extrusion–induced short–circuit failure inthin–film conductors using Al–based metallurgies.

The phenomenon of electromigration–induced masstransport is attributed to atomic flux during the passage ofcurrent through a polycrystalline thin–film conductor, as aresult of electromigration in the lattice and at the grainboundaries. There is a temperature gradient dependence ofelectromigration failures. An analysis of electromigrationtests on the lifetime of Cr/Al–Cu conductors covered withpolymide passivation showed that the electromigrationfailure location is typically nearer to the location ofmaximum temperature gradient, whereas the location of anontemperature–gradient–induced failure was randomlydistributed.

Hillock FormationHillocks in die metallization can form as a result of

electromigration or exposure to extended periods undertemperature cycling conditions. Hillock formation as aresult of electromigration often occurs upstream in the senseof the electron flow, from the area of voiding. Hillocks growfastest at the down–stream edge, closest to the source ofmigrating metallization. Both voiding and hillock formationcan occur, sometimes on top of each other. Thisphenomenon of simultaneous voiding and hillock formationoccurs at temperatures in the neighborhood of 140 to 200C.

Hillock formation produced by extended periods undertemperature cycling conditions is believed to be due to aself–diffusion process that occurs in the presence of strainswithin the metallization. These strains may be due to amismatch in the thermal expansion coefficients of themetallizations (Au), underlying refractory layer (TiW), Si,and SiO2. Hillock growth is more extensive in filmsdeposited on room–temperature substrates than on heatedsubstrates, indicating that the effect may vary with grainsize. Hillocks can cause electrical shorts between theadjacent lines and fracture of the overlying dielectric film.In double–level metallized devices, hillocks can result inshorts between the underlying metal layer and the overlyingmetal layer. Hillocks can be caused by electromigration.They can result in thin dielectric sites that are susceptible tosubsequent breakdown of the intermetal dielectric. Hillockformation is largely remedied by use of alloyed metal suchas Al–Cu and improvements in the technologies ofpassivation and packaging. Hillock formation is more afunction of temperature cycling and temperature gradientsand is mildly dependent on temperature in the neighborhoodof 400C.



Contact SpikingContact spiking is the penetration of metal into the

semiconductor in contact regions at temperatures typicallyabove 400C. This failure mechanism is accompanied bysolid–state dissolution of the semiconductor material intothe metal or the alloy of metallization system with the metalsemiconductor interface moving vertically or laterally intothe semiconductor. Contact spiking in chips is observed athigh chip temperatures or localized high contacttemperatures. Localized high temperatures may causefailure of the chip to substrate bond, thus increasing thethermal resistance or producing a thermal runaway of thedevice, or resulting in a large degree of electrical overstress.

Contact spiking can occur in device fabrication when thedevice is exposed to high temperatures. This failuremechanism can be minimized by using silicon containingaluminum alloys such as Al–1% Si or using barrier metalssuch as Ti–W. Metal spikes penetrate into the electricallyactive region of the device causing increased leakage currentor shorting. It is not possible to characterize suchinterdiffusion failure mechanisms by an activation energybecause of their irregular behavior.

Migration of Al along Si defects has been observed inNMOS LSI logic devices, due to contact migration alsoknown as electrothermomigration. Failures are acceleratedby elevated ambient temperature in the neighborhood of400C. This failure mechanism may be dominant duringVLSI manufacture and packaging when the temperaturesexceed 400C.

Metallization MigrationMetal migration occurs between biased lands under

conditions conducive to electro crystallization. Dendriticgrowth is a common cause of failure. Conditions for metalmigration include:

1. A level of current density at the tip of the dendritein the neighborhood of 10 A/cm2.

2. Spheroidal and parabolic diffusion.3. Sufficient liquid medium such as condensed water.4. Applied voltage which exceeds the sum of anodic

and cathodic potentials in equilibrium with theelectrolyte

5. Materials with defects which allow watercondensation to satisfy the current densityrequirement.

Metallization migration involves the formation ofaluminum growths beneath the silicon dioxide layer.Metallization migration occurs during deposition ofconductors on silicon dice due to the combined effects ofelevated temperature and electrical stress. It has beenreported that triangular–shaped aluminum growths formedbeneath the silicon dioxide layer when conductormetallization was deposited at high temperature on siliconsubstrate. The triangles formed within minutes afterdeposition of an 8000 angstrom thick aluminum layer on

silicon at temperatures from 500 to 577C. The time forgrowth formation decreases with increasing temperature.Growth caused local electrical short circuits. The hightemperatures at which this failure phenomenon occursmakes it a recessive mechanism in the normal operation ofmicroelectronic devices.

Corrosion of Metallization and Bond PadsCorrosion is typically defined as the chemical or

electrochemical reaction of a metal with the surroundingenvironment. The mechanisms of corrosion can be dividedinto two types: dry, such as oxidation of aluminum in air andwet, where the reaction occurs as in the presence of anelectrolyte, a moist environment, and an electromotiveforce. Dry corrosion is of minor importance insemiconductor devices, since the corrosion process is selfpassivating for the metal, fanning a thin oxide film whichprevents further oxidation. Wet corrosion, in the presence ofan ionic contaminant and moisture, can provide a conductivepath for electrical leakage between adjacent conductors,dendrite growth, or corrosion of device metallization orbond pads. Corrosion typically begins when the temperatureinside the package is below the dew point, enablingcondensation inside the package. During operation, heatdissipated by the die is often enough to raise the temperatureto evaporate the electrolyte. Elevated temperature due todevice power thus acts as a mechanism to inhibit thecorrosion process.

Stress Corrosion in PackagesStress corrosion is a failure phenomenon which occurs

around 300C and above, predominantly in power devices.Electrochemical corrosion interacting with mechanicalstress is a potential cause of failure. Failures are typicallytransgranular and result from the acceleration of the fatigueprocess by corrosion of the advancing fatigue crack. Forexample, craze cracking of polymers occurs in halogenatedsolvent vapors. Adsorbed moisture films due to high relativehumidity exposure cause static fatigue of the leadzinc–borate sealing glass. The distinct mechanism ischemical attack on glass, and the time to failure is usuallymodeled by an Arrhenius equation of temperature whichactivates above 300C. The rate of galvanic corrosion in thepresence of a liquid electrolyte increases as temperature isincreased due to a more rapid rate of electron transfer.Typically corrosion products in microelectronic devices,such as Al(OH)3, are derived from reaction processes whichare monotonically increasing functions of temperature.Although the corrosion rate depends in part on thesteady–state temperature, corrosion rate also depends on themagnitude and polarity of the corrosion galvanic potentialwhich are functions of the electrolyte concentration, pH,local flow conditions, and aeration effects. Finally, as notedpreviously, elevated temperature due to componentoperation and especially continuous high power, acts asmeans to inhibit corrosion.



Wire FatigueThe wires used to connect die bond pads to leads can fail

due to cyclic temperature changes resulting from repeatedflexing of the wire. The most prevalent failure site is the heelof the wire. Wire–bond failures are typically due to thedifferential coefficient of thermal expansion between thewire and the package as the device is heated and cooleddown during temperature and power cycling. Failures maybe inhibited by high loops, though small dimensions ofpresent–day packages impose stringent requirements on theloop dimensions, making this solution often impractical.

Wire Bond FatigueA wire bond subjected to temperature change experiences

shear stresses between the wire, the bond pad, and thesubstrate as a result of differential thermal expansion.Intermetallic brittleness and growth is enhanced bytemperature cycling. When bonded together, gold andaluminum present a problem when subjected to temperaturecycling. Au–Al intermetallics are more susceptible toflexure damage than pure Au and Al wires. Kirkendall voidsoccur at the interface between the wire and the bond padwhen the contacting materials are gold and aluminum.Kirkendall voids form when either the aluminum or golddiffuses out of one region faster than the other can diffusefrom the other side of that region. Vacancies pile up andcondense to form voids, normally on the gold–rich sidealong the gold–to–aluminum interface.

The rates of diffusion vary with temperature and aredependent upon the adjacent phases, as well as on thenumber of vacancies in the original metals. The compoundsformed in the intermetallic are often called purple plaguebecause of the purple appearance of the gold–aluminumcompound. Studies show that the formation of significantamounts of purple plague is negligible below 150C.Intermetallic compounds are mechanically strong, brittle,and electrically conductive. Temperature and power cyclingcan cause failure as a result of differential thermal expansionbetween the intermetallic and the surrounding metal, andreduce mechanical bond strength as a result of voiding of thesurrounding metal, usually accompanying intermetallicformation. Gold–aluminum intermetallics are stronger thanpure metals and their growth is enhanced by increasedtemperature and temperature cycling.

Generally, the bond strength is more a function oftemperature cycling than steady–state temperature in therange of temperature between –55C and 125C, althoughthe bond strength decreases as a function of temperatureabove 150C for gold–aluminum bonds and above 300Cfor gold–copper bonds.

Die FractureThe die, the substrate or the leadframe, and the case of a

package typically have different thermal expansioncoefficients. For example, die are usually made of siliconwhile the substrate is typically alumina, berylia, or copperhaving a coefficient of thermal expansion different from the

die material. As the temperature cycle magnitude risesduring temperature and power cycling, tensile stresses aredeveloped in the central portion of the die and shear stressesare developed at the edges of the die. Ultimate fracture of thebrittle die can occur suddenly without any plasticdeformation when surface cracks at the center of the die orat the edge of the die reach their critical size and propagateduring thermal cycling to the critical crack size.

Vertical cracking of the die is caused by tensile stressesand horizontal cracking is caused by high shear stresses atthe edges. The brittle failure criterion can be represented bythe size of a critical crack on the external die surface.Microcracks are developed in the die during manufacture. Insome cases these microcracks may be large enough to causebrittle failure of the die. A pre–existing defect may developinto a crack under the influence of thermal cycling in the die.This crack may not be of critical size at the applied servicestress, but may grow to critical size gradually by stablefatigue propagation. The rate of fatigue crack propagationper cycle is determined by the cyclic change in stressintensity factor, a measure of the stress at or around the cracktip. The stress generated in the die during temperaturecycling is dependent on the number and magnitude of thetemperature cycles.

Die Adhesion FatigueIn a typical power or environmental temperature cycle,

the die, the die attach, the die substrate, and the packageexperience temperature differences and temperaturegradient differences. Because they also have differentcoefficients of thermal expansion, the bond between the dieand the substrate can experience fatigue failure.

The most common die attach defects are voids. Thepresence of edge voids in the die attach induces highlongitudinal stresses during power and environmentaltemperature cycling. These voids can act as microcrackswhich propagate during power cycling resulting indebonding of the die from the substrate or the substrate fromthe case. Voids are responsible for weak adhesion, dielifting, increased thermal resistance, and poor power cyclingperformance. Solder and some epoxies have been shown tocrack and detach during temperature cycling. Voids canform from melting anomalies associated with oxides ororganic films on the bonding surfaces, out gassing of the dieattach, trapped air in the bonds, and shrinkage of solderduring solidification. Insufficient plating, improper storage,lack of cleaning, or even diffusion of oxidation proneelements from an underlying layer can generate voids duringmelting of die attaches. In other instances, dewetting ofsolder results in excessive voiding, especially when asolderable surface, a poor solderable underlying metal, orexcess soldering time produces an intermetallic compoundnot readily wet by the solder. Even under ideal productionconditions, voids are often present due to solventevaporation or normal outgassing during cooling of organicadhesives. Although voids can form from a number ofsources, they are normally limited to an acceptable level



through process control. The actual package construction,the die attach unit materials, and the overall voidconcentration determine the actual effect of voiding ondevice reliability. While small concentrations of randomvoids have little effect on the peak junction temperature, alarge–size void may reduce the thermal performance of thedevice by creating a large temperature gradient.

Cracking in Plastic PackagesThermal coefficient of expansion (TCE) mismatches

drive the failure mechanisms of cracking of plasticpackages. Silicon has a TCE of about 3 ppm/C, whilemolding compounds typically have a TCE of about 20ppm/C below the glass transition temperature. Most leadframe materials are either Alloy 42 with a TCE of 4.7ppm/C or copper with a TCE of about 17 ppm/C.

A typical process involves die attachment with adhesivecure at 270C using polyimide adhesive or at l70C usingepoxy adhesive, followed by encapsulation and cure of themolding compound at 170C. Negligible stress isestablished at these elevated temperatures, but the thermalcoefficient of expansion differentials causes increasingstress as the ambient temperature is lowered. The die attachproduces a bending moment at room temperature that putsthe surface of the die into tension and the bottom of the dieinto compression. The magnitude of the tensile stress at thesurface of the die is proportional to the thickness of the die.Encapsulation superimposes a compressive stress on the die,and tends to place the molding compound under tension.Cracks therefore have a tendency to propagate in themolding compound.

Cracks in packages are a reliability concern because theyprovide a path for the entry of contaminants. Shear stressesare applied on the surface of the chip due to differentialthermal expansion between the plastic encapsulant and thepassivation layer, resulting in the fracture of the passivationlayer, which forfeits its action as an impurity getter andbarrier. This also causes lateral displacement of theinterconnection lines on the surface of the chip and shortsbetween the overlying and underlying interconnectionpatterns in devices with two or more layers ofinterconnection. The effects of stresses applied by plastic aremore pronounced in larger chips especially at the chipcorners. Resilient conformal coating on the die and the useof plastic encapsulants with a lower coefficient of thermalexpansion are some of the methods used to decrease thermalstress effects in the passivation layer, due to thermalcoefficient mismatches. Damage of passivating film ofplastic encapsulated devices can occur due to thermallyinduced stress at the encapsulant passivation layer interface.The location of aluminum corrosion coincides with defectsin the passivating film, typically caused by differentialthermal stress from the encapsulant. Cracks also initiate dueto stress concentrations at the top edge of the die or at thebottom edge of the lead frame, or due to voids in the moldingcompound. The cracks propagate under the influence oftemperature cycling.

Delamination is a failure mechanism that occurs betweenthe die and molding compound and between the moldingcompound and the lead frame due to shrinkage aftermolding. During board assembly, plastic surface mountcomponents (PSMCs) are subjected to temperatures in therange of 215–260C and heating rates of as high as 25C/secduring normal operational temperature cycles. In addition toTCE driven stresses, if the heating or cooling rates are muchhigher than 10C/sec, thermal stresses associated withinternal temperature gradients can be appreciable. Moistureabsorbed by the package molding compound evaporatesunder high temperatures, creating an internal pressurecausing cracking (generally referred to as the popcornmechanism). It is possible for PSMCs to absorb moistureduring storage in normal ambients for vapor–driven stressesto dominate the mechanics of the package. The main factorsinfluencing the propensity to crack include: peaktemperature reached during soldering, moisture content ofthe molding compound, dimensions of the die, thickness ofthe molding compound under the die, and the adhesion of thedie to the lead frame. Baking prior to soldering or the use ofporous encapsulants eliminates this problem.

Design for ReliabilityIn general, about the only reliability–improvement

measure available to electronic equipment level designers isto derate. As mentioned earlier, derating is a technique bywhich either the operational stresses acting on a device orstructure are reduced relative to rated strength, or thestrength is increased relative to allocated operating stresslevels. For example, manufacturers of rectifiers specifylimits for blocking voltage, forward current, powerdissipation, and junction temperature. The equipmentdesigner has the choice to select an alternative component,or make a change in the operating conditions (i.e., derate aspecific parameter, such as temperature, below the ratedlevel).

The derating factor, typically defined as the ratio of ratedlevel of a given “stress” parameter to its actual operatinglevel, is actually a margin of safety or a “margin ofignorance.” The amount of derating is determined by theimpact that a failure could cause, and by the amount ofuncertainty inherent in the reliability derating model and allits inputs. Ideally, this margin should be kept to theminimum required, so as to maintain the cost–effectivenessof the design. This puts the responsibility on the reliabilityengineer to identify, as unambiguously as possible, the ratedstrength, the relevant operating stresses, and the reliabilities.

Steady–state temperature has typically been assumed tobe the easiest parameter to derate. However, only a few ofthe failure mechanisms are strongly dependent onsteady–state temperature in the range of operatingtemperatures between –55C to 150C, and the use of theArrhenius temperature equation as a generic relationship ismisleading.



Examinations of case histories indicate that temperature’srelationship to reliability may be more a case of exposingincompatibilities between operational requirements anddesign or manufacturing processes. In other words, theproduct as designed is not suitable for operation in thedesired environment without changes. In such cases certainquestions must be addressed before taking action:• Will lowered temperature by itself avoid the

experienced failures? If so, how much should it belowered and how is the conclusion reached?

• Will higher temperature by itself accelerate theexperienced failures? If so, how much should it beraised and how is the conclusion reached?

• Will lowering the magnitude of temperature changeavoid the experienced failures? If so, how much shouldit be lowered and how is the conclusion reached?Each action has its own costs, and the designer or user

must fully understand the implications of each to producecost–effective, reliable equipment. Often, temperature isjudged to be the culprit, and blaming temperature may shiftemphasis away from actual design or manufacturinginadequacies. In some cases where temperature may beidentified as an important ingredient in the explanation forunreliability, the product as designed is not suitable foroperation in the desired environment without beingchanged.

To be effective, derating criteria must target the rightstress variables to address a given failure mechanism,clearly specify the inputs to failure models, and recommendtests to measure the parameters accurately. Physics of failureconcepts can serve to relate allowable operating stresses todesign strengths, through quantitative modeling of therelevant failure mechanisms. Field measurements may alsobe used, in conjunction with modeling simulations, toidentify the actual operating stresses at the failure site. Oncethe failure models have been quantified, the impact ofderating on the effective reliability of the component for agiven load can be determined. Quantitative correlationsbetween derating and reliability enable designers and usersto tailor the margin of safety more effectively to the level ofcriticality of the component, leading to better and morecost–effective utilization of the functional capacity of thecomponent.

Reliability TestingThe following summary gives a brief description of the

various reliability tests. These tests are commonlyperformed by manufacturers to ensure that a product isproperly designed and assembled. Quality products do notfail in the field from these environmental conditions. Not allof the tests listed are performed by each product group, andother tests not described are sometimes performed whenappropriate. In addition, some form of preconditioning maybe used in conjunction with the following tests.

High–Temperature Operating LifeHigh–temperature operating life testing is performed to

accelerate failure mechanisms that are thermally activatedthrough the application of extreme temperatures at biasedoperating conditions. The temperature and voltageconditions used will vary with the product being stressed.All devices used in the test are sampled directly after finalelectrical test with no prior burn–in or other prescreeningunless called out in the normal production flow. Testing caneither be performed with dynamic signals applied to thedevice or in static bias configuration. Common failuremodes include parametric shifts and catastrophic events.Common failure mechanisms include foreign material,crack and bulk die defects, metallization, and wire and diebond defects.

Temperature CycleTemperature cycle testing accelerates the effects of

thermal expansion mismatch among the differentcomponents within a specific die and packaging system.During temperature cycle testing, devices are inserted intoa cycling system and held at the cold dwell temperature longenough to incorporate thermal stabilization and appropriatecreep and stress relaxation of the materials. Following thiscold dwell, the devices are heated to the hot dwell where theyremain for another minimum time period. The systememploys a circulating air environment to assure rapidstabilization at the specified temperature. The dwell at eachextreme, plus the two transition times, constitute one cycle.Test duration for this test varies with device and packagingsystem employed. Typical test duration is for 1000 cycles,with some tests extended to look for longer–term effects.Common failure modes include parametric shifts andcatastrophic events. Common failure mechanisms includewire bond, cracked or lifted die, and package failure.

Thermal ShockThe objective of thermal shock testing is similar to that for

temperature cycle testing. However, thermal shock providesadditional stress in that the device is exposed to a suddenchange in temperature due to the rapid transfer time. Failuremechanisms caused by temperature transients andtemperature gradients can be detected with this test. Devicesare typically placed in a fluorocarbon bath and cooled to aminimum specified temperature. After being held in the coldchamber for some minimum period of time, the devices aretransferred to an adjacent chamber filled with fluorocarbonat the maximum specified temperature. Test duration isnormally for 1000 cycles with some tests being extended tolook for longer–term effects. Common failure modesinclude parametric shifts and catastrophic events. Commonfailure mechanisms include wire bond, cracked or lifted die,and package failure.



Temperature/Humidity Bias (THB)Temperature/humidity bias (THB) is an environmental

test designed to measure the corrosion/moisture resistanceof plastic encapsulated circuits. A nominal reverse bias isapplied to the device to create the electrolytic cells necessaryto accelerate corrosion of the metallization or bond padswithout heating the device. Most groups are tested to 1000hours with some groups extended beyond to look for longerterm effects. A typical test condition is: TA = 85C to 95C,rh = 85% to 95%, and bias = 80% to 100% of the maximumrating. Common failure modes include parametric shifts,high leakage, and catastrophic. Common failuremechanisms include die corrosion or contaminants such asforeign material on or within the package materials, andpoor package sealing. The purpose of themoisture–resistance test is to evaluate the moistureresistance of components under temperature/humidityconditions typical of tropical environments. A typical testcondition is: TA = –10C to 65C, and rh = 80% to 98%.Common failure modes include parametric shifts in leakageand mechanical failure. Common failure mechanismsinclude corrosion or contaminants on or within the packagematerials, and poor package sealing.

AutoclaveAutoclave is an environmental test that measures device

resistance to moisture penetration and the resultant effects ofgalvanic corrosion. Conditions often employed during thetest include 121C, 100% relative humidity, and 15 psig.Corrosion of the die is the expected failure mechanism.Autoclave is a highly accelerated and destructive test. Thistest may be followed by other tests to further accelerate thecorrosion failure mechanism. Common failure modesinclude parametric shift, high leakage, and catastrophicevent. Common failure mechanisms include die corrosion,contaminants such as foreign material on or within thepackage materials, or poor package sealing.

Pressure/Temperature/Humidity Bias (PTHB)This test is performed to accelerate the effects of moisture

penetration with the dominant effect being corrosion. Thistest detects similar failure mechanisms as THB but at agreatly accelerated rate. Conditions usually employedduring this test are a temperature of 125C or greater,pressure of 15 psig or greater, humidity of 100%, and a biaslevel. The purpose of the moisture resistance test is toevaluate the moisture resistance of components undertemperature/humidity conditions typical of tropicalenvironments. A typical test condition is: TA = –10C to65C, and rh = 80% to 98%. Common failure modes includeparametric shifts in leakage and mechanical failure.Common failure mechanisms include corrosion or

contaminants on or within the package materials, and poorpackage sealing.

Cycled Temperature Humidity BiasThis test is used to examine the ability of devices to

withstand the combined effects of temperature cycling, highhumidity, and voltage. This test differs from a typicalhumidity test in its use of temperature cycling.

Power Temperature CyclingThis test is performed on semiconductor devices to

determine the effects of alternate exposures to extremes ofhigh and low temperature with operating voltagesperiodically applied and removed. This is more of aperformance assessment than a reliability test. Test durationis normally for 1000 cycles with some tests being extendedto look for longer–term effects. Common failure modesinclude parametric shifts and catastrophic events. Commonfailure mechanisms include wire bond, cracked or lifted die,and package failure.

Power CyclingThis test is performed at a constant ambient temperature

with operating voltage(s) periodically applied and removed,producing a high operating junction temperature typicallybetween 50C and 150C above ambient.

Low–Temperature Operating LifeThis test is performed primarily to accelerate hot carrier

injection effects in semiconductor devices by exposing themto room ambient or colder temperatures with the use ofbiased operating conditions. Threshold shifts or parametricchanges are typically the basis for failure. The length of thistest varies with temperature and bias conditions employed.

Mechanical ShockThis test is used to examine the ability of the device to

withstand a sudden change in mechanical stress, typicallydue to abrupt changes in motion as seen in handling,transportation, or actual use. A typical test condition is:acceleration = 1500 g; orientation = Yl plane; t = 0.5 ms, andnumber of pulses = 5. Common failure modes include open,short, excessive leakage, and mechanical failure. Commonfailure mechanisms include die and wire bonds, cracked die,and package defects.

Constant AccelerationThis test is used to indicate structural or mechanical

weaknesses in a device/packaging system by applying asevere mechanical stress. A typical test condition used is:stress level = 30 kg. Common failure modes includemechanical failure. Common failure mechanisms includepoor package design.



Solder HeatThis test is used to examine the device’s ability to

withstand the temperatures seen in soldering over a moreextended period as compared to the typical exposure levelsseen in a production process. Electrical testing is theendpoint criterion for this stress. Common failure modesinclude parameter shifts, and mechanical failure. Commonfailure mechanisms include poor package design.

Lead IntegrityThis test is used to examine the mechanical properties of

a device’s leads, welds, and seals. Various conditions can beemployed and provided for: tensile loading, bendingstresses, torque or twist, and peel stress. The failure isdetermined visually under 3x to l0x magnification.

SolderabilityThe purpose of this test is to measure the ability of device

leads/terminals to be soldered after an extended period ofstorage (shelf life). Common failure modes include pinholes, dewetting, and nonwetting. Common failuremechanisms include poor plating and contaminated leads.

Variable Frequency VibrationThis test is used to examine the ability of the device to

withstand deterioration due to mechanical resonance. Atypical test condition is: peak acceleration = 20 g; frequencyrange = 20 Hz to 20 KHz. Common failure modes includeopen, short, excessive leakage, and mechanical failure.Common failure mechanisms include die and wire bonds,cracked die, and package defects.

Statistical Process ControlInitial design improvement is one method that can be used

to produce a superior product. Equally important tooutgoing product quality is the ability to produce productsthat consistently conform to specifications. Processvariability is the basic enemy of semiconductormanufacturing, since it leads to product variability.Statistical process control (SPC) replaces variability withpredictability. Use of SPC methods assures the product willmeet specific process requirements throughout themanufacturing cycle. The emphasis is on defect prevention,not detection. Predictability through SPC methods requiresthe manufacturing culture to focus on constant andpermanent improvements.

Circuit performance is often dependent on the cumulativeeffect of component variability. Tightly controlledcomponent distributions give the customer greater circuitpredictability. These programs require improvements incycle time and yield predictability achievable only throughSPC techniques. The benefit derived from SPC helps themanufacturer meet the customer’s expectations of higherquality and lower cost product.

Capability of 6σ means parametric distributions will becentered within the specification limits with a productdistribution of ±6 σ about the mean. This capability, showngraphically in Figure 196, details the benefits in terms ofyield and outgoing quality levels. This compares a centereddistribution versus a 1.5 σ worst–case distribution shift.

To better understand SPC principles, brief explanationshave been provided. These cover process capability,implementation, and use.

Figure 196. AOQL and Yield from a Normal Distribution of Product with 6 Capability

–6σ –5σ –4σ –3σ –2σ –1σ 0 1σ 2σ 3σ 4σ 5σ 6σ

Distribution CenteredAt ±3 σ 2700 ppm defective

99.73% yieldAt ±4 σ 63 ppm defective

99.98937% yieldAt ±5 σ 0.57 ppm defective

99.999943% yieldAt ±6 σ 0.002 ppm defective

99.9999998% yield

Standard Deviations From Mean

Distribution Shifted 1.566810 ppm defective93.32% yield6210 ppm defective99.379% yield233 ppm defective99.9767% yield3.4 ppm defective99.99966% yield



Process CapabilityOne goal of SPC is to ensure a process is capable. Process

capability is the measurement of a process to produceproducts consistently to specification requirement. Thepurpose of a process capability study is to separate theinherent random variability from assignable causes. Oncecompleted, steps are taken to identify and eliminate the mostsignificant assignable causes. Random variability isgenerally present in the system and does not fluctuate.Sometimes, these are considered basic limitations

associated with the machinery, materials, personnel skills,or manufacturing methods. Assignable–causeinconsistencies relate to time variations in yield,performance, or reliability.

Traditionally, assignable causes appear to be random dueto the lack of close examination or analysis. Figure 197shows the impact on predictability that assignable cause canhave. Figure 198 shows the difference between processcontrol and process capability.

Figure 197. Impact of Assignable Causes on Process Predictability

Figure 198. Difference Between Process Control and Process Capability

SIZE

Process “under control” – all assignable causes areremoved and future distribution is predictable.

SIZE

TIME

TIME

PREDICTION

? ?

??

? ?

????

SIZETIME

Lower UpperSpecification Limit Specification LimitIn control and capable(variation from random

variability reduced)

SIZE

TIME

Out of control(assigned causes present)

In control (assignablecauses eliminated)

In control but not capable(variation from randomvariability excessive)



A process capability study involves taking periodicsamples from the process under controlled conditions. Theperformance characteristics of these samples are chartedagainst time. In time, assignable causes can be identified andengineered out. Careful documentation of the process is keyto accurate diagnosis and successful removal of theassignable causes. Sometimes, the assignable causes willremain unclear, requiring prolonged experimentation.

Elements which measure process variation control andcapability are Cp and Cpk, respectively. Cp is thespecification width divided by the process width orCp = (specification width) 16 σ. Cpk is the absolute value ofthe closest specification value to the mean, minus the mean(X), divided by half the process width or Cpk = (closestspecification) – X /3 σ.

For critical parameters, the process capability is typicallyacceptable with a Cpk = 1.33. The desired process capabilityis a Cpk = 2 and the ideal is a Cpk = 5. Cpk, by definition,shows where the current production process fits withrelationship to the specification limits. Off–centerdistributions or excessive process variability will result inless than optimum conditions.

SPC Implementation and UseSome parameters are sensitive to process variations while

others remain constant for a given product line. Often,specific parameters are influenced when changes to otherparameters occur. It is both impractical and unnecessary tomonitor all parameters using SPC methods. Only criticalparameters that are sensitive to process variability arechosen for SPC monitoring. The process steps affectingthese critical parameters must be also identified. It is equallyimportant to find a measurement in these process steps thatcorrelates with product performance. This is called a criticalprocess parameter.

Once the critical process parameters are selected, asample plan must be determined. The samples used formeasurement are organized into rational subgroups ofapproximately two to five pieces. The subgroup size shouldbe such that variation among the samples within the

subgroup remains small. All samples must come from thesame source (for example, the same mold press operator,etc.). Subgroup data should be collected at appropriate timeintervals to detect variations in the process. As the processbegins to show improved stability, the interval may beincreased. The data collected must be carefully documentedand maintained for later correlation. Examples of commondocumentation entries would include operator, machine,time, settings, and product type.

Once the plan is established, data collection may begin.The data collected will generate X and R values that areplotted with respect to time. X refers to the mean of thevalues within a given subgroup, while R is the range orgreatest value minus least value. When approximately 20 ormore X and R values have been generated, the average ofthese values is computed. The values of X and R are used tocreate the process control chart. Control charts are theprimary SPC tool used to signal a problem.

Once the variability is identified, the cause of thevariability must be determined. Normally, only a few factorshave a significant impact on the total variability of theprocess. Most techniques may be employed to identify theprimary assignable cause(s). Out–of–control conditionsmay be correlated to documented process changes. Theproduct may be analyzed in detail using best– versusworst–part comparisons or product analysis lab equipment.Multivariance analysis can be used to determine the familyof variation (positional, critical, or temporal). Lastly,experiments may be run to test theoretical or factorialanalysis. Whatever method is used, assignable causes mustbe identified and eliminated in the most expeditious mannerpossible.

After assignable causes have been eliminated, newcontrol limits are calculated to provide a more challengingvariability criteria for the process. As yields and variabilityimprove, it may become more difficult to detectimprovements because they become much smaller. When allassignable causes have been eliminated and the pointsremain within control limits, the process is said to be in astate of control.



Chapter 13

Cooling Principles



In many high current rectifier diode applications, thelosses are large enough that a heat exchanger is required inorder to prevent the junction temperature from exceeding itsrated limit and running the risk of failure. This chapterprovides background information for a designer toinvestigate the thermal management considerations forrectifiers. Design charts and discussions of basic principlesare presented. The focus is on the thermal analysis of heatexchangers. However, tradeoffs involving deviceperformance and reliability, the environmental usageconditions, the accessibility to a coolant, and cost must alsobe considered as part of the design process.

Thermal Resistance ConceptsHeat is transferred by conduction (heat travels through a

material), convection (heat is transferred by physical motionof a fluid), and radiation (heat is transferred byelectromagnetic wave propagation). Semiconductorsdepend on conduction as a means of transferring heat fromthe device junction to the external surface of the package.Heat transfer from the package to the external environmentdepends on the method of interconnection of the package(i.e., leaded or leadless connection to a heat exchanger orprinted wiring board) and the dominant mode of heattransfer (i.e., convection typically dominates when forcedair or liquid cooling is used, while radiation may dominatein vacuum or high altitude applications).

The basic equation for heat transfer is:

q hAT (13.1)

where q = rate of heat transfer (W),

h = heat transfer coefficient or thermaltransmittance (W/in2/C),

A = cross–sectional area normal to the path of heatflow (in2),

∆T = temperature difference between regions ofheat transfer (C).

Electrical engineers find it easier to work in terms ofthermal resistance. From Equation 13.1, die thermalresistance Rθ is:

RTq

1hA (13.2)

where the coefficient h depends upon the heat transfermechanism.

When determining cooling capability, it is simpler to useh rather than R because cooling due to convection andradiation may be handled as two thermal paths in parallel.

An analogy between Equation 13.2 and Ohm’s Law isoften made to form models of heat flow. Note that ∆T couldbe thought of as a voltage, thermal resistance corresponds toelectrical resistance (R), and power (q) is analogous tocurrent (T). This gives rise to the basic thermal resistancemodel for a semiconductor mounted to a heatsink indicated

by Figure 199. Although a case–mounted part is shown, themodel is generally applicable. For leadlesssurface–mounted parts, the dominant path for heat transferis through the package case. With lead–mounted rectifiers,most of the heat leaves the junction via conduction throughthe leads. Thermal models for lead–mounted parts arediscussed in Chapter 2.

The equivalent electrical circuit may be analyzed usingKirchoff’s Law and the following equation results:

TJ PD (RJC RCS RSA) TA (13.3)

where RθJA = total thermal resistance junction toambient (RθJA + RθCS + RθSA)

RθJC = semiconductor thermal resistance(junction to case),

RθCS = interface thermal resistance (case toheatsink),

RθSA = heatsink thermal resistance (heatsink toambient).

With rectifiers having significant reverse power losses,junction–to–ambient thermal resistance must be consideredearly in the design. The thermal characteristics of thesemiconductor are described in Chapter 2.

The interface case–to–sink thermal resistance (RθCS)resulting from imperfect mating surfaces and use ofinsulators may be appreciable in high–current applications.Factors involved in minimizing RθCS are discussed in thenext chapter.

This chapter is devoted to explaining the variablesaffecting the heatsink to ambient thermal resistance RθSA. Itis assumed that the design problem has been reduced to onewhere the total power dissipation of the rectifier and therequired heatsink temperature limit are known. Knowing theupper ambient temperature permits Equation 13.3 to besolved for the limit RθSA.

The thermal resistance of the heat exchanger, or heatsink,is an important part of the thermal design, especially forstud– or base–mounted rectifiers. Heatsinks may transferheat to the ambient by natural convection and radiation, orforced air or liquid cooling may be employed. As a roughapproximation for silicon rectifiers, for dissipating powerlevels over 100 W, forced air cooling tends to be mosteconomical in terms of space and cost; for power levels over2000 W, liquid cooling is typically required. Schottkyrectifiers, because of their lower maximum junctiontemperature limit, may require forced air or liquid coolingat lower power levels. However, the current levels areroughly the same because of the lower forward voltage of theSchottky diode. In terms of thermal resistance, values as lowas 1C/W can be achieved with large volume freeconvection heatsinks. Use of air flow can produce values aslow as 0.05C/W, while use of liquid cooling can closelyapproximate the infinite heatsink.



ÇÇÇÇÇÇ

ÉÉÉÉ

Figure 199. Basic Thermal Resistance Model Showing Thermal to Electrical Analogyfor a Semiconductor

ÉÉÍÍÍÍ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

Temperature Reference

Solder TerminalNut

Heat Sink

Mica Insulators

Flat Washer

Die

TJ, Junction Temperature

TC, Case Temperature

TS, Heat SinkTemperature

TA, AmbientTemperature

RJC

RCS

RSA

PD

In the following sections, factors of importance in naturalconvection cooling, forced–air cooling, and liquid coolingare discussed. The intent is to acquaint the electricalengineer with the basic principles involved. Reference [1]provides a place to begin further study and has an extensivelist of references.

ConductionConduction is a process of heat transfer in which heat

energy is passed from one molecule to the next, while theactual molecules involved in the transfer remain in theiroriginal positions. In an opaque solid, heat conduction is theonly means of heat transfer, where heat flows from the hotto the colder areas of the solid. Conduction can occur inliquids and gases, but the amount of heat transferred isgenerally smaller for the same geometry.

The thermal resistance attributed to conduction, Rθ (cond),is often modeled in terms of the one–dimensional equation:

R(cond) XkA (13.4)

where Rθ (cond) = thermal resistance (C/W),

X = length of thermal path (in),

kθ = thermal conductivity (W/inC),

A = area normal to the thermal path (in2).(The heat transfer coefficient h is kθ/X.) The coefficient

of thermal conductivity is a material property, which canrange over five orders of magnitude. Thermal conductivityfor a number of materials used in electronics is given inTable 26.

Heatsink design often involves cost–effectivelyminimizing conduction resistance. In large area plates,conduction resistance may be significant and may play a keypart in determining a design in which the volume and weightof the heatsink must also be minimized.

ConvectionConvection is the transfer of heat by the physical motion

or mixing action of a fluid, such as air or water. When themovement is due entirely to temperature differences within

the fluid, which results in differences in density, themechanism is called natural convection. Note that in agravity field, heated air expands, becomes less dense andtherefore lighter than the surrounding air, and rises. This inturn creates the “natural” movement of air. When the motionof the fluid is produced by mechanical methods, such as fansand pumps, the mechanism is called forced convection.

Table 26. Thermal Conductivity of VariousMaterials at 27C

MaterialsConductivity

W/in–C

Silver 10.7

Copper 9.75

Gold 7.86

Aluminum, pure 5.75

Beryllia, 99.5% pure 6.20

Aluminum, 68S 5.34

Beryllia, 95% 4.13

Magnesium 4.16

Aluminum 6061–T6 4.13

Red brass 2.92

Yellow brass 2.51

Beryllium cooper 2.19

Pure iron 1.99

Phosphor bronze 1.36

Soft steel 1.23

Monel 0.94

Hard steel 0.58

Thermal compound 0.018

Mica 0.015

Mylar film 0.0042

Air 0.00083



Natural ConvectionThe following equation applies for the natural convection

of vertical plates (heatsink) suspended in free air at groundlevel:

hc 2.21 103TS TAL0.25

(13.5)

where hc = convection heat transfer coefficient(W/in2C),

L = height of the heatsink (in),

TS = surface temperature of the heatsink (C).

Figure 200 is a plot of Equation 13.5. The average naturalconvection coefficient hc defines the thermal characteristicsof the air film that encapsulates the plate. The constant is afunction of air density, temperature of ambient air in contactwith the plate, and orientation and shape of the heatsink. Thevalue of 2.21 x l0–3 applies for standard pressure andtemperature at sea level for rectangular plates suspendedfreely in still air. For other conditions, the “constant” mustbe altered [2].

Air density is a significant factor in convection cooling.Since density varies with altitude, a correction factor isindicated on Figure 201. Note that a 10% loss ineffectiveness occurs at about 5000 ft. In space, convectionis zero. Values for hc must be multiplied by the numberobtained from Figure 201 to obtain the proper value.

Plate shape and orientation also affect convection cooling.Table 27 indicates procedures for obtaining the significant

dimension L and a correction factor Fc for rectangular,circular, and cylindrical surfaces in either a horizontal orvertical position. For horizontal mounting, the sum of theconvection thermal transmittance from the top and bottomsurfaces must be found. When both surfaces are exposed toair, the overall thermal resistance is about 25% higher thanwould be the case of a vertical plate of the same significantdimension L. For an enclosed chassis, the contribution of thebottom surface of the upper plate is negligible.

As an example of the use of the data, the convectionthermal resistance of a 4 in. x 6 in. plate will be found (totalsurface area = 4 x 6 x 2 = 48 in2). Assume the surfacetemperature is 120°C and the ambient is 60°C. For mountingwith the 4 in. side in a vertical plane (the most efficientmounting), read hc = 4.4 x 103 W/in2°C from Figure 200.Using Equation 13.2, Rθ(conv) = 1/(4.4)(10–3)(48) =4.74°C/W. If the plate were mounted with the 6 in. side in avertical plane, hc = 4 x 10–3 W/in2°C resulting in a 10%increase in Rθ(conv).

For horizontal mounting, a new value of L must be foundfrom the relations in Table 27. Dimension L calculates to be2.4 in. resulting in hc = 5 x l0–3 W/in2°C at TS–TA = 60°C.The area of each side is 24 in2. Using the correction factorsgiven in Table 27, hc(top) = (0.9)(5) 10–3 = 4.5 x 10–3 Thecontribution of the bottom surface, if it is exposed, is0.45(5)10–3 = 2.25 x l0–3 W/in2°C. The total value ofRθ(conv) = 1/(4.5 + 2.25)(10–3)(24) = 6.15°C/W. Thus, thehorizontal mounting result is about 30% worse than the mostfavorable vertical position.

Figure 200. Free Convection Coefficient forRectangular Plates of Various Heights, L

10 20 30 50 70 100 200

9.010

8.0

6.0

5.0

4.0

3.0

2.0

7.0

TS – TA , Fin Temperature Rise (°C)

T∆ = 60°C

L = 1”

2”

4”

10”

h c, C

onve

ctio

n C

oeffi

cien

t W

/in2

– °C

) x

(10–

3 )

Figure 201. Altitude Correction Factor for FreeConvection Heat Transfer

0 20 40 60 80 100

0.7

0.5

0.3

0.2

0.1

1.0

Altitude in 1,000 Feet

Cor

rect

ion

Fac

tor

Table 27. Significant Dimension L and Correction Factor Fc for Convection Thermal Resistance

Significant Dimension L Correction Factor Fc

Surface Position L Position Fc

Rectangular Plane Vertical Height (max 2 ft) Vertical Plane 1.0g

Horizontal Length x Width/(Length + Width) Horizontal Plane, facing downward 0.45

Circular Plane Vertical /1 x Diameter Horizontal Plane, facing upward 0.9

Cylinder Horizontal Diameter Horizontal 0.82y

Vertical Height (max 2 ft) Vertical 0.9



Forced ConvectionIn forced convection a fluid is moved by or through the

heatsink by an external source, such as a fan or a pump.Because the fluid flow rate may be quite high, forcedconvection is capable of reducing the heatsink thermalresistance to extremely low values.

Forced–air convection produces a drastic reduction inthermal resistance of any heatsink as compared to naturalconvection due to a “scouring” effect upon the insulatingboundary layer of dead air at the fin surface. Naturalconvection cooling is primarily dependent upon the volumeand material of the heatsink, while forced convectioncooling can be related to the airflow, fin spacing, and thedegree of coupling to the air stream.

The heat transfer coefficient for the usual case of turbulentair flow parallel to a plate may be expressed as:

hf 6.63 103 (V3L)0.25 (13.6)

where hf = forced convection heat transfer coefficient(W/in2 – C),

V = free stream velocity (linear feet per minute),

L = length of the plate (in).The constant is affected by air density and temperature.

The value given is based upon operation at sea level at anaverage air temperature over the heat exchanger of 600°C.As a design aid, values have been calculated from Equation13.6 and are plotted in Figure 202. Note that a shortdimension in the flow direction increases the coefficientsignificantly. The curves stop at points where the flow isbecoming laminar and consequently Equation 13.6 does notapply. In the laminar region, hf is higher than anextrapolation of the curves would indicate. Note thatEquation 13.6 should not be used for plates with L less than4 in., as the flow is laminar when it first encounters the plate.Short plates do not permit development of turbulent flow.

As an example, the forced convection thermal resistancewill be found for the 4 in. x 6 in. plate (surface area = 48 in2)used in the previous example. Assume that the 4 in. side isparallel to the flow direction and the air flow rate is 2000LFM. Reading from Figure 202, hf ≈ 1.4 W/in2°C.Therefore, Rθ = 1/(l/4)(48) = 0.015°C/W. This value is about300 times better than that obtained with natural convection.However, improvements this large are not achieved inpractice because of material thermal resistance losses.

0.8

0.6

0.4

0.2

0

1.0

0 400 800 1200 1600 2000 2400 28

1.2

1.4

1.6

TA = 60°C

L = 4”

6”

10”

20”

Figure 202. Heat Transfer Coefficient forForced Air Convection

V, Air Velocity (LFM)

h f, F

orce

d C

onve

ctio

n C

oeffi

cien

t (W

/in2

– °C

)

Water or liquid cooling is similar in principle to that offorced air. The heat transfer coefficient is related to velocityin a manner similar to that described by Equation 13.6.Normally, the liquid cooled system is purchased as a unitwhose characteristics are provided by the manufacturer.

RadiationThe third process by which heat can be transferred is

radiation. The ability of a body to radiate thermal energy atany particular wavelength is determined by the bodytemperature and surface characteristics. An ideal radiator iscalled a blackbody which, by definition, radiates themaximum amount of energy at any wavelength. The ratio ofenergy emitted by any surface to that of a blackbody at thesame temperature is called the emissivity .

Incident radiation on a surface is partially absorbed,reflected, and, in some cases, transmitted through thesurface. However, materials used for heatsinks are opaqueand do not transmit radiation. The ability of a surface toabsorb the total incident radiation on it is defined by the termabsorptivity a. As with the emissivity, the absorptivity of asurface is dependent upon the source temperature (i.e.,wavelength of incident radiation) and the receiving bodysurface characteristics.

Many materials exhibit the property of having a = e whenthe absorber and the emitter are at temperatures within500°C of each other. These materials are called gray bodiesand emissivity values for some common materials are listedin Table 28.



The basic equation for the thermal transmittance or heattransfer coefficient when radiation is taking place betweentwo gray bodies is:

hr 3.68 103 TS1004 TA

1004(TS TA)

(13.7)

Table 28. Typical Emissivities of Common Surfacesat 25CÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

SurfaceÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

EmissivityÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Aluminum, AnodizedÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.7–0.9ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Alodine on AluminumÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.15ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Aluminum, PolishedÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


Copper, PolishedÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


Copper, OxidizedÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


Rolled Sheet SteelÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


Air Drying EnamelÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


Oil PaintsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


VarnishÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.89–0.93

where hr = radiation heat transfer coefficient (W/in2°C)ε = emissivity,TS= surface temperature (°K),TA = ambient temperature (°K).

As with convection, the thermal resistance is inverselyproportional to area. Since temperature affects the results ina complex manner, Equation 13.7 is plotted in Figure 203 interms of 0°C. The strong effect of temperature upon theradiation coefficient is apparent. As with convection, a largetemperature drop can occur in large area plates due toresistance losses, whereby the extremities of the heatsink arenot as effective as the center.

If radiation is obstructed by nearby objects, the “constant”in Equation 13.7 will need to be modified by a factor (fr)which is smaller than unity. If the object is at the sametemperature as the fin, an adjustment can be made byconsidering the geometry of the radiation pattern. It isgenerally satisfactory to consider an unobstructed fin’sradiation as originating at the center of the fin and beingspherical (hemispherical on each side of the fin). Anobstruction will interrupt radiation, or subtract a sector fromthe sphere; fr is approximately the ratio of the solid angleremaining in the obstructed sphere to the solid angle (4 πsteradians) of the complete sphere.

The fin should be shielded from bodies of highertemperature. Otherwise, the fin will be heated by radiationinstead of being cooled.

Figure 203. Radiation Coefficient for a Black Bodyhaving an Unobstructed Pattern

10 30 50 70 100 200

0.80.7

0.6

0.5

0.4

0.9

20

1.0

1.5

2.0

TA = 100°C

75°C

50°C

25°C

TS – TA, Temperature Rise of Plate (°C)

h r, R

adia

tion

Coe

ffici

ent (

Wat

ts/in

2 –

°C)

x 10

–2

Equation 13.7 also assumes that the radiating body issmall compared to the enclosing body. Other configurationsrequire a modification of the emissivity value. For the caseof two large parallel plates or for the case where the enclosedbody is large compared to the enclosing body, the effectiveemissivity ef is given by:

f1

11 1

2 1

(13.8)

where: ε1 and ε2 are the emissivities of the two surfaces.Other situations require an in–depth analysis of the problem.

As an example of the use of the data for radiation thermalresistance, R(rad) for the 4 in. x 6 in. plate previously usedwill be found. From Figure 203, at TA = 60°C and TS =120°C, ht = 0.7 x 102 W/in2°C. If the plate were painted(preferably black), ε = 0.9 and Rθ(rad) =1/(0.9)(0.7)(10–2)(48) = 3.3°C/W. This value is less than theconvection value because of the high emissivity and highsurface temperature allowed.

Surface emissivity is unimportant when forced air orliquid cooling is used, because the effect of radiation isnegligible. However, for natural convection cooling,radiation plays a significant roll and surfaces having highemissivity should be used. As Table 28 shows, polishedsurfaces should be avoided and anodized aluminum andpainted surfaces are preferable. Tests on natural convectionheatsinks which are made commercially reveal a decrease intotal thermal resistance of approximately 25% at highambient temperatures when a dull black finish is used asopposed to a bright mill finish.



Fin EfficiencyBecause of resistance losses in the fin material, both

conduct on and radiation cooling efficiencies decrease withdistance from the heat source. Fin efficiency is defined as theratio of total heat dissipated by an identically shaped fin ofinfinitely conducting material under the same conditions.Knowing the efficiency, (η). the fin dissipation, (q), may becalculated from:

q Aht (ts tA) (13.9)

where A = fin surface area,

ht = the total heat transfer coefficient,

TS = the temperature of the heatsink at the heatsource,

TA= the temperature of the ambient.

Similarly the fin thermal resistance Rθ is:

RSA1

Aht(13.10)

If fins are made of relatively thick, highly conductivematerial, fin efficiency is close to 100% and the total finthermal conductance is the sum of the convection andradiation components. At the other extreme, if the fin is quitethin and/or the material has low conductivity, the finextremities are ineffective because of high resistance losses.

Both extremes are wasteful of material and costly but thelatter extreme is encountered when a chassis or otherstructure is used as a cooling fin for semiconductors. Therange between these extremes is rather narrow.

The analysis of fin efficiency is more manageable whenperformed using a circular fin, and when heat transfer bymeans of convection and radiation from the fin edge isneglected. The more commonly used geometries arehandled by converting their dimension to an equivalent

radius using the formulas in Table 29. The fin thickness (S)is generally a negligible factor in the equivalent radius.

An important factor in fin efficiency is the heat inputradius, ri. Figure 204 shows how it is found for the popularstud and diamond base packages. It is essentially the averagevalue of the dimensions of the heat input source.

By analyzing the temperature drop and heat dissipated bya volume element in an annular ring, a parameter isdiscovered which is a characteristic of the material and theheat transfer coefficient. This parameter, which plays animportant role in fin efficiency, is called the “natural radius”of the fin (R) and is given by:

R kS2ht (13.11)

where kθ = the thermal conductivity of the fin material,

S = fin thickness

ht = total heat transfer coefficient of the fin.For convenience in problem solving, Equation 13.11 is

plotted in Figure 205 for 63S aluminum plates of standardthickness. Since the term kθS is a constant for any one of thecurves of Figure 205, the data may be used for heatsinks ofother material by considering the thermal conductivity dataof Table 26. For example, since copper has almost twice theconductivity of 63S aluminum, a copper plate of 1/32 in. hasthe same relationship of ht to S as does a 1/16 in. aluminumplate.

Further analysis yields the equations necessary to plotFigure 206 and the fact that an optimum fin design isachieved when the fin efficiency is 50%. An optimum fin istaken as one which has minimum volume and thereforeminimum material which generally results in minimum cost.For the optimum fin, the outer radius is approximately equalto the natural radius (when the fin outer radius is largecompared to the heat input radius).

Table 29. Equivalent Outer Radius (r0) for Various Fin Geometries

b2

+ 2bs a b + ( a + b) s d

21 +

2s

dπ

s

b a

b b

s

ds

(Satisfactory for b%2a)

π



ÉÉÉÉÍÍÍÍ

R, N

atur

al R

adiu

s (in

.)

0.005 0.01 0.02 0.03 0.05 0.07

7.0

5.0

3.0

2.0

1.00.007

10

ht, Total Heat Transfer Coefficient (W/in2°C)

Figure 204. Relation of Semiconductor Device Dimensions to Heat Input Radius ri

Figure 205. Effect of Fin Thickness and Heat Transfer Coefficient upon the NaturalRadius of Type 63S Aluminum Fins

ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÈÈÈÈ

Ë Ë

(a) Stud Packages

(b) Diamond Base Packages

D2

b

D h D b

D b

D h

D b

r i

ro

r i =+

=

S

0.1

1/4”

3/64”

1/8”

1/32”

3/32”S=1/16”

3/16”

To illustrate the use of the data, the efficiency of the 4 in.x 6 in. plate used in the previous examples will be discussed.Assume a DO–5 package is attached which has an effectiveheat input radius close to 0.22 in. The effective outer radiusr0 from Table 29 is 24/π (neglecting S) or 2.78 in. Therefore,r0/ri = 12.6. For an optimum fin (h = 50%) R/r0 12.6 from

Figure 206. Therefore R = 2.78 in. The fin thickness isdetermined from Equation 13.11 or Figure 205. From theprevious two examples, ht = (0.63 + 0.44) 10–2 = 0.0107.Therefore, S maybe less than 1/32 in. for an aluminum fin.Overall thermal resistance is found from Equation 13.10 andis 3.9°C/W for this example.



0.97

0.70

0.98

0.60

0.40

0.95

0.30

108.0

6.05.04.0

20

304050

1.0 2.0 3.0 5.0 8.010

i ,

20 30 40 50 80100

0.60.5

0.4

0.3

0.2

0.81.0

2.0

3.0

60

80100

R/r

Nat

ural

Fin

Rad

ius/

Hea

t Inp

ut R

adiu

s

ro/ri, Outer Fin Radius/Heat Input Radius

Figure 206. Fin Efficiency as a Function of R/ri and ro/ri

0.02

0.01

0.05

0.10

0.20

0.50

0.80

0.90’1 = 0.99

An improvement in fin efficiency or a reduction in fin sizefor a desired thermal resistance is achieved by increasing theradius of the heat source. In practice, this can be achieved bybrazing copper material to the heatsink. Suppose that 2 in.diameter discs are brazed to each side of the plate in theabove example and that the thermal resistance of the discsis negligible. Now r0/ri = 2.78 and R/ri = 2.78 also. FromFigure 206, the fin efficiency is increased to 80%. Theadvantage of a large highly conductive semiconductorpackage over a smaller one is thus also apparent.

Application and Characteristics ofHeatsinks

The material in this section provides general practicalinformation necessary to select and use heatsinks in free andforced convection. In most cases, a commercial heatsink isused in manufactured equipment. The most importantcharacteristics of heatsinks are specified by themanufacturer. By using the basic principles of heat transfer,the behavior of heatsinks under a variety of conditions maybe predicted. Furthermore, the data for Figures 201 through206 may be used to design single–fin heatsinks and to obtainthe thermal resistance of a metal chassis or a PCB.

Heatsinks for Free Convection CoolingHeatsinks can be grouped into three categories:

1. Flat vertical–finned types. Normally aluminumextrusions with or without an anodized blackfinish, they are unexcelled for natural convectioncooling and provide reasonable thermal resistanceat moderate air–flow rates for forced convection.

2. Cylindrical or radial vertical–finned types.Normally cast aluminum with an anodized blackfinish, they are used when maximum cooling inminimum lateral displacement is required.

3. Cylindrical horizontal–finned types. Normallyfabricated from sheet–metal rings with a paintedblack matte finish, they are used in confinedspaces for maximum cooling in minimum verticaldisplacement but are less efficient than the othertwo types.



The thermal resistance can be related fairly well to thesurface area and the volume of the heatsink as illustrated byFigures 207 and 208. The data of most interest is forheatsinks of categories 1 and 2; the category 3 types do notfit into a pattern and are of little interest for power rectifiers.The steady–state characteristics typical of a category 1heatsink are shown in Figure 209. The slope of the curvevaries from 3°C/W at low power levels to about 2°C/W athigh levels. The improvement in thermal resistance resultsfrom the convection and radiation components becomingmore effective as temperature increases. The transient

characteristics are shown in Figure 210. Note that thetemperature below 2 minutes is proportional to the squareroot of time, a characteristic of one dimensional heat flow.The time to reach equilibrium is dependent upon the mass ofthe heatsink and requires about 20 minutes. Therefore,patience is required when evaluating the overall steady statethermal behavior of a system. Note that at times much lessthan the time for thermal equilibrium, the effective thermalresistance can be quite low, which can be used to advantagewhen the power diode is used intermittently.

Figure 207. Relation of Surface Area to ThermalResistance for Categories of Commercial Aluminum

Heatsinks as Compared to an Aluminum Plate

RθSA, Heat Sink Thermal Resistance (°C/W)

1.0 2.0 5.0 10 20

100

50

20

10

Category 3Black CylindricalHorizontal Fins

Category 2Black CylindricalVertical Fins

Category 1Black FlatVertical Fins

Polished 1/8” Thick Square Plate

Figure 208. Relation of Volume to ThermalResistance for Categories of Aluminum

Heatsinks as Compared to an Aluminum Plate

1.0 2.0 3.0 5.0 7.0 10

20

10

5.0

2.0

1.0

50

100

Category 3Black CylindricalHorizontal Fins

Category 2Black CylindricalVertical Fins

Category 1Black FlatVertical Fins

Polished 1/8” Thick Square Plate

RθSA, Heat Sink Thermal Resistance (°C/W)

Sur

face

Are

a (in

2 )

Vol

ume

(in3 )

Figure 209. Typical Category 1 Heatsink NaturalCorrection Thermal Characteristics

0 2 4 6 8 10

40

30

20

10

0

50

60

12 14 16 18 20 22 24 26

PD, Power Dissipation (Watts)

C)

Abo

ve A

mbi

ent A

ir ( °

Figure 210. Thermal Response of Typical Category1 Heatsink

0.02 0.05 0.1 0.2 0.5 2.0

0.2

0.1

0.05

0.02

0.01

0.5

1.0

r(t)

, Tra

nsie

nt T

herm

al

t, Time (Minutes)

1.0 5.0 10 20

ZSA(t) = r(t) RSA

Impe

danc

e (N

orm

aliz

ed)

Fin Vertical in Free Air



Heatsinks for Forced Air CoolingA natural reaction, when a designer finds that a

semiconductor is running too hot when mounted to thelargest heatsink permissible in the system, is to add a fan orblower. Although results may seem satisfactory, a morecompact and less expensive cooling system generally resultsif a heat exchanger designed for use with forced air is used.Improvement in RθSA due to forced air is illustrated inFigure 211. The asymptotic behavior at high flow rates istypical of forced air cooling and indicates that the heatsinkis becoming conduction limited.

When forced air cooling is employed, an interlock isgenerally necessary to prevent catastrophic system failure inthe event of a blower malfunction. The use of an air–switch,comprised of a moving vane in the air flow mechanicallycoupled to a microswitch, can be used to interlock theelectrical system.

Figure 211. Performance Under Forced Airflow ofTypical Category 1 Natural Convection Heatsink

Air Flow (Lb/Min)

°T

herm

al R

esis

tanc

e (

C/W

att)

0 0.2 0.4 0.6 0.8 1.0

1.2

1.0

0.8

0.6

0.4

1.4

1.6

1.2

1.0 Lb Air/Min = 480’/MinVelocity Over Fins Through0.0322 Sq Ft Frontal Area AtNormal Pressure and 75°F(Air Density 0.065 Lbs/Cu Ft.)

The basic air flow rate equation is:

T 1.76 PDVA (13.12)

where ∆T = the change in air temperature (C),

PD = the power dissipation (W),

V = air velocity in linear feet per minute (LFM),

A = area of duct or chamber (ft2).

For example, if a flow rate of 500 LFM is required in a onesquare foot duct and the power to be dissipated is 1000 W,the air temperature will increase by 3.5°C. The product VAis the volume of air flow required in cubic feet per minute(CFM).

Most efficient use of a given air flow will be achieved bylocating components demanding minimum temperature rise(for example, semiconductors) closer to the inlet end of thecooling column and locating those elements for whichmaximum temperature rise is permitted (for example,power resistors) at the exhaust end.

Determination of the required air flow must also take intoaccount the location of the airmover (fan or blower). If theairmover is located at the intake, its own heat loss must beadded to the power which the system is required to dissipate.In this location, however, the ambient temperature which theblower experiences will be relatively low. At the exhaust, theairmover operates in a higher ambient temperature but itsown power loss does not raise the ambient air of theassembly and is, therefore, generally preferable.

Pressure DropAn important aspect of forced air cooling is that of

pressure drop. There is always a frictional resistance to fluidflow which is a function of geometry, velocity, andproperties of the fluid. The resistance causes a back pressure,often called pressure drop, ∆P.

For a passage of given geometry, pressure drop willincrease with the square of air flow. With constant air flow,changes in the geometry that either restrict area or interferewith flow will result in an increase in pressure drop.

Airmovers deliver a decreasing amount of airflow as theresistance to flow or pressure rise increases. Maximum flowoccurs at zero pressure rise and vice versa. Thus, for anairmoving system, a unique operational point is determinedby the combination of the pressure drop and flow ratecharacteristics of the airmover and the heat exchanger asillustrated in Figure 212.

Figure 212. System Operating Point. The OperationalPoint of a Cooling System of

Given Geometry and a Given Fan Occurs at theIntersection of the System’s Pressure Drop vs.

Air Flow, and of the Fan’s Pressure Rise vs. Air Flow

Operating Point

Heat

Fan

Air Flow

P, C

hang

e in

Pre

ssur

e

Exchanger



Except for long straight ducts and certain bends andtransition pieces, pressure drop is difficult or impossible tocalculate. It is generally simpler to mount any type ofairmover in the system and measure the resulting flow andpressure. Even if only one point is obtained, a systemcharacteristic or impedance curve may be derived byassuming the impedance curve is quadratic. Knowing theCFM required, the resulting pressure is read from theimpedance graph and an airmover meeting theserequirements may be selected.

Note that an increase in flow from 50 to 100 CFM on thecurve would increase the pressure requirements from 1.0 in.to 4.0 in., which is a large increase. At a certain point, if moreair is required, the designer is well advised to open airpassages in the system so that the impedance is lowered,rather than increasing the pressure capabilities of theairmover.

For a given flow rate and fixed volume, any change ingeometry that increases the heat transfer will increasepressure drop causing the operational point on Figure 212 tomove to the left. Therefore, for every system–and–fancombination, there is an optimum fin geometry. If volume iscritical, it is best to select a coder–fan combination from amanufacturer. Often, semiconductor manufacturers offerrectifier heatsink assemblies designed for forced air servicesuch as that shown in Figure 213.

Figure 213. A 650 A Rectifier for 3–Phase ServiceHaving Integral Heatsink Designed

for Forced Air Systems

Fan Laws1. Speed: The following fan laws express the manner

in which the various quantities, in any fixedsystem, vary with speed of the air moving devices:a. CEM varies directly with rpm,b.SP (static pressure) varies as the square of the rpm,c. HP (horsepower) varies as the cube of the rpm.

Note that if the impeller speed is doubled, the CFM isdoubled, the static pressure is multiplied by four and thehorsepower required is multiplied by eight.

2. Density: The performance rating of any impelleracting at a constant speed in a fixed system will bealtered by a change in air density in the followingmanner:a. CFM remains constant,b.SP varies directly with air density.

Density is as important as velocity in forced convectioncooling. Since density decreases with altitude, an airmoverwhich has just sufficient capacity at sea level is inadequateat 50,000 ft. In order to provide an airmover that willfunction efficiently at all altitudes, special slip motors areavailable which operate at higher speeds as the loaddecreases. Consequently, the motor maintains a constantmass flow rate in terms of pounds per minute, in spite of thechanges in density caused by altitude.

Liquid CoolingFor very high current requirements, liquid cooling is

required. Heat exchanger manufacturers’ catalogs should beconsulted for selections of suitable systems. The generalprinciples outlined under air cooling also apply for liquidcooling. That is, Equation 13.7 applies, the pressure drop,flow rate relationship is quadratic, and the fan laws alsoapply. Typical performance of a liquid cooled dissipator isshown in Figure 214.

Figure 214. Typical Performance of a Liquid CooledMounting Surface

0 0.1 0.2 0.3 0.4 0.5

80

60

40

20

0

100

0.6 0.7 0.8 0.9 1.0

8.0

6.0

4.0

2.0

0

10

Liquid Flow (Gallons per Minute, Water)

RCA

∆P

RC

A, T

herm

al R

esis

tanc

e (°

C/k

W)

P,

Pre

ssur

e D

rop

(PS

I)



Component PlacementTraditionally, placement techniques have focused on

improving routability based on minimizing the totalwirelength between interconnected components. However,electronic card assembly (ECA) reliability, which can bemeasured in terms of time to failure, cycles to failure, or thefailure rates of the individual components, theinterconnections, and the printed wiring board (PWB), isalso affected by component placement.

The thermal characteristics of an electronic system aredependent on both the thermal management techniquesbeing employed and the positioning of the heat dissipatingcomponents. When considering placement, an examinationof both the cooling methods and the failure mechanisms isrequired.

In the case where the model for the total failure rate, hT(t),is time independent, the positioning of the components onthe board requires minimizing, as follows:

hThi(Ti,Ti)i 1

n(13.13)

where hi is the failure rate of the i–th part.On the other hand, the method used in examining failures

due to time dependent failure is based on minimizing thetime, or the number of cycles to failure, Nf For example, ifthe failure mechanism is fatigue caused by temperature

cycling, then the number of cycles to failure is oftenmodeled by the Manson–Coffin formulation and has theform:

Nf A(KT)n (13.14)

where A, K, and n are based on environmental, geometric,and material properties. The constant n represents the slopeon a log–log plot of Ni versus (K∆T) and has a negativevalue.

The optimal reliability method used in failure rateplacement cannot always be employed because maximizingthe sum of the individual number of cycles to failure does notnecessarily ensure the best situation for the component withthe lowest cycle to failure component is maximized.Therefore, placement of components based on fatiguefailures requires that the components with minimum cyclesto failure are successively maximized. Mathematicallystated the placement problem becomes

Max(MinNfi) for i 1, &&& , n (13.15)

The placement of semiconductors on the heatsink is alsoimportant in order to achieve the lowest temperature rise.Figure 215 shows preferred positions. It is generally moreeconomical to use one heatsink with several properly placedtransistors than to use individual heatsinks. Coolingefficiency increases and the unit cost decreases under suchconditions. Details of placement methods can be found inreferences [1,2,3].

Figure 215. Proper Rectifier Placement for Components having Equal Power Dissipation.Located in this fashion, each semiconductor will operate at the same case temperature and

maximize the heatsink performance. In natural convection, mounting must be vertical.

10%

40%

70%

65%

15%

50%

Exhaust

Air

Flo

w

References1. M. Pecht, Handbook of Electronic Packaging,

Marcel Dekker, N.Y 1991.2. D. Steinberg, Cooling Techniques for Electronic

Equipment, John Wiley & Sons, N.Y., 1980.

3. Osterman, M. and Pecht, M., “Placement forReliability and Routability of Convectively CooledPWBs,” IEEE Transactions on Computer–aidedDesign of Integrated Circuits and Systems, Vol. 9,No. 7, July 1990, pp. 734–744.



Chapter 14

Assembly Considerations for PrintedCircuit Boards



$#

A rectifier diode package style is chosen based upon thepower being dissipated and the assembly technique.Generally, assembly costs are lower when the diode packageis soldered directly to the printed circuit board (PCB), usingeither insertion mount or surface mount, rather thanmounting with screws, clips, or other hardware on a separateheatsink. However, the power dissipation capability ofconventional PCBs is limited because of the board’srelatively poor thermal conductivity. With conventionalglass–epoxy boards, component power dissipation istypically limited to 3 W, while more costly metal–backedboards allow dissipations up to about 10 W. Themetal–backed board can be attached to a heatsink for evenhigher dissipation, but this is not often done because thetemperature of all components on the board is raised toapproximately that of the case of the power components.Thus, in high–power applications, the rectifier diode isusually mounted directly to a heatsink with wires used toconnect the component to the PCB.

Many early–life field failures have been traced to faultymounting procedures which cracked the die, cracked thepackage case impairing its moisture resistance, or mountedthe package in a way that increased its thermal resistance(reduced its ability to transfer the heat away from the die).The objective of a good mounting procedure is to secure thepackage without causing any physical damage and toprovide a low thermal resistance path to the heatsinkmaterial. In the sections to follow, mounting considerationsare explained for insertion or through–hole PCBs andsurface mount PCBs.

Insertion MountingAlthough insertion or through–hole printed circuit boards

have been the industry standard since the 1960s, errors arestill made in mounting components, particularly whenappreciable power must be dissipated. Thermal capabilitiesare often misjudged and mechanical damage can occur.

For insertion–mounted components in a free convectionenvironment, the primary path of heat transfer is through theleads as discussed in Chapter 2. Sufficient board metal needsto surround the lead insertion hole to act as a heatsink. Acircular pattern is most efficient per unit area because thethin board metal has a fairly high thermal resistance.Sometimes semiconductor manufacturers provideinformation as shown in Chapter 2 that may prove helpful.Otherwise, a required pad area can be calculated using theprinciples discussed in Chapter 13. Before committing aboard assembly to production, the diode lead temperatureshould be measured using a fine wire thermocouple underworst–case conditions.

Although the leads of axial–leaded and tab–mountpackages are somewhat flexible and can be formed forinsertion mounting, it is not a recommended procedure to doso because of the risk of damage to the package or die. Often,

a mechanical arrangement can be chosen that makeslead–forming unnecessary. Many lead–forming options areavailable from the manufacturers upon special request.Preformed leads remove the user’s risk of device damagecaused by bending.

If, however, lead–forming is done by the user, severalbasic considerations should be observed, When bending thelead, support must be placed between the point of bendingand the package. For forming small quantities of units, a pairof pliers may be used to clamp the leads at the case, whilebending with the fingers or another pair of pliers. Forproduction quantities, a suitable fixture should be made thatalso includes lead cutting, thereby eliminating repeatedhandling of the device.

The following general rules should be observed to avoiddamage to the package:

1. A lead bend radius greater than 1/16 inch isadvisable.

2. No twisting of leads should be done at the case.3. No axial motion of the lead should be allowed

with respect to the case.Leads are not designed to withstand excessive axial pull.

Force in this direction greater than 4 lb may result inpermanent damage to the device. If the mountingarrangement imposes axial stress on the leads, a conditionthat may be caused by thermal cycling, some method ofstrain relief should be devised, such as an expansion elbowformed in the lead. When wires are used for connections,care should be exercised to assure that movement of the wiredoes not cause movement of the lead at the lead–to–casejunctions. Highly flexible or braided wires are good forproviding strain relief. Wire–wrapping of the leads ispermissible, if the lead is restrained between the plastic caseand the point of the wrapping.

The leads may be soldered providing specifications areobserved. Typically, the maximum soldering temperaturefor a plastic encapsulated part must not exceed 240°C, andmust be applied for not more than 5 sec at a distance greaterthan 1/8 inch from the case. These numbers can varydepending upon the package type and manufacturer. In allcases, the manufacturer’s data sheet should be consulted forthe actual specifications. Glass or metal packaged partsusually allow higher temperatures. A removable heatdissipator, clamped on the lead near the body duringsoldering, reduces the chance of damage when control oftemperature and time is not precise, such as with handsoldering. Rosin or activated rosin fluxes are preferred whileorganic or acid fluxes should not be used.

Pins, leads, and tabs must be handled and connectedproperly to avoid undue mechanical stress that could causesemiconductor failure. Change in mechanical dimensions asa result of thermal cycling over operating temperatureextremes must be considered.



The pins and lugs of metal packaged devices usingglass–to–metal seals are not designed to handle anysignificant stress. If abused, the seals can crack, destroyingthe hermetic seal. Wires may be attached using sockets,crimp connectors, or solder, provided the data sheet ratingsare observed. When wires are attached directly to theterminals, flexible or braided leads are recommended toprovide strain relief.

The screw terminals of modules such as thePOWERTAP package look deceptively rugged. Since theflange base is mounted to a rigid heatsink, the connection tothe terminals must allow some flexibility. A rigid buss barshould not be bolted to terminals. Lugs with braid arepreferred.

In all cases, the manufacturer’s data sheets should beconsulted for recommended mounting procedures andtorque specifications. Many packages have specialrequirements.

Surface–Mount TechnologySurface–mount technology (SMT) began in the early

1970s when electronic manufacturers began to mountminiaturized components directly on the surface of printedcircuit boards, a technique evolving from thick film hybrids.SMT is being used increasingly to meet the electronicindustry’s demand for boards that are smaller, cheaper, andmore reliable.

In surface mounting, the components are soldered directlyon top of solder pads called footprints, rather than insertingthe leads into holes. Surface–mount devices (SMDs) caneither be leaded or leadless. The footprint conforms to thelead layout of the surface–mount component. Two commonsurface–mount footprints are shown in Figure 216. Acomparison between insertion–mount and surface–mount isshown in Figure 217. Surface mounting has severaladvantages over the insertion–mount method. For example,SMDs are typically 30% to 60% smaller than theirinsertion–mount versions. With the smaller package sizeand the elimination of the through–hole, board densities can

dramatically increase. The use of surface mount also allowscomponents to be placed on both sides of the PCB. The useof surface–mount chip capacitors, resistors, andsemiconductors could theoretically give SMT boardspackaging densities similar to hybrids. All this increaseddensity results in lower parasitic inductances andcapacitances. Smaller and denser PCBs result in reducedsystem costs by factoring in effects such as cabinet size,connectors, and cabling.

The current component industry trend is to make allpopular leaded products available in surface–mountpackaging. This gives the designers the ability tomanufacture complete surface–mount assemblies asopposed to hybrid boards–that is, boards which contain bothsurface–mount and insertion–mount components. Selectinga suitable surface–mounted rectifier diode equivalent to aleaded device generally requires more than a casual look, asthe designer may be confronted by a number of differentpackages.

A number of industry committees play a role incommunicating the importance of standardization to thecomponent manufacturer. The JEDEC, ETA, IPC, andSMTA set the standards in the United States while the ElMis the counterpart of JEDEC in Japan. These committees setstandards in packaging, outline dimensions, pin spacings,tape and reel specifications, etc.

In conjunction with the industry trend to use automaticplacement equipment for surface–mount components, mostsurface–mount semiconductors are packaged in theindustry–standard tape and reel format per EIA 481. Thecurrent packaging method is a conductive plastic tape withembossed cavities that serve as a pocket for the individualdevice. These tape sizes range from 8 to 24 mm dependingupon the size of the device. A sealing tape is then applied toretain the device. The reels are typically 7 or 13 inch, the7 inch reel handling a smaller quantity of devices. Some ofthe larger packages, such as the D2PAK, may also bepackaged in plastic tubes which are sometimes referred to asrails or sticks.



Figure 216. Typical Footprints of Surface–Mount Rectifiers

(0.090)2.3

(0.236)6

0.089”

inchesmm

(0.236)6

(0.118)3

(0.075)1.9

(0.063)1.6

0.085”

0.108”

(0.090)2.3

(0.063)1.6

DPAK SMB

Figure 217. Comparison of (a) Insertion–mount and (b) Surface–mount PCB

DUAL IN–LINE PACKAGE

RESISTOR

CHIP COMPONENTS

PLASTIC, LEADEDCHIP CARRIER

SMALL–OUTLINEPACKAGE

(a) (b)



Surface–Mount Rectifier PackagesA designer building a surface–mount assembly has a

choice of a number of surface–mount packages offered bythe semiconductor industry. Depending on the number ofleads, these packages can house either single or dual(center–tap) rectifier diodes. There are leadless diodes,SOT–type packages such as SOT–89 and SOT–223, and theSMB and SMC packages which are two leaded packagesdesigned specifically for diodes. For higher power levels,there are the DPAK and the D2PAK. Some of the morecommon surface–mount rectifier packages and their generalcharacteristics are shown in Table 30.

Two common types of lead forms are in use on rectifierSMDs. SOTs, DPAKS, and D2PAKs have “gull–wings”;SMBs and SMCs have the “J” bend. Both of theseconfigurations are shown in Figure 218. Gull–winged leadsare more easily probed by test leads, and gull–wingedpackages are easily handled by automated pick–and–placeequipment. Packages with J–bend leads have smallerfootprints and take up less real estate on the printed circuitboard. The disadvantage is that their solder joints are noteasily inspected and test points must be provided to accessthe leads.

The power dissipation ratings listed in Table 30 assumesthat the packages are mounted to a typical glass epoxy boardwith the minimum recommended size footprints (as shownon the manufacturer’s data sheet) at an ambient temperatureof 25C. Higher power dissipation can be achieved byproviding improved heat dissipation through the use ofmetal–backed boards and ceramic substrates.

Although the term “SOT” stands for small outlinetransistor, the packages are also used for rectifier products.These are plastic rectangular–shaped packages of varyingsizes with gull–wing leads. The number of leads is three forthe SOT–23, and four for the SOT–89 and the SOT–223.The power dissipation ratings range from 225 mW for theSOT–23 up to 830 mW for the SOT–223.

The SC–59 package is similar to the SOT–23 and iscommon in Japan. This package is very close to the SOT–23in size and has the same thermal and electrical

characteristics. Despite similarities, the SC–59 requires adifferent footprint.

For very high–density, low–power applications, theJapanese have developed several packages smaller than theSOT–23. These packages are the SC–70 and SC–90. TheSC–90 is about a third and the SC–70 about half the size ofthe SOT–23, with power dissipation ratings of 125 and 150mW respectively. The SC–70 package is also manufacturedin five– and six–leaded versions to accommodate diodes ina number of different configurations using monolithic chips.Due to their small size and resulting handling difficulties,these packages are slowly beginning to gain acceptanceoutside Japan.

SMB and SMC packages resemble “SO” type integratedcircuit packages except for wide leads bent in a modifiedJ–bend pattern. The packages have a maximum powerdissipation rating of 0.8 and 1.2 W, respectively. Althoughphysically larger, the SMB fits the same footprint as the l–WMELF. The SMB package is an alternative to the leadlessMELF and, due to its shape, it is generally easier to handlein manufacturing.

The DPAK developed by ON Semiconductor was the firsttrue power package developed for surface–mountapplications. The DPAK resembles a miniature TO–220. Incomparison with other plastic power packages, the DPAK isphysically smaller than a D2PAK yet larger than an SMB andSMC. The DPAK allows for a large selection of higherpower surface–mount devices since it can house a die sizeconsiderably larger than the MELF and SOT type packages.The largest high–power surface mount package presentlyavailable is the D2PAK, a package capable of handling thesame size die as the TO–220 package with a powerdissipation rating of 2.5 W. Both the DPAK and the D2PAKhave gull–winged leadforms with the center lead clipped,leaving the tab for the anode connection.

Prior to the introduction of the DPAK and the D2PAK, theconventional TO–220 package was used for surfacemounting by forming the leads into a gull wing lead formand, sometimes, shearing the tab. (Shearing the tab is a veryquestionable procedure that often causes a fracture in the diethat in turn leads to a latent failure.)

Figure 218. Lead Variations in Surface–mount Components

J–BendGull–Wing



Table 30. Surface–Mount Rectifier Packages


PackageDestination


GeneralPackage Description


Max #LeadsÁÁÁÁÁÁÁÁÁÁÁÁ

Max DieSize (Mils)


Max PD(Watts)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description(Not To Scale)


SC–90 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Low Power,Plastic – Gull–Wing Leads

ÁÁÁÁÁÁÁÁ

3 ÁÁÁÁÁÁÁÁ

15 x 15ÁÁÁÁÁÁÁÁÁÁ



SC–70ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



6ÁÁÁÁÁÁÁÁÁÁÁÁ

21 x 21ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



SOT–23(TO–236)






0.225 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


SC–59 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ







SOT–89(TO–243AA)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ




60 x 60ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.6ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


SOT–223(TO–261AA)


Medium Power,Plastic – Gull–Wing Leads






SMB(DO–214AA)


Medium Power,Plastic – J–Leads






SMC(DO–214AB)


High Power,Plastic – J–Leads






DPAK(TO–252)


High Power,Plastic – Gull–Wing Leads and Tab






D2PAK(TO–263)


High Power,Plastic – Gull–Wing Leads and Tab




2.5

Thermal Management of Surface–MountRectifiers

One of the major considerations when doing a new designis removing the heat from an assembly. The problembecomes even more severe when attempting miniaturizationthrough the use of surface–mount technology. The problemis magnified to a greater extent when placing powersurface–mount components such as the DPAK or a D2PAKon a surface–mount board assembly. Thermalcharacteristics of surface–mount packages are a majorconsideration since an increase in junction temperature TJcan have an adverse effect on the long term operating life ofthe component.

The surface–mount rectifier is soldered to a footprint asshown on the data sheet. This footprint is recommended toachieve the power dissipation ratings as shown on the datasheet. By using a larger footprint and more thermallyconductive PCB or substrate materials, the powerdissipation capability can be increased. The dedicatedamount of PCB area should be based upon thermalmanagement of the circuit. If it is too large, it will defeat the

whole concept of using surface mount; if it is too small, itwill limit the power–handling capability of the device.

The designer has the choice of either allocating a largerarea of copper clad to the footprint or using the smaller andthermally more efficient but more costly ceramics andmetal–backed board materials. Designing more complexmechanical thermal assemblies can raise thepower–handling capabilities of these packages. The use ofhigher power components will more than likely dictate theuse of such alternate board materials in order to properlymanage the thermal characteristics of the assembly.

When using surface–mount rectifiers, the board materialmay be a glass epoxy, a ceramic substrate, or a metal–backedboard to which the device is soldered. The sink–to–ambientthermal impedance will be a function of the substratematerial, the size of the footprint available for heatspreading, the proximity of other additional thermal loadson the board, and the velocity of air flow (in the case offorced air cooling). The heat–sinking capacity of the boardor substrate will depend on the thermal conductivity of theboard material. The reduction in thermal resistance



obtainable will depend on board material, thickness, and airvelocity across the board. The use of alternate (non–FR–4)circuit board materials opens up a whole range ofcapabilities for using the DPAK and D2PAK packages athigher power levels in surface–mount applications.Thorough testing of the prototype is the only way to provethe adequacy of a particular thermal design.

Manufacturers of PCB and substrate materials areconstantly working to improve the thermal efficiency oftheir materials and to develop new materials.

Board MaterialsThe printed circuit board material for surface–mount

components plays a crucial role in ensuring the electrical,thermal, and mechanical reliability of the electronicassembly. There are many types of available materials andit is important to carefully evaluate the important boardproperties in light of the final application of the product,before a board material can be selected in a cost–effectivemanner. Each material has a set of properties with particularadvantages and disadvantages, as seen in Table 31. Nomaterial will satisfy all design needs or applications andcompromises in material properties should be sought thatoffer the best tailoring to suit end–productcost–effectiveness.

Printed circuit boards vary from very basic single–sidedboards to very sophisticated multilayer constraining–corestructures. In high–reliability applications, thermalmanagement and solder joint reliability concerns oftenpreclude the use of conventional glass epoxy PCB materials.However, there are some selection criteria that are commonto all PCB materials as shown in Table 32 which lists designparameters and material properties that affect systemperformance. Also, Table 33 lists the properties of the mostcommon board materials.

When components are surface mounted, solder acts asboth the electrical and the mechanical attachment medium.Mounted to traditional printed circuit board materials, suchas glass epoxy, the thermal expansion mismatch between thecomponent and the board can cause solder joint stressfailures when a wide operational temperature range isencountered. This problem becomes more apparent withlarger component package sizes as the thermal expansionmismatch stress is proportional to package size. Equationsare available (see for example IPC–SM–785, Guidelines forAccelerated Reliability Testing of Surface Mounted SolderAttachments) for predicting the life of the solder attaches butfor the case of normal rectifier packages, the packagedimensions are small enough that thermal expansionmismatch fatigue is not a dominant failure mechanism.

With higher packaging densities and larger individualdies, surface–mount PCBs are often required to removemore heat per unit area than with conventionalinsertion–mount PCBs. As discussed in Chapter 2, theprimary path of heat transfer for SMDs is through the leads,with the exception of the DPAK and the D2PAK.Unfortunately, conventional organic base board materials

are relative poor thermal conductors and can requireheatsinks or sophisticated cooling mechanisms for thermalmanagement, with resultant penalties in system weight andsize. Again, before committing a board assembly toproduction, the diode lead temperature should be measuredusing a fine wire thermocouple, under worst–caseconditions.

Table 33 summarizes some of the more importantproperties of board materials. However, forsurface–mounting purposes, the properties that mostsignificantly influence the selection of board material,besides thermal conductivity, are glass transitiontemperature (Tg) and coefficient of thermal expansion(CTE). The simplest definition of glass transitiontemperature is just what its name suggests: the temperatureat which the material changes from a “glass–like” structureto a soft rubber–like consistency. At this temperature,significant changes occur in the mechanical properties of thematerial. These changes can cause process, handling, andperformance problems.

The coefficient of thermal expansion is a measure of howmuch a material expands per degree of temperature changeand is expressed in units of inch/inch per/C or parts permillion/C. The reinforcing woven fabric materials used intypical multilayer board laminates have a lower CTE thanthe resin. As a result, the composite laminates have theirexpansion restrained in the in–plane directions and, due tothis restraint, the expansion of the laminate in theout–of–plane direction can be increased over that of theresin alone. Above the Tg, this out–of–plane expansion CTEcan increase as much as fivefold and result in substantialstrains in plated–through holes.

In general, PCBs will fit into one of four basic categoriesof construction: organic base material, nonorganic basematerial, constraining core, and supporting plane ormetal–backed boards.

The most common board material in use is FR–4, anepoxy fiberglass laminate. Alternative resins to epoxy arethe polyimide, multifunctional epoxies (FR–5). Drivenprimarily by the military requirements for improvedreliability, in–service thermal performance, and fieldrepairability, the polyimides have evolved as the mostcommonly used material in the high–performance laminatemarket. The reason the polyimide resins are used is not thatthey have a better CTE than epoxies, but that they have asubstantially higher Tg. Most solder reflow operations occurbelow the polyimide Tg, not incurring the problems of thehigh out–of–plane expansion and resin softening as withepoxies. Thus, the problems associated with “pad lifting”during processing is minimized, and the board repairabilityis enhanced. BT–type resins can be used in place ofpolyimide at a lower cost.

New fabric–reinforcing materials such as quartz andaramid fiber fabrics are being used to improve the inplaneCTE characteristics of boards over those obtained with fiberglass. Unfortunately, due to the extra cost of the materials as



well as the extra processing costs, such as in drill–bit wear,these newer materials have not yet reached general use.

Nonorganic or ceramic–based boards have come directlyfrom hybrid circuit technology with its associated capabilityfor extremely high interconnection densities. These boardshave a lower CTE, no worries of a glass transitiontemperature, and better thermal conductivity but cost morethan typical organic–based boards.

Constraining core materials such as copper–Invar–copperor copper–graphite have been developed for use inmultilayer PCBs primarily to tailor to the boards overallthermal properties. By varying the ratio of high thermalexpansion copper to low thermal expansion Invar, thecopper–clad Invar core can be adjusted from 3 to 10ppm/C. Figure 219 shows a typical multilayer board with

copper–clad Invar power and ground planes acting asconstraining cores. The overall CTE of the structure can betailored by varying the composition and thickness of theconstraining cores.

Often metal cores or backings are used as conductionplates in a PCB only to improve the overall thermalcharacteristics of the board. Figure 220 is a schematic of asimple one–layer metal–backed board specifically designedfor improved thermal performance for power SMDs. Usingan aluminum base plate with a thermally conductivedielectric layer, which is then overlaid by the copper circuitlayer, the component power dissipations can be easilydoubled. More complex multilayer laminates with “blind”or “buried” vias can also be bonded to conduction plates.

ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ

ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ

Figure 219. Typical Multilayer Board with Copper–Clad Invar Power and GroundPlanes Acting as Constraining Cores

ÍÍÍÍÍÍÍÍÍ

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

ÍÍÍÍÍÍÍÍÍ

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ



.0014 COPPER (SIGNAL)

.004 EPOXY–GLASS


.006 EPOXY–GLASS

.005 COPPER CLAD INVAR (GROUND)

.004 EPOXY–GLASS

.005 COPPER CLAD INVAR (POWER)

.006 EPOXY–GLASS



.004 EPOXY–GLASS

ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ

Figure 220. Schematic of a Simple One–Layer Metal–Backed Board Specifically Designed forImproved Thermal Performance for Power SMDs

ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ

ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ

ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ

Thermal Clad

SOLDER

COPPER

DPAK TAB

Ts

Tc DIE

SOLDER

ISOLATING

ALUMINUM

EPOXY

Thermal Clad is a trademark of the Bergquist Company



Table 31. Characteristics of Board Materials


Type ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Major Advantages ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Major DisadvantagesÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Comments


Organic base substrateEpoxy Fiberglass


Substrate size, weight, rework-able, dielectric properties, con-ventional board processing


Thermal conductivity, X, Y,and Z axis CTE


Because of its high X–Y plane, CTE,should be limited to environments andapplications with small changes intemperature and/or small packagesÁÁÁÁÁÁÁÁ


Polyimide FiberglassÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Same as epoxy fiberglass plushigh–temperature Z axis CTE,substrate size, weight, rework-able, dielectric properties


Thermal conductivity, X and Yaxis CTE, moisture absorp-tion


Same as epoxy fiberglass


Epoxy Aramid FiberÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Same as epoxy fiberglass, X–Yaxis CTE, substrate size, lightestweight, reworkable, dielectricproperties


Thermal conductivity, X and Yaxis CTE, resin microcrack-ing, Z axis CTE, water ab-sorption


Volume fraction of fiber can be con-trolled to tailor X–Y CTE; resin selec-tion critical to reducing resin micro-cracks


Polyimide Aramid Fiber ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Same as epoxy aramid fiber, Zaxis CTE, substrate size, weight,reworkable, dielectric properties


Thermal conductivity, X and Yaxis CTE, resin microcrack-ing, water absorption

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Same as epoxy aramid fiber


Polyimide Quartz(fused silica)


Same as polyimide aramid fiber.Z axis CTE, substrate size,weight, reworkable, dielectricproperties


Thermal conductivity, X and Yaxis CTE, Z axis CTE, dril-ling, availability, cost, low res-in content required


Volume fraction of fiber can be con-trolled to tailor X–Y CTE; drill wearouthigher than with fiberglass


Fiberglass/AramidComposite Fiber


Same as polyimide aramid fiber,no surface microcracks, Z axisCTE, substrate size, weight, re-workable, dielectric properties


Thermal conductivity, X and Yaxis CTE, water absorption,process solution entrapment


Resin microcracks confined to internallayers and cannot damage externalcircuitry


Fiberglass/TeflonLaminates


Dielectric constant, high temper-ature


Same as epoxy fiberglass,low–temperature stability,thermal conductivity, X and Yaxis CTE


Suitable for high–speed logic applica-tions, same as epoxy fiberglass


FlexibleDielectric


Light weight, minimal concern toCTE, configuration flexibility


SizeÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Rigid–flexible boards offer trade–offcompromises


Thermoplastic ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

3–D configurations, low high–volume cost


High injection–molding setupcosts


Relatively new for these applications


Nonorganic Base Alumina (ceramic)


CTE, thermal conductivity, con-ventional thick–film or thin–filmprocessing, integrated resistors


Substrate size, rework limita-tions, weight, cost, brittle, di-electric constant


Most widely used for hybrid circuittechnology


Supporting Plane Printed board bonded toplane support (metal ornonmetal)


Substrate size, reworkability, di-electric properties, conventionalboard processing, X–Y. axisCTE, stiffness, shielding, cooling


WeightÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

The thickness/CTE of the metal corecan be varied along with the boardthickness, to tailor the overall CTE ofthe composite


Sequential processedboard with supportingplane core


Same as board bonded to sup-porting plane


WeightÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Same as board bonded to supportingplane


Discrete WireÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High–speed interconnections;good thermal and electrical fea-tures


Licensed process, requiresspecial equipment


Same as board bonded to low–expan-sion metal support plane


Constraining CorePorcelainizedcopper–clad invar


Same as aluminaÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reworkability, compatiblethick–film materials


Thick–film materials still under devel-opment


Printed board bonded withcontraining metal core


Same as board bonded to sup-porting plane


Weight, internal layer regis-tration

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Same as board bonded to supportingplaneÁÁÁÁÁÁÁÁ


Printed board bonded tolow–expansion graphite fi-ber core


Same as board bonded to low–expansion metal cores, stiffness,thermal conductivity, low weight


CostÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

The thickness of the graphite andboard can be varied to tailor the over-all CTE of the composite


Compliant layer structuresÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Substrate size, dielectric proper-ties, X–Y axis CTE


Z axis CTE, thermal conduc-tivity


Compliant layer absorbs difference inCTE between ceramic package andsubstrate



Table 32. Board Structure Selection Criteria


ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Material Properties


DesignParameters


TransitionTemperature


Coefficientof ThermalExpansion


ThermalConductivity


TensileModulus


FlexuralModules

ÁÁÁÁÁÁÁÁÁ

DielectricConstant


VolumeResistivity


SurfaceResistivity


MoistureAbsorption


Temperature andPower Cycling


X


X


X


X


ÁÁÁÁÁÁÁÁÁ




ÁÁÁÁÁÁVibration ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

X ÁÁÁÁÁÁÁÁ

X ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ



MechanicalShock





XÁÁÁÁÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁÁ




ÁÁÁÁÁÁTemperature andHumidity


XÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁÁÁÁÁ

Power DensityÁÁÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ


ÁÁÁÁÁÁChip Carrier Size


ÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ


ÁÁÁÁÁÁCircuit Density


ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁCircuit Speed


ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

XÁÁÁÁÁÁÁÁ

Table 33. PCB Board Properties

Material Properties

Material

GlassTransition

Temperature(C)

X–YCoefficientof ThermalExpansion(ppm/C)(Note 5)

ThermalConductivity

(W/MC)

X–Y TensileModulus

(PSI 106)

DielectricConstant

(at 1.0 MHz)

VolumeResistivity

(/cm)

SurfaceResistivity

()

MoistureAbsorption

(%)

Epoxy Fiberglass 125 13–18 0.16 2.5 4.8 1012 1013 0.10

Polyimide Fiberglass 250 12–16 0.35 2.8 4.8 1014 1013 0.35

Epoxy Aramid Fiber 125 6–8 0.12 4.4 3.9 1016 1016 0.85

Polyimide Aramid Fiber 250 3–7 0.15 4.0 3.6 1012 1012 1.50

Polyimide Quartz 250 6–8 0.30 – 4.0 109 108 0.50

Fiberglass/Teflon 75 20 0.26 0.2 2.3 1010 1011 1.10

Thermoplastic Resin 190 25–30 – 3–4 1017 1013 NA –

Alumina–Beryllia NA 5–7 44.0 8.0 1014 – – –

Aluminum (6061 T–6) NA 23.6 200 10 NA 106 – NA

Copper (CDA101) NA 17.3 400 17 NA 106 – –

Copper–clad Invar NA 3–6 150XY/20Z 17–22 NA 106 – NA

Graphite (P–100) 160 –1.15 110XY/1.1Z 37 NA – – –

Graphite (P–75) 160 –0.97 40XY/.7Z 25 NA – – –

2. These materials can be tailored to provide a wide variety of material properties based on resins, core materials, core thickness, andprocessing methods.

3. The X and Y expansion is controlled by the core material and only the Z axis is free to expand unrestrained. Where the Tg will be the sameas the reinforced resin system used.

4. When used, a compliant layer will conform to the CTE of the base material and to the ceramic component, therefore reducing the strainbetween the component and the P&I structure.

5. Figures are below glass transition temperature, and are dependent on method of measurement and percentage of resin content.NA – Not applicable.



Surface–Mount AssemblyMost SMDs have leads which are either solder plated or

solder dipped, thus eliminating the need to pretin the leadsprior to mounting. Pretinned PCBs are provided by mostmanufacturers. This aids in the attachment of the SMDssince both the mechanical and electrical connections aremade at the footprint by reflowing solder and joining thepans. Unlike the leaded component joints where the leadsprovided additional mechanical strength, the SMD isdependent on the solder joint alone. This is why good solderjoints are so critical to SMT technology.

A good solder joint must meet three basic criteria: goodwetting of surfaces, fillet complete, and not too much solder.To meet these requirements the industry adopted masssoldering techniques. The quality of the end product isdetermined by the measures taken during the design andmanufacturing stages. A consistent standard of quality andreliability in the finished product is not attainable withmanual methods.

The assembly process involves the placement of thecomponents on the circuit board with a temporary means offastening to hold them in place. In insertion mounting, thecomponent leads are inserted into the holes and thenclinched, automatically aligning the package and holding itin place until soldering. With surface mounting, thepackages are more difficult to handle in assembly becausethey cannot be aligned during the pick–and–place operation.SMDs must be physically held in place either by an adhesiveor with solder paste, depending upon the final configurationand soldering process. Adhesives are used to hold in placeSMDs that will be undergoing a wave–soldering process. Ina reflow process, the solder paste holds the component inplace and alignment is not as much of a concern, as thecomponents generally will be pulled into alignment by thesurface tension of the molten solder. The first major step inPCB preparation is to “print” the solder paste onto the pads.This is done by a screen printer. This paste provides thenecessary solder to form the joint fillets that are so importantto electrical and mechanical connections. The component isthen placed on the fresh solder paste and the operation iscompleted through one of several different types ofsoldering processes. This process melts the solder and bondsthe SMD to the PCB. After the soldering operation, theboard is cleaned with a solvent and it is then ready fortesting.

There are two general classifications of solderingprocesses: reflow and wave soldering. Wave soldering is thetraditional method used for insertion mount components,and it can also be used for SMDs. In wave soldering, the PCBis inverted so the components are suspended under the boardand then passed through a molten stationary wave of solder.The solder wave simultaneously supplies the heat and thesolder to make the connection between the component andPCB footprint. In reflow soldering, solder paste is applied tothe PCB footprint before the component is placed. Theassembly is then heated until the solder paste reflows,

making the joint. Many reflow soldering techniques havebeen developed, which vary only in the method of heattransfer used.

With wave soldering, the component orientation withrespect to the direction is very important. The surfacetension of the solder can prevent molten solder fromreaching the downstream side of the component. The heightof the component body is also very critical. Componentswith heights up to 100 mils can typically be wave soldered.However power SMDs such as the D2PAK with a bodyheight of 175 mils are not suitable for wave solderingbecause of “shadowing.” Shadowing occurs when the bodyheight shadows the solder pads from the wave and thesurface tension of the molten solder prevents the solder fromreaching the far end of the component, as shown inFigure 221.

With the increased package density and the reduction ofspace between conductors, nonwetting, solder bridging, andshadowing are all problems for conventionalwave–soldering equipment. The dual wave method wasdeveloped to overcome the limitations of conventional wavesoldering. The first wave in a dual wave system is a narrow,turbulent jet–like fountain. The function of this wave is toensure that solder is forced into the component area and thatthe solder reaches all pads. The narrow length permits gasevolved from either the flux or component attachmentadhesives to escape. The turbulent jet flow of the waveprovides sufficient pressure to overcome the repelling andhydrodynamic turbulence caused by the component bodies,assuring that all pads are wetted with solder. The second,laminar, wave embodies the characteristics of aconventional wave–soldering machine and completes theformation of solder fillets and removes bridges. However,with increased circuit density and the resulting reduction ofspace between conductors, reflow soldering techniques arepreferred for surface–mount technology.

Vapor–phase reflow is the most common process used forsoldering SMDs. The soldering is accomplished byimmersing the assembly in boiling vapors. The vaporscondense and transfer heat to the board using the latent heatof condensation principle. Since the liquid boils at atemperature higher than the melting point of the solder, thesolder reflows. Vapor–phase reflow soldering offers theadvantages of rapid heating with precise temperaturecontrol which protects heat–sensitive components fromthermal damage. Vapor–phase reflow soldering produceseven heating regardless of the overall geometry and is aninherently clean operation as only continuously distilledvapors contact the assembly.

A key ingredient in reflow soldering is the solder paste.Solder paste consists of flux impregnated with small nodulesof solder. Solvents are added to the paste to provide optimumflow characteristics during screen printing of the paste ontothe substrate assembly. Solder paste reflow can be achievedby several techniques including conduction or convection



ovens, resistance soldering, infrared, laser, and vapor phasereflow.

In thermal conduction belt reflow soldering, the heatrequired for the reflow is conducted through the assembly.This is accomplished by a series of heated platens locatedunder a continuously moving belt. The platens areindividually controlled so that the reflow thermal profile canbe varied for assemblies with different thermalconductivities and masses. Generally there are at least twostages: a preheat zone to reduce the thermal shock and todrive off the flux solvents, and a reflow zone for the actualsoldering. Because the conduction of the heat through theassembly depends upon the contact of the assembly to thebelt, a weighted fixture is usually used to apply pressure tomultiple points on the assembly. The method is generallysuitable for small substrates with SMDs on the upper sideonly. If a reducing atmosphere, such as forming gas, is used,then solder post cleaning may not be required.

In thermal–convection or hot–air soldering, the assemblyis placed on a conveyor that passes it through various heatingzones where hot air or gases are blown across the board.Special attention must be paid to the air velocity. Too much

air can blow out or upset the solder in addition to displacingcomponents on the board. If there is too little air, poorconvective heat transfer will occur.

In resistance soldering, a heated element in physicalcontact with the joint is used to reflow the solder. Instead ofsolder paste, an extra thick layer of solder is usually plateddirectly onto the footprint.

Infrared reflow uses radiation to transfer heat to the solderpaste to cause reflow. With a conveyorized infrared oven,the assembly is passed through preheat zones beforereaching the high intensity reflow zone. The main difficultywith IR oven heating is obtaining and maintaining a uniformtemperature distribution across the assembly due toshadowing and variabilities in surface emissivity and energyabsorption. With careful process control, IR reflowsoldering can produce excellent results.

Laser soldering relies upon the absorption of laserradiation by a conductive pad to melt and reflow the solderpaste. Laser soldering is not a generally used process. It hasits place as a specialized process that takes advantage of thefact that, with its localized heating, it performs its functionon precisely the area to be processed, and on that area alone.

Figure 221. Shadowing in Wave Soldering: (a) Surface Tension and Body Height CanPrevent Molten Solder Reaching the Downstream End of the SMD, the “Shadow Effect”;

(b) Extending the Solder Land May Overcome Shadowing

ÄÄÄÄÄÄ

SUBSTRATEDIRECTION

ADHESIVESOLDER LANDS

ÄÄÄÄÄÄ

SUBSTRATEDIRECTION

SOLDER FLOW

SOLDER LANDSEXTENDED

(a)

(b)



Flux and Post Solder CleaningMany factors influence the quality and reliability of the

finished product: the soldering process itself, condition ofcomponents and substrates being soldered, the choice andapplication of the flux, and method of post–solder cleaning.Flux selection and post–solder cleaning are becoming themost important yet least understood factors insurface–mount manufacturing today.

The choice and application of the flux, plus the method offlux residue removal from the electronics assemblies arevery important in surface–mount technology reliability. Theflux removes surface oxides, prevents reoxidation, andassists in the removal of corrosive residues on the substrateduring subsequent post–solder cleaning. The flux improvesthe wettability of the solder joint surfaces. One must becareful, however, not to use a highly activated flux in orderto promote rapid wetting to compensate for ill–preparedsurfaces. The flux residues are corrosive and a mildlyactivated flux should be used wherever possible.

The major types of fluxes are shown in Table 34 with thetypes of cleaning processes suitable for removal of eachflux. In the electronics industry rosin/resin fluxes are themost popular.

Rosin is a solid resin obtained from pine trees which, in apure form but usually with additives, is frequently used as a

flux. The main characteristics of a flux are the ability topromote wetting to surfaces, called flux activity (cleaning ofsurface as solder is reflowing), and the corrosivity of fluxresidues after soldering. As a general rule the more active theflux, the more corrosive are its residues. In electronicassemblies that are exposed to elevated temperatures andhumidity, flux residues from fluxes can corrode themetallurgical tracks on the electronic assemblies andcomponent leads. Post–solder cleaning removes anycontamination, such as surface deposits, inclusions,occlusions, or absorbed matter, which may degrade thechemical, physical, or electrical properties of the electronicassemblies.

The removal of fluxes and flux residues after soldering isessential for reliable performance of the electronicassemblies. CFC–113 solvents mixed with alcohols were thesolvents of choice for electronic assemblies cleaning priorto concerns about depletion of the ozone layer.

The dilemma brought about by government regulationsand the confusion over the multitude of options for specificapplications, with no universal replacement for CFC–113,makes it difficult for the designer to select surface–mounttechnology since the reliability of this technology is verydependent on high–quality cleaning of the electronicassemblies.

Table 34. Types of Fluxes Used for Soldering

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁFlux


MilitaryApproved**


OrganicSolvent

ÁÁÁÁÁÁÁÁWater


Waterwith Saponifier


Terpenewith waterÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁR (nonactivated rosin)ÁÁÁÁÁÁÁÁÁÁa


ÁÁÁÁÁÁÁÁ



ÁÁÁÁÁÁÁÁÁÁRMA (rosin, mildly–activated)ÁÁÁÁÁÁÁÁÁÁa


ÁÁÁÁÁÁÁÁ



ÁÁÁÁÁÁÁÁÁÁRA (rosin, activated)ÁÁÁÁÁÁÁÁÁÁa, b


ÁÁÁÁÁÁÁÁ



ÁÁÁÁÁÁÁÁÁÁRSA (rosin, super–activated)ÁÁÁÁÁÁÁÁÁÁ


ÁÁÁÁÁÁÁÁ



ÁÁÁÁÁÁÁÁÁÁWS (water soluble)ÁÁÁÁÁÁÁÁÁÁc


ÁÁÁÁÁÁÁÁ



ÁÁÁÁÁÁÁÁÁÁSA (synthetic resin, activated)ÁÁÁÁÁÁÁÁÁÁd


ÁÁÁÁÁÁÁÁ



ÁÁÁÁÁÁÁÁÁÁLow SolidsÁÁÁÁÁÁÁÁÁÁ


ÁÁÁÁÁÁÁÁ



*1 to 10 percent solids.**U.S. MilitaryaPer the requirements of MIL–F–14256bMilitary approved for certain applications MIL–F–14258 Qualified Products List; also approved by U.K. Defense Standards.cApproved for use by U.K. Defense Standards.dConditionally approved for use by U.K. Defense Standards.Source: Adapted from Markenstein, Howard. 1983. ‘‘Solder Flux Developments Expand Choices,” Electronic Packaging and Production,April 1983, pp. 39–42.



Semiaqueous Cleaning ProcessA semiaqueous system is a process in which the

contaminants are dissolved from the electronic assembliesand the solvent/residue mixture is rinsed from the surface ina water stage. A solvent–emulsion cleaning system is shownin Figure 222. A solvent stage is the first step in the process,followed by an emulsion stage established in the first rinsestage by drag–out from the solvent stage with a smallamount of water added. Overflow from the emulsion stagecan be allowed to settle in the decanter vessel. This allows

the contaminants generated in the soldering process to beseparated from the aqueous effluent. The contaminantscollect in the hydrocarbon layer of the decanter. Theorganics in the water are primarily extracted surfactant fromthe cleaning agent formula. This is an important distinctionfrom aqueous cleaning, where all dirt and saponifiers areflushed down the drain. This allows the use of a closed–loopwater recycle system. With the correct filtration, eliminationof water discharge can be possible.

Figure 222. Semiaqueous Cleaning System (courtesy of Du Pont)

SOLVENT EMULSION WATER

SUPPLY WATER

TO DRYINGSYSTEM

WATER RINSE STAGE

EMULSION STAGEKCD–9438MAKEUP

9438 STAGE

DECANTER

TO BURN ORRECONSTITUTE

TO WASTE WATERTREATMENT OR RECYCLE

AIR KNIFE

SOLVENT + DIRT

WATER + SOAP



Chapter 15

Heatsink Mounting Considerations



%&

When the power dissipated in a rectifier diode exceedsapproximately 10 W, it is more practical to use an externalheatsink rather than a PCB to cool the diode. High–densitydesigns use a cold plate (a plate kept cooled by a flowingfluid) while the finned assemblies discussed in Chapter 13are used where space allocations are more generous. In anycase, proper mounting of the diode to the heatsink isnecessary to provide a low resistance path for heat transferand to secure the package without causing mechanicaldamage.

In many situations the case of the semiconductor must beelectrically isolated from its mounting surface. The isolationmaterial is, to some extent, a thermal isolator as well whichraises junction operating temperatures. In addition, thepossibility of arc–over problems is introduced if highvoltages are present. Various regulating agencies alsoimpose creepage distance specifications which furthercomplicate design. Electrical isolation thus placesadditional demands upon the materials used and themounting procedure.

A proper mounting procedure usually necessitates orderlyattention to the following:

1. Prepare the mounting surface.2. Apply a thermal grease (if required).3. Install the insulator (if electrical isolation is

desired).4. Fasten the assembly.5. Connect the terminals to the circuit.

Mounting procedures are dependent upon the package.However, packages can be placed into one of several genericclasses of packages. As newer packages are developed, it isprobable that they will fit into the generic classes defined.Unique requirements are given on data sheets pertaining tothe particular package. The following classes are defined:• Stud mount

• Range mount

• Pressfit

• Plastic–body mount

• Tab mount

Mounting Surface PreparationSince diodes are cooled by contact between the diode case

and the heatsink surface, it is important that the maximumpossible area of the diode case is in intimate contact with theheatsink. Consequently, surface flatness and finish shouldmeet minimum standards and the mounting method shouldideally distribute pressure evenly over the mating surfaces.Mounting holes and surface treatment must also beconsidered.

Surface FlatnessIn general, the heatsink mounting surface should have a

flatness and finish comparable to that of the semiconductorpackage. In lower power applications, the heatsink surfaceis satisfactory if it appears flat against a straight edge and isfree from deep scratches. In high–power applications, amore detailed examination of the surface is required.

Surface flatness is determined by comparing the variancein height (∆h) of the test specimen to that of a referencestandard as indicated in Figure 223. Flatness is normallyspecified as a fraction of the Total Indicter Reading (TIR).The mounting surface flatness, i.e., ∆h/TlR, if less than 4mils per inch (normal for extruded aluminum) is satisfactoryin most cases.

Surface FinishSurface finish is the average of the deviations both above

and below the mean value of surface height. For minimuminterface resistance, a finish in the range of 50 to 60 µ–in. issatisfactory; a finer finish is costly to achieve and does notsignificantly lower contact resistance. Tests using a copperTO–3 package with a typical 32 µ–in. finish, showed thatheatsink finishes between 16 and 64 µ–in. caused less than±2.5% difference in interface thermal resistance when thevoids and scratches were filled with a thermal jointcompound [1]. Most commercially available cast orextruded heatsinks will require spotfacing when used inhigh–power applications. In general, milled or machinedsurfaces are satisfactory if prepared with tools in goodworking condition.



ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ


Figure 223. Surface Flatness Measurement

REFERENCE PIECE

TIR

DEVICE MOUNTING AREA

SAMPLEPIECE

TIR = TOTAL INDICATOR READING

h

Mounting HolesMounting holes generally should only be large enough to

allow clearance of the fastener. The larger thick–flangepackages having mounting holes removed from thesemiconductor die location, such as the TO–3, maysuccessfully be used with larger holes to accommodate aninsulating bushing, but many plastic encapsulated packagesare intolerant of this condition. For these packages, a smallerscrew size must be used so that the hole for the bushing doesnot exceed the hole in the package.

Punched mounting holes have been a source of troublebecause, if not properly done, the area around a punchedhole is depressed in the process. This “crater” in the heatsinkaround the mounting hole can cause two problems. Thedevice can be damaged by distortion of the package as themounting pressure attempts to conform it to the shape of theheatsink indentation, or the device may only bridge thecrater and leave a significant percentage of itsheat–dissipating surface out of contact with the heatsink.The first effect may often be detected immediately by visualcracks in the package (if plastic), but usually an unnaturalstress is imposed, which results in an early–life failure. Thesecond effect results in hotter operation and may shortenlong–term life.

Although punched holes are seldom acceptable in therelatively thick material used for extruded aluminumheatsinks, several manufacturers are capable of properlyutilizing the capabilities inherent in both fine–edge blankingor sheared–through holes when applied to sheet metal ascommonly used for stamped heatsinks. The holes arepierced using Class A progressive dies mounted onfour–post die sets equipped with proper pressure pads andholding fixtures.

When mounting holes are drilled, a general practice withextruded aluminum, surface cleanup is important. Chamfers

must be avoided because they reduce heat transfer surfaceand increase mounting stress. However, the edges must bebroken to remove burrs which cause poor contact betweendevice and heatsink and may puncture isolation material.

Surface TreatmentMany aluminum heatsinks are black–anodized to improve

radiation ability and prevent corrosion. Anodizing results insignificant electrical but negligible thermal insulation. Itneed only be removed from the mounting area whenelectrical contact is required. Heatsinks are also availablethat have a nickel–plated copper insert under thesemiconductor mounting area. No treatment of this surfaceis necessary.

Another treated aluminum finish is indite, orchromate–acid dip which offers low resistance because of itsthin surface, yet has good electrical properties because itresists oxidation. It need only be cleaned of the oils and filmsthat collect in the manufacture and storage of the sinks, apractice which should be applied to all heatsinks.

For economy, paint is sometimes used for sinks; removalof the paint where the semiconductor is attached is usuallyrequired because of paint’s high thermal resistance.However, when it is necessary to insulate the semiconductorpackage from the heatsink, hard anodized or paintedsurfaces allow an easy installation for low–voltageapplications. Some manufacturers will provide anodized orpainted surfaces meeting specific insulation voltagerequirements, usually up to 400 V.

It is also necessary that the surface be free from all foreignmaterial, film, and oxide (freshly bared aluminum forms anoxide layer in a few seconds). Immediately prior toassembly, it is a good practice to polish the mounting areawith No. 400–600 grit paper or No. 000 steel wool, followedby an acetone or alcohol rinse. If steel wool is used, caremust be taken to remove all steel particles to avoid flashover.



Interface DecisionsEven with properly prepared mounting surfaces, when

any significant amount of power is being dissipated,something must be done to fill the air voids between matingsurfaces in the thermal path. Otherwise, the interfacethermal resistance will be unnecessarily high and quitedependent upon the surface finishes and pressure.

For several years, thermal joint compounds, often calledgrease, have been used in the interface. They have aresistivity of approximately 60C/W/in. whereas air has1200C/W/in. Since surfaces are highly pockmarked withminute voids, use of a compound makes a significantreduction in the interface thermal resistance of the joint.However, the grease causes a number of problems, asdiscussed in the following section.

To avoid using grease, manufacturers have developed dryconductive and insulating pads to replace the moretraditional materials. These pads are conformal andtherefore partially fill voids when under pressure.

Thermal Compounds (Grease)Joint compounds are a formulation of fine zinc or other

conductive particles in a silicone oil or other synthetic basefluid, which maintains a grease–like consistency with timeand temperature. Since some of these compounds do notspread well, they should be evenly applied in a very thinlayer using a spatula or lintless brush, and wiped lightly toremove excess material. Some cyclic rotation of the packagewill help the compound spread evenly over the entire contactarea. Some experimentation is necessary to determine thecorrect quantity; too little will not fill all the voids, while toomuch may permit some compound to remain betweenwell–mated metal surfaces where it will substantiallyincrease the thermal resistance of the joint.

To determine the correct amount, several semiconductorsamples and heatsinks should be assembled with different

amounts of grease applied evenly to one side of each matingsurface. When the amount is correct, a very small amount ofgrease should appear around the perimeter of each matingsurface as the assembly is slowly torqued to therecommended value. Examination of a dismantled assemblyshould reveal even wetting across each mating surface. Inproduction, assemblers should be trained to slowly apply thespecified torque even though an excessive amount of greaseappears at the edges of mating surfaces. Insufficient torquecauses a significant increase in the thermal resistance of theinterface.

To prevent accumulation of airborne particulate matter,excess compound should be wiped away using a clothmoistened with acetone or alcohol. These solvents shouldnot contact plastic–encapsulated devices, as they may enterthe package and cause a leakage path or carry in substanceswhich might attack the semiconductor chip.

Data showing the effect of compounds on several packagetypes under different mounting conditions is shown inTable 35. The rougher the surface, the more valuable thegrease becomes in lowering contact resistance; therefore,when mica insulating washers are used, use of grease isgenerally mandatory. The joint compound also improves thebreakdown rating of the insulator.

The silicone oil used in most greases has been found toevaporate from hot surfaces with time and become depositedon other cooler surfaces. Consequently, manufacturers mustdetermine whether a microscopically–thin coating ofsilicone oil on the entire assembly will pose any problems.It may be necessary to enclose components using grease.The newer synthetic–base greases show far less tendency tomigrate or creep than those made with a silicone oil base.However, their currently observed working temperaturerange is less, they are slightly poorer on thermalconductivity and dielectric strength, and their cost is higher.

Table 35. Approximate Values for Interface Thermal Resistance Data from Measurements Performed in ONSemiconductor Applications Engineering LaboratoryDry interface values are subject to a wide variation because of extreme dependence upon surface conditions. Unless otherwise noted, thecase temperature is monitored by a thermocouple locate directly under the die reached through a hole in the heatsink.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interface Thermal Resistance (C/W)


Package Type and Data ÁÁÁÁÁÁÁÁÁÁ


Metal–to–MetalÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

With Insulator ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁJEDEC OutlinesÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁDescription


Test TorqueIn–Lb

ÁÁÁÁÁÁDry

ÁÁÁÁÁÁÁÁLubed

ÁÁÁÁÁÁDry

ÁÁÁÁÁÁLubed

ÁÁÁÁÁÁÁÁType

ÁÁÁÁÁÁÁÁ

SeeNoteÁÁÁÁÁÁÁÁ


DO–203AA, TO–210AA,TO–208AB


10–32 Stud 7/16ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

15ÁÁÁÁÁÁÁÁÁ


0.2ÁÁÁÁÁÁÁÁÁ



3 mil MicaÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


DO–203AB, TO–210AC,TO–208


1/4–28 Stud 11/16 HexÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

25 ÁÁÁÁÁÁÁÁÁ


0.1 ÁÁÁÁÁÁÁÁÁ



5 mil MicaÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁDO–208AA ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁPressfit, 1/2 ÁÁÁÁÁ

ÁÁÁÁÁ– ÁÁÁÁÁÁ


0.1 ÁÁÁÁÁÁ

– ÁÁÁÁÁÁ

–ÁÁÁÁÁÁÁÁ

– ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TO–204AA (TO–3) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Diamond Flange ÁÁÁÁÁÁÁÁÁÁ

6 ÁÁÁÁÁÁ

0.5ÁÁÁÁÁÁÁÁ

0.1 ÁÁÁÁÁÁ

1.3ÁÁÁÁÁÁ


3 mil MicaÁÁÁÁÁÁÁÁ

1


TO–213AA (TO–66) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Diamond Flange ÁÁÁÁÁÁÁÁÁÁ

6 ÁÁÁÁÁÁ

1.5ÁÁÁÁÁÁÁÁ

0.5 ÁÁÁÁÁÁ

2.3ÁÁÁÁÁÁ

0.9ÁÁÁÁÁÁÁÁ

2 mil MicaÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTO–126 ÁÁÁÁÁÁÁÁThermopad 1/4 x 3/8ÁÁÁÁÁ6 ÁÁÁ2.0ÁÁÁÁ1.3 ÁÁÁ4.3ÁÁÁ3.3ÁÁÁÁ2 mil MicaÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁTO–220ABÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁThermowatt

ÁÁÁÁÁÁÁÁÁÁ8

ÁÁÁÁÁÁ1.2

ÁÁÁÁÁÁÁÁ1.0

ÁÁÁÁÁÁ3.4

ÁÁÁÁÁÁ1.6

ÁÁÁÁÁÁÁÁ2 mil Mica

ÁÁÁÁÁÁÁÁ1, 2

1. See Figures 224, 225, and 226 for additional data on TO–3 and TO–220 packages.2. Screw not insulated. See Figure 234.



Conductive PadsBecause of the difficulty of assembly using grease and the

evaporation problem, some equipment manufacturers willnot, or cannot, use grease. To minimize the need for grease,several vendors offer dry conductive pads whichapproximate performance obtained with grease. Data for agreased bare joint and a joint using Grafoil , a dry graphitecompound, is shown in the data of Figures 224 and 225.Grafoil is claimed to be a replacement for grease when noelectrical isolation is required; the data indicates it doesindeed perform as well as grease. Another conductive padavailable from AAVID is called Kon–Dux. It is made witha unique, grain–oriented, flake–like structure (patentpending). Highly compressible, it becomes formed to thesurface irregularities of both the heatsink and thesemiconductor. Manufacturer’s data shows it to provide aninterface thermal resistance, better than a metal interfacewith filled silicone grease. Similar dry conductive pads areavailable from other manufacturers. They are a fairly recentdevelopment; long–term problems, if they exist, have notyet become evident.

Insulation ConsiderationsSince most power semiconductors use vertical device

construction, it is common to manufacture power diodeswith the anode electrically common to the case; the problemof isolating this terminal from ground is a common one. Forlowest overall thermal resistance which is quite importantwhen high power must be dissipated, it is best to isolate theentire heatsink/semiconductor structure from ground, ratherthan to use an insulator between the semiconductor and theheatsink. Heatsink isolation is not always possible, however,because of EMI requirements, safety reasons, and instanceswhere a chassis serves as a heatsink or where a heatsink iscommon to several nonisolated packages. In these situationsinsulators are used to isolate the individual componentsfrom the heatsink. Newer packages contain the electricalisolation material within, thereby saving the equipmentmanufacturer the burden of addressing the isolationproblem.

When an insulator is used, thermal grease is of greaterimportance than with a metal–to–metal contact because twointerfaces exist instead of one, and some insulatingmaterials, such as mica, have a hard, markedly unevensurface. With many isolation materials, reduction ofinterface thermal resistance by 50%–70% is typical whengrease is used.

Figure 224. Interface Thermal Resistance for a TO–204 (TO–3) Package

0.8

0.6

0.4

0.2

0

1

1.2

1.4

1.6

0 1 2 3 4 5

0 72 145 217 290 435

6

2

362

θ

°

[5]

[6]

[7]

[8]

[4][3][2]

[1]

0.4

0.3

0.2

0.1

0

0.5

0.6

0.7

0.8

0 1 2 3 4 5

0 72 145 217 290 435

6

1

362

θ

°

[5]

[6][7]

[4]

[3][2]

[1]

0.9

(a) TO–204AA (TO–3)Without Thermal Grease

(b) TO–204AA (TO–3)With Thermal Grease

(1) Thermalfilm , 0.002 (0.05) thick. (2) Mica, 0.003 (0.08) thick.(3) Mica, 0.002 (0.05) thick.(4) Hard anodized, 0.020 (0.51) thick.(5) Aluminum oxide, 0.062 (1.57) thick.

(6) Beryllium oxide, 0.62 (1.57) thick.(7) Bare joint – no finish.(8) Grafoil , 0.005 (0.13) thick.*

*GrafoiI is not an insulating material.(Data courtesy of Thermalloy, Inc.)



Data showing interface resistance for different insulatorsand torques applied to TO–3 and TO–220 packages areshown in Figures 224 and 225 for bare and greased surfaces.Similar materials to those shown are available from severalmanufacturers. It is obvious that with some arrangements,the interface thermal resistance exceeds that of thesemiconductor (junction–to–case).

The conclusion from Figures 224 and 225 is thatberyllium oxide is unquestionably the best choice. However,it is an expensive choice. (It should not be cut or abraded, asthe dust is highly toxic if inhaled.) Thermalfilm is a filledpolymide material which is used for isolation (variation ofKapton ). It is a popular material for low–powerapplications because of its low cost, ability to withstand hightemperatures, and ease of handling in contrast to mica whichchips and flakes easily.

A number of other insulating materials are also shown.They cover a wide range of insulation resistance, thermalresistance, and ease of handling. Mica has been widely usedin the past because it offers high breakdown voltage andfairly low thermal resistance at a low cost, but it certainlyshould be used with grease.

Silicone rubber insulators have gained favor because theyare somewhat conformal under pressure. Their ability to fillin most of the metal voids at the interface reduces the needfor thermal grease. When first introduced, they sufferedfrom cut–through after a few years in service. The onespresently available have solved this problem by havingembedded pads of Kapton or fiberglass. By comparingFigures 225(a) and 225(b), it can be noted that Thermalsil ,a filled silicone rubber, without grease has about the sameinterface thermal resistance as greased mica for the TO–220package.

Figure 225. Interface Thermal Resistance for a TO–220 Package

MOUNTING SCREW TORQUE

0 1 2 4 5 6

(IN–LBS)

4

3

2

1

0

5

[5][6]

[7][8]

[4]

[3]

[2]

[1]

[7][4][3][2]

[1]

0 1 2 4 5 63

4

3

2

1

0

5

θ

°

θ

°

MOUNTING SCREW TORQUE(IN–LBS)

(a) TO–220Without Thermal Grease

(b) TO–220With Thermal Grease

(1) Thermalfilm , 0.022 (0.05) thick.(2) Mica, 0.003, (0.08) thick.(3) Mica, 0.002 (0.05) thick.(4) Hard Anodized, 0.020 (0.51) thick.(5) Thermalsil II, 0.009 (0.23) thick.

(6) Thermalsil III, 0.006 (0.15) thick.(7) Bare Joint – no finish. (8) Grafoil, 0.005 (0.13) thick.*

*Grafoil is not an insulating material.(Data courtesy of Thermalloy, Inc.)

0 72 145 290 362 435217

INTERFACE PRESSURE (psi)

0 72 145 290 362 435217

INTERFACE PRESSURE (psi)



A number of manufacturers offer silicone rubberinsulators. Table 36 shows measured performance of severalof these insulators under carefully controlled, nearlyidentical conditions. The interface thermal resistanceextremes are over 2:1 for the various materials. It is alsoclear that some of the insulators are much more tolerant thanothers of out–of–flat surfaces. Since the tests wereperformed, newer products have been introduced. TheBergquist K–10 pad, for example, is described as havingabout two–thirds the interface resistance of the Sil Pad 1000,which would place its performance close to the Chomerics1671 pad. AAVID also offers an isolated pad calledRubber–Duc; however, it is only available vulcanized to aheatsink and therefore was not included in the comparison.Published data from AAVID shows RθCS below 0.3C/Wfor pressures above 500 psi. However, surface flatness andother details are not specified, so a comparison cannot bemade with other data in this note.

The thermal resistance of some silicone rubber insulatorsis sensitive to surface flatness when used under a fairly rigidbase package. Data for a TO–3 package insulated withThermalsil is shown in Figure 226. Observe that the “worstcase” encountered (7.5 mils) yields results having abouttwice the thermal resistance of the “typical case” (3 mils),for the more thermally conductive insulator. In order for

Thermalsil III to exceed the performance of greased mica,total surface flatness must be under 2 mils, a situation thatrequires spot finishing.

INT

ER

FAC

E T

HE

RM

AL

RE

SIS

TAN

CE

(°C

/W)

Figure 226. Effect of Total Surface Flatness onInterface Resistance Using Silicon Rubber Insulators

0.4

0.2

0

0.6

0.8

0 0.002 0.004 0.006 0.008 0.01

1

1.2

(1) Thermalsil II, .009 inches (.23 mm) thick(2) Thermalsil III, .006 (.15 mm ) thick

TOTAL JOINT DEVIATION FROM FLAT OVERTO–3 HEADER SURFACE AREA (INCHES)

Table 36. Thermal Resistance of Silicone Rubber Pads


Manufacturer ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Product ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RCS @ 3 Mils* ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RCS @ 7.5 Mils*


Wakefield ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Delta Pad 173–7 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

.790 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

1.175


Berquist ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sir Pad K–4 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


1.470


Stockwell Rubber ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

1867 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


1.015



Sil Pad 400–9 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


1.205


Thermalloy ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Thermalsil II ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


1.045


Shin–Etsu ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TC–30AG ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


1.260



Sil Pad 400–7 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


1.060


Chomerics ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



1.190


Wakefield ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Delta Pad 174–9 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


.755


Bergquist ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sil Pad 1000 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


.935


Ablestik ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Thermal Wafers ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


.990


Thermalloy ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Thermalsil III ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


1.035


Chomerics ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



.655

*Test Fixture Deviation from flat. From Thermalloy EIR86–1010.



Silicon rubber insulators have a number of unusualcharacteristics. Besides being affected by surface flatnessand initial contact pressure, time is a factor. For example, ina study of the Cho–Therm 1688 pad, thermal interfaceimpedance dropped from 0.90C/W to 0.70C/W at the endof 1000 hours. Most of the change occurred during the first200 hours where RθCS measured 0.74C/W. Because the pad“relaxed,” the torque on the conventional mountinghardware had decreased to 3 in.–lb from an initial 6 in.–lb.With nonconformal materials, a reduction in torque wouldhave increased the interface thermal resistance.

Because of the difficulties in controlling all variablesaffecting tests of interface thermal resistance, data fromdifferent manufacturers is not in good agreement. Table 37shows data obtained from two sources. The relativeperformance is the same, except for mica which varieswidely in thickness. At the time of this writing, ASTMCommittee D9 is developing a standard for interfacemeasurements.

The conclusion to be drawn from all this data is that sometypes of silicon rubber pads, mounted dry, will out–performthe commonly used mica with grease. Insulator andassembly cost may be a determining factor in making aselection.

Insulation ResistanceWhen using insulators, care must be taken to keep the

mating surfaces clean. Small particles of foreign matter canpuncture the insulation, rendering it useless or seriouslylowering its dielectric strength. In addition, particularlywhen voltages higher than 300 V are encountered, problemswith creepage may occur. Dust and other foreign materialcan shorten creepage distances significantly, so having aclean assembly area is important. Surface roughness andhumidity also lower insulation resistance. Use of thermalgrease usually raises the breakdown voltage of the insulationsystem but excess grease must be removed to avoidcollecting dust. Because of these factors, which are notamenable to analysis, hi–pot testing should be done onprototypes and a large margin of safety employed.

Insulated Electrode PackagesBecause of the nuisance of handling and installing the

accessories needed for an insulated semiconductormounting, equipment manufacturers have longed forcost–effective insulated packages since the 1950s. The firstto appear were stud–mount types, which usually have a layerof beryllium oxide between the stud hex and the can.Although effective, the assembly is costly and requiresmanual mounting and lead wire soldering to terminals on topof the case. Consequently, few rectifiers are available in aninsulated stud package. In the late 1980s, a number ofelectrically isolated parts became available from varioussemiconductor manufacturers. Insulated parts are generallyhandled the same as their noninsulated counterparts, butsome specify special procedures. With insulated parts it isespecially important to consult manufacturers’ data sheets.

Table 37. Performance of Silicon Rubber InsulatorsTested per MIL–I–49456



Measured Thermal Resistance(C/W)


MaterialÁÁÁÁÁÁÁÁÁÁÁÁ

Thermalloy Data(Note 3)


Berquist Data(Note 4)


Bare Joint, greasedÁÁÁÁÁÁÁÁÁÁÁÁ



BeO, greasedÁÁÁÁÁÁÁÁÁÁÁÁ



Cho–Therm, 1617ÁÁÁÁÁÁÁÁÁÁÁÁ



Q Pad (noninsulated)ÁÁÁÁÁÁÁÁÁÁÁÁ

–ÁÁÁÁÁÁÁÁÁÁ


Sil–Pad, K–10ÁÁÁÁÁÁÁÁÁÁÁÁ



Thermalsil IIIÁÁÁÁÁÁÁÁÁÁÁÁ



Mica, greasedÁÁÁÁÁÁÁÁÁÁÁÁ



Sil–Pad 1000ÁÁÁÁÁÁÁÁÁÁÁÁ



Cho–therm, 1674ÁÁÁÁÁÁÁÁÁÁÁÁ



Thermalsil IIÁÁÁÁÁÁÁÁÁÁÁÁ



Sil–Pad 400ÁÁÁÁÁÁÁÁÁÁÁÁ



Sil–Pad K–4ÁÁÁÁÁÁÁÁÁÁÁÁ


0.440

3. From Thermalloy EIR 87–1030.4. From Berquist Data Sheet.

Fastener and Hardware CharacteristicsCharacteristics of fasteners, associated hardware, and the

tools to secure them determine their suitability for use inmounting the various packages. Since many problems havearisen because of improper choices, the basic characteristicsof several types of hardware are discussed next.

Compression HardwareNormal split–ring lock washers are not the best choice for

mounting power semiconductors. A typical #6 washerflattens at about 50 lb, whereas 150 to 300 lb is needed forgood heat transfer at the interface. A very useful piece ofhardware is the conical compression washer, sometimescalled a Belleville washer. As shown in Figure 227, it has theability to maintain a fairly constant pressure over a widerange of its physical deflection–generally 20% to 80%.When installing, the assembler applies torque until thewasher depresses to half its original height. (Tests should berun prior to setting up the assembly line to determine theproper torque for the fastener used to achieve 50%deflection.) The washer will absorb any cyclic expansion ofthe package, insulating washer, or other materials caused bytemperature changes. Conical washers are the key tosuccessful mounting of devices requiring strict control of themounting force or when plastic hardware is used in themounting scheme. They are used with the large facecontacting the packages. A new variation of the conicalwasher includes it as part of a nut assembly. Called a Sync–Nut [2], the patented device can be soldered to a PC boardand the semiconductor mounted with a 6/32 machine screw.



Figure 227. Characteristics of the ConicalCompression Washers Designed for Use with

Plastic Body–Mounted Semiconductors

80

40

0

120

200

280

240

160

0 20 40 60 80 100

DEFLECTION OF WASHER DURING MOUNTING (%)

PR

ES

SU

RE

ON

PA

CK

AG

E (

LB–F

)

ClipsFast assembly is accomplished with clips. When only a

few watts are being dissipated, the small board–mounted orfree–standing heat dissipators with an integral clip, offeredby several manufacturers, result in a low–cost assembly.When higher power is being handled, a separate clip may beused with larger heatsinks. In order to provide properpressure, the clip must be specially designed for a particularheatsink thickness and semiconductor package.

Clips are especially popular with plastic packages such asthe TO–220. In addition to fast assembly, the clip provideslower interface thermal resistance than other assemblymethods when it is designed for proper pressure to bear onthe top of the plastic over the die. The TO–220 packageusually is lifted up under the die location when mounted witha single fastener through the hole in the tab because of thehigh pressure at one end.

Machine ScrewsMachine screws, conical washers, and nuts (or

Sync–Nuts ) can form a trouble–free fastener system forall types of packages which have mounting holes. However,proper torque is necessary. Torque ratings apply when dry;therefore, care must be exercised when using thermal greaseto prevent it from getting on the threads as inconsistenttorque readings result. Machine screw heads should notdirectly contact the surface of plastic packages as the screwheads are not sufficiently flat to provide properly distributedforce. Without a flat washer under the head, cracking of theplastic case may occur.

Self–Tapping ScrewsUnder carefully controlled conditions, sheet–metal

screws are acceptable. However, during the tapping processwith a standard screw, a volcano–like protrusion develops inthe metal being threaded; an unacceptable surface thatincreases the thermal resistance usually results. Whenstandard sheet metal screws are used, they must be used ina clearance hole to engage a speed–nut. If a self–tappingprocess is desired, the screw type must be used thatroll–forms machine screw threads.

RivetsRivets are not a recommended fastener for any of the

plastic packages. When a rugged metal flange–mountpackage is being mounted directly to a heatsink, rivets canbe used provided press–riveting is used. Crimping forcemust be applied slowly and evenly. Pop–riveting shouldnever be used because the high crimping force causesdeformation of most semiconductor packages. Aluminumrivets are much preferred over steel because less pressure isrequired to set the rivet and thermal conductivity isimproved.

The hollow rivet, or eyelet, is preferred over solid rivets.An adjustable, regulated pressure press is used so that agradually increasing pressure is used to pan the eyelet. Useof sharp blows could damage the semiconductor die.

AdhesivesAdhesives are available [3] that have coefficients of

expansion compatible with copper and aluminum. Highlyconductive types are available; a 10–mil layer hasapproximately 0.3C/W interface thermal resistance.Different types are offered: high–strength types fornonfield–serviceable systems or low–strength types forfield–serviceable systems. Adhesive bonding is attractivewhen case–mounted parts are used in wave–solderingassembly because thermal greases are not compatible withthe conformal coatings used and the greases foul the solderprocess.

Plastic HardwareMost plastic materials will flow, but differ widely in this

characteristic. When plastic materials form parts of thefastening system, compression washers are highly valuableto assure that the assembly will not loosen with time andtemperature cycling. As previously discussed, loss ofcontact pressure increases interface thermal resistance.



Fastening TechniquesEach of the various classes of packages in use requires

different fastening techniques. Details pertaining to eachtype are discussed in following sections. Some generalconsiderations follow.

To prevent galvanic action from occurring when devicesare used on aluminum heatsinks in a corrosive atmosphere,many devices are nickel– or gold–plated. Consequently,precautions must be taken not to mar the finish.

Another factor to be considered is that when acopper–based part is rigidly mounted to an aluminumheatsink, a bimetallic system results that will bend withtemperature changes. Not only is the thermal coefficient ofexpansion different for copper and aluminum, but thetemperature gradient through each metal also causes eachcomponent to bend. If bending is excessive and the packageis rigidly mounted by two or more screws, thesemiconductor chip could be damaged. Bending can beminimized by:

1. Mounting the component with the plane betweenthe screws, parallel to the heatsink fins to provideincreased stiffness.

2. Allowing the heatsink holes to be a bit oversizedso that some slip between surfaces can occur astemperature changes.

3. Using a highly conductive thermal grease ormounting pad between the heatsink andsemiconductor to minimize the temperaturegradient and allow for movement.

Stud MountParts in the stud–mount classification are shown in

Figure 228. Mounting errors with noninsulatedstud–mounted parts are generally confined to application ofexcessive torque or tapping the stud into a threaded heatsinkhole. Both these practices may cause a warpage of the hexbase which may crack the semiconductor die. The only

recommended fastening method is to use a nut and washer;the details are shown in Figure 229.

Insulated electrode packages on a stud–mount baserequire less hardware. They are mounted the same as theirnoninsulated counterparts, but care must be exercised toavoid applying a shear or tension stress to the insulationlayer, usually a beryllium oxide (BeO) ceramic. Thisrequirement dictates that the leads must be attached to thecircuit with flexible wire. In addition, the stud hex should beused to hold the part while the nut is torqued.

Press FitFor most applications, the press–fit case should be

mounted according to the instructions shown in Figure 230.A special fixture meeting the necessary requirements mustbe used.

Flange MountRectifier packages which fit into the flange mount

category are shown in Figure 231. Few known mountingdifficulties exist. The rugged base and distance between dieand mounting holes combine to make it extremely difficultto cause any warpage unless mounted on a surface that isbadly bowed or unless one side is tightened excessivelybefore the other screw is started. It is, therefore, goodpractice to alternate tightening of the screws so that pressureis evenly applied. After the screws are finger–tight, thehardware should be torqued to its final specification in atleast two sequential steps. A typical mounting installationfor a popular flange–type part is shown in Figure 232.Machine screws (preferred), self–tapping screws, eyelets, orrivets may be used to secure the package using guidelines inthe previous section, Fastener and HardwareCharacteristics.

Some packages specify a tightening procedure. Forexample, with the POWERTAP package, Figure 231(b),final torque should be applied first to the center position.

Figure 228. Stud–Mount Rectifier Packages: (a) Standard nonisolated types; (b) Isolated type

CASE 56–03DO–203AA

(DO–4)

CASE 245 CASE 257 CASE 42A(DO–5)

CASE 311(DO–4) DO–203AB

(DO–5)

(a) (b)



Figure 229. Isolating Hardware Used for aNonisolated Stud–Mount Package

INSULATOR

TEFLON BUSHING

INSULATOR

FLAT STEEL WASHER

SOLDER TERMINAL

CONICAL WASHER

HEX NUT

CHASSIS

Tab MountThe tab mount class is also used for rectifier diodes as

illustrated in Figure 233. Mounting considerations aresimilar to that for the popular TO–220 package, whosesuggested mounting arrangements and hardware are shownin Figure 234. The rectangular washer shown in the parts listunder column a is used to minimize distortion of themounting flange; excessive distortion could cause damageto the semiconductor chip. Use of the washer is onlyimportant when the size of the mounting hole exceeds 0.140in. (6/32 clearance). Larger holes are needed toaccommodate the lower insulating bushing when the screwis electrically connected to the case; however, the holesshould not be larger than necessary to provide hardwareclearance and should never exceed a diameter of 0.250 in.Flange distortion is also possible if excessive torque is usedduring mounting. A maximum torque of 8 in.–lb issuggested when using a 6/32 screw.

ÉÉÉÉ

Figure 230. Press–Fit Package

SHOULDER RING

.501.506 DIA.

RIVET

INTIMATECONTACT AREA

CHAMFER

.01 NOM.

HEATSINK

0.0499 0.001 DIA.±

.01 NOM.

COMPLETEKNURL CONTACT

AREA

ADDITIONALHEATSINK PLATE

THIN CHASSIS

HeatSink Mounting

Thin–Chassis Mounting

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉÉÇÇÇÇÇÇÇÇÇÇÇ

.24

The hole edge must be chamfered as shown to prevent shearing off the knurled edge of the case during press–in. The press-ing force should be applied evenly on the shoulder ring to avoid tilting or canting of the case in the hold during the pressingoperation. Also, the use of a thermal joint compound will be of considerable aid. The pressing force will vary from 250 to 1000pounds, depending upon the heatsink material. Recommended harnesses are: copper–less than 50 on the Rockwell F scale;Aluminum–less than 65 on the Brinell scale. A heatsink as thin as 1/8 may be used, but the interface thermal resistance willincrease in direct proportion to the contact area. A thin chassis requires the addition of a backup plate.



Figure 231. Flange–Mount Packages Used for Rectifiers

(a) TO–3 Variations (b) Plastic Power Tap

CASE 1, 3, 11TO–204AA

(TO–3)CASE 383 CASE 357B

Figure 232. Hardware Used for a TO–204AA (TO–3) Flange–Mount Part

NO. 6 SHEET METAL SCREWS

INSULATOR

INSULATINGBUSHING

SOCKET

POWERTRANSISTOR

HEATSINK

Figure 233. Several Types of Tab–Mount Parts

TO–220 AB TO–220AC



Care should be exercised to assure that the tool used todrive the mounting screw never comes in contact with theplastic body during the driving operation. Such contact canresult in damage to the plastic body and internal deviceconnections. To minimize this problem, some TO–220packages have a chamfer on one end. Packages without achamfer require a spacer or combination spacer andisolation bushing to raise the screw head above the topsurface of the plastic.

The popular TO–220 package and others of similarconstruction, lift off the mounting surface as pressure isapplied to one end. (See Appendix A, Figure 236) To counter

this tendency, at least one hardware manufacturer [4] offersa hard plastic cantilever beam that applies more evenpressure on the tab. In addition, it separates the mountingscrew from the metal tab. Tab mount parts may also beeffectively mounted with clips as shown in Figure 235. Toobtain high pressure without cracking the case, a pressurespreader bar should be used under the clip. Interface thermalresistance with the cantilever beam or clips can be lowerthan with screw mounting.

In situations where a tab mount package is making directcontact with the heatsink, an eyelet may be used; providedsharp blows or impact shock is avoided.

4–40 PAN OR HEX HEAD SCREW

Figure 234. Mounting Arrangements for Tab Mount TO–220 Package

6–32 HEXHEAD SCREW

(1) RECTANGULAR STEELWASHER

SEMICONDUCTOR(CASE 221,#221A)

(2) RECTANGULARINSULATOR

HEATSINK

(2) BUSHING

(3) FLAT WASHER

(4) CONICAL WASHER

6–32 HEX NUT

FLAT WASHER

INSULATING BUSHING

RECTANGULARINSULATOR

COMPRESSION WASHER

4–40 HEX NUT

HEATSINK

SEMICONDUCTOR(CASE 221,#221A)

(1) Used with thin chassis and/or large hole.(2) Used when isolation is required.(3) Required when nylon bushing is used.

a) Preferred Arrangement for Iso-lated or Nonisolated Mounting.Screw is at Semiconductor CasePotential. 6–32 Hardware is Used.Choose from Parts Listed Below.

b) Alternate Arrangement for IsolatedMounting when Screw must be at HeatsinkPotential. 4–40 Hardware is Used.Use Parts Listed Below.



Figure 235. Clip Mounting a TO–220 Mount Package

HEATSINK

CLIP

References1. Catalog #87–HS–9, page 8; Thermalloy, Inc., P.O.

Box 810839, Dallas, Texas 75381–0839.2. ITW Shakeproof, St. Charles Road, Elgin, IL

60120.

3. Robert Baston, Elliot Fraunglass and James P.Moran, “Heat Dissipation Through ThermallyConductive Adhesives,” EMTAS ‘83 Conference,Feb. 1–3, Phoenix, AZ.

4. Catalog, Edition 18, Richco Plastic Co., 5825 N.Tripp Ave., Chicago, IL 60546.



Appendix A

Measurement of Interface Thermal Resistance



Measuring the interface thermal resistance RθCS appearsdeceptively simple. All that’s apparently needed is athermocouple on the semiconductor case, a thermocoupleon the heatsink, and a means of applying and measuring DCpower. However, RθCS is proportional to the amount ofcontact area between the surfaces and consequently isaffected by surface flatness and finish and the amount ofpressure on the surfaces. The fastening method may also bea factor. In addition, placement of the thermocouples canhave a significant influence upon the results. Consequently,values for interface thermal resistance presented by differentmanufacturers are not in good agreement. Fasteningmethods and thermocouple locations are considered in thisAppendix.

When fastening the test package in place with screws,thermal conduction may take place through the screws, forexample, from the flange ear on a TO–3 package directly tothe heatsink. This shunt path yields values which areartificially low for the insulation material and dependentupon screw head contact area and screw material.MIL–I–49456 allows screws to be used in tests for interfacethermal resistance probably because it can be argued thatthis is “application oriented.”

Thermalloy takes pains to insulate all possible shuntconduction paths in order to more accurately evaluateinsulation materials. The ON Semiconductor fixture uses aninsulated clamp arrangement to secure the package whichalso does not provide a conduction path.

As described previously, some packages, such as aTO–220, may be mounted with either a screw through thetab or a clip bearing on the plastic body. These two methodsoften yield different values for interface thermal resistance.Another discrepancy can occur if the top of the package isexposed to the ambient air where radiation and convectioncan take place. To avoid this, the package should be coveredwith insulating foam. It has been estimated that a 15 to 20%error in RθCS can be incurred from this source.

Another significant cause for measurement discrepanciesis the placement of the thermocouple to measure thesemiconductor case temperature. Consider the TO–220package shown in Figure 236. The mounting pressure at oneend causes the other end – where the die is located – to liftoff the mounting surface slightly. To improve contact, ONSemiconductor TO–220 Packages are slightly concave. Useof a spreader bar under the screw lessens the lifting, but someis inevitable with a package of this structure. Threethermocouple locations are shown:

1. The ON Semiconductor location is directly underthe die reached through a hole in the heatsink. Thethermocouple is held in place by a spring whichforces the thermocouple into intimate contact withthe bottom of the semi’s case.

1. The JEDEC location is close to the die on the topsurface of the package base reached through a blindhole drilled through the molded body. Thethermocouple is swaged in place.

2. The Thermalloy location is on the top portion of thetab between the molded body and the mounting screw.The thermocouple is soldered into position.

ON Semiconductor

DIEE.I.A.

THERMALLOY

Figure 236. JEDEC TO–220 Package Mounted toHeatsink Showing Various Thermocouple Locations

and Lifting Caused by Pressure at One End

Temperatures at the three locations are generally not thesame. Consider the situation depicted in the figure. Becausethe only area of direct contact is around the mounting screw,nearly all the heat travels horizontally along the tab from thedie to the contact area. Consequently, the temperature at theJEDEC location is hotter than at the Thermalloy locationand the ON Semiconductor location is even hotter. Sincejunction–to–sink thermal resistance must be constant for agiven test setup, the calculated junction–to–case thermalresistance values decrease and case–to–sink values increaseas the “case” temperature thermocouple readings becomewarmer. Thus, the choice of reference point for the “case”temperature is quite important.

There are examples where the relationship between thethermocouple temperatures are different from the previoussituation. If a mica washer with grease is installed betweenthe semiconductor package and the heatsink, tightening thescrew will not bow the package; instead, the mica will bedeformed. The primary heat conduction path is from the diethrough the mica to the heatsink. In this case, a smalltemperature drop will exist across the vertical dimension ofthe package mounting base so that the thermocouple at theJEDEC location will be the hottest. The thermocoupletemperature at the Thermalloy location will be lower, butclose to the temperature at the JEDEC location as the lateralheat flow is generally small. The ON Semiconductorlocation will be coolest.



The JEDEC location is chosen to obtain the highesttemperature on the case. It is of significance because powerratings are supposed to be based on this reference point.Unfortunately, the placement of the thermocouple is tediousand leaves the semiconductor in a condition unfit for sale.

The ON Semiconductor location is chosen to obtain thehighest temperature of the case at a point where, hopefully,the case is making contact to the heatsink. Once the specialheatsink, to accommodate the thermocouple has beenfabricated, this method lends itself to production testing anddoes not mark the device. However, this location is not easilyaccessible to the user.

The Thermalloy location is convenient and is often chosenby equipment manufacturers. However, it also blemishes thecase and may yield results differing up to 1°C/W for aTO–220 package mounted to a heatsink without thermalgrease and no insulator. This error is small when comparedto the thermal resistance of heat dissipaters often used withthis package, since power dissipation is usually a few watts.When compared to the specified junction–to–case values of

some of the higher power semiconductors becomingavailable, however, the difference becomes significant andit is important that the semiconductor manufacturer andequipment manufacturer use the same reference point.

Another JEDEC method of establishing referencetemperatures utilizes a soft copper washer (thermal greaseis used) between the semiconductor package and theheatsink. The washer is flat to within 1 mil/inch, has a finishbetter than 63 µ–inch, and has an imbedded thermocouplenear its center. This reference includes the interfaceresistance under nearly ideal conditions and is, therefore,application–oriented. It is also easy to use, but has notbecome widely accepted.

A good way to improve confidence in the choice of casereference point is to also test for junction–to–case thermalresistance while testing for interface thermal resistance. Ifthe junction–to–case values remain relatively constant asinsulators are changed, torque varied, etc., then the casereference point is satisfactory.



Appendix B

NCP1200 10 W AC/DC Power Supply



'()**

VCC

K2TL431

IC1SFH6156–2

L12 x 27 mHCM

C322 µF16 V

C7100 µF/16 V

C6470 nF16 V

12 V @ 0.85

D2MBRS360T3

+

AdjFB

CS1

Gnd Drv

HV1

2

3

4

8

7

6

UniversalInput

M1MTP2N60E

+B1SMD

+

Ground

L222 µH

D3MUR160

T1

C52.2 nFY Type

R41.51 W

C247 µF400 V

R110

5

C91 nF

R61 k

R53.9 k

C4100 nF

R422 k2 WC8

10 nF400 V

R3560

+ C8470 nF16 V

1:0.1

R21 Meg

C1100 nFX2

Lp1.8 mH

NCP1200

Figure 237. A complete 10 W AC/DC wall adapter featuring an EMI filter.

Additional InformationThe following information is available on our web site at

www.onsemi.com or from the ON SemiconductorLiterature Distribution Center at 1–800–344–3860 or1–303–675–2175 in hard copy or CDROM

1. NCP1200/D, Technical Data Sheet, “PWMCurrent–Mode Controller for Low–PowerUniversal Off–Line Supplies.”

2. AND8032/D, Application Note, “Conducted EMIFilter Design for the NCP1200.”, ChristopheBasso.

3. NCP1200PAK/D, “NCP1200 Literature Pack.”4. MBRS320T3/D, Technical Data Sheet, “Surface

Mount Schottky Power Rectifier.”5. MUR120/D, Technical Data Sheet, “ MUR120

Series, SWITCHMODE Power Rectifiers.”



Index

Alphabetical Subject Index



Alphabetical Subject Index

AAdhesives 248. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analysis of Rectifiers with Capacitor–Input Systems 116. . . . . . . .

Appendix A 255. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application and Characteristics of Heatsinks 218. . . . . . . . . . . . . .

Assembly Considerations for Printed Circuit Boards 225. . . . . . . .

Autoclave 205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Average Forward Current (IO) 82. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Average Forward Voltage (VF(AV)) 79. . . . . . . . . . . . . . . . . . . . . . . .

Average Reverse Current IR(AV) 78. . . . . . . . . . . . . . . . . . . . . . . . . .

BBaker Clamp 175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Diode Functions in Power Electronics 155. . . . . . . . . . . . . . .

Basic Operation 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Single–Phase Rectifying Circuits 91. . . . . . . . . . . . . . . . . . . .

Basic Thermal Properties of Semiconductors 33. . . . . . . . . . . . . . .

Behavior of Rectifiers Used with Capacitor–Input Filters 115. . . . .

Behavior of Rectifiers with Choke–Input Filters 111. . . . . . . . . . . . .

Board Materials 230. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Breakdown Voltage 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CCapacitance 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case–Mounted Rectifiers 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Catching 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Circuit Variations 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamping 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clipping 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clips 248. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Common Polyphase Rectifier Circuits 101, 103. . . . . . . . . . . . . . . .

Comparison of Capacitor–Input andInductance–Input Systems 122. . . . . . . . . . . . . . . . . . . . . . . . .

Comparison of Circuits 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Component Placement 222. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Compression Hardware 247. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Concepts 197. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C (continued)

Conduction 212. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Conductive Pads 244. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Constant Acceleration 205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact Spiking 201. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Convection 212. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Cooling Principles 211. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Corrosion of Metallization and Bond Pads 201. . . . . . . . . . . . . . . . .

Cracking in Plastic Packages 203. . . . . . . . . . . . . . . . . . . . . . . . . . .

Current Ratings 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current Relationships 92, 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Cycled Temperature Humidity Bias 205. . . . . . . . . . . . . . . . . . . . . . .

DDC Forward Voltage (VF) 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC Reverse Blocking Voltage (VR) 77. . . . . . . . . . . . . . . . . . . . . . . .

DC Reverse Current (IR) 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Derating 198. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Design for Reliability 198, 203. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Design of Capacitor–Input Filters 117. . . . . . . . . . . . . . . . . . . . . . . .

Design Tradeoffs 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Die Adhesion Fatigue 202. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Die Fracture 202. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diode Peak Inverse Voltage 120. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diode Selection 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Doping of Semiconductors 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Drive Circuits for Bipolar Power Transistors 175. . . . . . . . . . . . . . .

Drive Circuits for Power MOSFETs 175. . . . . . . . . . . . . . . . . . . . . .

Dynamic Switching 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EElectrical Overstress 199. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electromigration 200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example of Power Supply Design 126. . . . . . . . . . . . . . . . . . . . . . . .

Example Parameter Extractions for the MURHB4OCT Diode 62. .

Example Peak Temperature Calculations 43. . . . . . . . . . . . . . . . . .

Externally Generated Voltage Surges 141. . . . . . . . . . . . . . . . . . . .



FFailure Data Collection and Analysis 199. . . . . . . . . . . . . . . . . . . . .

Failure Modes, Effects, and Criticality Analysis (FMECA) 199. . . .

Fan Laws 221. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fastener and Hardware Characteristics 247. . . . . . . . . . . . . . . . . . .

Fastening Techniques 249. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Filter Component Selection 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Filter Sections 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fin Efficiency 216. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fixed Drive Circuit 177. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Flange Mount 249. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Flux and Post Solder Cleaning 236. . . . . . . . . . . . . . . . . . . . . . . . . .

Flyback Converter 185. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Forced Commutation Analysis 164. . . . . . . . . . . . . . . . . . . . . . . . . .

Forced Convection 214. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Form Factor 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Formation of Energy Bands 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Forward Bias 18, 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Forward Bias (VA>0) and Reverse Bias (VA<0) 20. . . . . . . . . . . . .

Forward Converter 187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Forward DC Characteristics (IS, RS, N) 56, 63. . . . . . . . . . . . . . . .

Forward Power Dissipation 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Forward Recovery 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Forward Voltage 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Freewheeling 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fusing Considerations 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GGeneral Relationships in Polyphase Rectifiers 101. . . . . . . . . . . . . .

Graded Filters 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HHandling Nonrectangular Pulses 41. . . . . . . . . . . . . . . . . . . . . . . . . .

Harmonics 94, 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Heatsink Mounting Considerations 241. . . . . . . . . . . . . . . . . . . . . . .

Heatsinks for Forced Air Cooling 220. . . . . . . . . . . . . . . . . . . . . . . .

Heatsinks for Free Convection Cooling 218. . . . . . . . . . . . . . . . . . .

High–Current Parallel–Connected Diodes 107. . . . . . . . . . . . . . . . .

High–Order Cascade Voltage Multipliers 137. . . . . . . . . . . . . . . . . .

High–Temperature Operating Life 204. . . . . . . . . . . . . . . . . . . . . . . .

Hillock Formation 200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IInput Inductance Requirements 114. . . . . . . . . . . . . . . . . . . . . . . . .

Insertion Mounting 225. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Insulated Electrode Packages 247. . . . . . . . . . . . . . . . . . . . . . . . . . .

Insulation Considerations 244. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Insulation Resistance 247. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interface Decisions 243. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internally Generated Voltage Surges 145. . . . . . . . . . . . . . . . . . . . .

Ionic Contamination 200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JJunction Capacitance Characteristics (CEO, VJ, M, FC) 58. . . . . .

Junction Capacitance Characteristics (CJO, VJ, M, FC) 67. . . . . .

LLayout Considerations 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead Integrity 206. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead–Mounted Parts 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Liquid Cooling 221. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Low–Temperature Operating Life 205. . . . . . . . . . . . . . . . . . . . . . . .

MMachine Screws 248. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum (Peak) Forward Voltage (VFM) 79. . . . . . . . . . . . . . . . . . .

Maximum or Peak Reverse Current (IRRM) 78. . . . . . . . . . . . . . . . .

Mechanical Shock 205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Metal–Semiconductor Junctions 19. . . . . . . . . . . . . . . . . . . . . . . . . .

Metallization Migration 201. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mounting Holes 242. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mounting Surface Preparation 241. . . . . . . . . . . . . . . . . . . . . . . . . . .

Multiple Chip Devices 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NNatural Convection 213. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OOff–Line AC–DC Converters 191. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Overlap 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Overvoltage Snubbers 183. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .



PPassive Component Selection 126. . . . . . . . . . . . . . . . . . . . . . . . . .

Peak Nonrepetitive Reverse Voltage (VRSM) 77. . . . . . . . . . . . . . . .

Peak Repetitive Reverse Voltage (VRRM) 77. . . . . . . . . . . . . . . . . .

Peak Surge Forward Current (IFSM) 83. . . . . . . . . . . . . . . . . . . . . . .

Peak Working Reverse Voltage (VRWM) 77. . . . . . . . . . . . . . . . . . .

Plastic Hardware 248. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

pn Junctions 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Polyphase Rectifier Circuits 101. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Circuit Load Lines 179. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Conversion Circuits 184. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Cycling 205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Electronic Circuits 175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Rectifier Device Physics and Electrical Characteristics 9. .

Power Temperature Cycling 205. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Practical Aspects of Semiconductor Reliability 199. . . . . . . . . . . . .

Practical Drive Circuit Problems 167. . . . . . . . . . . . . . . . . . . . . . . . .

Press Fit 249. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pressure/Temperature/Humidity Bias (PTHB) 205. . . . . . . . . . . . . .

Process Capability 207. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Proportional Drive Circuit 178. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Push–Pull DC–DC Converters 187. . . . . . . . . . . . . . . . . . . . . . . . . .

RRadiation 214. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Real Diode Characteristics 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Rectification Ratio 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Rectification Ratios 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Rectification, Continuous Mode 163. . . . . . . . . . . . . . . . . . . . . . . . . .

Rectification, Discontinuous Mode 156. . . . . . . . . . . . . . . . . . . . . . .

Rectifier Diode Specifications and Ratings 75. . . . . . . . . . . . . . . . .

Rectifier Filter Systems 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Rectifier Voltage Multiplier Circuits 131. . . . . . . . . . . . . . . . . . . . . . .

Reliability Considerations 197. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reliability Testing 204. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reverse Bias 18, 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reverse Breakdown Characteristics (BV, IBV) 62, 70. . . . . . . . . . .

Reverse Breakdown Voltage V(BR) 78. . . . . . . . . . . . . . . . . . . . . . . .

Reverse Current 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

R (continued)

Reverse Recovery 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reverse Recovery Time Characteristics (TT) 59, 69. . . . . . . . . . . . .

Ripple 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ripple Factor 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Rivets 248. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SSecond Breakdown 199. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Self–Tapping Screws 248. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Semiaqueous Cleaning Process 237. . . . . . . . . . . . . . . . . . . . . . . . .

Semiconductor Junctions 17, 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Silicon Temperature Coefficient Formula for Forward Voltage 29. .

Six–Phase Full–Wave Bridge Circuits 106. . . . . . . . . . . . . . . . . . . .

Six–Phase Star Rectifier Circuit 106. . . . . . . . . . . . . . . . . . . . . . . . .

Snubber Diode Requirements 184. . . . . . . . . . . . . . . . . . . . . . . . . . .

Solder Heat 206. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Solderability 206. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SPC Implementation and Use 208. . . . . . . . . . . . . . . . . . . . . . . . . . .

SPICE Diode Model Parameter Extraction Methods 56. . . . . . . . . .

SPICE Diode Model Parameter Limitations and Restrictions 55. . .

Statistical Process Control 206. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stress Analysis 198. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stress Corrosion in Packages 201. . . . . . . . . . . . . . . . . . . . . . . . . . .

Stress Screening 198. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stud Mount 249. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Surface Finish 241. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Surface Flatness 241. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Surface Properties of Semiconductors 15. . . . . . . . . . . . . . . . . . . . .

Surface Treatment 242. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Surface–Mount Assembly 234. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Surface–Mount Rectifier Packages 228. . . . . . . . . . . . . . . . . . . . . .

Surface–Mount Technology 226. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Surge Current 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Surge Current Protection 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Surge Protection Circuits 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Switching 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synchronous Rectification 192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Architecture and Device Specification 198. . . . . . . . . . . . .



TTab Mount 250. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature and Area Effects 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Characteristics (EG, XTI) 61, 69. . . . . . . . . . . . . . . . . Temperature Cycle 204. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature/Humidity Bias (THB) 205. . . . . . . . . . . . . . . . . . . . . . . The Diode Model versus a Real Diode 53. . . . . . . . . . . . . . . . . . . . . The Diode Snubber 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Electrical Resistivity and Conductivity of Silicon and

Gallium Arsenide 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Fermi Level Concept 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Large–Signal DC Model 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Noise Model 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Small–Signal AC Model 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . The SPICE Diode Model 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Compounds (Grease) 243. . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Management of Surface–Mount Rectifiers 229. . . . . . . . . Thermal Models 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance Concepts 211. . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Response 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Runaway 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Shock 204. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three–Phase Double–Wye Rectifier with

Interphase Transformer 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . Three–Phase Full–Wave Bridge Circuit 105. . . . . . . . . . . . . . . . . . . Three–Phase Half–Wave Star Rectifier Circuit 103. . . . . . . . . . . . . Three–Phase lnter–Star Rectifier Circuit 104. . . . . . . . . . . . . . . . . . Transformer Considerations 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . Transformer Selection 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transformer Utilization 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient Protection of Rectifier Diodes 141. . . . . . . . . . . . . . . . . . . Transient Response of Semiconductors 38. . . . . . . . . . . . . . . . . . . Transistor Snubber Circuits 179. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn–Off Snubbers 182. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn–On Snubbers 180. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

U“Universal” Input Circuit 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use of Thermal Response Data 40. . . . . . . . . . . . . . . . . . . . . . . . . . Utilization Factor 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VVariable Frequency Vibration 206. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage and Current Relations in Filters 123. . . . . . . . . . . . . . . . . . .

Voltage Quadruples 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage Ratings 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage Regulation in Choke Input Systems 115. . . . . . . . . . . . . . .

Voltage Relationships 95, 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage Tripling Circuits 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage–Doubling Circuits 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

WWire Bond Fatigue 202. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Wire Fatigue 202. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .



ON SEMICONDUCTOR MAJOR WORLDWIDE SALES OFFICESAND REPRESENTATIVES

UNITED STATES

ALABAMAHuntsville 256–774–1000. . . . . . . . . . . . . . . . . .

CALIFORNIAEncino 818–654–9040. . . . . . . . . . . . . . . . . . . . . Irvine 949–623–8485. . . . . . . . . . . . . . . . . . . . . . Sacramento (Sales Rep) 916–652–0268. . . . . . San Diego 858–621–5100. . . . . . . . . . . . . . . . . Santa Clara (Sales Rep) 408–350–4800. . . . . . .

COLORADOLittleton 303–256–5884. . . . . . . . . . . . . . . . . . . .

FLORIDABoca Raton 561–995–1466. . . . . . . . . . . . . . . . Tampa 813–286–6181. . . . . . . . . . . . . . . . . . . . .

GEORGIADuluth 888–793–3435. . . . . . . . . . . . . . . . . . . . .

ILLINOISChicago 847–330–6959. . . . . . . . . . . . . . . . . . .

INDIANAKokomo 765–865–2085. . . . . . . . . . . . . . . . . . . Carmel (Sales Rep) 317–848–9958. . . . . . . . . . .

MASSACHUSETTSBoston 781–376–4223. . . . . . . . . . . . . . . . . . . .

MICHIGANLivonia 734–953–6704. . . . . . . . . . . . . . . . . . . .

MINNESOTAPlymouth 763–249–2360. . . . . . . . . . . . . . . . . .

NORTH CAROLINARaleigh 919–785–5025. . . . . . . . . . . . . . . . . . . .

PENNSYLVANIAPhiladelphia/Horsham 215–997–4340. . . . . . .

TEXASDallas (Sales Rep) 972–680–2800. . . . . . . . . . . .

UNITED STATES (continued)UTAH

Draper (Sales Rep) 801–572–4010. . . . . . . . . . . WASHINGTON

Seattle 425–646–7374. . . . . . . . . . . . . . . . . . . . WASHINGTON, D.C.

410–884–4086. . . . . . . . . . . . . . . . . . . . . . . . . . .

CANADAQUEBEC

Pointe Claire 514–695–4599. . . . . . . . . . . . . . . ONTARIO

Toronto 905–812–0092. . . . . . . . . . . . . . . . . . . .

INTERNATIONALBRAZIL

Sao Paulo 55–011–3030–5244. . . . . . . . . . . . . CHINA

Beijing 86–10–8518–2323. . . . . . . . . . . . . . . . . Chengdu 86–28–678–4078. . . . . . . . . . . . . . . . . Shenzhen 86–755–209–1128. . . . . . . . . . . . . . . Shanghai 86–21–6875–6677. . . . . . . . . . . . . .

CZECH REPUBLICRoznov 420 (0) 651–667–141. . . . . . . . . . . . . .

FINLANDVantaa 358 (0) 9–85–666–460. . . . . . . . . . . . .

FRANCEParis 33 (0) 1–39–26–41–00. . . . . . . . . . . . . . .

GERMANYMunich 49 (0) 89–93–0808–0. . . . . . . . . . . . . .

HONG KONGHong Kong 852–2689–0088. . . . . . . . . . . . . . . .

INTERNATIONAL (continued)ISRAEL

Herzelia 972 (0) 9–9609–111. . . . . . . . . . . . . . ITALY

Milan 39 (0) 2–530–0951. . . . . . . . . . . . . . . . . . JAPAN

Tokyo 81–3–5740–2700. . . . . . . . . . . . . . . . . . . KOREA

Seoul 82–2–528–2700. . . . . . . . . . . . . . . . . . . . . MALAYSIA

Penang 60–4–226–9368. . . . . . . . . . . . . . . . . . . MEXICO

Guadalajara 523–669–9100. . . . . . . . . . . . . . . . PHILIPPINES

Muntinlupa City 63–2–842–7141. . . . . . . . . . . . PUERTO RICO

San Juan 787–641–4100. . . . . . . . . . . . . . . . . . SINGAPORE

Singapore 65–298–1768. . . . . . . . . . . . . . . . . . . SWEDEN

Solna 46 (0) 8–5090–4680. . . . . . . . . . . . . . . . . TAIWAN

Taipei 886–2–2718–9961. . . . . . . . . . . . . . . . . THAILAND

Bangkok 66–2–653–5031. . . . . . . . . . . . . . . . . . UNITED KINGDOM

Aylesbury 44 (0) 1296–610400. . . . . . . . . . . . .

N. AMERICAN TECHNICAL SUPPORT1–800–282–9855 Toll Free


ON SEMICONDUCTOR STANDARD DOCUMENT TYPE DEFINITIONS

DATA SHEET CLASSIFICATIONS

A Data Sheet is the fundamental publication for each individual product/device, or series of products/devices, containing detailedparametric information and any other key information needed in using, designing–in or purchasing of the product(s)/device(s) it describes.Below are the three classifications of Data Sheet: Product Preview; Advance Information; and Fully Released Technical Data

PRODUCT PREVIEW

A Product Preview is a summary document for a product/device under consideration or in the early stages of development. TheProduct Preview exists only until an “Advance Information” document is published that replaces it. The Product Preview is oftenused as the first section or chapter in a corresponding reference manual. The Product Preview displays the following disclaimer atthe bottom of the first page: “This document contains information on a product under development. ON Semiconductor reserves theright to change or discontinue this product without notice.”

ADVANCE INFORMATION

The Advance Information document is for a device that is NOT fully qualified, but is in the final stages of the release process,and for which production is eminent. While the commitment has been made to produce the device, final characterization andqualification may not be complete. The Advance Information document is replaced with the “Fully Released Technical Data”document once the device/part becomes fully qualified. The Advance Information document displays the following disclaimer atthe bottom of the first page: “This document contains information on a new product. Specifications and information herein are subjectto change without notice.”

FULLY RELEASED TECHNICAL DATA

The Fully Released Technical Data document is for a product/device that is in full production (i.e., fully released). It replaces theAdvance Information document and represents a part that is fully qualified. The Fully Released Technical Data document is virtuallythe same document as the Product Preview and the Advance Information document with the exception that it provides informationthat is unavailable for a product in the early phases of development, such as complete parametric characterization data. The FullyReleased Technical Data document is also a more comprehensive document than either of its earlier incarnations. This documentdisplays no disclaimer, and while it may be informally referred to as a “data sheet,” it is not labeled as such.

DATA BOOK

A Data Book is a publication that contains primarily a collection of Data Sheets, general family and/or parametric information,Application Notes and any other information needed as reference or support material for the Data Sheets. It may also contain cross referenceor selector guide information, detailed quality and reliability information, packaging and case outline information, etc.

APPLICATION NOTE

An Application Note is a document that contains real–world application information about how a specific ON Semiconductordevice/product is used, or information that is pertinent to its use. It is designed to address a particular technical issue. Parts and/or softwaremust already exist and be available.

SELECTOR GUIDE

A Selector Guide is a document published, generally at set intervals, that contains key line–item, device–specific information forparticular products or families. The Selector Guide is designed to be a quick reference tool that will assist a customer in determining theavailability of a particular device, along with its key parameters and available packaging options. In essence, it allows a customer to quickly“select” a device. For detailed design and parametric information, the customer would then refer to the device’s Data Sheet. The MasterComponents Selector Guide (SG388/D) is a listing of ALL currently available ON Semiconductor devices.

REFERENCE MANUAL

A Reference Manual is a publication that contains a comprehensive system or device–specific descriptions of the structure and function(operation) of a particular part/system; used overwhelmingly to describe the functionality or application of a device, series of devices ordevice category. Procedural information in a Reference Manual is limited to less than 40 percent (usually much less).

HANDBOOK

A Handbook is a publication that contains a collection of information on almost any give subject which does not fall into the ReferenceManual definition. The subject matter can consist of information ranging from a device specific design information, to system design, toquality and reliability information.

ADDENDUM

A documentation Addendum is a supplemental publication that contains missing information or replaces preliminary information in theprimary publication it supports. Individual addendum items are published cumulatively. The Addendum is destroyed upon the next revisionof the primary document.

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Rectifier ApplicationsHandbook

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800-282-9855 Toll Free USA/Canada

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