Reconfigurable Communication System

DesignAnthony GaughtAnthony Gaught

Advisors:Advisors:Dr. In Soo Ahn and Dr. Yufeng LuDr. In Soo Ahn and Dr. Yufeng Lu

Department of Electrical and Computer EngineeringDepartment of Electrical and Computer EngineeringBradley University Peoria, IllinoisBradley University Peoria, Illinois

November 13, 2012November 13, 2012

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OutlineOutline

MotivationMotivation Brief Theory of QPSKBrief Theory of QPSK Project OverviewProject Overview Project DescriptionProject Description Project MilestonesProject Milestones SimulationSimulation Project StatusProject Status ConclusionsConclusions ReferencesReferences

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MotivationMotivation

Software defined radio (SDR) has Software defined radio (SDR) has advantages over traditional advantages over traditional communication systems.communication systems.

Design a reconfigurable digital Design a reconfigurable digital communication system using FPGA.communication system using FPGA.

QPSK system is studied for the project.QPSK system is studied for the project.

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Brief Theory of QPSKBrief Theory of QPSK

Binary phase shift keying (BPSK) is a modulation Binary phase shift keying (BPSK) is a modulation scheme which transmits one bit of data per symbol.scheme which transmits one bit of data per symbol.

Quadrature phase shift keying (QPSK) cuts the Quadrature phase shift keying (QPSK) cuts the bandwidth necessary to transmit data in half when bandwidth necessary to transmit data in half when compared to BPSK.compared to BPSK.

QPSK’s bit error performance is the same as that of QPSK’s bit error performance is the same as that of BPSK due to orthogonality of the I and Q carriers BPSK due to orthogonality of the I and Q carriers used in QPSK.used in QPSK.

QPSK is used in many applications such as cell QPSK is used in many applications such as cell phones, satellite communication, cable modems, phones, satellite communication, cable modems, and others.and others.

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Brief Theory of QPSKBrief Theory of QPSK

s(t) = I(t)*cos(2s(t) = I(t)*cos(2ππffoot) – Q(t)*sin(2t) – Q(t)*sin(2ππffoot)t)

Each symbol Each symbol represents two bits of represents two bits of data.data.

I and Q bits are I and Q bits are determined based on determined based on the phase of the the phase of the received symbol.received symbol.

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Project OverviewProject Overview

This project implements a QPSK This project implements a QPSK communication system consisting of both communication system consisting of both a transmitter and a receiver.a transmitter and a receiver.

The system is designed using VHDL and is The system is designed using VHDL and is implemented on Xilinx Spartan 3E FPGAs. implemented on Xilinx Spartan 3E FPGAs.

Allows for flexible transmission data rates.Allows for flexible transmission data rates.

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Project DescriptionProject Descriptionat the transmitterat the transmitter

Two-bit random data is generated.Two-bit random data is generated. The data is split into In-phase (I) and The data is split into In-phase (I) and

quadrature-phase (Q) components.quadrature-phase (Q) components. The data is shaped using raised cosine filters.The data is shaped using raised cosine filters. The data is over sampled.The data is over sampled. The data is modulated by cosine and sine The data is modulated by cosine and sine

carriers.carriers. The modulated signals are combined for The modulated signals are combined for

transmission.transmission.

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Project DescriptionProject Descriptionat the receiverat the receiver

The received signal is demodulated by The received signal is demodulated by local cosine and sine carriers.local cosine and sine carriers.

The data passes through a matched filter.The data passes through a matched filter. The data is down sampled. The data is down sampled. The data is fed into a threshold device.The data is fed into a threshold device. The output is displayed on an oscilloscope.The output is displayed on an oscilloscope.

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Milestone OneMilestone One The receiver and transmitter will be The receiver and transmitter will be

implemented on a single FPGA.implemented on a single FPGA. The transmitter is connected directly to The transmitter is connected directly to

the receiver.the receiver. A digital to analog converter (DAC) will be A digital to analog converter (DAC) will be

used to display data.used to display data.

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Milestone One Block Milestone One Block DiagramDiagram

I = transmitter side in-phase Q = transmitter side quadrature phaseI_r = receiver side in-phase Q_r = receiver side quadrature phaseS(n) = internal signal from transmitter to receiver

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Milestone TwoMilestone Two

The receiver and transmitter will be The receiver and transmitter will be implemented on different FPGA boards.implemented on different FPGA boards.

Data will pass through an (ADC) and a DAC Data will pass through an (ADC) and a DAC in this milestone.in this milestone.

A carrier recovery circuit and phase locked A carrier recovery circuit and phase locked loop will be implemented in the receiver.loop will be implemented in the receiver.

Adverse affects caused by channel Adverse affects caused by channel imperfections will be explored.imperfections will be explored.

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Milestone Two & Three Milestone Two & Three Block DiagramBlock Diagram

I = transmitter side in-phase Q = transmitter side quadrature phaseI_r = receiver side in-phase Q_r = receiver side quadrature phaseS(t) = signal from transmitter to receiver

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Milestone ThreeMilestone Three

High speed ADC and DAC modules will be High speed ADC and DAC modules will be used to connect the transmitter and used to connect the transmitter and receiver for assessing overall system receiver for assessing overall system operations.operations.

Bit error rate of the system will be used to Bit error rate of the system will be used to evaluate the overall system performance.evaluate the overall system performance.

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Simulation Results

I and Q data at the transmitter

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Simulation Results

The I and Q data are shaped using a set of raised cosine filters for controlling intersymbol interference.

0 5 10 15 20 25 30-20

0

20

40

60

80

# of Filter coefficients

Impulse Response of Raised Cosine Filter1515

Simulation Results

The recovered I and Q after being filtered are identical to theoretical results from MATLAB simulations.

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Simulation Results

The demodulated I and Q data match up with their theoretical results.

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Simulation Results

The demodulated I and Q data are then resized to bring the amplitude into a usable range for the Spartan 3E.

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Simulation Results

Received I and Q data appear as a constellation of 4 groups of points which matches the theoretical results well.

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Simulation Results

Transmitted and received I and Q data.

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Simulation Results

The transmitted and received I and Q data after being cleaned up by using a threshold device.

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Project StatusProject Status

Milestone one has been completed.Milestone one has been completed. Preliminary work for Milestone two has Preliminary work for Milestone two has

begun.begun. One of the biggest obstacles will be the One of the biggest obstacles will be the

implementation of the phase locked loop.implementation of the phase locked loop.

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ScheduleSchedule

1/24 - 2/07 phase locked loop and carrier recovery 1/24 - 2/07 phase locked loop and carrier recovery implementationimplementation

2/14 - 2/21 system optimization and evaluation2/14 - 2/21 system optimization and evaluation

2/28 - 3/07 high speed ADC and DAC implementation2/28 - 3/07 high speed ADC and DAC implementation

3/14 - 3/28 system evaluation 3/14 - 3/28 system evaluation

4/04 – 5/02 TBA note: the Bradley expo and project 4/04 – 5/02 TBA note: the Bradley expo and project presentation will occur during this period.presentation will occur during this period.

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ConclusionsConclusions

• FPGA design is flexible to build digital FPGA design is flexible to build digital communication systems. The methods communication systems. The methods used for modulation can be reconfigurable.used for modulation can be reconfigurable.

• The system has a fast design turn-around The system has a fast design turn-around time compared to conventional design time compared to conventional design using specialized hardware or DSP using specialized hardware or DSP processors.processors.

• SDR capabilities are to be investigated and SDR capabilities are to be investigated and demonstrated in the project.demonstrated in the project.

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ReferencesReferences Anton Rodriguez, and Michael Mensinger Jr., “Anton Rodriguez, and Michael Mensinger Jr., “Software-defined Radio using Software-defined Radio using

XilinxXilinx”, Senior Project Report, Department of Electrical and Computer ”, Senior Project Report, Department of Electrical and Computer Engineering, Bradley University, Peoria Illinois, May 2011.Engineering, Bradley University, Peoria Illinois, May 2011.

Anthony Gaught, “Anthony Gaught, “Software-defined Radio Symbol GeneratorSoftware-defined Radio Symbol Generator”, Junior ”, Junior Project Report, Department of Electrical and Computer Engineering, Project Report, Department of Electrical and Computer Engineering, Bradley University, Peoria Illinois, May 2012.Bradley University, Peoria Illinois, May 2012.

Anthony Gaught, Alexander Norton, and Christopher Brady., “Anthony Gaught, Alexander Norton, and Christopher Brady., “FPGA-based FPGA-based 16 QAM communication system16 QAM communication system”, EE 568 Report, Department of Electrical ”, EE 568 Report, Department of Electrical and Computer Engineering, Bradley University, Peoria Illinois, April 2012.and Computer Engineering, Bradley University, Peoria Illinois, April 2012.

Leon Couch, Leon Couch, “Digital and analog communication systems”“Digital and analog communication systems”, 8th ed., Boston: , 8th ed., Boston: Pearson, 2013.Pearson, 2013.

Charles Roth Jr., and Lizy John, “Digital systems design using VHDL”, 2Charles Roth Jr., and Lizy John, “Digital systems design using VHDL”, 2ndnd ed., United States: Thomson, 2008.ed., United States: Thomson, 2008.

Spartan-3E Data ManualSpartan-3E Data Manual, Xilinx, San Jose, CA,2009., Xilinx, San Jose, CA,2009. 2525

QuestionsQuestions

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