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Recent Research on One-Dimensional Silicon-BasedSemiconductor Nanomaterials: Synthesis, Structures,Properties and ApplicationsZhenyu Zhang a , Rujia Zou a , Li Yu a & Junqing Hu aa State Key Laboratory for Modification of Chemical Fibers and Polymer Materials , Collegeof Materials Science and Engineering, Donghua University , Shanghai, ChinaPublished online: 02 Sep 2011.

To cite this article: Zhenyu Zhang , Rujia Zou , Li Yu & Junqing Hu (2011) Recent Research on One-Dimensional Silicon-BasedSemiconductor Nanomaterials: Synthesis, Structures, Properties and Applications, Critical Reviews in Solid State and MaterialsSciences, 36:3, 148-173, DOI: 10.1080/10408436.2011.589233

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Critical Reviews in Solid State and Materials Sciences, 36:148–173, 2011Copyright c© Taylor and Francis Group, LLCISSN: 1040-8436 print / 1547-6561 onlineDOI: 10.1080/10408436.2011.589233

Recent Research on One-Dimensional Silicon-BasedSemiconductor Nanomaterials: Synthesis, Structures,Properties and Applications

Zhenyu Zhang,† Rujia Zou,† Li Yu, and Junqing Hu∗State Key Laboratory for Modification of Chemical Fibers and Polymer Materials, College of MaterialsScience and Engineering, Donghua University, Shanghai, China

The field of silicon nanowires (SiNWs) and silicon-based 1D nanostructured heterostructuresrepresent one of the most important research subjects within the nanomaterials family. A seriesof synthesis approaches of SiNWs and silicon-based 1D nanostructured heterostructures havebeen developed, and have garnered the greatest attention in the past decades for a variety of ap-plications. This article provides an overview on recent research on the synthesis, properties andapplications of SiNWs, silicon nanotubes (SiNTs) and complex silicon-based 1D nanostructures.

Keywords silicon nanowire, silicon nanotube, silicon-based 1D nanostructured heterostructure,synthesis, electromechanical devices, electronic devices, optoelectronic devices,biological and chemical sensors

Table of Contents

1. INTRODUCTION .............................................................................................................................................. 149

2. SYNTHESIS METHODS AND MECHANISMS OF SINWS AND SINTS .......................................................... 1502.1. Gas Phase Growth of SiNWs ......................................................................................................................... 150

2.1.1. Chemical Vapor Deposition (CVD) and Vapor-Liquid-Solid (VLS) Mechanism ...................................... 1502.1.2. Oxide-Assisted Growth Technique ...................................................................................................... 1512.1.3. Other Vapor-Phase Growth Technology ............................................................................................... 152

2.2. Solution-Liquid-Solid (SLS) Methods ............................................................................................................ 1532.3. Template-Directed Synthesis ......................................................................................................................... 1542.4. Top-Down Fabrication Technique (Chemical Etching Method) ......................................................................... 1542.5. Synthesis of Silicon Nanotubes (SiNTs) ......................................................................................................... 1552.6. Summary and Comparison ............................................................................................................................ 156

3. COMPLEX STRUCTURE ONE-DIMENSIONAL SILICON MATERIALS ....................................................... 1573.1. Radial Nanowire Heterostructures .................................................................................................................. 157

3.1.1. Epitaxial Nanowire Heterostructures (Side-to-Side) .............................................................................. 1583.1.2. Core-Shell Nanowire (Nanocables) Heterostructures ............................................................................. 159

3.2. Axial Nanowire Heterostructures ................................................................................................................... 1603.3. Hierarchical Nanowire Heterostructures ......................................................................................................... 1613.4. Summary ..................................................................................................................................................... 162

4. PROPERTIES AND APPLICATIONS ............................................................................................................... 1634.1. Mechanical Properties and Electromechanical Devices .................................................................................... 163

†These authors contributed equally to this work.∗E-mail: hu.junqing@dhu.edu.cn

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4.2. Electrical Properties and Electronic Devices ................................................................................................... 1644.3. Optical Properties and Optoelectronic Devices ................................................................................................ 1654.4. Biological and Chemical Sensors ................................................................................................................... 1664.5. Thermoelectric Properties ............................................................................................................................. 167

5. CONCLUSIONS AND OUTLOOK .................................................................................................................... 169

ACKNOWLEDGMENT ............................................................................................................................................ 169

REFERENCES ......................................................................................................................................................... 169

1. INTRODUCTIONThe core technology of the IT industry is microelectronic and

semiconductor integrated circuits, which are based on semi-conductor materials. The silicon-based semiconductor is theprimery material used, and is required to possess a series ofelectrical and optical properties. Monocrystalline silicon, andamorphous silicon are widely used in the large-scale integratedcircuit (LSI), solar battery, and other high-technology industries,and have become indispensable semiconductor materials.

Nanostructure is defined to describe structures with lateraldimensions in the range of 1 to 100 nm, which show fascinat-ing properties superior to their bulk counterparts. There are twoways to create nanostructures: the top-down approach, and thebottom-up approach. The top-down approach uses bulk sub-stances as raw materials, and the implement process containingmilling, etching, patterning and lithography, etc. The bottom-up approach builds structures from atoms or molecules intonanoscale devices with specific functions, such as thermal evap-oration, laser ablation, liquid phase deposition, etc.1 Nanotech-nology is a culmination of many facets of scientific and techno-logic developments in the nanorealm, including nanofabrication,nanomanipulation, nanomachineries, quantum devices, molec-ular machines, and molecular computers.2 As nanotechnologydevelops, combining the top-down and bottom-up strategies tofabricate nanodevices becomes more practical.

One-dimensional (1D) semiconductor nanostructures, in-cluding nanowires, nanorods, fibers, nanotubes, nanobelts, andnanoribbons, have attracted particular interest in recent decadesbecause of their special properties and potential applications. Inaddition, it is worthy to note so called quasi-one-dimensionalstructures or complex 1D structures including axial, radial, andmultiaxial nanowire heterostructures. These semiconductingnanowire heterostructures, with modulated compositions anddoping, enable the creation of interfaces and the formation ofdiverse functions, and have been exploited with respect to theirpotential applications in nanoelectronics and nanophotonics.3

Given their central role in the semiconductor industry and theexisting set of well-established fabrication technologies,4 siliconnanowire and silicon-based 1D nanowire heterostructures repre-sent one of the most important research subjects in the nanowireresearch community. Silicon is stable over a wide range of pro-

cessing temperatures and conditions, and it forms a chemicallyand electrically stable oxide with appropriate conductance andvalence band offsets. Silicon-based one-dimensional and quasi-one-dimensional materials have been discovered to exhibit novelfunctional electronic and optical properties due to their struc-tural one-dimensionality and related quantum-mechanical con-finement effects.5 For example, Si is poor in luminescence andcan be hardly explored as an optically active material for func-tional optoelectronic devices because of its indirect band gap.SiNWs, especially porous SiNWs, however, exhibit efficient vis-ible photoluminescence and might be applied as light-emittingdiodes and emitter materials for displays, lighting, and medi-cal imaging.6 Furthermore, SiNWs can be either p- or n-dopedwith impurities at a wide range of concentrations for improv-ing its electronic transport properties, optical sensing, and pho-tovoltaics, because of its useful band gap energy (at 1.1 eVor ∼1100 nm) near the red edge of the visible spectrum.7

Recently, several ingenious methods have been described forpreparing silicon nanotubes (SiNTs), as well as more complexstructures such as coaxial or radial silicon-based semiconduc-tor nanowire heterostructures, and all have shown outstandingperformance in electronic and optical properties with potentialapplications.

SiNWs represent one of the most important research sub-jects in the nanowire research community. Although only tworeviews (Chem. Rev., 2007, 107, 1454–1532; Adv. Mater., 2009,21, 2681–2702) have described the synthesis, properties, and ap-plications of SiNWs, a systematic introduction on silicon-based1D nanostructure including SiNWs, SiNTs, and other novelcomplex silicon-based 1D heterostructures has not yet been pre-sented. Recent in-depth study has revealed, more applicationsfor silicon-based 1D nanomaterials devices, but no recent re-views have described these new properties and applications. Inthis Review, we describe recent research on the synthesis, prop-erties and applications of SiNWs, SiNTs, and other complexsilicon-based 1D nanostructure. First, we present a systematicalsummary on the synthesis methods and mechanisms of SiNWsand SiNTs. Subsequently, we introduce, a series of complexsilicon-based 1D nanostructures and their properties. Finally,we provide a brief summary about recent research on SiNWs,and silicon-based 1D nanomaterials and their applications in the

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field of mechanics, electronics, optics, biology, chemistry, andthermoelectricity.

2. SYNTHESIS METHODS AND MECHANISMSOF SINWS AND SINTSMany effective methods have been developed for synthe-

sizing SiNWs and SiNTs with well controlled structures, andtheir properties and characterizations were studied. In this sec-tion, we will review some important approaches of preparingSiNWs and SiNTs, which are categorized as follows: gas phasegrowth, solution-based technique, template-assisted method andtop-down approach.

2.1. Gas Phase Growth of SiNWsSiNWs’ growth from thermal volatile gaseous silicon pre-

cursor is a proven technology that has high requirements onenvironment conditions, such as elevated temperature, high andeven ultrahigh vacuum inside the reaction chamber.

2.1.1. Chemical Vapor Deposition (CVD) andVapor-Liquid-Solid (VLS) Mechanism

In CVD, a volatile gaseous silicon precursor, such as silane(SiH4), disilane (Si2H6) or tetrachloride (SiCl4), serves as thesilicon source. When metal particles are present, either as con-taminants or as catalyst on the substrate, e.g., Au nanoparticles,the silicon precursor transports to the deposition surface and de-composes into Si and anisotropically grows into nanowire alongthe specific crystallographic orientation. The growth velocity ofsilicon wires varies from about 10−2 to 10+3 nm per minute, de-pending on temperature, pressure, and type of Si precursor used,but remains independent of diameter.8 The diameter and lengthof the SiNWs are associated with the particle size of the catalystand with growth time, respectively. Note that silicon oxidizeseasily form when exposed to oxygen at elevated temperatures,so it is crucial to reduce the oxygen background pressure. Inany case, it is useful to lower the base pressure of the CVDreactor down to high or even ultrahigh vacuum, which reducesunwanted contaminants and enables SiNWs’ growth at loweredtemperatures.9

As an effective approach to synthesize semiconductornanowires with modified morphologies and properties, CVDhas uniformly been investigated and explained by the vapor-liquid-solid (VLS) mechanism. Take the Au catalyst forexample—when the silicon substrate is placed in the ambienceof gaseous silicon precursor and elevated temperature above363◦C, the Au particles melt and dissolve gaseous silicon re-actant to form Au-Si nanosized liquid alloy droplets. As theincreasing of Si element deposits into Au liquid droplet till 19%(at.) Si content (according to the Au-Si Phase Diagram), Siatoms start to precipitate from the supersaturated droplet andbond at the liquid-solid interface, and the liquid droplet rises

from the Si substrate surface. The continuous process of absorp-tion, diffusion, and precipitation of Si leads to the growth of awire, with the alloy droplet riding atop the growing wire. The 1Dgrowth is mainly induced and dictated by the liquid droplets, thesize of which remains essentially unchanged during the entireprocess of wire growth. In this sense, each liquid droplet servesas a soft template to strictly limit the lateral growth of an individ-ual wire. The dominant coherent Au silicide/Si growth interfacesubsequently advances by lateral propagation of ledges, drivenby catalytic dissociation of disilane and coupled Au and Si diffu-sion.10 A major requirement is the presence of a solvent capableof forming liquid alloy with the target material, ideally, capableof forming eutectic compounds.11 Figure 1 is illustrates the VLSprocessing.

The advantage of the VLS process is that the diameter, length,orientation and composition of the nanowires are controllable.12

The diameter of the nanowire can be controlled by the size of cat-alyst nanoparticles. This method works well over a large rangeof sizes, from a few nanometers to several hundreds of microme-ters in diameter.13 The length and growth rates are in connectionwith the gaseous silicon precursor. The average SiNWs growthrates using Si2H6 reactant were 30 to 130 times faster than thoseobserved using SiH4 reactant under similar growth conditions.14

It has been confirmed that the growth direction of SiNWs pre-pared by the VLS process has a strong diameter dependence,with the small diameter SiNWs growing primarily along the[110] direction and the larger diameter SiNWs growing alongthe [111] direction.15 Figure 2 shows TEM images of the cata-lyst alloy/NW interface of SiNWs with [111] and [110] growthaxis, a 3.8 nm SiNW and cross-section, equilibrium shapes forthe NW and cross sections predicted by Wulff construction. Byintentionally doping with varietal precursors, electrical and op-tical properties along the axial direction can be controlled. Forinstance, the electronic transport measurements of the dopedSiNWs show better electric conductivity.16 The unique struc-ture of axial modulation-doped p-i-n nanowires have interestproperties and can be exploited in electrical and optical appli-cations.17

Au is the most frequently used catalyst material for growingSi nanowires by VLS method. The advantages that render Ausuch a favorable catalyst material are that Au is nontoxic, chem-ically inert, and easily available, that it possesses a eutectic pointat a low temperature but high Si solubility, that Au has a low va-por pressure at elevated temperatures, and that the Au-Si liquidalloy has a high-enough surface tension.18 The disadvantage ofVLS method may be the contamination caused by the necessaryuse of a metal (such as Au) particle as the catalyst, which mayresult in the change in the nanowire’s properties. Unfortunately,Au is considered as an impurity because it creates deep leveldefects in Si. The band gap discrepancy between impuritiesand semiconductor can affect the charge-carrier lifetime by act-ing as centers for charge-carrier recombination, which makes itincompatible with industrial electronic production standards.19

However, by selecting an appropriate catalyst, the effection of

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FIG. 1. (a) Schematic drawing that illustrates the VLS processing (b) Au-Si phase diagram. (Color figure available online.)

the contamination on specific properties of the nanowire canbe minimized. The analysis of catalyst and growth conditionscan be substantially simplified by considering the pseudo-binaryphase diagram between the metal catalyst and the solid materialof interest. Recently, numerous research efforts have focused onsearching for alternative catalyst materials and catalyst-free forSiNWs growth.20 For instance, Yang et al.21 chose Pt as a cata-lyst because it has a high melting point, and because Pt can bemade into nanoparticles with a tight size distribution and showsleakage current lowered by several orders of magnitude whenincorporated into silicon diodes compared to gold. Hu et al.22

synthesized novel silica fibers with a triangular cross section,which is not typical for amorphous materials, by Sn-catalyzedVLS process through the thermal co-decomposition of SiO andSnO powders. A list of catalyst materials for which success-

ful SiNWs synthesis has been reported: Ag, Al, Bi, Cd, Co,Cu, Dy, Fe, Ga, Gd, In, Mg, Mn, Ni, Os, Sn, Pb, Pd, Pt, Te,Ti, and Zn, etc.18 Wen and coworkers23 have recently formedcompositionally abrupt interfaces in silicon-germanium (Si-Ge)heterostructure nanowires by using solid aluminum-gold (Al-Au) alloy catalyst particles rather than the conventional liquidsemiconductor-metal eutectic droplets. Analogously to the VLSmechanism, the so-called vapor-solid-solid (VSS) mechanismcomes into play when wire growth is catalyzed by a solid cata-lyst particle instead of a liquid catalyst droplet.

2.1.2. Oxide-Assisted Growth TechniqueIn the oxide-assisted growth (OAG) method,24 oxides, in-

stead of metals particles, play the crucial role in inducing the

FIG. 2. (a) and (b) HRTEM images of the catalyst alloy/NW interface of a SiNW with [111] and [110] growth axis, respectively.Scale bar: 20 nm in (a) and 5 nm in (b). (c) TEM image of a 3.8 nm SiNW grown along the [110] derection and (d) HRTEMcross-sectional shape. Both scale bars in them are 5 nm. (e) and (f) Equilibrium shapes for the NW and cross-sections predictedby Wulff construction. (Reprinted with permission from Wu et al.15 Copyright 2004: American Chemical Society.) (Color figureavailable online.)

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nucleation and growth of high quality semiconductor nanowires.The major advantage of this approach is that no metal catalystsare needed, thus removing the risk for contamination, and there-fore not affecting the performance of nanowires in devices. Ina typical procedure, either pristine SiO powder or an equimo-lar mixture of silicon dioxide (SiO2) and silicon powder areplaced at the center of the tube furnace, where the temperatureis increased to as high as 1200 to 1400◦C during the process.The tube is evacuated to a base pressure and a carrier gas ofargon mixed with 5% H2 is lentamente introduced at one end ofthe tube furnace. The Si atoms collide with the carrier gas andform silicon clusters to nucleate and grow into nanowires on themicrothermal substrate at the position downstream. The temper-ature of the area around the substrate on which the nanowiresgrow is about 900 to 1100◦C, which is the important determinantof the diameters of the SiNWs. The nanowires formed generallycomprise a crystalline silicon core and a relatively thick amor-phous silicon oxide outer layer. SiNWs prepared by this methodare literally very long (micrometers), freestanding wires witha diameter of several nanometers to tens of nanometers. Also,Lee and coworkers25 synthesized highly oriented, large-scale,and very long SiNWs on flat silicon substrates by combininglaser ablation and thermal evaporation of SiO powder target.They confirmed that flowing carrier gas, temperature gradient,and planar substrate may be the main factors for the formationof oriented SiNWs.

In the OAG model, as the mechanism of the SiNWs growthshown in Figure 3, Si nanoparticles are first precipitated via thedecomposition of SiO described by the two equations followed:

SixO (s) → Six−1 (s) + SiO (s) (x > 1)

2SiO (s) → Si (s) + SiO2 (s)

The yield of SiNWs increased with increasing thermal evapora-tion temperature and the base pressure inside the tube furnace.26

SiNWs’ growth is determined by four factors. (1) The catalyticeffect of the SixO (x>1) layer on naowire tips, which enhancesatomic absorption, diffusion, and deposition. (2) The SiO2 com-ponent in the shells retards the lateral growth of nanowires.

FIG. 3. (a) The mechanism of the SiNWs from SiO powder.(b) TEM images of SiNWs grown by OAG method, the inset isa selected-area electron diffraction (SAED) pattern taken fromthis area. (Reprinted from Li et al.27 Copyright 2003: John Wileyand Sons.)

(3) Dislocations play a very important role in crystal growth.(4) The lowest energy surface (111) plays an important role inthe Si nanowire nucleation and growth. The growth directionsof SiNWs prepared by the OAG are mainly along the [112]and [110] directions, while those grown by the metal-catalystVLS method are mainly along [111].27 According to the relativesurface energy of Si, γ {110} > γ {100} > γ {111}, the {111}planes have the lowest surface energy. In order to minimize thesystem energy, SiNWs thus tend to grow predominantly alongthe [110] and [112] directions, so that the surface of the wiresare bounded by a larger number of {111} facets. Aside fromsurface energy, another determining factor is the coverage bySiO2. Since SiO2 has the highest growth rate on the Si {111}planes, fast oxidation may have retarded Si growth along thisatomically smooth surface.

The VLS mechanism and OAG mechanism each has itsadvantages. By combining the OAG and metal catalyst VLSprocesses, it is possible to assimilate the merits of both. Yaoet al.28 prepared high-density, oriented SiNWs arrays on (001)silicon substrates using the OAG method assisted with Au cat-alyst in a hot filament CVD system. Wang et al.29 synthesized asilicon-based periodic composite nanostructure using a periodicvolume-changing Sn particles as catalyst by taking advantageof both VLS and OAG processes.

2.1.3. Other Vapor-Phase Growth TechnologyMolecular-beam epitaxy (MBE) technique combining with

the VLS mechanism have been employed to synthesize high-quality SiNWs. In MBE, a solid high-purity silicon source isheated until Si starts to evaporate. A directional gaseous beamof evaporated source silicon atoms or molecules is aimed at thesubstrate where the atoms absorb and crystallize. Unlike othertechniques, MBE works under ultra-high vacuum condition of10-5 Torr, which reduces contamination and allows monitoringof the growth, surface structure and contamination in situ byusing surface probing techniques. The SiNWs synthesized byMBE usually grow on Si (111) substrates. The advantages ofMBE are: (1) the ultra-high vacuum can reduce contaminationand oxidation of SiNWs, (2) in situ monitoring of growth, and(3) excellent controllability of doping wires or heterostructuresby switching evaporation sources. Two major disadvantages ofMBE are limitation of its minimal diameter and low growthvelocity.30

Laser ablation technique can provide large quantities of ul-trathin nanowires with high aspect ratios directly from solidsource materials. As the schematic diagram shown in Figure 4,in the laser ablation procedure, a high temperature tube furnaceis purged with inert gas, and a high-power pulsed laser ablatesthe source material composites of silicon and metal catalysts.The silicon material ablated from the target cools by collidingwith inert-gas molecules, and Si atoms condense to liquid nan-odroplets with the same composition as the target. This methodrelies on the VLS mechanism, whereby the vapor generated by

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FIG. 4. (a) Proposed nanowire growth model of laser ablation.(b) The prepared SiNW structure with a crystalline Si core andamorphous SiOx sheath. (c) HRTEM image of the crystalline Sicore and amorphous SiOx sheath. (Reprinted with permissionfrom Morales and Lieber,31 Copyright 1998: American Associ-ation for the Advancement of Science.)

laser ablation dissolves in a molten metal catalyst and crystal-lizes to grow into nanowires when it gets supersaturated withsilicon. The advantages of laser-ablation for nanowire produc-tion are evident. First, there is no need for a substrate. Second,a simple mixture of the elements rather than specially preparedtarget is enough for the form of crystalline. Importantly, thecomposition of the resulting nanowires can be varied by chang-ing the composition of the laser target. Lieber et al.31 preparedbulk quantities of uniform single-crystal SiNWs with diametersof 6 to 20 nm and lengths ranging from 1 to 30 mm.

Vapor-phase growth technologies are so versatile that theycan be employed to produce silicon-based compounds or silicidenanowires. Hu et al.32 reported the production of large-quantitiesof high-purity and ultralong (millimeters) SiO2 nanowires usinga simple thermal oxidation route and silicon wafers as a sourcematerial. By selecting suitable gas source, e.g., NH3 or CH4, itis reasonable to expect that the aligned SiO2 nanowires (actingas a template or solid source material) can be converted toother aligned Si-based materials nanowires, e.g., SiC or Si3N4.For example, Zhang et al.33 prepared Si3N4 nanowires withdiameters of 10 to 70 nm by heating Si powder or Si/SiO2

mixture at high temperature in a N2 or NH3 flow.

2.2. Solution-Liquid-Solid (SLS) MethodsThe major advantages of the solution-based technique for

synthesizing nanomaterials are high yield, low cost, and easy

FIG. 5. (a) SLS growth of a Si nanowire: Si precursor decom-poses to generate Si atoms, which are consumed by the Au seedto form an Au/Si eutectic that promotes wire growth. (b) TEMimage of the as-synthesized SiNWs at 410◦C. (c) One SiNWwith a Au seed at the tip. (d) SiNWs grown using Bi nanocrystalsas seeds. (e) A SiNW longer than 3 µm. (Reprinted with permis-sion from Heitsch et al.35 Copyright 2008: American ChemicalSociety.) (Color figure available online.)

fabrication. Based on an analogy to the VLS process, Korgeland coworkers have successfully grown defect-free SiNWs withnearly uniform diameters of 4 to 5 nm and lengths up to severalmicrometers by employing a supercritical fluid as the solventfor the SLS process.34 The key strategy of their synthesis wasthe use of monodispersed, alkanethiol-capped Au nanocrystalsthat could serve as seeds to direct and confine the growth ofSi into nanowires having a narrow diameter distribution. Fig-ure 5a shows a schematic of the nanocrystal-directed nanowireself-assembly process. In a typical SLS process, a low melt-ing point metal as catalyst (e.g., Au) and Si precursor (e.g.,diphenylsilane) were dispersed in hexane, heated and pressur-ized above its critical point. According to the phase diagramfor Si and Au, under the reaction temperature of above 363◦C,the Si atoms most likely dissolve into the sterically stabilizedAu nanocrystal until reaching supersaturation (>19% (at.) of Sicontent), at which point they are expelled from the particle asa thin nanometer-scale wire. Recently, Korgel et al.35 demon-strated the first example of large quantities of crystalline SiNWsgrowth by the SLS mechanism at atmospheric pressure usingtrisilane (Si3H8) as a reactant in high boiling point solvents (e.g.,octacosane or squalane) and either gold (Au) or bismuth (Bi)nanocrystals as seeds. Figure 5b–5d show TEM images of theas-synthesized SiNWs.

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2.3. Template-Directed SynthesisTemplate-directed synthesis represents a straightforward

route to obtain 1D nanostructure. In this approach, the templatesimply serves as a scaffold within (or around) which the raw ma-terial is in situ generated and shaped into a nanostructure withits morphology complementary to that of the template.11 Theadvantages of this method are manifold, e.g., facile fabrication,controllable compositions and elemental distribution, uniformsize of nanostructures over other synthesis techniques.3 Alu-mina films containing anodically etched pores, polymer mem-branes, mesoporous silica, and zeolites are commonly used inthe template-directed synthesis. By using the CVD method,vapor-phase sputtering, liquid-phase injection, solution-phasechemical, sol-gel or the electrochemical method, the materialcan be loaded into the pores.

Using anodized aluminum oxide (AAO) membranes as tem-plates, which are fabricated on the substrate with pre-depositedgold nanoparticls, ordered single-crystal SiNWs arrays had beensynthesized.36 As the schematic of fabrication process shown inFigure 6, porous alumina membranes are previously preparedusing anodization of aluminum foils in an acidic medium,37

which contain a hexagonally packed 2D array of cylindricalpores with relatively uniform size and high pore density. Via theVLS mechanism, SiNWs form in the porous of the AAO. There-fore, the diameter and the length of the SiNWs produced can becontrolled by varying the pore diameter, length, and density inthe AAO templates and growth time. Finally, the nanowires canbe released from the templates by removal of the host matrix,resulting in the 1D nanostructure. Yang et al.38 described a tem-plate synthesis of high-density, vertical SiNWs on a Si (111)substrate with well-defined diameter and spacing.

FIG. 6. Schematics of nanowire fabrication via template-directed process. (a) cross-section of nanoporous alumina mem-brane. (b) electrodeposition of Au within pores. (c) VLS growthof SiNWs out of membrane surface. (d) SiNWs’ removal bymechanical agitation. (e) VLS growth of SiNWs within themembrane. (f) SiNWs’ removal by wet etching of membrane.(Reprinted with permission from Bogart et al.36 Copyright 2005:John Wiley and Sons.)

It has been demonstrated that zeolite can be employed as asacrificial template to fabricate very fine and uniform SiNWsvia the disproportionation reaction of SiO by thermal evapora-tion.39 In another research, SiNWs were synthesized within 5 nmdiameter pores of mesoporous silica template using a supercrit-ical fluid solution-phase approach.40 The silica matrix providesa method of producing a high density of stable, well-orderedarrays of SiNWs in a low dielectric medium.

2.4. Top-Down Fabrication Technique(Chemical Etching Method)

In order to synthesize SiNWs with a high degree of regu-larity, uniformity and adjustability in terms of crystallographicorientation, diameter, length and accurate position, top-downstrategies rather than other approaches are always adopted. Thetop-down fabrications of SiNWs can be put into two categories,i.e., horizontal nanowires lying on the substrate plane usuallyprepared by lithography and dry or wet etching steps,41 andvertical nanowires oriented more or less perpendicular to thesubstrate often prepared by reactive-ion etching.42

As a top-down approach, metal-assisted wet-chemical etch-ing of silicon substrates is considered as a promising resolventto achieve SiNWs with precise control of diameter, length, spac-ing, and density, avoiding high-cost and low-throughput conven-tional lithographic processes. The overall fabrication process isschematically depicted in Figure 7. A monolayer hexagonal ar-ray of nanospheres (e.g., polystyrene) or an ultrathin AAO mem-brane is placed on the silicon substrate, which is used as a pat-terning mask. In the case of nanospheres, the nanospheres mono-layer is subsequently underwent a reactive ion etching processto form a colloidal particle array, which leads the nanospheres tohave smaller diameters and not to be close-packed. Correspond-ingly, the pore size and density of the AAO membranes can becontrolled by varying the electrochemical parameters used inthe anodization reaction of aluminum. In the next step, a thinmetallic film (e.g., silver film) is thermally evaporated onto thesilicon substrate as a catalyst. Subsequently, an etching solutioncontaining deionized water, HF and H2O2 is used. The Si sur-face that comes in contact with the metal is selectively etched,leaving behind arrays of SiNWs whose diameter is predefinedby the size of holes in the metal film, while the length is deter-mined by the etching time. Finally, the nanospheres or the AAOtemplate and the metal film are removed by solvents.43

The formation mechanism of the metal-assisted etchingSiNWs is galvanic displacement reaction. Alternatively, the re-duction of metal ions (cathodic process) and the oxidation of Siatoms (anodic process) occur simultaneously on the Si surface,while the charge is exchanged through the Si substrate. Theschematic diagram of the etching mechanism and TEM imagesof the SiNWs are illustrated in Figure 8. The Si/AgNO3/HF sys-tem is composed of a corrosion-type redox couple: the cathodicreduction of Ag+ ions and its counterpart, the anodic oxidationand dissolution of silicon, which occurs locally beneath the Ag

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FIG. 7. Schematic depiction of the fabrication process using polystyrene nanospheres as patterning mask. (Reprinted withpermission from Huang et al.43 Copyright 2007: John Wiley and Sons.)

deposits. Therefore, the Ag particles trap into the pits vertically,resulting in the formation of SiNWs.44 The electrochemistry re-actions of the cathode and anode should be expressed as follows:

Cathode (Ag surface facing the electrolyte):

H2O2 + 2H+ + 2e− → 2H2O, E0 = 1.77V

Anode (Si in close contact with Ag):

Si + 2H2O → SiO2 + 4H+ + 4e−

SiO2 + 6HF → H2SiF6 + 2H2O

Si + 6HF → H2SiF6 + 4H+ + 4e−, E0 = 1.2V

Overall: Si + 2H2O2 + 6HF → H2SiF6 + 4H2O

Generally, the used metals in the galvanic displacement reac-tion are Ag, Au, and Pt salts with highly positive equilibrium re-duction potential.45 Peng et al.46 concluded that the autonomousmotion of metal particles (Ag and Au) in Si is highly uniform,yet directional and preferential along the (100) crystallographicorientation of Si, rather than always being normal to the siliconsurface. As for the etchant, Teo et al.47 discovered that NH4Fis as efficient an etchant as HF for SiNWs and that SiNWs arestable only in relatively narrow pH ranges of NH4F-buffered HFsolutions.

Metal-assisted wet-chemical etching allows control over thediameter, length, density42,44 and crystallographic orientationof the SiNWs.48,49 For example, single-crystal zigzag SiNWs

with different turning angles in wafer can be controlled viaselecting the crystallographic orientation of Si wafer, reactiontemperature, and etchant concentration.50 The morphology ofthe SiNWs is tunable from solid nonporous nanowires, non-porous/nanoporous core/shell nanowires, to entirely nanoporousnanowires by controlling the hydrogen peroxide concentrationin the etching solution.6 Analogously to the metal-assisted wet-chemical etching, Peng et al.51 successfully prepared large-areaSiNWs arrays on silicon wafers, without the use of a template inthe aqueous HF solution containing silver nitrate at low temper-ature, which demonstrated a simple method to the synthesis ofSiNWs based on the conventional electroless metal deposition(EMD) technique.

2.5. Synthesis of Silicon Nanotubes (SiNTs)The discovery of carbon nanotube (CNT) has raised a revolu-

tion to the semiconductor materials’ application due to their spe-cial structures and properties. Nevertheless, despite the fact thatcarbon and silicon belong to the same element group, the similarcorresponding structure SiNTs, are difficult to synthesize due tothe fact that Si is in sp3 hybridization state.52 The synthesis ofpolycrystalline/amorphous and single-crystal SiNTs may openup new and exciting possibilities for making different kinds ofnanosized heterostructures by filling a tube inner space or dec-orating tube outer surfaces with a foreign material. Synthesisof SiNTs has been demonstrated by several methods in recent

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FIG. 8. Mechanism of electroless Ag deposition on a Si substrate in HF/AgNO3 solution. (a) Ag+ ions in the vicinity of the siliconsurface capture electrons from Si and deposite in the form of metallic Ag nuclei on a nanoscopic scale. (b) Electron exchangebetween Ag+ ions and Si catalyze the subsequent reduction of Ag ions and oxidation of Si, inducing etching of SiO2 by HFsolution. (c) Ag particles trapped in these pits vertically. (d) TEM image showing a cross-sectional view of SiNWs arrays on anetched silicon wafer. (e) HRTEM image of a single silicon nanowire and its SAED pattern. (Reprinted with permission from Penget al.44,45 Copyright 2006: John Wiley and Sons.)

years, such as CVD technique with gold particles as catalysts53

or aluminum oxide templates,54,55 thermal disproportionation ofSiO56 or with zeolites as templates,39 arc-discharge gas-phasecondensation,57 hydrothermal route,58 molecular beam epitaxyon porous alumina,59 and low temperatures micelle nanolithog-raphy.60

Using a nanowire of another material which has a proximatecrystal lattice as template for silicon shell to form on is an inge-nious method to synthesize SiNTs. Hu et al.61 demonstrated thefabrication of single-crystalline SiNTs utilizing a thermal evap-oration method firstly. Due to the similar crystal structures andvery close lattice constants, zinc blende ZnS nanowires wereused as one-dimensional templates for epitaxial growth of thinmonocrystalline Si sheaths. Single-crystalline SiNTs formedafter chemical removal of ZnS cores, as shown in Figure 9. Fol-lowing this work, analogous researches devote to synthesis ofcrystal SiNTs were reported.62 The SiNTs were suitable for het-erostructure nanodevices such as field effect transistors (FETs),while SiNTs filled with different semiconducting materials withvarious band gaps can have interesting applications in electricaland optical nanodevices.

2.6. Summary and ComparisonFor a summary, the range of synthesis routes to SiNWs and

SiNTs introduced above are quite distinct in characteristics. As

the technology improving and different requirements for theproduct parameters, new methods may be exploited. We believethat the most appropriate method depends on the applicationto a large extent. Note that one should distinguish the two ap-proaches for the in-place fabrication on substrates and irrespec-tive of position fabrication of silicon nanowires. In the case ofin-place fabrication of SiNWs, it is considered that none of thebottom-up synthetic methods can compete with the top-downfabrication methods in terms of controllability, reliability, andsize variability, for example, the metal-assisted etching methodhighlighted above. The CVD technique, which always combineswith the VLS growth mechanism, allows for an epitaxial growthon silicon substrates at specific positions where catalyst metalparticles exist. It offers great versatility concerning process con-ditions, nanowire dimensions, and doping properties accordingto special applications. The ability to control the nanowire size,orientation, and location during growth is critically important,because it allows the growth and assembly of nanowires to becombined into one step, and facilitates the subsequent fabri-cation processes such as the formation of electrical contacts tonanowires, and broadens the design space for novel devices. De-spite of its advantage of combining epitaxial growth with a goodcontrollability of composition, the MBE approach lacks the vari-ability of CVD concerning nanowire diameters and aspect ratios.With respect to the synthesis of non-substrate-bound nanowires,

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FIG. 9. (a) High-magnification TEM image depicting a segment of a Si nanotube, and an ED pattern (inset) corresponding to the[110] zone axis of a Si single crystal. Scale bar: 20 nm. (b) HRTEM image of a Si nanotubular structure. Scale bar: 2 nm. (c) TEMimage of a segment of a Si nanotube. (d) Si elemental map as further evidence for a tubular structure. Scale bars in (c) and (d):100 nm. (e) Line-scanning (indicated by a line in (c)) elemental mapping highlighting the spatial Si elemental profile across thetube. (Reprinted with permission from Hu et al.61 Copyright 2004: John Wiley and Sons.) (Color figure available online.)

laser ablation combines a good controllability and variability ofthe nanowire composition with excellent nanowire quality andreasonable yield, and the solution-based growth techniques offera large-scale and high-yield nanowire. Additionally, except forbeing an interesting nanostructure, crystalline SiNTs may openup new and exciting possibilities for making different kinds ofnanosized heterostructures by filling the inside space or deco-rating the outside surfaces with another type of nanomaterial.

3. COMPLEX STRUCTURE ONE-DIMENSIONALSILICON MATERIALSDespite the ways in which silicon nanowire and nanotube

have matured in homogeneous systems, the 1D heterostructurenanostructure with well-defined interface has more interestingproperties and attracts greater attention. The reported nanowireheterostructures generally fall into three types: radial, axial,and multiaxial heterostructures. The concept of modulating theaxial and radial compositions has been recently exploited forthe fabrication of single-crystalline superlattice NWs and com-plex core/shell NW structures, with both IV and III-V semi-

conductor materials. Silicon-based semiconducting nanowireheterostructures with exquisite controlled dimensions, compo-sitions and crystallinities represent a new class of intriguingsystems for the investigation of structure-property relationshipsand related applications. Back in 1999, Hu et al.63 first reportedon the utilization of catalytic vapor growth for the prepara-tion of metal-semiconductor heterojunctions between CNTs andSiNWs. Lauhon et al.64 synthesized silicon and germanium core-shell and multishell nanowire heterostructures using a CVDmethod applicable to a variety of nanoscale materials. Becauseof the heterostructue interface, the silicon-based nanowires ex-hibit special properties and have potential applications to meetthe growing demands and specific requirements of new tech-nologies. In this section, we will systematically describe thesilicon-based one-dimensional complex nanostructures.

3.1. Radial Nanowire HeterostructuresRadial nanowires can be put into two categories, side-to-side

epitaxial heterostructure and core-shell nanowire (coaxial cable)

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heterostructrue. Both of the two are fundamentally interestingand have significant technological potential. It is deduced thatif one-dimensional heterostructures with a well-defined compo-sitional profile along the wire radial direction can be realizedwithin semiconductor nanowires, new nanoelectronic devices,such as nanowaveguide and nanocapcipator, might be obtained.

3.1.1. Epitaxial Nanowire Heterostructures (Side-to-Side)It is exciting and difficult to form biaxial and triaxial

nanowire heterostructures made of two or three single-crystalline semiconducting nanomaterials. Based on the crystal-lographic similarity, epitaxial biaxial silicon and II-VI semicon-ductor nanowire heterostructures can be theoretically achieved.Meanwhile, a similar lattice constant without large misfit dis-locations contributes to the electronic performance of a devicemade of such a nanowire heterostructure.

Herein, we primarily focus on our studies, in which side-to-side biaxial and sandwiched triaxial semiconducting nanowireheterostructures were produced in a deliberate and controlledmanner. There is an excellent epitaxial relationship between theconstituents within the nanowire heterostructures, which is quitedifferent from the previous reports, such as biaxial silicon-silicananowires39 and biaxial nanowires of silicon carbide-silicon ox-ide.65 Side-to-side Si-ZnS, Si-ZnSe biaxial nanowires, ZnS-Si-ZnS and Si-Si-SnO2 triaxial nanowires were synthesized via

a two-stage process under entire temperature control.66,67 Theresulting products are shown in Figures 10 through 12. Be-cause that diamond-like cubic Si and zinc blende ZnS havesimilar crystal structures and very close lattice constants (ZnS:a = 0.5431 nm, Si: a = 0.5420 nm), the effective epitaxialgrowth of ZnS nanowires on Si nanowire substrate should bepossible,68 and high-quality junctions between single-crystallinesub-nanowire domains form. These nanowire heterostructuresconsisting of two different semiconductors (Si, ZnS or ZnSe andSnO2) should lead to Si-based optoelectronic nanodevices andmake possible the combination of ZnS- or ZnSe- and SnO2-based nanodevices with a Si-integrated circuit. To continuealong this line of exploration, we synthesized ZnO-Si biaxialnanowire heterostructures via a simple post-oxidation by usingthe as-obtained ZnS-Si biaxial nanowires as templates.69 Theas-obtained ZnO-Si biaxial nanowire heterostructures exhibita significant enhancement of green luminescence compared tothe ZnO nanowires,70 which is attributed to the effect of poroussurface state and the defects increase after a post-oxidation pro-cess. The three layered radial Si-Si-SnO2 nanowire heterostruc-ture was achieved by a two-step template epitaxial growth. AsFigure 12 shows, the composite nanowire has a uniform di-ameter along its whole length. These Si-Si-SnO2 nanowire het-erostructures display unique intensive green luminescence emis-sion compared to that of UV emission of the near-band edge ofSnO2.

FIG. 10. (a) High-magnification TEM image depicting Si (light) and ZnS (dark) subnanowire sides within a Si-ZnS biaxialnanowire. (b–d) The Si, Zn, and S elemental maps demonstrating a well-defined compositional profile and an abrupt interface.Scale bars in (a–d) are 50 nm. (e) HRTEM images of the Si subnanowire, two sets of {111} (d111 = 0.3135 nm) planes designatedby double-lines. (f) HRTEM images of the ZnS sub-nanowire, two sets of {111} (d111=0.3123 nm) planes indicated by double lines.(g) HRTEM image taken from the Si-ZnS interface domain, revealing a well-epitaxial relationship between the sub-nanowiresof Si and ZnS. Scale bars in (e–g) are 2 nm. (Reprinted with permission from Hu et al.66 Copyright 2003: American ChemicalSociety.) (Color figure available online.)

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FIG. 11. (a) High-magnification TEM image of a straight side-to-side Si-ZnSe biaxial nanowire. An ED pattern (inset) taken fromthe Si-ZnSe interface area. The scale bar represents 50 nm. (b) HRTEM image of the ZnSe subnanowire growing along the [210]direction. (c) HRTEM image of the Si sub-nanowire growing along [001]. (d) HRTEM image taken from a Si-ZnSe interfacedomain, revealing a thin intermediate layer between the Si and ZnSe subnanowires. All scale bars in (b–d) are 2 nm. (Reprintedwith permission from Hu et al.66 Copyright 2003: American Chemical Society.)

3.1.2. Core-Shell Nanowire (Nanocables) HeterostructuresRadial core/shell nanowires represent an important class of

nanoscale building blocks with substantial potential for explor-ing fundamental electronic properties and realizing novel de-vice applications at nanoscale. SiNWs prepared via the OAGprocess have crystalline silicon core and coated with an amor-

FIG. 12. The typical diameters of the nanowires range from 50to 150 nm, and the diameters of Si bicrystalline nanowires andSnO2 nanowires within a nanowire heterostructure are ∼30 to100 nm. (Reprinted with permission from Hu et al.67 Copyright2010: Royal Society of Chemistry.)

phous oxide layer whose thickness is one-quarter to one-third ofthe nominal diameter. The outer amorphous silicon oxide shellforms due to high oxygen or water partial pressure in a reactor orthe structure post-exposure to air, as described previously. Thecrystalline silicon/amorphous silicon oxide core/shell NWs waslater further studied on its electrical properties and proposed tobe applied as novel nano-devices.71,72

It is apparent that the synthesis of radial nanowire/nanotubecore-shell heterostructures relies on the control of radial versusaxial growth. In the CVD technique, radial growth is achievedby altering conditions. The core serves as the template for thevapor-phase to homogeneously deposit on. Subsequent intro-duction of different reactants and/or dopants produces multipleshell structures of varying compositions or dopant concentra-tions, though epitaxial growth of these shells sometimes requiresmatching of lattice structures.

SiNW/CNT nanocable structure was synthesized by a sim-ple sonochemical solution method under mild ambient con-ditions and without metal catalysts, where SiNWs were usedas templates.73 Using CVD method, CNT/SiCNT,65 SiNW/cSiCNT,74 i-SiNW/p-SiNT, SiNW/SiOxNT,64 p-SiNW/cGeNT,i-GeNW/p-SiNT,75 and GeNW/SiOxNT76 core-shell nanostruc-tures were also reported early. Hu et al.77 demonstrated thegrowth of several germanium oxide and silicon oxide basedcomposite nanostructures and Ge/SiO2 coaxial nanocables,and proposed that the nano/microstructures are formed by aso-called Ge-catalyzed VLS process and temperature depen-dent, in which a certain temperature range corresponds to a

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specific morphology formed on the substrate.78 Recently,Patolsky et al.79 reported on the formation and characteriza-tion of single-crystalline Ge (core)/Si-Ge-Si (multishell) and Si(core)/Ge-Si (multishell) nanowire heterostructures with well-defined radial modulation of the chemical composition andthickness using VLS-CVD method. By controlling epitaxialgrowth on 1D nanostructure substrates to form nanowire het-erostructure and thus control its band gap, electrical propertiesof SiNWs can be improved substantially. Lieber and cowork-ers80 researched the 1D free-standing Ge/Si core/shell nanowireheterostructure, according to Figure 13, room temperature elec-trical transport measurements clearly show hole accumulation inundoped Ge/Si nanowire heterostructures, in contrast to controlexperiments on singlecomponent nanowires.

Using crystalline Si nanowires as templates, Si-core/CdSe-shell coaxial nanocables were synthesized by a simple one-stepthermal evaporation of CdSe powder at controlled experimentalconditions. Both the silicon core and the CdSe sheath are singlecrystalline.81 ZnS NW/SiNT core-shell nanocables were alsoachieved, as introduced in section 2.5.61 Because of the simi-lar crystal structures and very close lattice constants, the zincblende ZnS nanowires were able to be used as one-dimensiaonaltemplates for epitaxial growth of thin monocrystalline Sishell, giving rise to ZnS NW/SiNT core-shell nanocables (see

Figure 14). This core-shell nanostructure can be used to preparecrystalline SiNTs by chemical removal of the ZnS nanowirecores with HCl. Hu et al.82 also prepared silica nanotube-shelledGa-ZnS liquid metal-semiconductor nanowire heterojunction,which belongs to axial nanowire heterojunctions, while fromthe perspective of Si, it can be classified as silicon-based radialnanostructure.

In addition, silicon-metal radial nanostructures such as SiN-Wcore/metal shell, metal NW/SiNT have been reported. Forexample, Lieber et al.83 deposited metallic nickel onto SiNWsand the resulting coaxial nanocable may be represented bySiNW/NiNT. Transition metal atoms such as Mn and Fe lead toferromagnetic nanotubes making them interesting as nanomag-nets.84 Other previously reported silicon-metal core-shell nanos-tructured materials contain SiNW/AuNT,85 AuNW/SiO2NT,86

SiNW/Er-SiNW,87 etc.

3.2. Axial Nanowire HeterostructuresAxial heterostructures can be realized in a nanowire of two

or more different materials, or same material but with differ-ent dopants. Because of the potential barrier between adjacentconstituents, there may be appropriate current-voltage charac-teristics leading to new electrical and optical properties. This can

FIG. 13. (a) Schematic of a cross-section through the Ge/Si core/shell structure. (b) Band diagram for a Si/Ge/Si heterostructure.The dashed line indicates the position of the Fermi level, EF, which lies inside the Si band gap and below the Ge valance band edge.(c) HRTEM image of a Ge/Si core/shell nanowire with 15 nm Ge core diameter and 5 nm Si shell thickness. (d) Room temperatureelectrical transport in Ge/Si nanowires. I-VSD characteristics recorded on a 10 nm core diameter Ge/Si nanowire device with sourcedrain separation L = 1 µm. The different curves correspond to the back-gate voltage Vg values of +10 V (dashed line), 0 (solidline), and −10 V (dotted line). The upper inset I − Vg for the same device at VSD = −1 V. (e) I − VSD measurements on i-Si (blue,20 nm diameter, 1 µm channel length) and i-Ge (red, 20 nm diameter, 1 µm channel length) nanowires. The data were recordedfor Vg = 0 and −10 V, corresponding to off and on states, respectively. (Reprinted with permission from Lu et al.80 Copyright2005: National Academy of Sciences.) (Color figure available online.)

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FIG. 14. (a) TEM image of a segment of a ZnS NW/SiNT core-shell nanocable. (b) TEM image showing the residual segmentsof the ZnS nanowire template in the open-ended Si nanotube after treated with HCl solution. Scale bars in (a) and (b): 100 nm.(c) HRTEM image taken from the interfacial domain between the Si shell and ZnS core of a ZnS NW/SiNT core/shell nanowire,revealing an epitaxial relationship between the Si shell and the ZnS core. Scale bar: 2 nm. (d) Line-scanning (indicated by a whiteline in a) elemental mapping displaying Si, Zn, and S spatial elemental distribution profiles across the ZnS NW/SiNT core-shellinterface. (Reprinted with permission from Hu et al.61 Copyright 2004: John Wiley and Sons.) (Color figure available online.)

be realized by the creation of various heterostructures includingp-n junctions, metal-oxide-semiconductor junctions, or metal-semiconductor contacts that allow reliable signal processing.

Synthesis of junctions between carbon nanotubes and SiNWswas reported. The nanojunctions are obtained from two ap-proaches, i.e., CNTs growing from the SiNW end (SiNW-CNT)and SiNW growing from the CNT end (CNT-SiNW).63 Be-cause MWCNTs are typically metallic, these sharp SiNW-CNTnanojunctions exhibit typical behavior of metal-semiconductorjunctions. N-SiNW/p-SiNW superlattices were achieved withinthe nanowires by repeatedly modulating of the vapor-phasesemiconductor reactants during the growth of the wires, whichcomprise alternating p- and n-type SiNWs semiconductors.88

Similarly, periodic longitudinal heterostructures such as single-crystalline nanowires with longitudinal Si/SiGe superlatticestructure were successfully grown in a block-by-block fashion.These heterojunctions and superlattice formation are essentialfor many potential applications of semiconductor nanowiresin nanoscale optoelectronics.89 Fabrication and electrolumi-nescence of an n-ZnO nanorod/p-Si heterojunction were re-searched.90 Electroluminescent devices were constructed usinghigh-molecular-weigh polymers as the fill-in, and the I-V char-acteristics were diode-like.

Metal-semiconductor nanowire junctions can be prepared asa fundamental component of a novel miniaturized semiconduc-tor device. SiNW/metallic nickel silicide (NiSi) nanowire het-erostructures with atomically sharp metal-semiconductor inter-faces, ideal resistivities and high failure-current densities havebeen synthesized.83 The fabrication and structural characteri-zation of NiSi-Si nanowire heterostructures and superlatticesare shown in Figure 15. We also have prepared an end-to-endcrystallographically oriented In-Si nanowire contact that uni-

formly sheathed with amorphous silica through a simultaneousthermal evaporation of In and SiO powder mixture.91 As Fig-ure 16 shows, the diameter of the 1D nanostructure is ∼200nm. The In branch of a given junction, confined within the sil-ica nanotube, displays a thermal expansion similar to that ofbulk metallic In, which improves prospects for the design of aunique temperature-driven switch and/or sensor within a metal-semiconductor electronic device. Pt6Si5 and Ag-Si nanowireheterojunctions with no catalyst impurities were synthesizedvia combination of electrochemical deposition and CVD withAAO template.92

Transition metal silicides represent an extremely broad set ofrefractory materials that are currently employed for many appli-cations. Here, the 1D metal silicides nanowires are regarded asaxial structure despite no heterojunctions within them. Chem-ical synthesis of silicide nanowires is more complicated com-pared with other classes of nanomaterials due to the complexphase behavior between metals and silicon and the complexstoichiometries and structures of their resulting compounds.Recently, several synthetic strategies have been developed toprepare silicide nanowires to overcome this challenge. Schmittet al.93 reviewed the current strategies for synthesizing free-standing transition metal silicide nanowires, including NiSi,PtSi, FeSi2, CoSi, Mn4Si7, etc.

3.3. Hierarchical Nanowire HeterostructuresNew hierarchical heterostructures, in which the major cores

and the branches consist of different materials, have attractedconsiderable attention with respect to the realization of mul-ticomponent system functional electronic devices. Si- andGe- based materials in the functional structures represent an

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FIG. 15. (a) Fabrication of NiSi-Si nanowire heterostructures and superlattices. (1) Si nanowires (blue) dispersed on a substrate are(2) coated with photoresist (gray) and lithographically patterned, (3) selectively coated with Ni metal (green) to a total thicknesscomparable to the Si nanowire diameter, and (4) reacted at 550◦C to form NiSi, resulting in NiSi-Si nanowires. (b) Dark-fieldoptical image of a single NiSi-Si nanowire heterostructure. The bright green segments correspond to silicon and the dark segmentsto NiSi. (c) TEM image of a NiSi-Si nanowire. The bright segments of the nanowire correspond to silicon, and the dark segmentscorrespond to NiSi. (d) HRTEM image of the junction between NiSi and Si showing an atomically abrupt interface. Insets:two-dimensional Fourier transforms of the image depicting the [110] and [111] zone axes of NiSi and Si, respectively. (Reprintedwith permission from Wu et al.83 Copyright 2004: Nature Publishing Group.) (Color figure available online.)

alternative candidate for micro- and nanoelectronics develop-ment. Ye et al.94 have reported on the fabrication of a hierarchi-cal heterostructure consisting of single-crystalline Si nanowiresstanding on silica microwires, in which SiNW is physicallyplaced on the surface of a silica microwire, deteriorating thematerial semiconducting performance within a device.

Hu et al. reported the novel hierarchical heterostructuresmade of SiO2 nanowires on Si microwires95 and SiO2 nanowireson Ge nanowires,78 in which numerous aligned SiO2 nanowireshave been grown on Si or Ge single-crystalline wires through theformation of multiple junctions. Figure 17 shows SEM and TEMimages of the “pine-tree-branch”-like product. There are manyspherical particles attached to the tips of the structures, indicat-ing the Si core wires were grown by a Sn-catalyzed VLS process,and then served as a template for the growth of branching SiO2

nanowires by a VLS process. The diameters of the structuresare not uniform along their axes but gradually decrease from thebottoms to the tips. As-grown Si-SiO2 hierarchical heterostruc-tures exhibit intense cathodoluminescence in the visible regionpeaked at ∼462 nm, which is comparable to the best valuesreported for bulk crystalline SiO2 and amorphous SiO2 films,suggesting important candidate materials for optical communi-cation wires or fibers and other optical devices. In the SiO2/Genanowire hierarchical heterostructures, the product is composedof many curved wires with lengths of up to several hundreds ofmicrometers and many finer wires entwined around each thicktrunk wire. The twined wires grow as sub-wires rather than as

simple adhesions on each thick wire, forming self-assemblingmultiple nanojunctions.

The demonstrated synthesis of multibranched nanowirestructures introducing the possibility of fabricating hierarchicalnanostructures of increased complexity and functionality. Doerket al.96 reported growth of branching Si nanowires with controlover region of branching, which is seeded by Au-Si surfacemigration. This work highlights a facile route for the rationalsynthesis of branched nanowires, in which region of branchingand secondary growth may be controlled independently, render-ing the process essentially modular. Hetero-epitaxial growth ofsingle-crystalline GaAs whiskers on Si nanowire trunks form-ing hierarchical star-like structures with a six-fold symmetrywas also reported.97 The ability to prepare branched NW struc-tures should open new opportunities for both fundamental re-search and applications including monolithic three-dimensionalnanoelectronics and nanophotonics.

3.4. SummaryThe success of semiconductor integrated circuits has largely

hinged on the capability of forming heterostructures throughcontrolled doping and interfacing, as semiconductor het-erostructures enable the confinement of electrons and holes, theguiding of light, and modulation of phonon transport and carriermobility. The 1D nanowire heterostructures are applicable to actas building blocks of microscopic-scale devices and intergrated

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FIG. 16. (a) TEM image of typical In-Si nanowire heterojunction confined within a silica tube and respective EDS spectra takenfrom the regions indicated with the white circles on the nanowire. (b) STEM image depicting Si (light) and In (dark) domains withinan In-Si nanowire junction. (c–e) In, Si and O elemental maps demonstrating the elemental-spatial distribution. (f) ConsecutiveTEM images of melting and thermal expansion of an In column (the part of an In-Si heterojunction) during TEM heating in situ.(Reprinted with permission from Zhan et al.91 Copyright 2005: John Wiley and Sons.) (Color figure available online.)

circuits, ascribing to their particular structures and excellentproperties. Future developments will rely on improved fabrica-tion processes and novel synthesis methods to better control thedimensions, compositions, structures, interfaces, uniformity andyield of the heterostructures. It will be crucial for researchers todevise simple and reproducible strategies for assembling, ori-enting, and integrating nanowire heterostructures into functionalmicro-/nanoelectronic devices. Silicon-based nanoscale semi-conductor devices have been seen as the most promising tech-nique, and fabrication of semiconductor nanowire heterostruc-tures is expected to draw a wide field of applications with goodprospects.

4. PROPERTIES AND APPLICATIONSCompared with bulk materials, low-dimensional nanoscale

materials, with their large surface areas and possible quantum-confinement effects, exhibit distinct electronic, optical, andchemical properties. These fundamentally properties couldeventually lead to significant breakthroughs in their commer-cial applications. In the past decade, Silicon-based materials

nanostructures have garnered the greatest attention for a varietyof applications including electromechanical devices, electronicdevices, luminescent or electro optical devices, biosensors orchemical detectors, etc.

4.1. Mechanical Properties and ElectromechanicalDevices

Some nanostructures exhibit the superior mechanical prop-erties such as elastic modulus and fracture stress to those ofbulk materials.98,99 With these mechanical properties, nanoscalestructures have been considered for developing the mechani-cal devices such as nanoscale resonators. For example, CNTas nanoscale resonant device can bear ultrahigh resonant fre-quency in the range of 100 MHz to 1 GHz due to excellentelastic properties.100 Silicon nanowire has been regarded as oneof the popular nanoscale materials. It is believed that mechani-cal characterization of 1D silicon nanostructure is quite essentialfor further applications of SiNWs to electromechanical devicesas a sensor or actuator.

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FIG. 17. SEM images of Si-SiO2 hierarchical heterostructures.(a) Low-magnification view. (b) High-magnification view re-vealing a Si core wire and packed and aligned cover made ofSiO2 nanowires. (c, d) The tips terminating with a Sn ball.(e) A flat plate-like tip-end after removal of the Sn ball. (f) Thewave-like convexities on the Si wire’s surface along its axis, theinsets show ED patterns taken from the SiO2 nanowires (lowerleft) and the Si core wire (upper right), respectively. (Reprintedwith permission from Hu et al.95 Copyright 2005: John Wileyand Sons.)

In quantifying the size effects on elastic properties of SiNWsand predicting their performance, scientists demonstrated theexcellent fracture properties of SiNWs, which is a critical factorto the reliability of new nanodevices. The SiNWs showed ultra-high flexibility and extreme strength. The elastic-plastic-fractureprocesses of a single SiNW indicate that the large-strain plas-ticity of SiNWs via a brittle-ductile transition originates from adislocation-initiated amorphization, which is in contrast to themechanical behavior of bulk silicon.101 As Figure 18 shows, theforce-deflection distance curve in the large-displacement regimedemonstrates that the mechanical behavior of the SiNW still fol-lows Hooke’s law within the limits of less than 50 nN, whichdemonstrated the standard buckling behavior of a slender col-umn under the action of an axial load. At the maximum elasticpoint, the strain of the NW was ca. 1.5%, much higher than0.2% for most typical metallic materials. The elastic constant ofthe NW was determined to be 175-200 GPa. The critical loadPcr, the elastic modulus E, moment of inertia I0, length of theNW L0, and effective factor K agree with the Euler’s formula,Pcr= π2EI0/(KL0)2.102 It was verified that the elastic modulusof nanowires from AFM bending experiment is very sensitive toboundary conditions.103 Recently, Sohn et al.104 discovered thatelastic modulus of SiNW is well fitted to theoretical expectationfrom Hertz theory. It is proved that Young’s modulus of SiNWswith their diameter of ∼80 nm to ∼600 nm is independent of

FIG. 18. (a-f) A series of snapshot SEM images showing thecontinuous buckling of the SiNW. (g) Corresponding curve ofthe applied force F vs change in chord length |L-L0| when theNW was buckled. (h) Calculated stress-strain curve of the buck-ling of the NW. Inset: Schematic diagram of the deformationapproximation. (Reprinted with permission from Hsin et al.102

Copyright 2008: John Wiley and Sons.)

their diameters, indicating that finite size effect due to surfaceeffect does not play any role in elastic properties of nanowires.

Applying a strain to a silicon crystal results in a change inelectrical conductivity due to the piezoresistance effect (i.e.,change of resistivity with stress/strain), which can be exploredin order to improve the performance of silicon transistors. Yanget al.105 discovered that SiNWs possess an unusually largepiezoresistance effect compared with bulk Si crystal. By per-forming mechanical manipulations and electrical measurementssimultaneously, they evaluated the piezoresistance effect (orelectromechanical property) of the SiNWs. The longitudinalpiezoresistance coefficient along the direction of [111] and [110]oriented p-type SiNWs increases with decreasing diameter. Thisenhanced piezoresistance effect could find applications in sili-con nanotechnology, flexible electronics as well as in nanoelec-tromechanical system resonators.106 Intrinsic strains may existin many nanoscale materials, and strain sensitivity could bea basic issue affecting the performance of these nanostructure-based electronics. Utilizing the SiNWs for frequency conversionand exploiting their intrinsic strong piezoresistive effect, a newpiezoresistive detection technique has been developed.107

4.2. Electrical Properties and Electronic DevicesElectrical properties of SiNWs are totally different from that

of bulk Si because of unique structure and quantum size ef-fects. The main factor influencing the electrical conductivityof SiNWs must be the impurity elements, the concentration of

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the dopants and the distribution of electrically active n- and p-type dopants.108 The incorporation of electrically active dopantsin semiconductor materials is central to development of elec-tronic and optoelectronic devices. FET devices fabricated fromsingle crystal n-type SiNWs with controlled phosphorus dopantconcentrations exhibit greater mobilities than high-performanceplanar silicon FETs.109 The diameter of SiNW is another impor-tant factor affecting its electric properties. Scanning tunnelingspectroscopy measurements of the SiNWs show an increase inthe electronic band gap from 1.1 to 3.5 eV as the wire diametershrank from 7 to 1.3 nm, which will conform to the results oftheoretical calculations.4 Owing to the large surface-to-volumeratio of nanostructures, surface states invariably play a muchmore dominant role in the electrical characteristics of nanos-tructures than that in films and bulk crystals.110 For example, theconductance of oxide-coated SiNWs functionalized with aminosiloxanes increases as the pH value of the solution, suggest-ing the nanowire field-effect devices to detect species in liquidsolution.111 SiNWs modified by covalent Si-CH3 functionalitywithout intervening oxide, show atmospheric stability, high con-ductance values, and low surface defect levels, and allow for theformation of air-stable SiNW FETs having on-off ratios in ex-cess of 105 over a relatively small gate voltage swing (±2V).112

In addition, the conductivity of SiNWs exhibits high sensitiv-ity to humidity or various vapors,113 surface passivation114 andporous on its surface.6

By controlling epitaxial growth on 1D nanostructure sub-strates to form nanowire heterostructure and thus control its bandgap, electrical properties of SiNWs can be improved substan-tially. Free-standing Ge/Si core/shell nanowire heterostructurewas designed to improve its conductivity.115 It is demonstratedthat the band gap of the core-shell wire with a diameter of 5 nmis smaller than that of both pure Si and Ge wires with the samediameter, which is ascribed to the intrinsic strain between Geand Si layers due to the quantum confinement effect.116 Band-structure design and controlled epitaxial growth will open manyopportunities for fundamental studies on 1D nanowires in thefuture. Lieber et al.117 reported a general approach for 3D mul-tifunctional electronics based on the layer-by-layer assemblyof Ge/Si core/shell NWs building blocks, and fabricated FETsbased on ten vertically stacked layers. It was reported that top-gated Ge/Si NW FET heterostructures with high-κ dielectricsexhibit scaled transconductance and on-current values of3.3 mS µm-1 and 2.1 mA µm-1, respectively, which are three tofour times greater than those for state-of-the-art MOSFETs.118

Semiconductor nanowires composed of Si and other ma-terials can also function as FET devices.119–121 SiNWs basedtransistors exhibit superior properties to bulk single-crystallinedevices, and with the demonstration of addressing high-densitynanowire circuits, thus, they pose to be very promising build-ing blocks for future nanoelectronic devices. Yang et al.122

demonstrate the direct vertical integration of SiNW arrays intosurrounding gate field effect transistors, which exhibit satis-factory electronic properties. Axial modulation-doped SiNWs

were employed to fabricate electronic devices such as inde-pendent address decoders and tunable, coupled quantum dots,which are encoded by synthesis rather than created by con-ventional lithography-based techniques.123 Single-crystal PtSinanowires and PtSi/Si/PtSi nanowire heterostructures were fab-ricated into high-performance nanoscale FET from intrinsicSiNWs, in which the source and drain contacts are definedby the metallic PtSi nanowire regions, and the gate length isdefined by the SiNW region, as shown in Figure 19. Electri-cal measurements show nearly perfect p-channel enhancementmode transistor behavior with a normalized transconductanceof 0.3 mS/µm, field-effect hole mobility of 168 cm2/V·s, andon/off ratio >107, demonstrating the best performing devicefrom intrinsic SiNWs.124 Pure SiNTs were also suitable for FETfabrication. It was indicated that the SiNTs show weak n-typesemiconductivity, and a mobility of 3.7 × 10−2cm2/Vs, whichis 1 order larger than that of intrinsic Si.62 Methods have beendeveloped to fabricate three-dimensional integrate structures orelectronic array devices,125–128 which will enable their efficientand economical incorporation into devices, such as chemicalsensors, FETs, and nanomechanical resonators.129

4.3. Optical Properties and Optoelectronic DevicesBulk silicon does not emit visible light since it is an indi-

rect band gap material, hence Si can be hardly explored as anoptically active material for functional optoelectronics. How-ever, low-dimensional silicon nanostructures such as quantumdots and porous SiNWs can exhibit luminescence in the visi-ble range due to strong quantum confinement effect.6 In recentyears, SiNWs have been made into various functional optoelec-tronic devices.

NW-based photonic systems provide many interesting andnovel device concepts in comparison with planar technology,such as ultrafast optical studies of carrier dynamics in semi-conductor nanowires.130 Crossed NW devices are efficient p-n junction diodes if assembled with direct bandgap semicon-ductor NWs, such as efficient nanoscale light emitting diodes(LEDs),131,132 computing systems, ultrahigh density optical in-formation storage and multiplexed chemical/biological analy-sis.133 The development of high-sensitivity nanoscale photode-tectors is especially important for the realization of integratednanophotonic systems. Hayden et al.134 reported nanoscaleavalanche photodiodes (APDs) consisting of crossed Si-CdSnanowires p-n heterojunction diodes.

As silicon is the leading material used in the photovoltaic(PV) industry, SiNW solar cells have become the focus of PVresearch since SiNW solar cell design may be readily com-patible with the existing silicon industry and processing tech-nology. The use of single nanowires as photovoltaic elementspresents several key advantages, which may be leveraged toproduce high-efficiency, robust, integrated nanoscale PV powersources. As shown in Figure 20, two unique structural motifsthat can yield functional PV devices at the single nanowire

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FIG. 19. PtSi/i-Si/PtSi nanowire heterostructures. (a) Relative energy band alignment between PtSi and Si. (b) Schematic andSEM image of the device. (c) Drain current (ID) vs drain-source voltage (VD) at increasing negative gate voltages (VGS). (d) ID vsVG curves and the inset shows -ID vs VD in the exponential scale, highlighting the on/off ratio >107, and ambipolar transport witha subthreshold swing of 110 to 220 mV/decade for hole transport and 320 mV/decade for electron transport. (Reprinted from Linet al.124 Copyright 2008: American Chemical Society.) (Color figure available online.)

level include p-type/intrinsic/n-type (p-i-n) dopant modulationin axial and radial geometries.135 It was demonstrated singlecoaxial SiNW solar cells with short-circuit current density (Jsc)and power conversion efficiencies reaching 23.9 mA/cm2 and to3.4%, respectively, under 1 solar equivalent illumination.136 Ax-ial modulation-doped p-i-n and tandem p-i-n+-p+-i-n SiNW asbuilding blocks for photovoltaic devices were also fabricated.137

Fundamental studies of well-defined modulation-doped NWphotovoltaics should enable the intrinsic limits of nanoscale ele-ments to be defined, and such elements hold substantial promiseas building blocks for the development of nanoscale solar en-ergy conversion systems. Semiconductor heterojunctions canabsorb a different region of the solar spectrum and have en-hanced performances.138 For example, TiO2 coated Si nanowireheterostructures arrays exhibit higher photocurrent density dueto lower reflectance and higher surface area. Furthermore, then-n heterojunction could potentially increase the efficiency ofthe photovoltaic cell due to a higher open circuit voltage andhigher photocurrent.139 In addition, surface modification is aneffective way to improve optical properties of SiNWs, such ashydrogenated amorphous SiNWs,140 chemical-etching treat,141

and PtNP-decorated SiNWs photoelectrode.142

Metal modified SiNWs show good photocatalytic proper-ties.143 Metal (Au, Cu)-modified SiNWs are superior catalystsfor selective oxidation of hydrocarbons, while SiNWs are pow-erful substrate support (enhancing efficiency and selectivity) fornanocatalysts.144

4.4. Biological and Chemical SensorsSemiconductor nanowires configured as electronic devices

have emerged as a general platform for ultra-sensitive directelectrical detection of biological and chemical species, includingproteins, nucleic acids, small drug molecules and viruses.145,146

The detection technique possesses attractive features includinglable-free, ultrahigh sensitivity, exquisite selectivity, real-timeelectrical signal transduction and direct electrical readout.112

Biological macromolecules, such as proteins and nucleic acids,are typically charged in aqueous solution and, as such, can be de-tected readily by nanowire sensors when appropriate receptorsare linked to the nanowire active surface. For instances, two-terminal SiNW electronic devices that function as ultrasensitiveand good selective detectors of DNA,147 and one-dimensional

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FIG. 20. (a) Schematic of carrier generation and separation in axial and radial p-i-n nanowires. The pink and blue spheresdenote the holes and electrons, respectively. (b) Schematics of device composed of p-core, i-shell, n-shell and fabricating process:PECVD-coating SiO2, selective etching to expose the p-core, metal contacts depositing on the p-core and n-shell. (c) SEM imagescorresponding to schematics in (b). Scale bars are 100 nm (left), 200 nm (middle) and 1.5 µm (right). (d) Dark I-V curves ofa p-i-n device with contacts on core-core, shell-shell and different core-shell combinations. Inset is optical microscope imageof the device. Scale bar, 5 µm. (e) Dark and light I-V curves of the p-i-n silicon nanowire photovoltaic device. (Reprinted withpermission from Tian et al.135 Copyright 2009, Royal Society of Chemistry, and Tian et al.136 Copyright 2007: Nature PublishingGroup.) (Color figure available online.)

FET arrays with ultralong SiNWs were exploited to detect can-cer marker proteins.14

Because of high aspect ratio (<103) and sufficient rigid to bemechanically manipulated, SiNWs can be potentially utilized asa powerful tool for studying intra- and intercellular biologicalprocess. Kim et al.148 cultured mammalian cells on a silicon sub-strate with a vertically aligned SiNW array on it. The penetrationof the SiNW array into individual cells influences the longevityof the cells to some extent. Lieber et al.149 made an integration ofa nano FET device at the tip of an acute-angle kinked SiNW asFigure 21 indicates, which allows 3D probe presentation. Apartfrom exhibited conductance and sensitivity in aqueous solution,the 3D nano FET probes modified with phospholipid bilayerscan enter single cells to allow robust recording of intracellularpotentials.

As for chemical sensors of SiNWs, similar principles weredevoted to realize detection of chemical substances. For in-stances, HF-etched Si nanowires exhibit high chemical sensi-tivity of the resistance to NH3 and water vapor exposure,150 andSiNWs array coated with AgNPs can be explored as ultrahigh-sensitivity detection of Sudan dyes,151 and SiNWs covalentlymodified by fluorescence ligand have potential as optical sen-sor to realize a highly sensitive and selective detection ofCu(II).152

4.5. Thermoelectric PropertiesAnother important and unique property of SiNWs is ther-

moelectric, which interconvert thermal gradients and electricfields for power generation or for refrigeration. Thermoelec-tric materials, such as Bi2Te3, Sb2Te3, etc., currently find onlyniche applications because of their limited efficiency. Boukaiet al.153 reported that maximum efficient thermoelectric perfor-mance from SiNWs can be achieved by tuning nanowire sizeand impurity doping levels, and demonstrated an approximately100-fold improvement of ZT than bulk Si over a broad tem-perature range, including ZT ≈1 at 200 K. Here thermoelectricefficiency ZT is a function of the Seebeck coefficient or ther-moelectric power, and of absolute temperature, electrical andthermal conductivities, defined as ZT=S2σT/κ , S is the seebeckcoefficient, σ and κ are the electrical and thermal conductivities,respectively. Temperature is also the factor contributing to ZT aswell as κ and S2, Figure 22. Reduction of thermal conductivitycontributes to the improvement of ZT value. The thermal con-ductivities measurements of individual single crystalline SiNWswith different diameters show that SiNW thermal conductivity ismuch lower than the corresponding bulk value, that significantlyreduced from the bulk value of 150 (at 300 K) to ∼8 W/mk.154

The size dependence of thermal conductivity is a direct result ofstrong phonon boundary scattering at the nanowire surface. The

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FIG. 21. (a) SEM image of a doubly kinked nanowire with a cis configuration, L is the length of segment between two adjacentkinks, and false-color fluorescence image of a lipid-coated nanowire probe. Scale bars, 50 nm and 5 µm, respectively. (b) Schematicsof nanowire probe entrance into a cell. (c) Differential interference contrast microscopy images of phospholipid-modified nanoFET probe moved into contact and then away from the cell, scale bars, 5 µm. (d, e) Electrical recording of the nano FET probe withand without phospholipids surface modification. Green and blue arrows mark the beginnings of cell penetration and withdrawal,respectively. (Reprinted with permission from Tian et al.149 Copyright 2010: American Association for the Advancement ofScience.) (Color figure available online.)

FIG. 22. (a) False-color SEM image of the suspended platform device used to quantitate the thermopower and electrical andthermal conductivity of SiNW arrays. (b) Low-resolution micrograph of the suspended platform. (c) High resolution image of anarray of 20 nm wide SiNWs with Pt electrode. (d) The temperature dependence of the thermal conductivity κ . (e) The temperaturedependence of S2 for 20 nm wide SiNWs at various p-type doping concentrations. (Reprinted with permission from Boukai et al.153

Copyright 2008: Nature Publishing Group.) (Color figure available online.)

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thermal conductivity in SiNWs can be further reduced downto almost the amorphous limit by electrochemical synthesis oflarge-area, wafer-scale arrays of rough Si NWs.155 It achievedZT = 0.6 at room temperature in rough SiNWs of ∼50 nmdiameter that were processed by a wafer-scale manufacturingtechnique. At room temperature, bulk silicon is considered tobe both a good thermal conductor and electron conductor, whilerough SiNWs are essentially thermal insulators, at the sametime good electron conductors, making them good thermoelec-tric materials for waste heat recovery and power generation at arelevant temperature range.156

5. CONCLUSIONS AND OUTLOOKIn conclusion, this review described various synthesis meth-

ods of SiNWs and SiNTs, which can be categorized as gas phasegrowth, solution-based method, template-assisted method, andchemical etching method. The advantages and disadvantages ofthe bottom-up and top-down approaches were also briefly dis-cussed. Second we presented, a series of complex silicon-based1D nanostructures, including axial, radial, and hierarchical het-erostructures. Finally, we briefly summarized recent research onthe 1D silicon nanaoscale materials and their properties and ap-plications in the field of mechanics, electronics, optics, biology,chemistry, and thermoelectricity.

Given their central role in the semiconductor industry, andhence the existing set of well-established fabrication technolo-gies, SiNWs and silicon-based semiconducting nanowire het-erostructures are potentially very attractive. Due to the excellentelectron transport, thermal conduction, piezoelectricity, quan-tum confinement effect, and other unique properties, silicon-based nanoscale electronic and optoelectronic devices hold greatpromise for humankind. For instance, the practicability andminiaturization of molecular logic devices are of significance tomolecular computing, as well as to disease diagnosis, geneticscreening, and drug discovery. They may serve as powerful newtools for research in many areas of biology, the developments ofnanosensors, nanotransistors, photodetectors and photovoltaicdevices, etc. Thanks to the well-developed preparation technol-ogy and accurate characterization tools, great advances havebeen made in this field.

However, there are still many important issues remaining tobe addressed. Although the functionalization of nanotransistorsand nanosensors and other devices has been partially achieved,the research of SiNWs remains in its infancy. It is a long journeyto realize the assembly, orientation, and large-scale integrationof nanodevices. It remains a scientific challenge to controlledassembly of semiconductor nanowires into well-ordered arrays,which is essential for the implementation of integrated electronicand electromechanical systems. On the other hand, the impli-cations of dopants’ distribution in SiNWs and interfacial junc-tion in heterostructures to the materials’ performance should beinvestigated thoroughly. Future developments will rely on im-proved fabrication processes of silicon-based 1D nanostructures

and ultimately realization of the functionality of the nanostruc-tures.

Inspired by the excellent properties and applications ofSiNWs, it will lay the foundation of future science, technology,and industry in a variety of fields such as FETs, photovoltaics,biosensors or chemical detectors, etc. We are confident that wewill continue to make great strides in the science and technologyof nanoworld, based on Silicon.

ACKNOWLEDGMENTThis work was supported from the National Natural Science

Foundation of China (Grant No. 50872020), the Program forNew Century Excellent Talents of the University in China, the“Pujiang” Program of Shanghai Education Commission (GrantNo. 09PJ1400500), the “Dawn” Program of the Shanghai Edu-cation Commission (Grant No. 08SG32), the Science and Tech-nology Commission of Shanghai-based “innovation action plan”Project (Grant No. 10JC1400100), the Program for the Spe-cially Appointed Professor by Donghua University (Shanghai,P.R. China), the Program of Introducing Talents of Disciplineto Universities (No. 111-2-04) and the Innovation Foundationof DHU for PhD Graduates (No. BC20101224).

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