Recent Development of FinFET Technology for CMOS Logic and Memory Chung-Hsun Lin EECS Department...
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Transcript of Recent Development of FinFET Technology for CMOS Logic and Memory Chung-Hsun Lin EECS Department...
Recent Development of Recent Development of FinFET Technology for FinFET Technology for
CMOS Logic and MemoryCMOS Logic and Memory
Chung-Hsun LinChung-Hsun Lin
EECS DepartmentEECS Department
University of California at BerkeleyUniversity of California at Berkeley
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 2
OutlineOutline Why FinFETWhy FinFET
FinFET processFinFET process Unique features of FinFETUnique features of FinFET
Mobility, workfunction engineering, corneMobility, workfunction engineering, corner effectr effect, , QM, volume inversionQM, volume inversion
IssuesIssues Recent Recent FinFETFinFET Develop Develop
Triple-gate FinFET, Omega FET, Nanowire FinFETTriple-gate FinFET, Omega FET, Nanowire FinFET, , Independent gate, Multi-channel FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high-K Metal-gate/high-K FinFET, FinFET, SStrained FinFETtrained FinFET, Bulk FinFET, Bulk FinFET
MemoryMemory DRAM, SONOS, SRAMDRAM, SONOS, SRAM
ConclusionConclusion
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 3
MOSFET ScalingMOSFET Scaling
Same transistordesign concept
2000 2005 2010 2015 20201
10
100
GAT
E LE
NG
TH (n
m)
YEAR
LOW POWER HIGH PERFORMANCE
ITRS 2001 Projection
Technology Scaling
Investment
Market Growth
Better Performance/Cost
The first transistor 1947
The Power5 microprocessor
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 4
Scaling : Moore’s lawScaling : Moore’s law
•Source: Intel
Technology Drivers
• Reduced cost / function
• Improved performance
• Greater circuit functionality
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 5
Bulk-Si MOSFET Scaling IssuesBulk-Si MOSFET Scaling Issues
Leakage current is the primary barrier to scaling To suppress leakage, we need to employ:
Higher body doping lower carrier mobility, higher junction capacitance, increased junction leakage
Thinner gate dielectric higher gate leakage Ultra-shallow S/D junctions higher Rseries
Substrate
Gate
Source DrainLeff
Nsub
Xj
Lg
Tox
Desired characteristics:
- High ON current (Idsat)
- Low OFF current
G
S
Dcourtesy of Prof. Kuroda
Keio University
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 6
Issues for Scaling Issues for Scaling LLgg to <25 nm to <25 nm
VT variation (statistical dopant fluctuations)
Leakage
Incommensurate gains in Idsat with scaling
— limited carrier mobilities
— parasitic resistance
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 7
Advanced MOSFET StructuresAdvanced MOSFET Structures
Leakage can be suppressed by using a thin body
Ultra-Thin Body
GateGate
Silicon Substrate
Source Drain
TBOX
TSi
SiO2
SOI
Double Gate
Source Drain
Gate 1Gate 1 Vg
Tox
TSiSOI
Gate 2Gate 2
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 8
Thin-Body MOSFETsThin-Body MOSFETs
Control short-channel effects with Tbody
No channel doping needed! Relax gate oxide (Tox) scaling
Double-Gate is even more effective Scalable to 10nm gate lengths
Tbody
Ultra-Thin Body Double-Gate
Gate
Source Drain
Gate
Buried Oxide
Substrate
Source Drain
Gate
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 9
Electric Field ReductionElectric Field Reduction
Reduced vertical field in DG and UTB
No doping =No Qdepl!
Expected to benefit: Mobility Gate Leakage
Si
deplinveff ε
QQηE
+=
Gate
Buried Oxide
Substrate
Qinv
Thin-Body
Gate Qinv
QdeplBulk
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 10
Thin-Body MOSFETsThin-Body MOSFETs
Control short-channel effects with Tbody
No channel doping needed! Relax gate oxide (Tox) scaling
No channel doping needed!
Ion
Cload
Double-Gate is even more effective Scalable to 10nm gate lengths Potentially less Vt scatter (dopant fluctuation)
— Improved mobility•Lower vertical electric field•No impurity scattering
— Improved swing•Better control of SCE
•Lower VT
— No depletion or junction capacitance
Bulk
Idra
in
Vgate
DG
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 11
Circuit level benefitsCircuit level benefits
Thin body devices
Good control of SCE
Steep Sub-threshold swing
Higher Idsat
Lower Capacitance - No Cjunc and Cdepl
Better CV/I delay at lower power
2
4
68
10
20 Bulk UTB DG
Technology Lgate [nm]F
O4
Inve
rter
Del
ay [
ps]
50 35 25 18
Tbody,UTB
= 5nm
Tbody,UTB
< 5nm
Source: Leland Chang
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 12
Double-Gate MOSFETsDouble-Gate MOSFETs
Gate 1
Gate 2Current flow
S
Planar DG MOSFET
D
Vertical DG MOSFET
S
D
Current flow
Gate 1Gate 2
FinFET
S
D
Current flow
Gate 1Gate 2
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 13
Multi-Gate FinFETMulti-Gate FinFET
Rotation allows for self-aligned gates Layout similar to standard SOI FET
Gate
Drain Drain
Gate
Drain
Gate
Source
Gate
Source
Source
Drain
Gate
PlanarDG-FET
90° Rotation
FinFET
Gate
Source Drain
Gate
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 14
Poly Gate Deposition/Litho
Gate EtchSpacer Formation
S/D Implant + RTASilicidation
FinFET Process FlowFinFET Process Flow
SiO2
SOI SubstrateFin Patterning
Si Fin
BOX
Poly
Resist
Si3N4
Spacer
NiSi
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 15
FinFET Device StructureFinFET Device Structure
• All features defined by optical lithography and aggressive trimming
Gate
Source
Drain
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 16
10nm FinFET TEM10nm FinFET TEM
220ÅSiO2 cap
Lg=10nm
BOX
NiSi
Poly-Si
Si Fin
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 17
10nm FinFET I-V10nm FinFET I-V
Dual N+/P+ poly gates:- Need VT control
Low DIBLNMOS: 120 mV/V PMOS:
71 mV/V
Good SCE despite thick Tox (27Å EOT) & Wfin (26nm)- Due to large S/D doping gradient & spacer thickness
-1 0 110-9
10-7
10-5
10-3
10-9
10-7
10-5
10-3
NMOS PMOS
S=101mV/dec
S=125mV/dec
Vd=1.2V
0.1V
Vd=-1.2V
Dra
in C
urr
ent
[A/
m]
Gate Voltage [V]
-0.1V
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 18
Short-Channel EffectsShort-Channel Effects
Acceptable DIBL and subthreshold slope down to below 20nm Lgate
Nearly ideal (60mV/dec) subthreshold slope at long Lgate
NMOS better than PMOS due to slower As diffusion
0 20 40 60 80 1000
40
80
120
160
0
40
80
120
160
NMOS PMOS
Wfin
=26nm
DIB
L (m
V/V
)
Sub
thre
shol
d S
lope
(m
V/d
ec)
Gate Length (nm)
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 19
OrientationOrientation
Rotation by 45º changes orientation from (110) to (100) Intermediate rotation similar to (111)
<100>
<110>
(110)Surface
Gate
Sou
rce
Dra
in
(110) (100)
~(111) (110)
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 20
0.2 0.4 0.6 0.8 1.00
100
200
300
400
500Oxynitride
(111)
(110)
(100)
Ele
ctro
n M
ob
ility
[cm
2 /Vs]
Effective Field [MV/cm]0.2 0.4 0.6 0.8 1.0
0
100
200
300
400
500Oxynitride
(111)
(110)
(100)
Ho
le M
ob
ility
[cm
2 /Vs]
Effective Field [MV/cm]
How Mobility ChangesHow Mobility Changes
By shifting away from (100): e is degraded, h is enhanced
Can we benefit from changing the N/P ratio?
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 21
0
5
10
15
20
Oxynitride
Fanout=4
% D
elay
Sp
eed
up
vs.
(10
0)
Orientation(100) (111) (110) (100) NMOS
(110) PMOS
h, e
NAND
Inv
NOR
Gate DelayGate Delay
PMOS enhancement (20%) is larger than NMOS degradation (8%)
Net delay improvement
Trade off h and e
NOR: PMOS stack h very important Most improvement
NAND: NMOS stack h less important Least improvement
Lgate=35nm
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 22
Optimized FinFETOptimized FinFET
Trade off layout area for performance
Gate
Source
Drain
Source
Drain
Gate
Source
Drain
SourceDrain
(100) NMOS(110) PMOS
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 23
FinFET Layout AreaFinFET Layout Area
Non-(100) orientation saves area Higher PMOS Idsat reduces drawn W
45º orientation is less area efficient for smaller W These devices are small anyway…does it matter? Use only in critical path?
0.0
0.2
0.4
0.6
0.8
(100) (110) (111)
45oN / 90oP
90oN / 45oP
Idsatn,p=1.1mA
Lay
ou
t A
rea
[m
2 ]0
10
20
30
40
50
Idsatn,p=110mA
Lay
ou
t A
rea
[m
2 ]
Inverter
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 24
Hybrid-Orientation-Technology (HOT)
Super HOT: SOI version DSB: bulk version
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 25
VVTT: What CMOS Needs…: What CMOS Needs…
Need symmetrical VT’s for proper CMOS operation
Need low VT’s for speed
InputO
utp
ut
Inverter Response
VDD
VDD0
VIN=
VTN
VIN=
VDD-VTP
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 26
Single gate material VTn = -VTp = 0.4V
N+/P+ Poly VTn = -VTp = -0.2V
• For low body doping, desired M values are:
~ 4.5 eV for NMOS ~ 5.0 eV for PMOS
Need two separate work functions for NMOS and PMOS!
Gate Work FunctionGate Work Function
4.2 4.4 4.6 4.8 5.0 5.2
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
4.95eV
VT=0.2V
4.52eVP
+ Po
ly
N+ P
oly
VT=0.4V
VTn -VTp
Th
resh
old
Vo
ltag
e [V
]
Gate Workfunction [eV]
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 27
Molybdenum Molybdenum MM Engineering Engineeringby Ion Implantationby Ion Implantation
M can be lowered by N+ implantation and thermal annealM increases with
dose energy
(N segregates to SiO2
interface & forms Mo2N)
Anneal time = 15m except for 900oC (15s)TMo = 15nm
P. Ranade et al., IEDM 2002
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 28
Mo-Gated FinFETs (PMOS)Mo-Gated FinFETs (PMOS)
Y.-K. Choi et al., IEDM 2002
-0.8 -0.6 -0.4 -0.2 0.0 0.210-13
10-11
10-9
10-7
10-5
10-3
Drai
n Cu
rren
t, Id
[A/u
m]
Gate Voltage, Vg[V]
Mo
MoN(N2=5x1015cm-2)
Vt shift
Lg=80nm, TSi=10nm
Vds=0.05V
• Alternative technique:Full silicidication (NiSi) of n+/p+ Si gates(J. Kedzierski et al., W. Maszara et al., Z. Krivokapic et al., IEDM 2002)
• |Vt|=0.2V for lightly doped body, and is adjustable
by N+ implantation
Potential issues include: - dopant penetration- thermal stability - stress/adhesion- gate dielectric reliability
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 29
Corner Effect in Triple or More Corner Effect in Triple or More GatesGates
Corner EffectCorner Effect Different VDifferent Vthth at corner region at corner region Significant subthreshold leakage currentSignificant subthreshold leakage current Strong corner radius, body doping Strong corner radius, body doping
dependencedependence
B. Doyle et al., VLSI Tech., p. 133, 2003
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 30
Corner Effect [1]Corner Effect [1]
0 5 10 15 20 25 300
1
2
3
C
urre
nt D
ensi
ty (
A/c
m2 )
Position (nm)
z direction y direction
0 5 10 15 20 25 300
1x106
2x106
3x106
4x106
Cu
rre
nt
De
nsi
ty (
A/c
m2 )
Position (nm)
z direction y direction
DESSIS 3-D device DESSIS 3-D device simulatorsimulator
Ideal rectangular Ideal rectangular fin shapefin shape
NNsubsub=1e15cm=1e15cm-3-3
Vg=1 V
y
z Vg=0.2 V
y
z
2D current density distribution 2D current density distribution
S
D
G
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 31
Corner Effect [2]Corner Effect [2]
Nsub=5e18cm-3
Vg=0.2 V
Vg=1 V
2D current density distribution
y
z
y
z
2D current density distribution
-0.015-0.010
-0.0050.000
0.0050.010
0.015
0
1x1020
2x1020
3x1020
4x1020
0.000
0.005
0.0100.015
0.0200.025
0.030
Ele
ctro
n D
en
sity
(cm
-3)
Y Axis
X Axis
flat
corner
-0.015-0.010
-0.0050.000
0.0050.010
0.015
0.0
5.0x106
1.0x107
1.5x107
2.0x107
0.000
0.005
0.0100.015
0.0200.025
0.030
Cu
rre
nt D
en
sity
(A
/cm
2)
Y Axis
X Axis
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 32
3D Simulation w/ Various Shape of 3D Simulation w/ Various Shape of CornerCorner
Lg=1m, Wsi=30nm, Hsi=30nm, Tox=1nm R=0, 5, 10, 15m
0.0 0.5 1.0 1.5 2.01E-13
1E-11
1E-9
1E-7
1E-5
Nor
mal
ized
Dra
in C
urre
nt (
A/
m)
Gate Voltage (V)
R=15nm R=10nm R=5nm R=0nm
0.0 0.5 1.0 1.5 2.00.0
2.0x10-5
4.0x10-5
6.0x10-5
8.0x10-5
Nor
mal
ized
Dra
in C
urre
nt (
A/
m)
Gate Voltage (V)
R=15nm R=10nm R=5nm R=0nm
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 33
Short Channel BehaviorShort Channel Behavior
MG device with sharp corner shows better short channel behavior than the rounded corner
0 200 400 600 800 10000
20
40
60
80
100
D
IBL
(mV
/V)
Gate Length (nm)
R=0nm R=15nm
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 34
Double-humps induced by cap Double-humps induced by cap transistortransistor
30x30nm structure, Tox=3nm, Lg=1mm, Nsub=5e18cm-3
Cap transistor induced lower Vt is very significant.
It may attribute to thicker Tox, and more partial depleted.
0.3 0.6 0.9 1.2 1.5 1.80.0
1.0x10-6
2.0x10-6
3.0x10-6
4.0x10-6
dGm
/dV
g
Gate Voltage (V)
30x30nmL
g=1m, T
ox=3nm
Nsub
=5e18cm-3
0.0 0.5 1.0 1.5 2.01E-17
1E-15
1E-13
1E-11
1E-9
1E-7
1E-5
Dra
in C
urre
nt (
A)
Gate Voltage (V)
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 35
Volume Inversion [1]Volume Inversion [1]
eDensity
6.1E+13
5.3E+13
4.5E+13
3.6E+13
2.8E+13
2.0E+13
Gate Gate Gate Gate
Oxide Oxide
eDensity
6.1E+13
5.3E+13
4.5E+13
3.6E+13
2.8E+13
2.0E+13
N sub =10 15 cm -3 N sub =10 18 cm -3
T si T si
The electron density distribution from the 3-D ISE device simulator. Volume inversion is significant in intrinsic channel SDG (left).
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 36
Volume Inversion [2]Volume Inversion [2]
0.0 0.2 0.4 0.6 0.8 1.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6 Nsub
= 1015 cm-3
s0, 10nm
s, 10nm
s0, 20nm
s, 20nm
Ele
ctri
c P
ote
nti
al (
V)
Gate Voltage (V)
For intrinsic channel doping, volume inversion is valid and the potential through the Si film is flat in the subthreshold region.
The inversion charge (current) in the subthreshold region is proportional to Tsi.
0.0 0.2 0.4 0.6 0.8 1.01E-15
1E-13
1E-11
1E-9
1E-7
1E-5
Tsi
Nsub
= 1015
cm-3
Tsi = 10 nm Tsi = 20 nm
Inve
rsio
n c
har
ge
shee
t d
ensi
ty (
C/c
m2 )
Gate Voltage (V)
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 37
QM Surface Potential CorrectionQM Surface Potential Correction
Undoped case
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 38
I-V VerificationI-V Verification
Model can predict both subthreshold and strong inversion region well.
0.0 0.5 1.0 1.5 2.00.0
1.0x10-5
2.0x10-5
3.0x10-5
4.0x10-5
5.0x10-5
6.0x10-5
Dra
in C
urre
nt (
A/
m)
Gate Voltage (V)
Symbols: 2D simulationLines: Model
Classic QM
0.5 1.0 1.5 2.01E-14
1E-12
1E-10
1E-8
1E-6
1E-4
Dra
in C
urre
nt (
A/
m)
Gate Voltage (V)
Symbols: 2D simulationLines: Model
Classic QM
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 39
S/D Series Resistance IssueS/D Series Resistance Issue
S/D series resistance will degrade the performance of thin body device
Can be improved by the selective Si epitaxy raised S/D
J. Kedzierski et al., IEDM 2001
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 40
OutlineOutline Why FinFETWhy FinFET
FinFET processFinFET process Unique features of FinFETUnique features of FinFET
Mobility, workfunction engineering, corneMobility, workfunction engineering, corner effectr effect, , QM, volume inversionQM, volume inversion
IssuesIssues Recent Recent FinFETFinFET Develop Develop
Triple-gate FinFET, Omega FET, Nanowire FinFETTriple-gate FinFET, Omega FET, Nanowire FinFET, , Independent gate, Multi-channel FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high-K Metal-gate/high-K FinFET, FinFET, SStrained FinFETtrained FinFET, Bulk FinFET, Bulk FinFET
MemoryMemory DRAM, SONOS, SRAMDRAM, SONOS, SRAM
ConclusionConclusion
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 41
Triple-Gate TransistorTriple-Gate Transistor
B. Doyle et al., VLSI Tech. 2003
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 42
Omega-Gate TransistorOmega-Gate Transistor
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 43
5nm Nanowire FinFET5nm Nanowire FinFET
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 44
Independent Gate FinFETIndependent Gate FinFET
Control the threshold voltage Ideal rectangular shape of Si fin
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 45
Independent Gate FinFETIndependent Gate FinFET
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 46
Multi-Channel FinFETMulti-Channel FinFET
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 47
Metal Gate FinFETMetal Gate FinFET
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 48
Metal-Gate FinFETMetal-Gate FinFET
Vth adjustment Improvement of IonK.G. Anil et al., VLSI Tech. 2005
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 49
TiN/HfO2 FinFETTiN/HfO2 FinFET
Vth adjustment Reduce Gate
leakageN. Collaert et al., VLSI Tech. 2005
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 50
Inverted T Channel (ITFET)Inverted T Channel (ITFET)
UTB + FinFET Continuous effective width
L. Mathew et al., IEDM 2005
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 51
Strained FinFETStrained FinFET
25% drain current enhancement of PFET by introducing recessed Si0.8Ge0.2 S/D
Compressive stress and raised S/D P. Verheyen et al., VLSI 2005
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 52
Impact of Gate-Induced StrainImpact of Gate-Induced Strain
MuGFETs with TiSiN gate (+3GPa stress as deposited)
Eeff=0.4MV/cm
Stress [MPa] Mobility Enhancement [%]
σxx σyy σzz(100)
NMOS(110)
NMOS(100)
PMOS(110)
PMOS
Experiment 4 59 8 10
Inverse PR Model -540 -290 -1900 4 59 -1 10
0
100
200
300
400
500
0 0.2 0.4 0.6 0.8
(100) metal(110) metal(100) poly ref(110) poly ref4%
59%
NMOS0
100
200
300
400
0 0.2 0.4 0.6 0.8
(100) metal(110) metal(100) poly ref(110) poly ref10%
8%
PMOS
xy
z
xy
z
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 53
Issue of Fin FormationIssue of Fin Formation
Neutral beam etching can accomplish damage (defect) free fabrication of high aspect ratio fin.
Higher mobility is obtained in NB device due to atomically-flat surface
K. Endo et al., IEDM 2005
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 54
Sidewall Spacer Transfer (SWT) Sidewall Spacer Transfer (SWT) ProcessProcess
Both gate and fin are formed by SWT SiN is selected as hard mask
material for Si RIE on top of fin Can be used as the CMP stopper
during poly gate planarization (important for gate SWT)
Suppress the agglomeration of Si fin during selective Si epi
Prevent the leakage of the top corner Used as RIE stopper in the gate RIE
processA. Kaneko et al., IEDM 2005
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 55
SWT ProcessSWT Process
The threshold voltage uniformities for SWT FinFETs of 15nm fin and 15nm gate length over the wafer is better than ArF and EB lithography
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Selective Gate Sidewall Spacer Selective Gate Sidewall Spacer Formation Formation
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FinFET on Bulk Si SubstrateFinFET on Bulk Si Substrate
Bulk FinFET has the advantages of cheaper wafer cost, ease of combination with conventional bulk CMOS.
K. Okano et al., IEDM 2005
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Characteristics of Bulk FinFETCharacteristics of Bulk FinFET
Better subthreshold swing Better short channel control Negligible body effect
T. Park et al., VLSI 2003
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OutlineOutline Why FinFETWhy FinFET
FinFET processFinFET process Unique features of FinFETUnique features of FinFET
Mobility, workfunction engineering, corneMobility, workfunction engineering, corner effectr effect, , QM, volume inversionQM, volume inversion
IssuesIssues Recent Recent FinFETFinFET Develop Develop
Triple-gate FinFET, Omega FET, Nanowire FinFETTriple-gate FinFET, Omega FET, Nanowire FinFET, , Independent gate, Multi-channel FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high-K Metal-gate/high-K FinFET, FinFET, SStrained FinFETtrained FinFET, Bulk FinFET, Bulk FinFET
MemoryMemory DRAM, SONOS, SRAMDRAM, SONOS, SRAM
ConclusionConclusion
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DRAM application of Bulk FinFETDRAM application of Bulk FinFET
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DRAM application of Bulk FinFETDRAM application of Bulk FinFET
Negative word line bias is introduced due to lower VT
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NWL SchemeNWL Scheme
Lower VT (doping concentration) FinFET combined with NWL scheme can provide lower leakage and higher performance
NWL bias is critical to refresh fail bit
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SONOS Application of FinFETSONOS Application of FinFET
High Performance FinFET SONOS flash cells with gate length of 20nm is demonstrated.
Program/erase window of 2V with high P/E speed (Tp=10ms, TE=1ms)
J. Hwang et al., TSMC 2005
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SONOS Application of FinFETSONOS Application of FinFET
Excellent endurance: up to 10K P/E cycles
Good retention: 1.5V after 10years retention time
J. Hwang et al., TSMC 2005
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FinFETs based 6-T SRAMsFinFETs based 6-T SRAMs
Large fraction of the total chip area will be memory1
Leakage problem
Limited by impact of variations
WL
BL
V DD
M 5 M 6
M 4
M 1
M 2
M 3
BL
VR VL
pulldown
access
load
FinFETs offer good control of short channel effects
1Source : Ranganathan, 2000
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Static Noise MarginStatic Noise Margin
• The minimum noise voltage at the storage node needed to flip the state
• Large SNM is desirable
Make pulldown device stronger relative to access transistor
Source: Bhavnagarwala, 2001
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SNM spread with variationsSNM spread with variations
Thicker Si body better Higher performance
due to Rs limitations Greater noise
immunity (SNM) Lesser spread in
SNM
0
0.05
0.1
0.15
0.2
0.25
0.3
0.1 0.15 0.2 0.25SNM (V)
Pro
bab
ilit
y
Tsi = 11nm
Tsi = 15nm
Taurus Device Simulation
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SNM spread with variationsSNM spread with variations
To improve SNMa) Wpulldown - 2 fins
b) Laccess
c) eff, pulldown>eff, access
(100)pulldown device
(110) access device
0
0.1
0.2
0.3
0.1 0.15 0.2 0.25SNM (V)
Pro
bab
ility
(100)/1fin
(100 )/ 2 fins
(110) / 1fin
TSi = 15nm
Taurus Device Simulation
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FinFET Circuit design tradeoffsFinFET Circuit design tradeoffs
Advantages Excellent SCE
control Scalability Double-gates are
self-aligned Insensitivity to
channel doping
Limitations Gate material Contact/Series
resistance Area efficiency
(fin pitch) Back gate routing
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ConclusionConclusion
Unique FinFET physics are introduced.Unique FinFET physics are introduced.
Recent developing effort on FinFET Recent developing effort on FinFET technology are discussedtechnology are discussed Triple-gate FinFET, Omega FET, Nanowire Triple-gate FinFET, Omega FET, Nanowire
FinFETFinFET, , Independent gate, Multi-channel Independent gate, Multi-channel FinFET, Metal-gate/high-K FinFET, Metal-gate/high-K FinFET, FinFET, SStrained trained FinFETFinFET, Bulk FinFET, Bulk FinFET
FinFET based CMOS and memory cells are FinFET based CMOS and memory cells are very promising for sub-32 technology very promising for sub-32 technology node.node.
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Thank you very much Thank you very much for your attentionfor your attention