Reading VHDL 7 Datapaths Here we shall consider the construction of the data-paths in our CPU, those bits which will compute our desired function or process.

1. DataPath 1 The Humble Register. A CPU datapath consists of ALUs, MUXes, and Registers. We have seen VHDL code for a MUX already. Code for an ALU is straightforward, but the behaviour and code for a register may cause you a little trouble. So lets first investigate how a reg works in isolation. Heres the symbol for a register

clear D load clock Q

The register is memory and at any time will hold a value. Whatever value is in the register appears at the output Q. (By the way think of all datapaths as 8-bit). How do you get a value into the register? Via the input D (also 8 bits). But this value does not just get directly in. In other words, the registers contents (and its output) may be different from the value waiting to get input at D. So how does this value waiting actually get in? It has to be clocked in by the clock signal. And it will only get in if the signal load is high on a low-to-high transition of the clock signal. Like this:

clock

load

Data input to reg now

Lets have a look at the VHDL code for a register:

12 entity reg is 13 port ( clock : in std_logic; 14 clear : in std_logic; 15 load : in std_logic; 16 D : in std_logic_vector( 7 downto 0); 17 Q : out std_logic_vector( 7 downto 0)); 18 end reg; 19 20 architecture Behavioural of reg is 21 begin 22 process (clock,clear,load) 23 begin 24 25 if clear = '1' then Q

That means we wish to add 3 to the number A, and perhaps output the result. We may need to do this many times. So what do we need?

1. A register to hold the value of A 2. An ALU to do the addition 3. The constant 3 to add 4. A way of feeding back the previous result into a new calculation. 5. An output from our machine.

Following out discussions in class, youll agree that the following architecture is required:

There is a register Reg A which stores number A. The ALU does the add 3stuff and theres an output signal. Note that there are three inputs to this datapath: The clear, load and clock signals into the register which define its behaviour. And there is one output output from the datapath. Note there is no data. The register can be cleared to 0 using its clear input signal. How does this circuit work? Well say we assert the clear signal on the reg. This will set its contents to 00000000, which will appear directly on its output. It will go immediately into the alu which will sum 0 with 3, and 3 will appear immediately at the output of the alu. This is fed back into the regs input, but will not go straight in. Remember the reg only accepts an input when (i) the load signal is high (1) and (ii) there is a low-to-high clock transition. When these signals are aswserted then the 3 is loaded and stored, and immediately appears at the output of the reg where it falls once more into the alu to be summed with 3 to give 6 and so on.

clear load clock

D Reg A

Q 3

reg2alu const

X Y ALU

Z

alu2reg

output

Signals marked with a blob are inputs and outputs to the datapath

Lets now analyze the VHDL code to synthesize this CPU. Well take a top-down approach, starting from the datapath description, and bottoming out at the individual components.

58 --------------- now define the whole datapath -------------------59 ---library ieee; 60 use ieee.std_logic_1164.all; 61 use ieee.std_logic_unsigned.all; 62 63 entity datapath is 64 port ( clock,load,clear : in std_logic; 65 output : out std_logic_vector (7 downto 0)); 66 end datapath; 67 68 architecture Structural of datapath is 69 70 component alu 71 port ( X : in std_logic_vector (7 downto 0); 72 Y : in std_logic_vector (7 downto 0); 73 Z : out std_logic_vector (7 downto 0)); 74 end component; 75 76 component reg 77 port ( clock,load,clear : in std_logic; 78 D : in std_logic_vector (7 downto 0); 79 Q : out std_logic_vector (7 downto 0)); 80 end component; 81 82 signal reg2alu : std_logic_vector (7 downto 0); 83 signal alu2reg : std_logic_vector (7 downto 0); 84 signal const : std_logic_vector (7 downto 0); 85 86 begin 87 88 const

Lines 86-93 define the working of the whole datapath. First we assign the value 3

const in line 88.

f the components, their interconnection, is defined in lines 90-1. First we take the register. You must read line 90 while keeping an eye on lines 77-

t

put signals orrespond to those it expects.

ecified how the alu is connected; it gets its inputs from e signal reg2alu, and const and sends it output to alu2reg which feeds back

level to the specification of the components of the datapath. Well ke one example, the ALU. Heres the VHDL code for the ALU:

and

m. But we have to generate the input ontrol signals. We need a clock, some loads and a clear. And we should arrange for

te

to But the wiring-up o979. The latter tell us that reg expects input signals clock, load, clear, an input value on bus D. And the reg will output a value on bus Q. Line 90 says that the regs clock load and clear are assigned to the datapaths clock load and clear. Also thathe input value D is actually the datapath alu2reg (check out the schematic!). Finally, that the Q output is assigned to the datapath reg2alu. In other words, we have specified to the reg which input and outc Similarly in line 91 we have spthinto the register. Now lets go up ata

12 ------------------- first define the ALU------------------------13 entity alu is

X,Y)

14 port ( X : in std_logic_vector (7 downto 0); 15 Y : in std_logic_vector (7 downto 0); 16 Z : out std_logic_vector (7 downto 0)); 17 end alu; 18 19 architecture Behavioural of alu is 20 21 begin 22 23 process(24 begin 25

X+Y; 26 Z

low the load signals are positioned with respect to the rising edges of the clocks. Loads are stable high during these clock transitions.

3. DataPath 4 A more complex CPU

ets now turn to a more complex CPU datapath. We shall now have (i) data coming

alu1 alu0 function

Linto the circuit, and (ii) an ALU which can execute four functions. Heres the circuit:

First lets define the ALU function. Well there are four possible functions we shall use, each selected by one of the four combinations of the two alu signals alu0 andalu1:

0 0 passthrough 0 1 X +Y 1 0 X OR Y 1 1 X AND Y

clear

3 ALU X Y

Reg A

reg2alu alu2reg

const

load clock

Z

output

mux2alu

input

alu0

muxSel

alu1

The register is unchanged from the previous e mux has two inputs in0 and in1 and we shall agree to fix things so that when muxSel = 0 then in0 is

do? Im not certain! Certainly more than the previous one. his is one question for you to answer. But first, lets glance at the VHDL. Again we

xample. The

selected and so forth. What can this datapathTshall start with the top-level, the structural code where we connect various bits together:

81 entity datapath is 82 port ( clock,load,clear : in std_logic;

nto 0); nto 0);

;

downto 0);

oad,clear : in std_logic; std_logic_vector (7 downto 0);

0));

std_logic; n std_logic_vector (7 downto 0);

tor (7 downto 0);

------

port map(muxSel,input,const); l,mux2alu,reg2alu,alu2reg);

eg,reg2alu);

83 muxSel : in std_logic; 84 aluSel : in std_logic_vector (1 dow85 input : in std_logic_vector (7 dow86 output : out std_logic_vector (7 downto 0))87 end datapath; 88 89 architecture Structural of datapath is 90 91 component alu 92 port ( aluSel : in std_logic_vector (1 93 X : in std_logic_vector (7 downto 0); 94 Y : in std_logic_vector (7 downto 0); 95 Z : out std_logic_vector (7 downto 0)); 96 end component; 97 98 component reg 99 port ( clock,l100 D : in101 Q : out std_logic_vector (7 downto 102 end component; 103 104 component mux 105 port ( sel : in 106 in0 : i107 in1 : in std_logic_vec108 opt : out std_logic_vector (7 downto 0)); 109 end component; 110 111---------------------- Now Build the datapath -------112 113 signal mux2alu : std_logic_vector (7 downto 0); 114 signal alu2reg : std_logic_vector (7 downto 0); 115 signal reg2alu : std_logic_vector (7 downto 0); 116 signal const : std_logic_vector (7 downto 0); 117 118 begin 119 const

pair of alu select signals (note this is a 2-bit logic vector). We also have an 8-bit input bus and an 8-bit output bus. Signals interconnecting the various components are defined in lines 113-116 where

e naming is fairly obvious (thanks to a little inspiration). The actual interconnecting

inspect this:

y we must glance at the code for the MUX :

this done in lines 120-122 where these interconnect signals are used. The complete structure should now be clear. Lets turn to the ALU code and

13 entity alu is 14 port ( aluSel : in std_logic_vector (1 downto 0);

std_logic_vector (7 downto 0);

X; Z Z 27 when "10" => Z Z

59 entity mux is 60 port ( sel : in std_logic; 61 in0 : in std_logic_vector (7 downto 0); 62 in1 : in std_logic_vector (7 downto 0); 63 opt : out std_logic_vector (7 downto 0)); 64 end mux; 65 66 architecture Behavioural of mux is 67 begin 68 process(sel,in0,in1) 69 begin 70 if (sel = '0') then opt