9.design of high speed area efficient low power vedic multiplier using reversible logic gate
RCA - CSA Adder Based Vedic Multiplier · PDF fileRCA - CSA Adder Based Vedic Multiplier ......
-
Upload
duongnguyet -
Category
Documents
-
view
243 -
download
4
Transcript of RCA - CSA Adder Based Vedic Multiplier · PDF fileRCA - CSA Adder Based Vedic Multiplier ......
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7603
RCA - CSA Adder Based Vedic Multiplier
D Khalandar Basha1*, P Prakash1**, D M K Chaitanya2 and K Aruna Manjusha3
Department of Electronics and Communication Engineering, 1Institute of Aeronautical Engineering, Dundigal, Hyderabad, Telangana, 500043, India.
* Orcid Id: 0000-0002- 8754-0602, ** Orcid Id: 0000-0001- 5431-5647
2Vardhaman College of Engineering, Shamshabad, Hyderabad, Telangana, 501218, India.
3Marri Laxman Reddy Institute of Technology, Dundigal, Hyderabad, Telangana, 500055, India.
Abstract
In any Digital Signal Processing (DSP) systems multiplier is
the major key block. Multiplier plays a prominent role in
Digital filtering, Digital communications and spectral
analysis. Currently DSP applications are targeting at low
power and high speed systems and hence power dissipation,
becomes one of the major primary design constraints. This
paper presents the design of Multiplier architectures using
Urdhva Tiryakbhyam Sutra in Vedic Mathematics. By using
this sutra (algorithm) 4x4, 8x8 and 16x16 Vedic Multiplier
architectures are designed These designs are obtained in three
methods with a sub module design, a total of six designs of
each 4x4, 6x6, 8x8 and 16x16 are made.
Keywords: Digital Signal Processing (DSP), Urdhva
Tiryakbhyam (UT Sutra), Vedic Multiplier(VM), Ripple
Carry Adder (RCA), Carry Save Adder (CSA).
INTRODUCTION In ancient India Vedic Mathematics was popularly followed
and it is applied in various mathematical branches. The word
Vedic represents ‘The store house of all Knowledge’ Vedic
mathematics is mainly based on 16 sutras and it was
rediscovered in 20th century. In each sutra there are certain
limitations. Among these 16 sutras in Vedic Mathematics
Urdhva Tiryakbhyam Sutra is considered as a Multiplier
technique in this paper [1]. Due to the parallel computational
approach Vedic multiplier approaches the Overall speed and
power consumption [2,3].
The designs in this paper are obtained using CMOS technique,
the main important characteristics of CMOS devices is they
have high noise immunity and low static power consumption
as a result CMOS device does not produce as much of waste
heat compared to Transistor Transistor Logic (TTL) or N-type
Metal Oxide Semiconductor (NMOS) logic, which commonly
has some standing current even when not changing the state
[4,5].
As DSP applications are targeting at low power and high
speed systems, power dissipation becomes a major design
constraint [6,7]. Based on low power application adder RCA
and fastest adder CSA [8-10]. Vedic Multiplier architectures
are designed and the parameters average power consumed and
overall delay are compared.
URDHVA TIRYAKBHYAM (UT SUTRA)
Urdhva Tiryakbhyam Sutra’ in Vedic Mathematics is
generally used for multiplication. The Vedic words Urdhva
means vertical and Tiryakbhyam means crosswise. Therefore,
by vertical and crosswise direction two binary numbers can be
multiplied. Generation of all partial products can be obtained
with the concurrent addition, by using UT sutra NxN
multiplier architectures can be generated. Fig 1 shows analogy
of 2x2 Vedic Multiplication for 2-bit binary numbers and Fig
2 shows the analogy of 4x4 Vedic Multiplication for 4-bit
binary numbers.
The partial product generation indicated in Fig 1 and Fig 2 is a
vertical and crosswise lines, all the partial products can be
generated with concurrent addition. Similarly, as Fig 1 and
Fig 2 analogy of 8x8 and 16x16 Vedic multiplication can be
obtained for 8-bit and 16-bit binary numbers.
Figure 1: 2x2 Vedic Multiplication
Figure 2: 4x4 Vedic Multiplication
In order to design 4x4, 8x8 and 16x16 Vedic Multiplier in
different modules, 2x2 Vedic Multiplier block is designed,
with this block 4x4, 8x8, 16x16 Vedic Multiplier architectures
are designed.
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7604
VEDIC MULTIPLIER
Based on the UT Sutra 4x4, 8x8, 16x16 Vedic Multiplier
architectures are designed in 45nm technology based on
CMOS (Complementary Metal Oxide Semiconductor)
technique. These designs are obtained in three methods with a
sub module design, a total of six designs of each 4x4, 6x6,
8x8 and 16x16 Vedic Multipliers are designed and
Implemented, finally, the parameters average power
consumed and overall delay of each architectures are
compared.
Table 1: Methods followed in Vedic Multiplier.
The different methods followed in Vedic Multiplier are shown
in the above Table 1. As seen in the above Table.1 4x4, 8x8,
models with a sub module. Model 1 is designed using Ripple
Carry Adder (RCA), Model 2 uses Carry Save Adder (CSA)
and Model 3 is a hybrid model which uses CSA and RCA.
16x16 Vedic Multipliers are designed in three different
models with a sub module. Model 1 is designed using Ripple
Carry Adder (RCA), Model 2 uses Carry Save Adder (CSA)
and Model 3 is a hybrid model which uses CSA and RCA.
Now a 2x2 Vedic Multiplier architecture block is designed, by
using this block remaining architectures of different modules
4x4, 8x8, 16x16 are designed.
2X2 VEDIC MULTIPLIER
The analogy of 2x2 Vedic Multiplication for 2-bit binary
numbers is show in the Fig. 1 the partial product generation
indicated in Fig. 1 is a vertical and crosswise lines, all the
partial products can be generated with concurrent addition.
Figure 3: Block diagram of 2x2 Vedic Multiplier.
Figure 4: Schematic of 2x2 Vedic Multiplication.
The above Fig. 3 and Fig. 4 is the block diagram and
Schematic of 2x2Vedic Multiplier for a 2-Bit binary number
containing four AND gate blocks for partial product
generation and two half adders for required addition process.
4X4 VEDIC MULTIPLIER
The analogy of 4x4 Vedic Multiplication for two binary
numbers is show in the Fig. 2. Vedic Multiplier for 4X4
architectures are designed by Using a 2x2 Multiplier Block all
partial products are generated in parallel, addition of this
partial products are accomplished by using RCA Based, CSA
Based, Hybrid Based Adders using CSA & RCA in Model 3.
The result obtained by multiplication of two 4-Bit binary
inputs A = A3 A2 A1 A0 and B = B3 B2 B1 B0 is S = S7 S6
S5 S4 S3 S2 S1 S0. Divide A and B in two parts A= A3 A2
and A1 A0 whereas B = B3 B2 and B1 B0. By using 2x2
Vedic Multiplier blocks 4x4 Multiplier architecture is
designed. The 8-bit product can be written as
S = A X B = (A3 A2) X (B3 B2) + (A3 A2) X (B1 B0) + (A1
A0) X (B3 B2) + (A1 A0) X (B1 B0).
RCA based Vedic Multiplier
Figure 5:Block diagram of RCA based 4X4 Vedic Multiplier
SIZE MODULE SUB
MODULE
4X4 VEDIC
MULTIPLIER
8X8 VEDIC
MULTIPLIER
16X16 VEDIC
MULTIPLIER
RCA BASED
1. Using RCA
2. Using modified
RCA
CSA BASED
1. Using CSA
2. Using modified
CSA
HYBRID
BASED
1. Using CSA &
RCA
2. Using modified
CSA & RCA
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7605
Figure 6: Modified RCA blocks used in 4X4 Multiplier 2
Figure 7: Schematic of RCA based 4x4 Vedic Multiplier 1
In this Model 4x4 Multiplier is designed in two modules
Multiplier 1 is designed using RCA based and Multiplier 2 is
designed using Modified RCA based, three RCA blocks are
used in this architecture. The Fig. 5 shown above is the block
diagram of 4x4 Vedic Multiplier using RCA.
Multiplier 1 in Fig. 7 uses three 4-bit RCA blocks whereas
Multiplier 2 in Fig. 8 is designed using Modified RCA blocks,
the unnecessary full adder blocks are replaced by half adders
this is shown in Fig. 6.
Figure 8: Schematic RCA based 4x4 Vedic Multiplier 2
CSA based Vedic Multiplier
Figure 9: Block diagram of CSA based 4x4 Vedic Multiplier
Figure 10: Modified CSA blocks used in 4x4 Multiplier 2
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7606
In this Model 4x4 Multiplier is designed in two modules
Multiplier 1 is designed using CSA based and Multiplier 2 is
designed using Modified CSA based, three RCA blocks are
used in this architecture. The Fig. 9 shown above is the block
diagram of 4x4 Vedic Multiplier using CSA.
Multiplier 1 in Fig 11 uses two 4-bit CSA blocks whereas
Multiplier 2 in Fig 12 is designed using Modified CSA blocks,
the unnecessary full adder blocks are replaced by half adders
this is shown in Fig 10.
Figure 11: Schematic of CSA based 4x4 Vedic Multiplier 1
Figure 12: Schematic of CSA based 4x4 Vedic Multiplier 2
Hybrid based Vedic Multiplier
In this Model 4x4 Multiplier is designed in two modules
Multiplier 1 is designed using CSA & RCA based and
Multiplier 2 is designed using Modified CSA & RCA based,
one CSA and RCA block is used in this architecture. The
Fig. 13 shown below is the block diagram of Hybrid based
4x4 Vedic Multiplier using CSA & RCA.
Figure 13: Block diagram of Hybrid based 4x4 Vedic
Multiplier
Figure 14: Modified CSA & RCA blocks used in 4x4
Multiplier 2
Multiplier 1 in Fig. 15 uses one 4-bit CSA & RCA blocks
whereas Multiplier 2 in Fig 16 is designed using Modified
CSA blocks, the unnecessary full adder blocks are replaced by
half adders this is shown in Fig 14.
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7607
Figure 15:Schematic of Hybrid based 4x4 Vedic Multiplier 1
Figure 16:Schematic of Hybrid based 4x4 Vedic Multiplier 2
Similarly Vedic Multiplier for 8x8 and 16x16 are designed
using RCA based, CSA based and hybrid based Adders.
8X8 VEDIC MULTIPLIER
RCA based Vedic Multiplier
Figure 17:Block diagram of RCA based 8x8 Vedic Multiplier
Figure 18: Modified RCA Blocks used in 8x8 Multiplier 2
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7608
Figure 19: Schematic of RCA based 8x8 Vedic Multiplier 1
Figure 20: Schematic of RCA based 8x8 Vedic Multiplier 2
CSA based Vedic Multiplier
Figure 21: Block diagram of CSA based 8x8 Vedic Multiplier
Figure 22: Modified CSA blocks used in 8X8 Multiplier 2
Figure 23: Schematic of CSA based 8x8 Vedic Multiplier 1
Figure 24: Schematic of CSA based 8x8 Vedic Multiplier 2
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7609
Hybrid based Vedic Multiplier
Figure 25: Block diagram of Hybrid based 8x8 Vedic
Multiplier
Figure 26: Modified CSA & RCA blocks used in 8X8
Multiplier 2
Figure 27: Schematic of Hybrid based 8X8 Vedic
Multiplier 1
Figure 28:Schematic of Hybrid based 8X8 Vedic Multiplier 2
16X16 VEDIC MULTIPLIER
RCA based Vedic Multiplier
Figure 29: Block diagram of RCA based 16X16 Vedic
Multiplier
Figure 30: Modified RCA blocks used in 16X16 Multiplier 2
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7610
Figure 31: Schematic of RCA based 16x16 Vedic
Multiplier 2
Figure 32: Schematic of RCA based 16x16 Vedic
Multiplier 2
CSA based Vedic Multiplier
Figure 33: Block diagram of CSA based 16x16 Vedic
Multiplier
Figure 34: Modified CSA blocks used in 16X16 Multiplier 2
Figure 35: Schematic of CSA based 16x16 Multiplier 1
Figure 36: Schematic of CSA based 16x16 Multiplier 2
Hybrid based Vedic Multiplier
Figure 37: Block diagram of Hybrid based 16x16 Vedic
Multiplier
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7611
Figure 38: Modified CSA & RCA blocks Used in 16X16
Multiplier 2
Figure 39: Schematic of Hybrid based 16x16 Vedic
Multiplier 1
Figure 40: Schematic of Hybrid based 16x16 Vedic
Multiplier2
RESULTS
Wave Forms:
2X2 Vedic Multiplier
Figure 41: Waveform of 2x2 Vedic Multiplier.
4x4Vedic Multiplier
Figure 42: Waveform from A0 to S4.
Figure 43: Waveform from A3 to S7.
8x8 Vedic Multiplier
Figure 44 : Waveform from A0 to B4.
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7612
Figure 45: Waveform from B4 to S8.
Figure 46: Waveform from S3 to S15.
16x16 Vedic Multiplier
Figure 47: Waveform from A0 to A12.
Figure 48: Waveform from A11 to B8.
Figure 49: Waveform from B7 to S4.
Figure 50: Waveform from S3 to S16.
Figure 51: Waveform from S15 to S28.
Figure 52: Waveform from S19 to S31.
ANALYSIS
The analysis of the parameters, average power consumption
and overall delay of the architectures are obtained in 45nm
technology using Monte Carlo simulation (MC) in Cadence.
This are illustrated in the below Tables.
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 18 (2017) pp. 7603-7613
© Research India Publications. http://www.ripublication.com
7613
Table 2: Comparison of 4x4 Vedic Multiplier Architecture.
Table 3: Comparison of 8x8 Vedic Multiplier Architecture.
Table4: Comparison of 16X16 Vedic Multiplier Architecture.
DISCUSSION
Among all the Vedic Multiplier architectures in this paper,
power consumption and overall delay of the multiplier
architectures is found to be low in RCA based Multiplier 2 (in
modified RCA) design.
CONCLUSION
The goal of this project is to design Implement and analysis of
Vedic Multiplier architectures based on Urdhva Tiryakbhyam
sutra in Vedic Mathematics. As compared to other Multiplier
architectures in this paper, power consumption and overall
delay of the multiplier architectures is found to be low in RCA
based Multiplier 2 (modified RCA) design. Reducing the
power consumption and delay is an important requirement for
various applications and Vedic Multiplication technique is
appropriate for this purpose. The idea proposed in this paper
may set a way for future research in this direction.
ACKNOWLEDGMENTS
The author would like to thank the Management, Director,
Principal, Head of the Department of Institute of Aeronautical
Engineering, Hyderabad for their support and guidance in
completion of this research paper.
REFERENCES
[1] Swami Bharati Krisna Tirthaji Maharaja, “Vedic
mathematics”, original edition, Motilal Banarasidass
publishers.
[2] Manoj R, Mahaveera K, "Application of Vedic
Mathematics for Computationa of Basic DSP
operations.", International Journal of Innovative Research
in Science, Engineering and Technology (IJIRSET), Vol.
5,Special Issue 9, pp 488-493, May 2016.
[3] Devika Jaina, Kabiraj Sethi, Rutuparna Panda, “Vedic
mathematics based multiply accumulate unit”,
International conference on computational intelligence
and communication networks”,pp. 754-757,7-9 October
2011.
[4] K. Lal Kishore, V.S.V Prabhakar," VLSI Design ", I.K.
International Pvt Ltd..
[5] Sung-Mo Kang and Yusuf Leblebici, “ CMOS digital
integrated circuits- analysis and design”, third edition,
Tata McGraw-Hill education Pvt. Ltd.
[6] Chandrasekaran,A, nd Broderson, Low Power Digital
Design, Kluwer Academic Publishers,1995.
[7] Pascal Constantin Hans Meier,"Analysis and Design of
Low Power Digital Multipliers", A Disseration Submitted
to the Graduate School,Carnegie Mellon University,
Pittsburgh, Pennsylvania, August 1999.
[8] R.Uma, Vidya Vijayan, M. Mohanapriya, Sharon Paul,
"Area, Delay and Power Comparision of Adder
Topologies", International Journal of VLSI design &
Communication Systems (VLSICS)Vol.3,No.1, pp 153-
163, February 2012.
[9] Sulakshna Thakur, Pradeep Kumar,"Area-Efficient &
High Speed Ripple Carry based Vedic Multiplier" SSRG
International Journal of Electronics and Communication
Engineering (SSRG-IJECE)-EFES,pp 6-10, April 2015.
[10] Premananda B.S, Samarth S. Pai, Shashank B., Shashank
S. Bhat," Design and Implementation of 8-Bit Vedic
Multiplier", International Journal of Advanced Research
in Electrical, Electronic and Instrumentation
Engineering,(IJAREEIE),Vol. 2, Issue 12,pp 5877-5882
December 2013.
MODULE
Sub Module
Avg
Power
(µW)
Overall
Delay
(ns)
RCA BASED Multiplier 1 3.256 90.27
Multiplier 2 2.911 90.29
CSA BASED Multiplier 1 4.511 90.43
Multiplier 2 3.197 90.51
HYBRID BASED Multiplier 1 4.295 90.43
Multiplier 2 3.012 90.53
MODULE
Sub Module
Avg
Power
(µW)
Overall
Delay
(ns)
RCA BASED Multiplier 1 28.30 90.86
Multiplier 2 25.23 90.63
CSA BASED Multiplier 1 34.76 91.27
Multiplier 2 26.69 90.82
HYBRID BASED Multiplier 1 42.33 90.84
Multiplier 2 25.68 90.79
MODULE
Sub Module
Avg
Power
(µW)
Overall
Delay
(ns)
RCA BASED Multiplier 1 142.8 91.38
Multiplier 2 121.8 91.19
CSA BASED Multiplier 1 183.2 91.57
Multiplier 2 132.7 91.17
HYBRID BASED Multiplier 1 200.7 91.16
Multiplier 2 127.7 91.59