PROJECT – Random Access Memory Design

SUBMITTED TO – Sir Anirban Chakraborty (HOD)

PRESENTED BY –

NAME ROLL NO.

● Akshay Biswas 911

● Udaysankar Dey

● Hiranmay Bhattacharya 907

CLASS – CMSA (1st Year)

Define Memory

Define RAM

Difference Between ‘Memory’ & ‘Storage’

Classification of ‘Memory’

Why it called Randomly Accessible Memory

Classification of RAM

Statistics of RAM

RAM Design

Words in a single memory cell

Demonstrate a single cell

Memory Address Map

Using of Decoders

Memory Connection to CPU

How RAM Works Read Cycle

Write Cycle

Dimensions of Memory

Access 1-D Memory Access

2-D Memory Access

Vs.

The difference between storage and memory is

that non-volatile storage is used to hold programs

and data until purposely changed or removed by

the user, while volatile memory is a temporary

workspace for retrieving programs and processing

data. Storage consists of drives (hard, optical,

USB, solid state) where Memory consists of RAM

chips that lose their content when power is

removed.

Memory Storage

Classification of Memory :

Memory

Serial

FIFO LIFO

Random Access

Read/Write

SRAM DRAM

Read-Only

A Randomly Accessible Memory :

We can store data in pieces in multiple

different memory address ranges and access

them anytime as needed,

so we can read and

write data to different

addresses (locations) in

the memory array

anytime, rather than

sequentially

(non-randomly) like on

a tape reel. Random

access is MUCH faster.

The principal technology used for main memory

is based on Semiconductor IC. The term

“Semiconductor” refers to a material that has

electrical conductivity greater than an

“insulator” but less than “conductor”.

Semiconductors are made from pure elements,

typically silicon. In a process called doping, small

amounts of impurities are added to pure

semiconductors causing large changes in the

conductivity of the material. Integrated Circuit

RAM chips are available in two possible operating

modes, STATIC & DYNAMIC.

More About RAM :

SRAM vs DRAM :

MAIN MEMORY(RAM) DESIGN :A semiconductor RAM IC typically has a word organized

array structure and contains all required access circuitry,

including address decoders and control circuits. Fig.(2.1)

shows a simple structure of a 1K × 8 RAM that

incorporates eight bipolar cells of the type shown in

Fig.(2.2) .

WORDS IN SINGLE MEMORY CELL :

From an exterior viewpoint a high speed

memory is very much like a ‘BLACK BOX’ with

a number of locations or addresses into which

data can be stored. It’s organized into ‘WORDS’

of fixed length. As the

Fig.(2.3) indicate, a

given memory is

divided into ‘N’

‘WORDS’, where ‘N’

generally is some

power of 2. And each

word has the same

number of bits, called

‘WORD LENGTH’(M).

Demonstrate a single cell :In any memory there must be a basic memory cell.

Here Fig.(2.4) shows a basic memory cell consisting

of an RS flip-flop with associated control circuitry.

And Fig.(2.5) shows a basic memory cell consisting

a transistor and a capacitor.

MEMORY ADDRESS MAP :The addressing of

memory can be

established by means

of a table called

‘Memory Address Map’,

that established

specifies the memory

address assigned to

each chip. To

demonstrate with a

particular example,

assume that a

computer system needs

1K of RAM. The RAM

chips to be used are

specified in Fig.(2.6).

Continued…The memory address map for this configuration is

shown in Tab.(2.1).

Using 0f decoders :The part of the system that selects the cells to be read

from and written into is the decoder. For each of the

possible 2n

binary numbers that can be taken by the n

input cells, the matrix will select a unique output line

out of them. Fig.(2.8) shows a decoder that is a basic

2:4 decoder where n = 2, 2n = 4(Output) which can select

only one unique output line.

Memory Connection to cpu :RAM chips are connected

to a CPU through the

data and address buses.

The low-order lines in

the address bus select

the byte within the chips

and other lines in the

address bus select a

particular chip through

its chip select input. The

connection of memory

chips to the CPU is

shown in Fig.(2.9).

How ram works :

The bus used to connect the memory

generally consists of :

1) A set of address lines to carry the

address of the particular word in memory

to be used (these are effectively an output

from a MAR on the microprocessor chip);

2) A set of data wires to input data from

the memory and output data to the

memory;

3) A set of control wires to control the

READ and WRITE operation.

Read cycle :The READ control signal work as

follows :

1) The address lines,‘A1 – A7,’ must

be set to the address to be read from.

2) Because of a ‘READ’ operation the

‘RD’ line is set to a ‘1’.

3) The ‘CS’ or chip select line must

be enable or it’s value set to ‘1’, for

this operation.

4) Remember the selected data can

be read out until the ‘CS’ line is

made a ‘0’ again.

5) The data bits mar then be read on

line ‘DO’ & ‘DI’ not used in read cycle.

WRITE cycle :The WRITE control signal work as

follows :

1) The address lines,‘A1 – A7,’ must

be set to the address to be read from.

2) Because of a ‘WRITE’ operation

the ‘WR’ line is set to a ‘1’.

3) The ‘CS’ or chip select line must

be enable or it’s value set to ‘1’, for

this operation.

4) The data to be write are placed on

‘DI’ lines.

5) The selected data can be read out

until the ‘CS’ line is made a ‘0’ again.

6) The data bits mar then be read on

line ‘DO’.

Dimensions of memory access :

1-D Memory Access :-

The memory organization

in Fig.(3.2) has a basic

linear-select (1-D)

selection system. As an

example, consider a

parallel decoder for a

4096-word memory, There

will be 12 inputs per AND

gate, and 4096 AND gates

are required. If a

transistor is required at

each AND gate’s input,

then 12 × 4096 = 49,152

transistor will be required.

Continue…

This is a four-address

memory with 3 bits per

word. The memory

address register selects

the memory cells to be

read from or written into

through a 2/4 decoder,

which select three flip-

flops for each address in

the memory address

register.

2-D Memory Access :-

In the 2-D selection, we

need to add another

SELECT input to our basic

memory cell; this is show

in Fig.(3.3).

Fig.(3.4) shows a 2-D

memory selection system

using this cell. Two

decoders are required for

this memory, which has

16 words of only 1 bit per

word. The MAR has 4 bits

and, thus, 16 states.

2-D Memory Access :-

For a 4096-word 1-

bit-per-memory the

two dimensional

selection system

would have two

decoders, each with

six inputs. Each

would have requires

26 × 6 =384 diodes or

transistors, that is a

total of 768

transistors for the

both.

Row

Address

Decoder

Column

Address

Decoder

Reference :

Computer System Architecture (3rd

Edition) by M. Morris Mano

Computer Architecture And Organization

(2nd Edition) by John P. Hayes

Computer Architecture And Logic Design

by Thomas C. Bartee