Single-Path Programming on aChip-Multiprocessor System

RePP 2009 : Workshop on Reconciling Performance with Predictability

Raimund Kirner

this is joint work with

Martin Schöberl and Peter Puschner

How do we know the timing is right?

2

RTCS

Environment ?

response time

How do we know the timing is right?

3

RTCS

Environment ?

response time

schedulability analysis (global system behavior)

WCET analysis (local system behavior)

WCET analysis (local system behavior)

WCET analysis (local system behavior)

WCET analysis (local system behavior)

WCET analysis (local system behavior)

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The State of the Art on WCET Analysis

• Despite 20 years of research, there are still serious open problems in WCET analysis

• Most challenging problem: high complexity of today’s processors

• Manual interaction with the user is required for path analysis.

• Industrial SW development tools lack comprehensive support for WCET analysis

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Current Trend: Multi-Core Computing

• Adds to the complexity of system design and verification!

• Without careful hardware design towards predictability, WCET analysis is much more complex!

• Timing interaction between different cores should be avoided whenever possible Design pattern: “Temporal Firewalls”

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Our Approach

• Multi-core computing

• Reference platform:JOP (Java Optimized Processor)

• Prioritized goals:

– Temporal predictability / stability first

– Performance second

Hardware: JOP Chip-Multiprocessor

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Legend:M: local method cacheS: local stack cacheSPM: local scratchpad memory

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The Task Model

• Simple tasks (no blocking of a task) [Kopetz97]

• Periodic task activation (time-triggered)• Inter-process communication with shared

memory• A task run consists of three phases:

– read (only read shared memory)– exec (no access to shared memory)– write (only write to shared memory)

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The Programming Model

• Single-path (SP) computing (use of conditional data-flow instead of conditional control-flow)

• SP computing doesn’t have to be explicitly programmed automatic transformation of programs into SP programs possible (by compiler)

• WCET-oriented programming- includes SP computing as a pattern

Single-Path Transformation

Transform input-data dependent branches into sequential predicated code, rest remains unchanged

Technique based on: if-conversion

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if cond

res := expr1 res := expr2

P := cond(P) res := expr1(not P) res := expr2

Predicated execution

Hardware Support for Single-Path Programming

String a = ”true” ;

String b = ” false ” ;

String result ;

int val ;

boolean cond = true;

val = Native.condMove(1, 2, cond);

System.out.println(val );

result = (String) Native.condMoveRef(a, b, cond);

System.out.println( result );

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Hardware Support for Time-Predictable Task Activation

SysDevice sys = IOFactory.getFactory().getSysDevice();

int time = sys. cntInt ;

time = time – (time % TDMA) + 1000;

sys.deadLine = time;

“sys.deadLine = time” blocks until the deadline is reached

12Maximum jitter without synchronization to the memory arbiter: length of TDMA round - 1

Example: Safety-Critical Control Application

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Example: Complex Communications

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Example: Multi-Core Scheduling

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C

A+B

A+BA+B

A+B

A+B

A+B

C

C

D

D

DEEE Task List:

A … STSampler τ1 B … STSampler τ2 C … STController τ3 D … STGuard τ4 E … STMonitor τ5

Task Phases:

1. Read

2. Exec

3. Write

Example: Measured SP Exec. Times

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Conclusion and Outlook

• Ultra time-predictable hardware/software approach–Inter-core communication with global memory–No system-on-chip networking–Synchronized task activation relative to TDMA –based

memory arbiter–Local caches on each core to improve TDMA-based

memory access performance• Tool support desired for creating efficient time-predictable

schedules

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Special Issue on WCET AnalysisCall for Contributions

• Journal of Systems Architecture (Elsevier)• Editors: Andreas Ermedahl, Peter Puschner• Important Dates:

January 10, 2010 Submission DeadlineJuly 1, 2010 Journal in print

• Web: www.elsevier.com/locate/sysarc