Radix 2 Encoding

7/28/2019 Radix 2 Encoding

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Radix-2 Encoding

Algorithm inefficient with isolated 1'sExample: 001010101(0) recoded as 011111111 ,

requiring 8 instead of 4 operations

Situation can be improved by examining 3 bits of X at

a time rather than 2


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Radix-4 Encoding


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y(2i+1) y(2i) y(2i-1) y(i)` X 2X Sign Zero

0 0 0 0 0 0 0 1

0 0 1 1 1 0 0 0

0 1 0 1 1 0 0 00 1 1 2 0 1 0 0

1 0 0 -2 0 1 1 0

1 0 1 -1 1 0 1 01 1 0 -1 1 0 1 0

1 1 1 1 0 0 1 1

Modified Booths Encoder


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Simplified sign extension method

PP80

PP80

PP80

PP80

PP70

PP60

PP50

PP40

PP30

PP20

PP10

PP00

1 PP81

PP81

PP71

PP61

PP51

PP41

PP31

PP21

PP11

PP01

S

1 PP82

PP82

PP72

PP62

PP52

PP42

PP32

PP22

PP12

PP02

S

PP83

PP83

PP73

PP63

PP53

PP43

PP33

PP23

PP13

PP03

S

S

P15

P14

P13

P12

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

P0


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Proposed Modified Booths Encoder


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Proposed Booth selector


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Adding Last Row of PP with Sign bit:-

We add last PP row with corresponding signbit.

It is done to avoid usage of higher level ofcompressor.

Only 10 bit Half adders are used instead ofFull adders if compressors were used.


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Compression of PP using 4:2 Compressor


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A 16-bit Parallel Adder to compute final sum

(product):-

Done to compute the Sum of Sum and carry of

compressor output.

Parallel addition is used Since it gives a

reasonable speed with lesser area.


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Logic gates used in

Encoder and selector

No. of Logic gates used

in Encoder and selector

NOT 3

2 I/P -XOR 2

2 I/P-NAND 3

3 I/P-NAND 4

Logic gates used in Encoder and selctor


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Total Number of

transistors in Encoder and

selector combined design

(For comuting 1 PP)

%Improvement/Enhancem

ent in Number of

transistors with respect to

Proposed design for


Conventional Booth

multiplier[1]

62 -11%

Modified Wen-Changs

method[2]

90 +22%

Our Proposed Encoder and

Selector

70 -

Z. Hung and M. D.

Ercegovac Encoder and

Selector[5]

66 -6%

Transistors used in our Proposed Design

Result Analysis


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Propoagation Delay for


combined (Normalized

with respect to Inverter

i.e. Inverter delay is 1)

%Improvement/Enhance

ment in Propogation

Delay with respect to

Proposed design for


Conventional Booth

multiplier[1]

13.6 +45%

Modified Wen-Changs

method[2]

8.4 +12%

Our Proposed Encoder

and Selector

7.4 -

Z. Hung and M. D.

Ercegovac Encoder and

9.0 +17%

Speed Improvization


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CONCLUSION

An efficient Booths Encoder and Selector has beendeveloped using a redisigned MBE.

With achieving 7.4 Normalized gate delay of

propagation for Encoder and Selector, remarkable is

the speed improvement.

However the increase in sizing can be tolerated sincethe achieved speed is remarkable.


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REFERENCES

[1] Neil Weste, David Harris (2005). CMOS VLSI DESIGN (3rd Ed).Pearson Publications.

[2] Razaidi Hussein , Ali Yeon Md. Shakaff, Norina Idris, ZalimanSauli, Rizalafande Che Ismail and Afzan Kamarudin. An EfficientModified Booth Multiplier Architecture 2008 IEEE InternationalConference on Electronic Design. December 1-3, 2008, Penang,Malaysia.

[3] Shiann-Rong Kuang, Jiun-Ping Wang, and Cang-Yuan Guo.Modified Booth Multipliers With a Regular Partial Product Array.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII:EXPRESS BRIEFS, VOL. 56, NO. 5, MAY 2009.

[4] Wen-Chang, Y. & Chein-Wei, J. High-speed Booth encoded parallelmultiplier design, IEEE Transactions on Computer, 2000.

[5] Z. Huang and M. D. Ercegovac, High-performance low-powerleft-to right array multiplier design, IEEETrans.Comput., vol. 54,no. 3, pp. 272283, Mar. 2005.


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REFERENCES

[6] Ercegovac. T. L. M. D. (2003). Digital Arithmetic. California, USA:

Morgan Kaufmann Publishers.

[7] Razaidi et al, Analysis of various Modified Booth Encoder (MBE)

and proposal for an efficient Modified Booth Encoder, IEEE

Regional Symposium on Microelectronics, December, 2007

[8] Rizalafande Che Ismail, A Complex Multiplier Using Booth

Wallace Algorithm, M.Eng. RMIT, 2005

Radix 2 Encoding

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