R E G L E RTEKNIK L - control.isy.liu.se

Linkoping Studies in Science and TechnologyThesis No. 883

Equalization of Distortionin A/D Converters

Jonas Elbornsson

REGLERTEKNIK

AUTOMATIC CONTROL

LINKÖPING

Division of Communication SystemsDepartment of Electrical Engineering

Linkopings universitet, SE–581 83 Linkoping, SwedenWWW: http://www.comsys.isy.liu.se

Email: [email protected]

Linkoping 2001

Equalization of Distortion in A/D Converters

c© 2001 Jonas Elbornsson

Department of Electrical Engineering,Linkopings universitet,SE–581 83 Linkoping,

Sweden.

ISBN 91-7373-020-3ISSN 0280-7971

LiU-TEK-LIC-2001:20

Printed by UniTryck, Linkoping, Sweden 2001

To Ulrika

Abstract

Modern communication systems require A/D converters with very high sam-ple rate and high accuracy. CMOS technology is suitable for integratingA/D converters on a chip at a low cost and low power consumption. How-ever, the CMOS manufacturing process is quite inaccurate, which leads toerrors in the A/D converters.

Traditionally the A/D converters are calibrated after they are manufac-tured to correct these errors. This is a time-consuming and costly process.The characteristics of an A/D converter normally change during its life-time due to, for instance, temperature changes and aging. This cannot becompensated for in the calibration.

In this thesis, we investigate how errors in A/D converters can be es-timated and corrected without the need for calibration. The estimationshould be done using only the signal that is used in the application.

Three different types of errors are discussed in this thesis. The firsttype of error is static nonlinear errors caused by component inaccuracies inCMOS technology. Two methods are proposed for estimation and correctionof these errors. The most general method requires only that the amplitudedistribution is smooth. With the other method the performance is a littlebetter but it requires knowledge of the amplitude distribution of the inputsignal. The estimation methods are evaluated on simulated data and datafrom a real A/D converter.

The second type of error is dynamic nonlinear errors in the sample-and-hold circuit which inevitably occurs when the sample rate increases. Someideas about how to correct these errors are discussed.

The third type of error is timing errors in time interleaved A/D con-verters, where the idea is to increase sample rate by parallelization of theconversion. A method for estimation and correction of these errors is pro-posed. This method requires that most of the signal energy is limited toa frequency band below about 1/3 of the Nyquist frequency, but requiresno other knowledge of the signal. This estimation method is evaluated onsimulated data.

i

Acknowledgments

First of all, I would like to thank my supervisor, Professor Fredrik Gustafs-son, for guidance in the work that has lead to this thesis. I also want tothank Professor Lennart Ljung for drafting me to the Control & Communi-cation group in Linkoping.

My work in this thesis has been in the field between signal processingand electronics. Dr. Jan-Erik Eklund at Ericsson Microelectronics and thepeople in the Electronic devices group, supervised by Professor ChristerSvensson, at the Physics Department have helped me understand how theA/D converters work.

All the people in the Control & Communication group are gratefullyacknowledged. Especially I want to thank Fredrik Tjarnstrom, Frida Gun-narsson and Erik Geijer who have proofread the thesis and given valuablecomments and suggestions for improvement.

This work was financially supported by ECSEL (Excellence Center inComputer Science and Systems Engineering in Linkoping) graduate schoolin Linkoping.

Finally I would like to thank my wife, Ulrika, for her love and supportduring the writing of this thesis, and my family for always being there forme.

ii

Contents

1 Introduction 11.1 A/D Converter Structures . . . . . . . . . . . . . . . . . . . . 2

1.1.1 Successive Approximation ADC . . . . . . . . . . . . . 21.1.2 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . 51.1.3 Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . 51.1.4 Interleaved ADCs . . . . . . . . . . . . . . . . . . . . . 71.1.5 Slope A/D Converters . . . . . . . . . . . . . . . . . . 8

1.2 Specifications of A/D Converters . . . . . . . . . . . . . . . . 81.2.1 Quantization . . . . . . . . . . . . . . . . . . . . . . . 81.2.2 DC Specifications . . . . . . . . . . . . . . . . . . . . . 81.2.3 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.2.4 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . 101.2.5 Dynamic Specifications . . . . . . . . . . . . . . . . . 11

1.3 ADC Applications in Communications Systems . . . . . . . . 131.3.1 Digital Subscriber Line Technology . . . . . . . . . . . 131.3.2 Software Radio . . . . . . . . . . . . . . . . . . . . . . 17

1.4 Parallels to Blind Equalization . . . . . . . . . . . . . . . . . 211.5 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . . 231.6 Outline and Contributions . . . . . . . . . . . . . . . . . . . . 23

iii

iv Abstract

2 Equalization of Static Nonlinearities in SA-ADC 252.1 A/D Converter Description . . . . . . . . . . . . . . . . . . . 26

2.1.1 SA-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 262.1.2 Binary Search Algorithm . . . . . . . . . . . . . . . . 272.1.3 Subranging Technique . . . . . . . . . . . . . . . . . . 27

2.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . 292.2.1 Resistance Errors . . . . . . . . . . . . . . . . . . . . . 292.2.2 Subranging Mismatch . . . . . . . . . . . . . . . . . . 32

2.3 Equalization with known Input Distribution . . . . . . . . . . 342.3.1 Assumptions and Notation . . . . . . . . . . . . . . . 342.3.2 Estimation Method . . . . . . . . . . . . . . . . . . . . 352.3.3 Criterion Functions . . . . . . . . . . . . . . . . . . . . 362.3.4 Amount of Data . . . . . . . . . . . . . . . . . . . . . 402.3.5 Parameter Update . . . . . . . . . . . . . . . . . . . . 432.3.6 Initial Value Estimation . . . . . . . . . . . . . . . . . 452.3.7 Reference Level Estimation Algorithm . . . . . . . . . 46

2.4 Equalization with Unknown Input Distribution . . . . . . . . 472.4.1 Assumptions . . . . . . . . . . . . . . . . . . . . . . . 472.4.2 Estimation Overview . . . . . . . . . . . . . . . . . . . 482.4.3 Amplitude Distribution Estimation . . . . . . . . . . . 482.4.4 Parameter Estimation . . . . . . . . . . . . . . . . . . 502.4.5 Estimation Algorithm . . . . . . . . . . . . . . . . . . 51

2.5 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522.5.1 Known Amplitude Distribution . . . . . . . . . . . . . 522.5.2 Unknown Amplitude Distribution . . . . . . . . . . . . 642.5.3 Subranging ADC . . . . . . . . . . . . . . . . . . . . . 69

2.6 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 752.6.1 ADC Description . . . . . . . . . . . . . . . . . . . . . 752.6.2 Algorithm Modification . . . . . . . . . . . . . . . . . 752.6.3 Data Acquisition . . . . . . . . . . . . . . . . . . . . . 782.6.4 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . 782.6.5 Implementation Aspects . . . . . . . . . . . . . . . . . 79

2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3 Equalization of Dynamic Distortion in S/H 833.1 The Sample-and-Hold Operation . . . . . . . . . . . . . . . . 83

3.1.1 The Ideal Sample-and-Hold Circuit . . . . . . . . . . . 843.1.2 The NMOS Transistor . . . . . . . . . . . . . . . . . . 843.1.3 The Bottom Plate Sampler . . . . . . . . . . . . . . . 87

3.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . 92

Contents v

3.3 Model Based Equalization of Sample-and-Hold Nonlinearities 923.4 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4 Equalization of Static Jitter in Parallel ADC 994.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024.3 Timing Error Estimation Algorithm . . . . . . . . . . . . . . 102

4.3.1 Timing Error Estimation in Interleaved Perfect Sam-pling Units . . . . . . . . . . . . . . . . . . . . . . . . 102

4.3.2 Noise Sensitivity . . . . . . . . . . . . . . . . . . . . . 1054.3.3 Quantization Effects . . . . . . . . . . . . . . . . . . . 1074.3.4 Noise estimation Algorithm . . . . . . . . . . . . . . . 110

4.4 Error compensation . . . . . . . . . . . . . . . . . . . . . . . 1124.5 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

4.5.1 Timing error estimation . . . . . . . . . . . . . . . . . 1124.5.2 Noise compensation . . . . . . . . . . . . . . . . . . . 1144.5.3 Quantization effects . . . . . . . . . . . . . . . . . . . 1194.5.4 Implementation Aspects . . . . . . . . . . . . . . . . . 122

4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

5 Conclusions 1255.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255.2 Further Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Bibliography 129

vi Contents

Notation

Symbols

Symbol Explanationu(t) Analog input signaly(t) Output signalyi(t) Output signal from ith channel∆nyi[k, l] yi[k] − y{(i−n) mod M}[l]

∆nyi[k] ∆nyi[k, k]

∆yi[k] ∆1yi[k, k]

z[k] Output from equalizere[k] White noisew[k] Colored noiseλ Noise varianceti Timing error from ith channelθ∗i True error between reference levels i− 1 and iΘ∗ True error vector Θ∗ = [θ∗1 · · · θ∗n]Tθi Estimated error between reference levels i− 1 and iΘ Estimated error vector Θ = [θ1 · · · θn]TfX(x) True amplitude distribution for signal x(t)fX(x,Θ) Estimated amplitude distribution for signal x(t)

vii

viii Contents

Symbol ExplanationRyi,i−j

[l] E(∆jyi[k, k− l])

N Number of samples from one ADCM Number of interleaved ADCsV(·) Criterion function, goodness measureTs Sampling intervalfs Sampling frequencyfc Cut-off frequency or signal bandwidthfin input signal frequencyT TransposeE ExpectationE limN→∞ 1

N

∑Nk=1E

Abbreviations

Abbreviation ExplanationA/D Analog to DigitalADC Analog to Digital ConverterADSL Asynchronous DSLAMPS Advanced Mobile Phone SystemCMOS Complementary MOSD-AMPS Digital AMPSdB decibelDC Direct CurrentDMT Discrete Multi ToneDNL Differential Non-LinearityDSL Digital Subscriber LineDSP Digital Signal ProcessorFSK Frequency Shift KeyingGSM Global System for Mobile CommunicationHDSL High bit rate DSLIF Intermediate FrequencyINL Integral Non-LinearityISDN Integrated Services Digital NetworkLNA Low Noise AmplifierLSB Least Significant BitMOS Metal Oxide Semiconductor

Contents ix

Abbreviation ExplanationMSB Most Significant BitNMOS Negative doped MOSPAM Pulse Amplitude ModulationPOTS Plain Old Telephone ServicesPSK Phase Shift KeyingPSTN Public Switched Telephone NetworkQAM Quadrature Amplitude ModulationRADSL Rate Adaptive DSLRF Radio FrequencyRMSE Root Mean Square ErrorSA Successive ApproximationSFDR Spurious Free Dynamic RangeSH Sample and HoldSNR Signal to Noise RatioSNDR Signal to Noise plus Distortion RatioVDSL Very high bit rate DSLxDSL HDSL, ADSL, VDSL,...

x Contents

1Introduction

The trend in modern communication systems is to make everything digi-tal. Only ten years ago, analog mobile phone technology was still dominant(NMT, AMPS). These systems are now almost completely replaced by digi-tal systems (GSM, D-AMPS). Today analog television and broadcast radioare being replaced by digital systems. There are many reasons for thischange of technology of which some are listed below

• The information can be compressed and therefore the frequency rangecan be better utilized, e.g., more mobile phones.

• Cryptography can be used to avoid malicious listeners.

• Channel coding can be used to reduce sensitivity to disturbances.

• Digital electronics is much easier to construct and cheaper to manu-facture, especially for complex systems.

• Signal processing can be done in software instead of in hardware.

Since the digital signal is used to carry analog information, such as speechand pictures, A/D and D/A converters are usually required to convert thesignal at some stage. As more and more of the communication is done digi-tally, the demands on the A/D and D/A converters increase. With a highersample rate, faster information interchange can be achieved. Lowering of

1

2 Chapter 1 Introduction

the production cost allows the use of A/D converters in cheap products.With lower power consumption, the A/D converters can be used in mo-bile terminals. To achieve high sample rates at a low cost and low powerconsumption, the use of integrated CMOS circuits is a good solution. Oneproblem with this technology is that the accuracy of the components is quitelow. Calibration of these circuits is costly and time consuming. Therefore alot of money could be saved in the manufacturing process if the calibrationcould be avoided.

The aim of this thesis is to present methods to eliminate the errors inthe output signal from the CMOS-circuits without any calibration.

This chapter begins with a description of different A/D converter stru-cures in Section 1.1. In Section 1.2 a description of different specificationsfor A/D converter performance follows. In Section 1.3 some applications forA/D converters are described. The link to blind equalization is describedin Section 1.4. The chapter ends with a problem definition in Section 1.5and an outline of the rest of the thesis in Section 1.6.

1.1 A/D Converter Structures

In this section some different A/D converter structures are briefly described.The A/D converters that are treated in this thesis are described in moredetail in the following chapters. More information about A/D converterstructures can be found in e.g. [64]. This section overwievs the most fre-quently used technologies.

In general, the conversion from analog signal to digital signal is donein two steps as shown in Figure 1.1. First a quantization in time is donein a sample-and-hold circuit. After that, a quantization in amplitude isdone with a resistance ladder and a comparator. This process is furtherdescribed in the next subsection. The sample-and-hold circuit holds thesignal at a constant level while the amplitude quantization is done. Thesample-and-hold circuit is required since the analog signal otherwise mightchange during the amplitude conversion which would lead to inconsistentresults.

1.1.1 Successive Approximation ADC

The Successive Approximation ADC (SA-ADC) basically consists of a re-sistance ladder and a comparator, see Figure 1.2. A voltage is applied overthe resistance ladder and the digital value is found by comparing the analogvoltage, uSH, to the voltages, ri, between the resistances in the resistance

1.1 A/D Converter Structures 3

sample−

and−

hold

Time

quantization

resistance

ladder

and

comparator

Amplitude

quantization

Figure 1.1 Two step conversion from analog to digital signal.

SH

comparator

resistance ladder0

r1

r2

r3

r4

r5

r6

r7

u(t) uSH

Figure 1.2 Successive Approximation ADC. The digital value isfound by comparing the analog signal, uSH, to the ref-erence levels ri.


ladder. The search for the correct digital value is done by the binary searchalgorithm. The search starts in the middle of the ladder, if the analog volt-age is larger than the reference the search continues in the upper half ofthe ladder otherwise in the lower half. This continues until the correct levelis found. In this search algorithm, one bit of precision is found in everycomparison so that an n-bit SA-ADC requires n comparisons. This A/Dconverter structure is further described in the next chapter.

Subranging SA-ADC

A high precision SA-ADC would require a very long resistance ladder, sincean n-bit SA-ADC requires 2n resistances. The length of the ladder can bereduced by introducing subranging stages. In a subranging SA-ADC, theconversion is divided into two or more steps, see Figure 1.3. In a two stage

SH

resistance ladder 1 resistance ladder 2

electrical connection

comparator

Figure 1.3 Subranging SA-ADC. The conversion is done in twosteps with two resistance ladders.

subranging ADC, with n = n1 + n2 bits, the n1 most significant bits arefirst found by a resistance ladder of length 2n1 . Then the n2 least significantbits are found by comparing the residue of the analog signal to the referencelevels in the second resistance ladder of length 2n2 .

Pipelined SA-ADC

In a pipelined SA-ADC, a second sample-and-hold circuit is used in thesecond subranging stage to hold the residual signal during the search forthe least significant bits, see Figure 1.4. In this way, another conversion


SH

resistance ladder 1 resistance ladder 2

comparator

SH

Figure 1.4 Pipelined SA-ADC.

can be started in the first stage before the second is completed, and thesampling rate can be increased.

The Successive Approximation A/D converters are used in systems whichrequire very high bandwidth and high dynamic range. This can for examplebe radio base stations and DSL (Digital Subscriber Line) modems.

1.1.2 Flash ADC

In a flash ADC, one comparator is used for each reference level, see Fig-ure 1.5. A flash ADC is very fast since the comparison of all levels is doneat the same time. The drawback of the flash ADC is that it requires alot of hardware since an n-bit flash ADC requires 2n comparators. Thepower consumption is also high in flash A/D converters since all the 2n

comparators must be used in every sample.Flash A/D converters are used in systems which require very high sam-

pling rate. The requirements on dynamic range cannot be too high however,since a Flash A/D converter with many bits requires a lot of hardware. FlashA/D converter technique is usually limited to 6− 10 bits.

1.1.3 Sigma-Delta ADC

In a sigma-delta ADC, oversampling is used to increase the precision. Thesigma-delta A/D conversion principle is shown in Figure 1.6. The conver-sion is done by a 1-bit A/D converter. A feedback loop with a 1-bit D/Aconverter is used to produce a serial output where the mean over a finiteinterval gives the digital word. The sigma-delta ADC has extremely highlinearity since the A/D converter only consists of a switch. Linearity means


SH

decoderarray

comparatorresistanceladder

Figure 1.5 Flash ADC. The conversion speed is here improved byusing one comparator for each digital level.

+1-bitA/D

clock

1-bitD/A

DigitalLow-Pass/Decimator

K(z)

Figure 1.6 Sigma-delta ADC. A feedback loop and high oversam-pling is here used to achieve good performance.


here that the distance between adjacent digital levels is constant over thefull range of the ADC. A filter K(z) can be used in the feedback loop to im-prove stability margins. Because of the oversampling the sigma-delta ADCcan only be used for narrow-band signals.

The Sigma-Delta A/D converters are used in narrow band applicationswith high demands on linearity, for example mobile terminals.

1.1.4 Interleaved ADCs

To increase the bandwidth of the A/D conversion, several A/D converterscan be used in parallel, see Figure 1.7. Here the A/D converters are inter-

ADC1

ADC2

ADC3

ADCM

samplingclock

delay

u

y

Figure 1.7 Interleaved ADC. The conversion speed is here im-proved by using several A/D converters in parallel.

leaved in time so that the effective sampling frequency is n times higher ifn ADCs are used. This reduces the demands of conversion speed comparedto a single ADC. The sample-and-hold circuit must, however, still be fastenough to track the signal that should be converted. This type of A/Dconverter is further discussed in Chapter 4.

Interleaving of A/D converters improves the sampling rate a lot. Timeinterleaved A/D converters can be used in systems with very high speedrequirements, for example radio base stations and VDSL modems.


1.1.5 Slope A/D Converters

A slope A/D converter consists basically of an integrator and a counter.The signal is integrated in a capacitor and the counter measures the time ittakes for the integrator to reach a certain level, this time is proportional tothe signal amplitude. This kind of A/D converter can be made with highaccuracy but it is very slow.

Slope A/D converters are used to measure slowly varying signals andDC signals. Typical applications are digital voltmeters.

1.2 Specifications of A/D Converters

In this section we will discuss different measures of performance for A/Dconverters. These performance measures are more thoroughly describedin [64].

1.2.1 Quantization

The quantization in time and amplitude in an A/D converter gives a theo-retical limit of how well a signal can be reconstructed. The sampling intervalgives a limit of the maximum input frequency that can be represented ac-curately. According to the Nyquist theorem, the highest signal frequencycan not be higher than half the sampling frequency.

Because of the amplitude quantization there will always be an errorbetween the analog signal value and the digital signal value. These errorscause rounding noise on the output signal. The quantization noise limitsthe performance of the A/D converter.

1.2.2 DC Specifications

Here specifications for DC performance are described. These are measures ofthe actual deviations from an ideal A/D converter, but do not say anythingabout how dynamic signals are affected.

Integral Non Linearity and Monotonicity

The Integral Non Linearity (INL) is a measure of the average deviationfrom the ideal A/D converter curve. Let ∆k be the deviation of the k’thbit from a straight line through zero and full scale. Adding all these errorsresults in zero since the straight line goes through the actual full scale, seeFigure 1.8. The Integral Non Linearity is defined as the sum of all positive

1.2 Specifications of A/D Converters 9

Digital output

Analog input

000001

010011

100101

110

111

∆1

∆2

∆3

Figure 1.8 The Integral Non-Linearity of an A/D converter. Solidline is the A/D converter levels. Dashed line is the ideal,infinite precision, conversion line from analog to digital.

or all negative errors:

INL =∑k:∆k>0

∆k = −∑k:∆k<0

∆k =1

2

∑k

|∆k| (1.1)

An A/D converter is monotonic if the digital output is guaranteed to benon-decreasing when the analog input is increasing. It can be shown that aconverter is monotonic if INL < 1

2LSB (Least Significant Bit).

Differential Non Linearity

The Differential Non Linearity (DNL) describes the error between two ad-jacent levels. The difference in analog signal between two adjacent levelsshould in the ideal case correspond to 1 LSB. The deviation from this valueis the DNL. An A/D converter therefore has one DNL value for each digitallevel, see Figure 1.9.


Analog input

Digital output

0 10

1

2

3

4

2 3 4

Exampleof DNL

Figure 1.9 DNL curve for 2-bit ADC. Solid line is the ideal A/Dconverter curve and dashed line is the A/D converterwith errors.

1.2.3 Offset

Amplitude offset in an A/D converter causes a non-zero output when theinput is zero. The amplitude offset is very important to keep small in DCsystems, e.g., voltmeters, and in interleaved A/D converter structures wheredifferent offsets in different ADCs cause distortion of the output signal.

The timing offset is a deviation from the nominal sampling time. Thisoffset is not important when a single A/D converter is used (as long as itis constant). But in interleaved A/D converters, these offsets will causeirregular sampling intervals, which lead to distortion of the signal. Timingoffsets in interleaved ADCs are hereinafter referred to as static jitter.

1.2.4 Scaling

The scaling of an A/D converter causes amplitude errors. If u(t) is theanalog input and y(t) is the digital output we have, disregarding othererrors, that

y(t) = σu(t) (1.2)

1.2 Specifications of A/D Converters 11

The scaling errors are important in DC systems where it is important thatthe measured level is correct. It is also important in interleaved A/D con-verters where different scaling in different A/D converters causes distortion.

1.2.5 Dynamic Specifications

The dynamic specifications describe how much a signal is distorted by quan-tization and other errors. We assume here a signal model

y(t) = s(t) + e(t) + d(t) (1.3)

where s(t) is the analog input signal and y(t) is the digital output. Thequantization noise is described by e(t) and d(t) is the harmonic distortion,i.e., errors caused by nonlinearities in the ADC and dynamic nonlinearitiesin the sample-and-hold circuit.

Signal-to-Noise Ratio

The Signal-to-Noise Ratio (SNR) of the ADC depends mainly on the ampli-tude quantization. SNR is usually measured in decibel (dB) and is definedas

SNR = 10 logP(s)

P(e)(1.4)

where s(t) is the signal and e(t) is the noise. Here P(·) denotes power. Witha quantization step of qs, the mean squared error due to quantization willbe

E(e2) =1

qs

∫qs/2−qs/2

e2de =1

12q2s (1.5)

since the quantization error for most signals can be assumed to be uniformlydistributed. The assumption of uniform distribution is true if the amplitudedistribution of the input signal is approximately constant between two ref-erence levels, which it usually is. A full scale sinusoid converted in an n-bitADC will have a peak-to-peak amplitude of App = 2nqs. The RMS (Rootmean square) value of this signal is Arms =

2nqs

2√2

. From the energy of thesignal and the energy of the noise, we can calculate the theoretical SNR

SNR = 10 logA2rms

E(e2)= 10 log 2n

√1.5 = 6.02n + 1.76 (1.6)


Signal-to-Noise plus Distortion Ratio

The Signal-to-Noise plus Distortion Ratio (SNDR) is defined as

SNDR = 10 logP(s)

P(y − s)(1.7)

where s(t) is a sinusoidal signal. That is, the SNDR is a measure of thepower of everything that does not come from the signal itself, i.e., bothnoise and harmonics.

Spurious Free Dynamic Range

The Spurious Free Dynamic Range (SFDR) is measured with a sinusoidalinput signal. The SFDR is the difference between the signal energy and theenergy of the largest harmonic, measured in dB. Figure 1.10 shows how theSFDR is measured. In Chapter 2 we will see that the SFDR can be improvedby about 15dB by the correction methods. This improvement correspondsto more than two bits of precision. This means that, for instance, weakercarriers in a mobile telephone system can be identified.

0 0.2 0.4 0.6 0.8 1−50

−40

−30

−20

−10

0

10

Normalized frequency

Sig

nal e

nerg

y [d

B]

SFDR=30dB

Figure 1.10 Definition of SFDR. The highest peak comes from thesignal, the SFDR is the distance from this peak to thehighest distorsion peak.

1.3 ADC Applications in Communications Systems 13

Total Harmonic Distortion

Total Harmonic Distortion (THD) is defined as the signal energy comparedto the sum of the energy of all harmonic distortion components.

THD = 10 logP(s)

P(d)(1.8)

Dynamic Range

The concept of dynamic range is used to describe the performance of anA/D converter. It should describe the range where different signals can beseparated. The notation here is a little sloppy. Dynamic range is often usedboth for SFDR and SNDR and it should therefore be used with care. If aprecise performance measure is wanted, SFDR or SNDR should be used.

1.3 ADC Applications in Communications Systems

In this thesis, only wide band ADCs are discussed. We will in this sectiondescribe two applications that require wide band A/D converters with highdynamic range: DSL modems and Software Radio. Other applications thatuse narrow band A/D converters, such as mobile phones, are not discussedhere.

1.3.1 Digital Subscriber Line Technology

The telephone network is designed for voice communication. Therefore thebandwidth is adjusted for the human voice, 300-3400 Hz. During the lastdecades, the demands on data communication have increased. Data com-munication over telephone lines is very cost effective since the infrastructurealready covers almost every home. The most common way of communicat-ing over telephone lines is with voice band modems. The bandwidth of3kHz is however rather narrow and the bit rate limit of voice band datacommunication (56kb/s) has already been reached. Another drawback withvoice band data communication is that the telephone communication isblocked while the modem is used. Digital Subscriber Line (DSL) technol-ogy provides fast digital communication over the PSTN (Public SwitchedTelephone Network) [62, 25, 47]. It also allows telephone communicationand data communication simultaneously. However, this technology requiresreceivers with very high dynamic range. The first DSL standard was theISDN (Integrated Services Digital Network) at 144kb/s. This bit rate was


until a few years ago assumed to be the fastest rate possible over PSTN(Public Switched Telephone Network). Today we have HDSL (High bit rateDSL) at 1.5Mb/s, ADSL (Asymmetric DSL) at 6Mb/s and striving towardsVDSL (Very high bit rate DSL) at 52Mb/s.

In ADSL and VDSL a frequency band above the voice band is usedfor the data communication, see Figure 1.11. This allows data communi-cation and voice communications simultaneously over the same telephoneline. In ISDN and HDSL, however, the voice band and data communicationsband overlaps. The data communication band is divided into one band for

Telephone band

Guard bandUpstream band

Downstream band

Frequency

Figure 1.11 Frequency allocation for DSL.

upstream transmission and one band for downstream transmission. By al-locating different bandwidths for upstream and downstream transmission,asymmetric communication can be achieved, i.e., higher downstream bitrate than upstream, since usually more data is downloaded than uploadedby an end user. To avoid crosstalk, i.e., interference between upstream anddownstream signal, two methods can be used. The first method is to sep-arate the upstream and downstream band as in Figure 1.11, this is knownas Frequency Division Multiplexing (FDM). The other method is to sepa-rate upstream and downstream signals in time, i.e., one timeslot is used fordownstream communication and the next for upstream communication, thisis known as Time Division Multiplexing (TDM). Both these methods areused in DSL. Between the voice band and the DSL band a guard band isallocated to avoid interference between voice and data. Table 1.1 shows thelimits of the communications frequency bands for the different DSL tech-


DSL type ISDN HDSL ADSL VDSLVoice bandstart [kHz] 0.3 0.3 0.3 0.3

Voice bandend [kHz] 3.4 3.4 3.4 3.4

Guard bandstart [kHz] – – 3.4 3.4

Guard bandend [kHz] – – 25 300

Upstream bandstart [kHz] 0.3 0.3 25 300

Upstream bandend [kHz] 4 196 160 700

Downstream bandstart [kHz] 0.3 0.3 240 1000

Downstream bandend [kHz] 4 196 1100 Variable

Table 1.1 The DSL frequency bands.

nologies [42], standardized by ANSI [1, 2]. Since the PSTN is designed forvoice communication, the data communication band is highly attenuated.Therefore the high speed DSL technology only works if the receiver has highdynamic range. A critical part here is the A/D converter.

Modulation

Telephone lines can only transmit analog signals. Therefore the DSL sig-nals must be modulated before transmission. Modulation means that thedigital signal changes some property of a sinusoidal carrier signal depend-ing on the value of the digital signal. The carrier can be modulated bychanging for instance the phase (PSK), the frequency (FSK), or the ampli-tude (PAM) [32]. In for example Pulse Amplitude Modulation (PAM), eachsymbol in the digital signal, mk, determines the amplitude of a pulse thatmodulates the carrier during a time Tb.

x(t) = mkφ(t)sin(ωt), kTb ≤ t < (k+ 1)Tb (1.9)


A symbol can consist of one or several bits. A two-dimensional carrier canalso be used. This means that two orthogonal signals are used as carrier

s(t) = cos(ωt) + i sin(ωt) (1.10)

The components of the carrier are referred to as the inphase (I) and thequadrature (Q) part of the signal. The inphase and quadrature parts canthen be modulated independently by for example PAM. The two dimen-sional PAM is called QAM (Quadrature Amplitude Modulation). In Fig-ure 1.12, QAM diagrams of different sizes are shown. The QAM modulationis used for xDSL transmission [62].

I

Q

4−QAM

I

Q

16−QAM

I

Q

64−QAM

Figure 1.12 QAM modulation diagrams

DMT

To avoid too much interference between adjacent symbols, the channel musthave good characteristics. This means that the gain should be constant overall frequencies and the phase should be linear. The telephone line is far fromthis ideal situation in the frequency band used for DSL transmission. Thetelephone line typically has a low pass characteristic as exemplified in Fig-ure 1.13. The modulation techniques assume a channel with flat frequencycharacteristics, otherwise a lot of intersymbol interference will occur, i.e.,adjacent symbol interfere wit heach other. This means that this a low passchannel is not suitable for communication. Therefore the frequency bandis divided into several frequency separated channels, and a carrier is mod-ulated with digital data in each channel. This type of signal is called aDMT-signal (Discrete MultiTone).


Frequency

1

4kHz

Figure 1.13 Example of a telephone line frequency characteristics.

In ADSL, 256 channels are used for the downstream transmission and 32channels for the upstream transmission. Each channel has a bandwidth of4.3125kHz. In each channel, the carrier is modulated with QAM. The size ofthe QAM-diagram is adaptively decided by the current SNR in each channel.The altering QAM size changes the transmission capacity. Therefore, thebit rate in DSL systems changes with the channel quality.

The amplitude distribution for each channel is basically a sinusoidalamplitude distribution. The amplitude distribution of a sinusoidal signal isquite constant except near the maximum and minimum signal values therethe amplitude distribution is very high. This means that the amplitudedistribution is shaped like a bathtub. With 256 channels the amplitudedistribution for the total signal will be close to a Gaussian distributionaccording to the central limit theorem.

A DSL modem requires an A/D converter with high bandwidth (inADSL the total bandwidth for downstream transmission is 4.3125·256kHz =

1.1MHz) and high dynamic range to separate the weak tones at high fre-quencies from harmonics of strong tones at lower frequencies.

1.3.2 Software Radio

A traditional radio receiver requires a lot of analog components, see Fig-ure 1.14. First the radio signal is received by the antenna. The signal is thenamplified by the LNA (Low Noise Amplifier). These parts are the only onesthat are shared by all radio channels [9, 10]. After these components one re-


LNA

Antenna

Filter Filter

Mixer Mixer

I

Q

Variable Fixed

ADC

Shared One receiver per channel

Figure 1.14 A traditional radio receiver architecture.

ceiver is required for each channel. The RF (Radio Frequency) signal is firstdownconverted by a mixer and a local oscillator with variable frequency toan IF (Intermediate Frequency) signal. The IF frequency is the same for allchannels. The IF signal is then downconverted to the baseband. Betweenthe mixers, analog filters are used to discriminate frequencies outside thesignal band. The last step before digitization is to decompose the signal intoinphase and quadrature components. These signals are then converted in anarrow band ADC. In e.g. GSM900 the total bandwidth is about 25MHzwhile the channel bandwidth is about 200kHz [55]. A GSM base station cantherefore handle more than 100 channels and with the traditional techniqueone receiver is required for each channel.

If the ADC is moved closer to the antenna, more components can beshared for all channels and more of the signal processing can be done insoftware. This means that the hardware cost can be substantially reduced.An ideal software radio would consist of an antenna, one ADC that samplesdirectly on the antenna signal, one DAC that generates the outgoing an-tenna signal and a DSP (Digital Signal Processor). All the signal processingshould then be done in software in the DSP [52], see Figure 1.15. This idealsituation is, however, not realizable today. One step towards the ideal soft-ware radio is reachable though, see Figure 1.16 [9, 46]. Here a wide bandmixer and a fixed local oscillator is used to downconvert the whole signalband to IF. The IF signal is usually a band pass signal above the base band.After that a wideband ADC converts the analog IF signal to a digital signalwhich is separated into different channels in software. The rest of the signal


LNA

Antenna

FilterWideband

FastADC

DSP

Shared One DSP per channel

Figure 1.15 The ideal soft radio architecture.

LNA

Antenna

Filter

Wideband

WidebandFast

ADC

Mixer

DSP

Shared One DSP per channel

Fixed

Figure 1.16 A soft radio receiver architecture.

processing is then done in software in a DSP.There are other advantages with a soft radio architecture, besides the

hardware reduction. A software radio base station could be reconfiguredwithout replacing any hardware [61]. The same hardware could also be usedfor different systems, e.g., GSM and D-AMPS, since all the signal processingis done in software. The software radio can in the future also be useful in


handheld terminals [63]. Instead of implementing several radio receivers formultiband mobile phones, one receiver could be used for all systems anddifferent software packages could be used to switch between systems. Inhandheld terminals the power consumption is however still limiting the useof this technique.

The requirements on the ADC in a soft radio architecture are very high.When the signal is received in the antenna in for instance a radio basestation, some of the carriers are strong and some of the carriers are muchweaker. When this wide band signal is converted in the ADC the SFDRmust be high enough so that a weak carrier can be separated from harmonicsfrom the strong carriers [68], see Figure 1.17. The SNDR must also be high

Frequency

Carrierpower

Noise floor

Strongcarrier

Harmonic WeakCarrier

Figure 1.17 Weak carrier close to harmonics from strong carrier.

so that weak carriers can be seen above the noise floor.The IF maximum frequency is still usually rather high. According to the

Nyquist sampling theorem the signal must be sampled with at least twicethat frequency. The fact that the IF signal is a bandpass signal can howeverbe used to reduce the sampling frequency by using undersampling [66]. If weknow that the signal is confined to the frequency interval [f1, f2], a samplingfrequency fs ≥ f2− f1, where fc =

f1+f22

is a multiple of fs, is enough, seeFigure 1.18. The undersampling technique reduces the speed requirementson the amplitude quantization part of the ADC. The sample-and-hold circuitmust still have the same bandwidth as with Nyquist sampling to track thefast varying signal. Despite the undersampling technique, the ADC is stillthe critical part in software radio [46]. In Table 1.2 the sampling speed for

1.4 Parallels to Blind Equalization 21

Frequency

OriginalIF signal

AliasedIF signal

f1 f2fs

Figure 1.18 The principle of undersampling. The signal lies ina frequency band between f1 and f2. The samplingfrequency, fs, is smaller than 2f2 and the signal istherefore aliased to the base band.

Number of Sampling speed Manufacturerbits [MSamples/s]

8 1000 Signal Processing Technology, Inc.10 200 Analog Devices12 100 Analog Devices14 65 Burr-Brown

Table 1.2 State-of-the-art performance for ADC speed

today’s fastest commercial ADCs are listed for different number of bits. Aswe can see in this table the sampling speed increase a lot when the numberof bits is reduced. If the errors in the ADC can be corrected, the samedynamic range can be achieved with fewer bits and by that the samplingspeed could be significantly increased.

1.4 Parallels to Blind Equalization

In many communications systems, the signal is distorted by the channelbetween sender and receiver. In wire transmission, there are echoes thatdistorts the signal. In radio communiction, there is distortion caused bymultipath fading, i.e., the signal arrives as a sum of different timedelays.There is also linear dynamical distortion in all communication channels.


The typical situation is that we only have access to the received signal.An A/D converter is a similar system in the sense that only the output ismeasurable. The analog input signal is distorted by the A/D converter andthe digital output is therefore not correct. In communication systems thechannel is normally approximately inverted by a linear filter. To invert thechannel the channel must be known. The classical way of identifying thechannel is to send a known training signal with regular intervals and thenmeasure the output, yt. The training signal can however be eliminated andthe channel can be identified from only the received signal. This is knownas blind equalization [4, 5], see Figure 1.19. The blind equalization can

channel equalizerut yt ut

Figure 1.19 The equalization problem

however not be done without any knowledge of the signal. In communicationchannels for example the input alphabet is known [30, 34]. The problemin A/D converters is similar, we have an A/D converter with unknowncharacteristics and we can only measure the output, see Figure 1.20. The

equalizerut yt ut

ADC

Figure 1.20 The equalization problem in an ADC

prior information about the input signal that is used in the equalization ofan A/D converter is different for different types of errors. For equalizationof static nonlinear amplitude errors, a spatial smoothness assumption isused. This means that the amplitude distribution of the input signal, fU(u),should be smooth. This is further described in Chapter 2. For timing errorequalization, a temporal smoothness assumption is used. This means thatthe input signal should be bandlimited. The timing error equalization isfurther described in Chapter 4.

1.5 Problem Definition 23

1.5 Problem Definition

Real A/D converters are far from ideal. There are many kinds of errorsthat deteriorate the performance. The sample-and-hold circuit introducesnonlinear dynamic errors depending on input amplitude and input slope.The conversion step introduces static nonlinear errors and possibly missingdigital levels. In time interleaved A/D converters, there are timing errorsand amplitude offset errors that cause nonuniform sampling intervals. Allthese errors can cause a deterioration of the signal quality correspondingto several bits. If these errors could be corrected, the same dynamic rangecould be achieved with fewer bits. This would reduce cost and improve thesampling speed. The traditional way of improving the accuracy is calibra-tion. Calibration is very time-consuming and costly, and it cannot adapt tochanges in the errors. The purpose of this thesis is to develop methods forblind estimation of these errors without calibration. This means that theerrors should be estimated on-line, when the A/D converter is used. Theestimates should also adapt to changes in the errors caused by for exampleaging and changes in temperature.

1.6 Outline and Contributions

This thesis is divided into three major chapters, where each chapter de-scribes one type of error that occurs in A/D converters.

Chapter 2 begins with a description of static amplitude errors. Thecause of these errors is also described for one type of A/D converters (SA-ADC). Two methods for estimation of these errors are also presented. Thefirst method assumes that the amplitude distribution of the input signal isknown. The other method only assumes that the amplitude distribution issmooth. The chapter ends with simulations and measurements on a realA/D converter, that illustrates the performance of the estimation method.

In Chapter 3, nonlinear dynamic errors in the sample-and-hold circuitare treated. A model of the sample-and-hold circuit is described, and someideas of how these errors could be corrected are presented.

Chapter 4 treats timing errors in parallel, time-interleaved, A/D con-verters. The interleaved A/D converter structure is described. A methodfor estimation of the timing errors without knowledge of the input signal ispresented. The chapter ends with simulations that show the performanceof the estimation methods.

The thesis ends in Chapter 5 with conclusions and suggestions for future


work in the A/D converter error estimation area.The contributions of this thesis are:

• The blind estimation method for static amplitude errors in A/D con-verters. Today, all correction methods involve either a known trainingsignal for calibration, or a known signal shape.

• A preliminary study on a model based approach for estimation ofnon-linear dynamic errors in sample-and-hold circuits.

• The estimation method for timing errors in interleaved A/D convert-ers.

Some of the results in this thesis have been published as conference pa-pers. In the Conference on Computer Science and Systems Engineeringin Linkoping 1999 [21], the estimation method for static amplitude errorswith known input amplitude distribution was presented. In the IEEE Inter-national ASIC/SOC Conference 2000 [22], the estimation method for staticamplitude errors with unknown input amplitude distribution was presented.This method, with measurements on a real A/D converter, was also pre-sented in the Conference on Computer Science and Systems Engineering inLinkoping 2001 [23]. The timing error estimation method will appear in theIEEE International Conference on Acoustics Speech and Signal Processing2001 [24].

2Equalization of Static

Nonlinearities in SA-ADC

This chapter treats the problem of estimating the true transfer function ofan A/D converter. The A/D converter is here seen as a static function thatmaps the analog input signal to a digital output signal. Due to imperfectionsin the manufacturing process the conversion is not ideal. The traditionalway to overcome these imperfections is to calibrate the A/D converter whenit is manufactured. Calibration is time-consuming and costs a lot of money.The A/D converter characteristics may also change when it is used, e.g.,due to temperature change or aging. This means that the A/D converterhas to be recalibrated at regular intervals to keep its performance. A lotof time and money could be saved if the errors could be estimated andcorrected online, when the A/D converter is used. The analog input signalis of course unknown (otherwise we would not need the A/D converter). Aknown training signal would require a signal generator, or a memory and aD/A converter, on the A/D converter chip. These solutions are costly andcomplex to implement. Therefore only the digital output signal can be usedfor the error estimation. This chapter deals exactly with this problem: howto estimate and correct static errors using only the output signal.

The outline of the chapter is as follows. Section 2.1 describes how theA/D converter works in the ideal case. In Section 2.2, a description of whatcauses the errors in the A/D converter and how the errors affect the outputsignal follows. Section 2.3 describes the equalization method with known

25

26 Chapter 2 Equalization of Static Nonlinearities in SA-ADC

input signal amplitude distribution. In Section 2.4, this method is extendedso that it also works with unknown input signal amplitude distribution. InSection 2.5, an A/D converter is simulated and the equalization methodsare applied to the output signal. The chapter ends with Section 2.6 wherethe algorithm is tested on a real A/D converter.

2.1 A/D Converter Description

In this section, the structure of the ADC is described. More detailed in-formation about different A/D conversion methods can be found in for in-stance [64].

2.1.1 SA-ADC

The type of A/D converter that is discussed in this chapter is called Suc-cessive Approximation A/D converter (SA-ADC). This A/D converter wasbriefly described in Chapter 1, but is again described here in more detail.The SA-ADC consists basically of a sample-and-hold circuit, a resistanceladder and a comparator. The sample-and-hold circuit is required to keepthe analog input signal at a constant level during each sampling interval.

uSH(t) = u(kTs), kTs ≤ t < (k+ 1)Ts (2.1)

Here u(t) and uSH(t) are the input and output signals from the sample-and-hold circuit. The sample-and-hold circuit is discussed in more detail inchapter 3. The resistance ladder, see Figure 2.1, defines the possible digitalvalues. A constant voltage, A, is applied over the whole resistance ladder.

r0

r1

r2

r3

0

A

R

R

R

R

Figure 2.1 Resistance ladder for a 2-bit SA-ADC.

2.1 A/D Converter Description 27

The available digital values are the voltages between the resistances. Thismeans that for an n-bit ADC, the resistance ladder must have 2n resistors.With all resistances equal, the kth level, rk, will have the value Ak2−n.The comparator, see Figure 2.2, is used to compare the analog signal witha reference value. The comparator is an amplifier with infinite gain that isused to decide if the input signal is larger than a reference level or not.

cout =

{C if uSH(t) > rk−C if uSH(t) < rk

(2.2)

2.1.2 Binary Search Algorithm

To find the correct digital level, the analog signal is first compared to thelevel in the middle of the resistance ladder. If the analog signal is largerthan this reference value, the most significant bit (MSB) is set to zero,and the search is continued in the lower half of the ladder. Otherwise theMSB is set to one and the search continues at the upper half. This processcontinues until the correct level is found, see Figure 2.3. The correct level isthe nearest reference level smaller than the analog signal. This method offinding the digital values is called the binary search algorithm. The precisionis increased with one bit for every comparison.

2.1.3 Subranging Technique

In a high precision SA-ADC the resistance ladder would be very long. A16-bit ADC requires 216 = 65536 resistances. To avoid this the subrangingtechnique can be used [19, 41]. In a subranging SA-ADC two or more shorterresistance ladders are used in series. In an m + n subranging ADC the m

uSH

rk

±C

Figure 2.2 Comparator for SA-ADC. rk is a reference level fromthe resistance ladder and uSH is the signal from thesample-and-hold circuit. The output of the comparatoris a positive or negative constant depending on whichof the inputs that is largest.


0

1

2

3

4

u=1.5

0

1

2

3

4

u=1.5

1.5

2

−C

y=**

1.5

1

C

y=0* y=01

Figure 2.3 The binary search algorithm in a 2-bit ADC. The ref-erence levels are: 0, 1, 2, 3. The analog signal, u, is 1.5.u is first compared to level 2 and the MSB is set to 0.In the next step u is compared to 1 and the LSB is setto 1.

1

2

0

1

2

3

4

5

6

7

Figure 2.4 Subranging SA-ADC. The most significant bits arefound in the first ladder, the least significant bits arethen found in the second ladder.

most significant bits are found from the first resistance ladder and the nleast significant bits are found from the second resistance ladder. Usually,the full range of the second resistance ladder is longer than one step in thefirst ladder, see Figure 2.4. This overlap is used to correct dynamic errorsin the ADC. The result of a dynamic error is that an incorrect decisionis made in the first ladder. With the overlap of the second ladder, thiserror can be corrected since the signal still lies in the range of the second

2.2 Problem Formulation 29

ladder. This means that the output of the ADC is redundant and it is notpossible, from the digital output, to find the values from each subrangingstep. This is shown by the following example: Suppose the ADC consistsof two subranging steps, each with three bits. Denote the values from thesesteps a, b ∈ 0, · · · , 7. The digital output is formed as y = 3 · a + b. In thiscase a = 0, b = 4 gives the same y as a = 1, b = 1.

2.2 Problem Formulation

The previous section described how the A/D converter should work if allthe components were perfect. In a real A/D converter, there are errors inmany of the components. In this section, a description of how errors in theresistances affect the performance follows.

2.2.1 Resistance Errors

Assume first that all resistances in the resistance ladder are equal. Thetransfer function (here a static mapping) from the analog input signal, u(t),to the digital output signal, y(t), will then become a step function withequal length of all steps, see Figure 2.5. By applying an input signal withknown amplitude distribution, the amplitude distribution of y(t) can bestudied. Figure 2.5 shows the amplitude distribution of y(t) when u(t)

has a uniform amplitude distribution over the full range of the ADC. Inthis case y(t) has the same amplitude distribution as u(t). If there areerrors in the resistances, there will also be errors in the digital referencelevels. Figure 2.6 shows the transfer function of an A/D converter witha differential nonlinearity (reference level error) of up to 50%. If there isa long distance between reference levels rk and rk+1, there will be manysamples with the value k. Therefore the amplitude distribution of y(t) isnot the same as the amplitude distribution of u(t) in this case as shown inFigure 2.6. If the errors are known an equalizer can be constructed thatmaps y(t) to the correct reference values, see Figure 2.7. With the transferfunction of the ADC and the equalizer in series, the amplitude distributionof the corrected output, z(t), is the same as the amplitude distribution ofu(t), see Figure 2.8. The amplitude distribution of z(t) is here normalizedwith the width of each interval. This is the natural discretization of theamplitude distribution of u(t) when we have known reference levels. By


0 1 2 3 4 5 6 7 80

1

2

3

4

5

6

7

8Transfer function for ideal ADC

u(t)

y(t)

a. Mapping from analog input to dig-ital output. Dashed line indicatesthe ideal, non quantized, mapping.

0 1 2 3 4 5 6 70

0.02

0.04

0.06

0.08

0.1

0.12

0.14Amplitude distribution of y(t)

digital value

b. Amplitude distribution for the out-put signal when the input signal isuniformly distributed over the fullrange.

Figure 2.5 Characteristics for an ideal A/D converter.

0 1 2 3 4 5 6 7 80

1

2

3

4

5

6

7

8Transfer function for ADC with errors

u(t)

y(t)

a. Mapping from analog input to dig-ital output. Dashed line indicatesthe ideal, non quantized, mapping.

0 1 2 3 4 5 6 70

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2Amplitude distribution of y(t)

digital value

b. Amplitude distribution for the out-put signal when the input signal isuniformly distributed.

Figure 2.6 Characteristics for an A/D converter with static errorsin the resistance ladder.


ADC equalizeru(t) y(t) z(t)

Figure 2.7 A/D converter and equalizer.

0 1 2 3 4 5 6 7 80

1

2

3

4

5

6

7

8Transfer function for ADC and equalizer in series

u(t)

z(t)

a. Mapping from analog input to com-pensated digital output. Dashedline indicates the ideal, non quan-tized, mapping.

−1 0 1 2 3 4 5 6 7 80

0.02

0.04

0.06

0.08

0.1

0.12

0.14Amplitude distribution of z(t)

digital value

b. Amplitude distribution for thecompensated output signal whenthe input signal is uniformly dis-tributed.

Figure 2.8 Characteristics for an A/D converter followed by anequalizer.

amplitude distribution of z(t) we then mean

fZ(k) =number of samples at level k

rk+1− rk, k = 0, . . . , 2n− 1 (2.3)

Note:

• The actual reference levels cannot be changed.

• We can only adjust the digital levels to the reference levels that weactually have, so that we get a linear A/D converter.

The errors in the resistances are however usually unknown. Instead of look-ing at the errors in the resistances, the errors in the reference levels can


be studied. This is equivalent since the reference levels can be calculatedfrom the resistance values. If the voltage over the whole resistance ladderis Vladder = 2nV , the k’th reference level is

rk =

∑ki=1Ri∑2ni=1Ri

2nV (2.4)

where Ri is the ith resistance. It is more natural to look at the errors inthe reference levels since these levels give the digital signal values. Thefirst level, r0 = 0, is assumed to be correct since it is connected to ground.In an n-bit ADC there is therefore 2n − 1 unknown levels. Assume thatthe nominal distance between adjacent reference levels is 1. This is norestriction since any other distance can be rescaled to this distance. Theerror in the distance between reference levels rk−1 and rk is denoted θk, i.e.,θk = rk− rk−1− 1. The error parameters are collected in the error vectorΘ = [θ1θ2 . . . θ2n−1]

T. The ADC maps the analog signal onto a digital valueaccording to

y(t) = k if rk ≤ u(t) < rk+1, k = 0, . . . , 2n− 1 (2.5)

Here u(t) is assumed to be limited to the range of the ADC before theconversion, so that in an n-bit ADC 0 ≤ u(t) < 2n.

2.2.2 Subranging Mismatch

In a subranging ADC another kind of error is introduced besides the resis-tance errors described in the previous section. If a ladder in the subrangingstructure is longer or shorter than the expected length there will be match-ing errors between the subranging stages. Figure 2.9(a),(b) shows how errorsin the resistance values influence the amplitude distribution of the output.In Figure 2.9(c), two subranging stages are shown where the length of thesecond stage fits the length of one interval in the first stage. In Figure 2.9(d)we can see the amplitude distribution of the output when the input is uni-formly distributed, here it is correct since we have no resistance errors andno matching errors. In Figure 2.9(e), the interval in the first subrang-ing stage is too long. Therefore peaks occur in the amplitude distributionaround the transition between levels in the first stage, see Figure 2.9(f).These peaks are caused by the redundancy, since {a = 011, b = 001} and{a = 010, b = 111} give the same output value. In Figure 2.9(g) the intervalin the first stage is too short, causing dips in the amplitude distribution,Figure 2.9(h).


110101100011010001

111

000

011

010

Stage 1 Stage 2

y z

z

z

110101100011010001

111

000 110111

010001000

Code density,HM

Decimal CodeD

3⋅6+1=19:y=011,z=001

3⋅6+2=20:y=011,z=010

2⋅6+6=18:y=010,z=110

2⋅6+5=17:y=010,z=101

2⋅6+4=16:y=010,z=100

2⋅6+3=15:y=010,z=011

2⋅6+2=14:y=010,z=010

2⋅6+1=13:y=010,z=001

1⋅6+6=12:y=010,z=110

011

010

Stage 1 Stage 2

yz

z

z

110101100011010001

111

000110111

010001000

Err

or

Code density,HM

Decimal CodeD

2⋅6+7=19:y=010,z=1113⋅6+1=19:y=011,z=001

2⋅6+6=18:y=010,z=110

2⋅6+5=17:y=010,z=101

2⋅6+4=16:y=010,z=100

2⋅6+3=15:y=010,z=011

2⋅6+2=14:y=010,z=010

2⋅6+1=13:y=010,z=0011⋅6+7=13:y=010,z=111

3⋅6+2=20:y=011,z=010

1⋅6+6=12:y=010,z=110

011

010

Stage 1 Stage 2

yz

z

z

110101100011010001

111

000

011010001000E

rror

Code density,HM

Decimal CodeD

3⋅6+2=20:y=011,z=010

3⋅6+3=21:y=011,z=011

2⋅6+6=18:y=010,z=1102⋅6+5=17:y=010,z=1012⋅6+4=16:y=010,z=100

2⋅6+3=15:y=010,z=011

2⋅6+2=14:y=010,z=010

2⋅6+1=13:y=010,z=0011⋅6+6=12:y=010,z=110110

101

111

3⋅6+1=19:y=011,z=001

1⋅6+5=11:y=010,z=101

(c) (d)

(f)(e)

(g) (h)

Single stage

D (binary code)

Code density,HM

Decimal CodeD

(a) (b)

654321

7

0

Figure 2.9 Mismatch in a subranging ADC. Resistance errors (a)causes errors in the amplitude distribution (b). Sub-ranging with perfect matching (c) gives a correct am-plitude distribution (d). Mismatch between subrangingstages (e) and (g) gives peaks and dips in the amplitudedistribution (f) and (h).


Implementation independent parameterization

Here the subranging structure is not taken into account. The ADC is seenas one ladder where the distance between some of the levels might be zero orvery long, corresponding to the mismatch errors in the subranging structure.With this parameterization, the levels in the second stage will have manyerror parameters, one for each level in the first ladder. These parameterscan also take on different values despite that they have the same value bythe physical implementation. The parameterization will be the same as inthe previous section except that there will not necessarily be 2n levels, sincethere is some overlap between the first and the second ladder. We have thenthe parameter vector Θ = [θ1 . . . θm]T, where m + 1 is the total number ofnominal levels.

2.3 Equalization with known Input Distribution

In this section a method for estimating and correcting errors in the referencelevels is described. Parts of these results have been presented previouslyin [21]. Estimation methods based on histograms of the output signal andknown amplitude distribution of the input signal have been used earlier.In for example [27, 15] a known training signal is used. In [28, 14] anadditional A/D converter with very high accuracy is used to estimate thetrue amplitude distribution.

2.3.1 Assumptions and Notation

The analog input signal is denoted u(t) and the digital output signal isdenoted y(t). The corrected digital signal is denoted z(t). The amplitudedistribution of u(t) is denoted fU(u) and the amplitude distribution of y(t)is denoted fY(y). The measured amplitude distribution is an estimate offY(y) and is denoted fY(y). The amplitude distribution of the correctedsignal, z(t), depends on the parameter vector Θ = [θ1, . . . , θ2n−1] and is de-noted fZ(z,Θ). θk denotes the deviation from the nominal distance betweenadjacent levels, i.e., θk = rk− rk−1 − 1. Θ∗ denotes the true error param-eters. We assume that the reference level errors are the only errors in theA/D converter. We also assume that these errors change much more slowlythan the sample time. This is a reasonable assumption since the sample rateusually is in the order of MHz and the temperature, for example, is quiteconstant during at least some seconds. The normal input signal should beused for the identification, i.e., no special calibration signal is available. y(t)

2.3 Equalization with known Input Distribution 35

is the only measurable signal. This means that the estimation method mustbe blind. We make no temporal assumption about u(t), i.e., its spectralcontent can be anything. The only assumption that we make on u(t) isthat its amplitude distribution, fU(u), is known.

2.3.2 Estimation Method

The basic idea is to find a parameter vector Θ that gives the same theoreticalamplitude distribution as the measured amplitude distribution, i.e., to finda mapping y→ z = g(y, Θ) such that fZ(z, Θ) = fY(y).

The measured amplitude distribution, fY(y), is found by counting thenumber of samples at each reference level, rk, i.e., by making a histogramof y(t). This means that in an n-bit ADC, fY(y) can be calculated in 2n

points, y = 0, . . . , 2n−1. Since fY(y) should be interpreted as a distributionfunction it is normalized so that

2n−1∑y=0

fY(y) = 1 (2.6)

fU(u) is a continuous function that is defined in the range 0 ≤ u(t) <

2n. fZ(z, Θ) is calculated in 2n discrete, but in general non-uniformly dis-tributed, points. fZ(rk, Θ) is the expected normalized number of samples inthe range [rk, rk+1)

fZ(rk, Θ) =

∫rk+1

rk

fU(u)du, k = 0, . . . , 2n− 1 (2.7)

To find the correct error parameters we should find a loss function, V(Θ),that has its global minimum at Θ = Θ∗ when the number of data tends toinfinity. It is usually not possible to find the minimizing argument analyt-ically. Instead a numerical minimization method should be applied. Themost commonly used minimization method is the steepest-descent method(sd) [8, 13].

Θ0 = 0

Θk+1 = Θk− µ∇V(Θ) (2.8)

∇V(Θ) is the gradient of V(Θ) and it can be calculated either analyticallyor, if it is more convenient, as a finite difference approximation.

(∇V(Θ))i ≈V(Θ+ εei) − V(Θ)

ε(2.9)


(∇V(Θ))i is here the ith component of the gradient and ei denotes a basisvector, which is zero except in the ith position where it is one. µ is thestep length of the steepest descent algorithm. Since Θ is updated in thenegative gradient direction, the loss function is guaranteed to decrease if µis small enough. If µ is chosen too small, the convergence will be very slow.If instead µ is chosen too large, the loss function may not converge. Toavoid this trade-off, a variable µ can be chosen instead [13]. µ is initiatedwith a large enough value, µ0, then µ is decreased until V(Θ) decreases.With this modification the stability of a small µ can be combined with thefast convergence of a large µ. Another problem is how to chose µ0. Wedo not know anything about the magnitude of ∇V(Θ), but we know thatno component of Θ should ever be changed more than 1 since that is thenominal distance to the next reference level. If the gradient is normalizedwith its largest value and µ0 = 1 is used we know that the largest changein Θ is at most 1 [13].

Θ0 = 0

Θk+1 = Θk− µ∇V(Θk)

max∇V(Θk)(2.10)

The step size, µ, is in each iteration decreased until the loss function de-creases, i.e., until V(Θk+1) < V(Θk). There are other minimization meth-ods that converge in fewer iterations, e.g., Newtons method or the Gauss-Newton method. These methods are not used in this application for tworeasons:

• The estimation algorithm should be implemented in hardware. TheNewton method and the Gauss-Newton method involves a Hessian ora Hessian approximation that should be inverted. Matrix inversionsare very difficult to implement in hardware.

• A lot of memory would be required to store the hessian. In, for ex-ample, a 14-bit ADC the Hessian is a 16384 × 16384 matrix.

2.3.3 Criterion Functions

Four different loss functions are evaluated here: the mean squared error, thenormalized mean squared error, the mean absolute error and the normalizedmean absolute error. The estimation algorithm is simulated in Section 2.5with these four loss functions to find out which one that works best.


Mean squared error

The mean squared error is here denoted VMSE(Θ)

VMSE(Θ) =

2n−1∑k=0

(fY(k) − fZ(rk, Θ))2 (2.11)

Some advantages of this loss function are:

• It is easy to differentiate.

• Larger weight is given to the parts of the distribution function thatare large. These parts are used more often and are therefore moreimportant to correct. Also the values in these parts are more reliablesince more samples are taken in these parts.

Some disadvantages are:

• Errors in the parts of the distribution function that has relatively lowexcitation will not give much contribution to the loss function even ifthe errors are quite large.

Normalized mean squared error

The normalized mean squared error loss function is denoted VNMSE(Θ).

VNMSE(Θ) =

2n−1∑k=0

(Qk− 1)2 (2.12)

Qk =

{1 if fY(k) = 0fY (k)

fZ(rk,Θ)otherwise

(2.13)

If there are no samples at some level rk, the corresponding term in VNMSEshould not contribute to the error. Therefore Qk = 1 when fY(k) = 0.Otherwise the minimization would drive the intervals that are not excited tozero. One advantage with this loss function compared to VMSE is that errorsin the parts of the ADC that do not have high excitation also contributesignificantly to the loss function. A disadvantage with this is however thatthese parts of fY(k) are less reliable due to poor excitation.


Mean absolute error

The mean absolute error loss function is denoted VMAE(Θ).

VMAE(Θ) =

2n−1∑k=0

|fY(k) − fZ(rk, Θ)| (2.14)

The advantage of this loss function compared to VMSE and VNMSE is thateven small errors give relatively large contribution to the loss function.

Normalized mean absolute error

The normalized mean absolute error loss function is denoted VNMAE.

VNMAE(Θ) =

2n−1∑k=0

|Qk− 1| (2.15)

where

Qk =

{1 if fY(k) = 0fY (k)

fZ(rk,Θ)otherwise

(2.16)

This normalization is done for the same reason as the normalization ofVMSE(Θ).

Convergence

All these loss functions have the global minimum, V(Θ) = 0, at Θ = Θ∗

when the data length tends to infinity. The difference lies in the convergencerate of the numerical algorithm and if there are local minima in the lossfunctions. The minimization algorithm is not guaranteed to converge tothe global minimum if there are local minima. Figure 2.10 shows contourplots of the four different loss functions listed above with Gaussian inputdistribution. In these plots we have an A/D converter with two unknownreference levels. With more reference levels it would be hard to visualize theresult. The global minimum in these plots is in the origin. The loss functionsare plotted for θ1, θ2 varying from −1 to 1. This is the interesting range sincevalues outside this range are impossible by the physical implementation. Aθi < −1 would imply that rk < rk−1, which is impossible since that wouldrequire a negative resistance in the resistance ladder. In these plots thereare no local minima for any of the loss functions. Outside the range of theseplots there are however local minima. The risk of getting stuck at a local


−1 −0.5 0 0.5 1−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

θ1

θ2

a. VMSE(Θ)

−1 −0.5 0 0.5 1−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

θ1

θ2

b. VNMSE(Θ)

−1 −0.5 0 0.5 1−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

θ1

θ2

c. VMAE(Θ)

−1 −0.5 0 0.5 1−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

θ1

θ2

d. VNMAE(Θ)

Figure 2.10 Contour plots of different loss functions, generatedwith a Gaussian input signal. The global minimumis in the origin and is marked with *.


minimum is, however, quite small if the search is initiated close enough tothe global minimum. This does not say that there are no local minimacloser to the global minimum if there are more reference levels than threeor if the amplitude distribution is different, but hopefully the structure isquite similar. The simulations in Section 2.5 also show that the algorithmusually converges to the global minimum.

2.3.4 Amount of Data

Even if the numerical algorithm converges to the global minimum it is notnecessarily the correct error vector, Θ = Θ∗, since we only have finite num-ber of data. We will in this section investigate how much data that isrequired to get a good enough estimate of the amplitude distribution.

Deviation from expected amplitude distribution

In an n-bit ADC, y(t) can take on 2n different values, y(t) ∈ [0, 1, . . . , 2n−

1]. With known error parameters, Θ∗, and known input distribution, fU(u),we can calculate the probability, pk(Θ∗), of each digital value, k.

pk(Θ∗) =

∫k+1+∑k+1i=1 θ

∗i

k+∑ki=1 θ

∗i

fU(u)du, k = 0, . . . , 2n− 1 (2.17)

Assume that we collect N samples of y(t). The prior distribution is thesame for each sample we take. This means that we pick samples withreplacement from the distribution fY(k). Denote with Xk the number ofsamples that have the value k. The stochastic vector, fX(X0, . . . , X2n−1),obeys the multinomial distribution, that is a multivariable extension of thebinomial distribution [7, 31].

fX(x) =N!

x0! · · · x2n−1!px00 · · ·p

x2n−1

2n−1 (2.18)

2n−1∑k=0

xk = N

Here we have omitted the argument Θ∗ in pk(Θ∗) for simplicity. With thisdistribution function we can calculate the expected deviation of measuredamplitude distribution from the theoretical amplitude distribution. Themarginal distributions of the multinomial distribution are binomial distribu-tions. To understand this we can study the case where we are only interested


in the number of samples at level k. Then we have two possible outcomesof a sample, either it is at level k or not at level k, and pk is the proba-bility that it is at level k. This is a binomial distribution, Xk ∈ Bi(N,pk).The expected number of samples at each level can be calculated from thebinomial distribution

E(Xk) = Npk, k = 0, . . . , 2n− 1 (2.19)

Define the mean square relative deviation from the expected value as

D = 2−n

2n−1∑k=0

(Xk−Npk)2

(Npk)2

(2.20)

This is a stochastic variable, and the expected value of D is a measure ofhow good the approximation of the amplitude distribution is. To calculateE(D), we need the variance of Xk [7].

Var(Xk) = Npk(1− pk), k = 0, . . . , 2n− 1 (2.21)

From this variance we can calculate the expected mean square deviation

E(D) = E(2−n

2n−1∑k=0

(Xk−Npk)2

(Npk)2

) = 2−n

2n−1∑k=0

E[(Xk−Npk)2]

(Npk)2

= 2−n

2n−1∑k=0

Var(Xk)

(Npk)2

= 2−n

2n−1∑k=0

1− pk

Npk(2.22)

E(D) is a measure of how how close the measured histogram is to the trueamplitude distribution. What we are interested in is how close the minimiz-ing error vector Θ0 is to the true error vector Θ∗ on average, i.e., we want toknow E(2−n

∑2n−1k=0 (θ0k− θ∗k)

2). E(D) is however a good measure of this er-ror, that is E(2−n

∑2n−1k=0 (θ0k− θ∗k)

2) ≈ E(D) if the amplitude distribution isapproximately locally constant. If the input signal is uniformly distributedwe have from (2.17) that pk = 2−n(1+ θ∗k+1). If θk is small this gives that

E(2−n

2n−1∑k=0

(θ0k− θ∗k)2) = E(2−n

2n−1∑k=0

(2nXk/N− 2npk)2) = E(D) (2.23)

This is approximately true even if the amplitude distribution is not uniformas long as it does not change abruptly. Figure 2.11 shows a plot of

√E(D)

for different values of N and different number of bits in the ADC. In this


101

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1010

10−5

10−4

10−3

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100

101

102

103

104

Expected deviation from theoretical amplitude distribution

Number of samples

Exp

ecte

d de

viat

ion

n=2 n=4 n=8 n=14

Figure 2.11 Relative mean square error of the measured amplitudedistribution, with Gaussian input distribution. n ishere the number of bits in the A/D converter.

plot we have assumed an input signal with Gaussian amplitude distributionwith the mean, µ, in the center of the ADC and the standard deviation, σ,chosen such that ±5σ coincides with the edges of the ADC. Here it seemslike the error is quite large even with very much data. This large mean erroris caused by large errors near the edges of the ADC where the excitationis low. If we look at the mean square error for the levels in the middle ofthe ADC, which are the most important ones, the situation is much better,see Figure 2.12. If u(t) has a uniform or sinusoidal distribution, the error issmaller since there are no levels with such low excitation, see Figures 2.13and 2.14 respectively. From these plots we can see that a lot of data areneeded to achieve good precision, especially for A/D converters with manyreference levels. The accuracy increases also quite slowly with the amountof data. To increase the accuracy a factor of 10 we need about 100 timesmore data. This is quite constant, independent of the distribution. TheseA/D converters are, however, supposed to be used for very high sample


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101


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Exp

ecte

d de

viat

ion

n=2 n=4 n=8 n=14

Figure 2.12 Relative mean square error of the measured amplitudedistribution, with Gaussian input distribution. Themean value for the centermost levels, correspondingto 1.25σ, are shown here. n is the number of bits inthe A/D converter.

rates (some MHz) so some million samples are collected in a few seconds.

2.3.5 Parameter Update

The estimation algorithm should update the parameters continuously whenthe A/D converter is used, to adapt to changes in the parameters due tofor instance temperature changes. The most obvious way to update theparameters would be to collect a batch of data, make an estimation basedon this data and replace the previous estimate with the estimate from thelatest batch of data.

As we saw in the previous section, a lot of data is required to get agood estimate of the amplitude distribution. Usually, we cannot collectenough data to get good excitation near the edges of the ADC. Therefore,there is a risk that Θ will adjust to the actual dataset instead of the correct


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Number of samples

Exp

ecte

d de

viat

ion

n=2 n=4 n=8 n=14

Figure 2.13 Relative mean square error of the measured amplitudedistribution, with uniform input distribution. n is thenumber of bits in the A/D converter.

amplitude distribution, i.e., there might be an overfit to data. To avoidthis, Θ can be updated recursively with a forgetting factor, λ [29, 67]. If wehave an estimate Θk after estimation from k batches of data and we makean estimate Θ0k+1 from batch number k + 1, the estimate after k + 1 datasets is

Θk+1 = λΘk+ (1− λ)Θ0k+1 (2.24)0 < λ ≤ 1

This means that Θ will be a weighted mean of the estimates from severalbatches of data. λ should usually be chosen close to, but not equal to, 1.This means that older estimates are slowly “forgotten” and the algorithmcan adapt to changes in the reference levels. With this recursion we alsoavoid the case where a batch of data deviating from the assumed amplitudedistribution could destroy the estimate.


101

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Number of samples

Exp

ecte

d de

viat

ion

n=2 n=4 n=8 n=14

Figure 2.14 Relative mean square error of the measured amplitudedistribution, with sinusoid input distribution. n is thenumber of bits in the A/D converter.

2.3.6 Initial Value Estimation

If the input signal is uniformly distributed, the probability of getting asample with value k is:

P(y = k) =

∫rk+1

rk

2−ndu = 2−n(rk+1− rk) = 2−n(1+ θk) (2.25)

This means that Θ in this case can be calculated analytically from themeasured amplitude distribution, fY(y).

θk =

{fY(k)2

n− 1 if fY(k) 6= 0

0 if fY(k) = 0(2.26)

This only holds if the input signal is uniformly distributed, but with asmooth input signal distribution the amplitude distribution can be assumedto be approximately constant locally. This means that we can calculated


P(y = k) approximately

P(y = k) =

∫rk+1

rk

fU(u)du ≈ fU(k)(rk+1− rk) = fU(k)(1+ θk) (2.27)

From this we can get a good initial guess

θk =

{fY(k)/fU(k) − 1 if fY(k) 6= 0

0 if fY(k) = 0(2.28)

and by that reduce the number of iterations.

2.3.7 Reference Level Estimation Algorithm

The reference level estimation method is summarized in Algorithm 2.1. Notethat two different iteration indices are used in this algorithm:

• k denotes the iteration number of the minimization algorithm.

• l denotes the number of the batch of data.

Algorithm 2.1 (Reference level estimation with known amplitudedistribution)

Initialization

•Choose the number of data, N, for each amplitude distribution esti-mate.

•Choose a stopping criterion for the minimization algorithm.

•Choose the forgetting factor, λ, for the recursive update.

•The amplitude distribution, fU(u), of u(t) is assumed known.

•Calculate the initial theoretical amplitude distribution, fZ(z, 0).

•Calculate the initial loss function, V(0).

•Initialize the steepest descent update step, µ = 1.

Data collection and amplitude distribution estimate

•Collect N samples from the A/D converter.

•Calculate fYl(y) by counting the number of samples at each level.

•Normalize fYl(y), f0Yl

(y) =fYl (y)∑2n−1

y=0 fYl (y)=fY (y)

N

•Initialize the error vector: θk =

{fY(k)/fU(k) − 1 if fY(k) 6= 0

0 if fY(k) = 0

2.4 Equalization with Unknown Input Distribution 47

Update parameter estimate

1.Calculate the gradient, ∇V(Θk), either analytically or by finite differ-ences.

2.Normalize the gradient, ∇0V(Θk) =∇V(Θk)

max |∇V(Θk)|

3.Update the parameter estimate, Θk+1 = Θk− µ∇0V(Θk).

4.Calculate new loss function, V(Θk+1).

5.If V(Θk+1) > V(Θk) decrease step size, µ = µ/2, and repeat from step3, otherwise continue.

6.Increase the iteration index, k, by one and repeat steps 1− 6 until thestopping criterion is reached. In an on-chip implementation with real-time demands the natural choice here is a fixed number of iterations.

7.Denote the final value of Θ by Θ0l

8.Update Θ with new estimate, Θl = λΘl−1+ (1− λ)Θ0l

New data are collected continuously while the A/D converter is used, andthe estimation steps restart with a new batch of data every time a newestimate is finished.

2.4 Equalization with Unknown Input Distribu-

tion

Usually we have no exact knowledge of the amplitude distribution of theinput signal. If the amplitude distribution of the input signal is smooth, theestimation algorithm can however be used. This section is based on [22].

2.4.1 Assumptions

Since the amplitude distribution of the input signal is unknown, we have toestimate it first from output data. For this estimation we have to assumethat the amplitude distribution of the input signal is smooth. Note:

• We make no temporal assumption on the input signal. That is, itsspectral content can be anything.

• We only use a smoothness assumption on the signal’s amplitude dis-tribution fU(u).


2.4.2 Estimation Overview

The parameter estimation is divided into two steps:

• The amplitude distribution of the measured signal, fY(y), is com-puted as an approximation of the real amplitude distribution, fY(y),of y(t). From the smoothness assumption of the amplitude distri-bution, we can approximate fU(u) by a smoothed version of fY(y),fY(y)→ fU(u).

• Next: find a mapping y → z = g(y,Θ) such that fZ(z,Θ) ≈ fY(y),where fZ(z, 0) = fU(u).

2.4.3 Amplitude Distribution Estimation

The errors in the reference levels are assumed to be random. This meansthat we can use the model

fY(k) = fU(k) + e(k) (2.29)

where e(k) is a random signal. With the assumption that fU(u) is smooth wecan conclude that fU(u) is bandlimited to a low pass band. In Figure 2.15the DFT of a true Gaussian histogram and a histogram measured by annonideal A/D converter are shown. Note that these are the DFTs of theamplitude distribution curves and do not have anything to do with thespectral content of the signals, u(t) and y(t). We can see that the DFT ofthe ideal Gaussian histogram is confined to a narrow low pass band whilethe DFT of the measured histogram is spread over the whole frequencyrange. This means that we can estimate fU(u) from the measured amplitudedistribution fY(y) by low pass filtering fY(y). A zero phase filter must beused to avoid phase errors in the estimated amplitude distribution, i.e., thatthe estimated amplitude distribution is moved towards higher levels. Thiscan be achieved by forward-backward filtering of an ordinary low pass filter,H(q) [29].

fU(k) = H(q)H(q−1)fY(k) (2.30)

The estimate fU(k) can only be calculated for 2n discrete levels and shouldbe an estimate of the mean value of fU(u) between two reference levels,normalized with the distance between the levels, rk+1− rk.

fU(k) ≈∫rk+1

rkfU(x)dx

rk+1− rk(2.31)


0 0.2 0.4 0.6 0.8 110

−7

10−6

10−5

10−4

10−3

10−2

10−1

100


Figure 2.15 DFT of an ideal Gaussian histogram (dashed) andDFT of a Gaussian histogram measured by a non idealA/D converter (solid).

Since some of the useful parts of fY(y) are also attenuated by the low passfilter, fU(u) will not converge exactly to the true amplitude distributioneven with infinite amount of data. How large this bias is depends on theproperties of the amplitude distribution. The bias will be smaller the moreconfined the amplitude distribution is to a low pass band. The cut-offfrequency, fc, of the low pass filter is a tuning parameter and it must bechosen for each application. This gives the estimate of fZ(rk, 0) = fU(k).fZ(rk, Θ) can be approximately calculated by interpolation between adjacentvalues of fU(k).

fZ(rk, Θ) ≈ fU(k) +fU(k+ 1) + fU(k)

2

k∑i=1

θi

−fU(k) + fU(k− 1)

2

k−1∑i=1

θi (2.32)


2.4.4 Parameter Estimation

The parameters are estimated by minimization of a function that has itsglobal minimum at the true parameter value Θ∗. The minimization is inprinciple the same as for the case with known histogram, but a few remarksshould be made:

• The estimated amplitude distribution, fU(u), has rather low accuracywhere the excitation is low, that does not improve much with moredata. Therefore we do not want the errors in these parts to contributetoo much to the loss function. This means that the normalized lossfunctions, VNMSE(Θ) and VNMAE(Θ), are probably not very useful,since all levels give the same contribution to the loss function here.

• We cannot guarantee that the loss function has its global minimumat the true parameter vector, since the amplitude estimate is biased.

The derivatives of fZ(rk, Θ) can in this case be calculated analytically fora general signal distribution, since parameter dependence in fZ(rk, Θ) isexplicit.

∂fZ(rk, Θ)

∂θm=

fU(k+1)−fU(k−1)

2if m < k

fU(k+1)+fU(k)

2if m = k

0 if m > k

(2.33)

If the mean square error loss function is used, its gradient is linear in theparameters.

(∇VMSE(Θ))m = −2

2n∑k=1

(fY(k) − fZ(rk, Θ))∂fZ(rk, Θ)

∂θm(2.34)

This means that the parameter estimate could be calculated analytically.For implementation reasons this is, however, not a good way to solve theproblem.

• An exact solution requires a matrix inversion, which is difficult toimplement in hardware.

• Even if a signal processor is available, storing the matrix would requiretoo much memory. Already a 10-bit ADC would give a 1024 × 1024matrix.

Because of this the steepest descent method is used for minimization as forthe case with known amplitude distribution.


2.4.5 Estimation Algorithm

The reference level estimation method for signals with unknown amplitudedistribution is summarized in Algorithm 2.2. Note that two different itera-tion indices are used in this algorithm:

• k denotes the iteration number of the minimization algorithm.

• l denotes the number of the batch of data.

Algorithm 2.2 (Reference level estimation with unknown inputsignal amplitude distribution)

Initialization

•Choose the number of data, N, for each amplitude distribution esti-mate.

•Choose a stopping criterion for the minimization algorithm.

•Choose the forgetting factor, λ, for the recursive update.

•Initialize the steepest descent update step, µ = 1.

•Choose the cut-off frequency, fc, for the low pass filter.

•Choose the type of low pass filter and the filter order.

Data collection and amplitude distribution estimate

•Collect N samples from the A/D converter.

•Calculate fYl(k) by counting the number of samples at each level.

•Normalize fYl(k), f0Yl

(k) =fYl (k)∑2n−1

y=0 fYl (k)=fY (k)

N

•Estimate the amplitude distribution of the input signal by low passfiltering fYl(k):fUl(k) = H(q)H(q−1)fYl(k)

fZl(rk, 0) = fUl(k)

•Calculate the initial loss function:VMSE(0) =

∑2n−1k=0 (fYl (k) − fZ(rk, 0))

2

•Initialize error vector, θk = fY/fU(k) − 1, k = 0, . . . , 2n− 1.

Update parameter estimate

1.Calculate the gradient, ∇VMSE(Θk):(∇VMSE(Θ))m = −2

∑2nk=1(fY(k) − fZ(rk, Θ))

δfZ(rk,Θ)

δθm


δfZ(rk,Θ)

δθm=

fU(k+1)−fU(k−1)

2if m < k

fU(k+1)+fU(k)

2if m = k

0 if m > k

2.Normalize the gradient, ∇0VMSE(Θk) =∇VMSE(Θk)

max |∇VMSE(Θk)|

3.Update the parameter estimate, Θk+1 = Θk− µ∇0VMSE(Θk).4.Calculate new loss function, VMSE(Θk+1).

5.If VMSE(Θk+1) > VMSE(Θk) decrease step size, µ = µ/2, and repeatfrom step 3, otherwise continue.

6.Increase the iteration index, k, by one and repeat steps 1 − 6 untila stopping criterion reached. When we have real time demands, themost natural choice here is a fixed number of iterations.

7.Denote the final value of Θ by Θ0l

8.Update Θ with new estimate, Θl = λΘl−1+ (1− λ)Θ0l

New data are collected continuously while the A/D converter is used, andthe estimation steps restarts with a new batch of data every time the pre-vious estimate is finished.

2.5 Simulations

In this section an A/D converter is simulated to show the performance of thecorrection algorithm. Only the static reference level errors are consideredin the simulations. Other errors may influence the performance in a realA/D converter. Measurements from a real A/D converter are studied inSection 2.6.

2.5.1 Known Amplitude Distribution

The algorithm for estimation with known input amplitude distribution ishere evaluated on simulated data. Here the A/D converter is simulated withthree different input signals:

• Gaussian input u(t) ∈ N(µ, σ). The mean value, µ, is chosen to themean value full range of the A/D converter. The standard deviation,σ, is chosen such that ±5σ coincides with the full range of the ADC.

• Sinusoidal input u(t) = A sin(ωt) +C. The offset, C, is chosen to themean value of the A/D converter range. The amplitude, A, is chosensuch that the sinusoid fits into the A/D converter full range.

2.5 Simulations 53

• Uniform input u(t) ∈ U(0, 2n). The input is uniformly distributedover the full range of the A/D converter.

Two cases will be studied:

• ADC without subranging where the parameter errors are randomlygenerated from a uniform distribution, θi ∈ U(−0.1, 0.1), i.e., theerrors are at most 10% of the nominal interval.

• Subranging ADC: A three-stage subranging ADC with 4, 4, 5 bits inthe respective stages is simulated. Mismatch errors are introduced inboth stages.

Some simulations concerning convergence and choice of criterion functionare shown only for the Gaussian case, the results are quite similar for theother signal types.

Amount of data and convergence

Here a Gaussian input signal is used in all the simulations.The A/D converter is first simulated without errors for different amount

of data and different number of levels in the A/D converter. From thesesimulations the amplitude distribution, fY(y), is calculated and comparedto the theoretical distribution fY(y). The root mean square error,

√D =

√√√√2−n

2n−1∑y=0

(fY(y) − fY(y)

fY(y))2 (2.35)

is shown in Figure 2.16. The dashed line shows the mean square error inthe 2n/8 most centered levels, which is the most important part of theamplitude distribution function since the excitation is very low near theedges in this case. This plot should be compared to the theoretical expectedmean square errors in Section 2.3.4. We can see that the plot in Figure 2.16shows rather good resemblance with Figure 2.11 and Figure 2.12. 10Monte-Carlo simulations of an 8-bit ADC have been done to generate these plots.

In Figure 2.17 the RMSE of the parameter estimate is shown for differentamount of data. The four different loss functions are compared for a fixednumber of iterations (1000). This is relevant for the implementation aspectsince there is a limited amount of time available for the calculations if thealgorithm should work in real-time. An 8-bit ADC without subranging hasbeen used in these simulations. Figure 2.17a shows the RMSE for all levels


101

102

103

104

105

106

107

108

10−4

10−3

10−2

10−1

100

101

Number of data

Mea

n er

ror

Figure 2.16 Relative mean squared error of the measured ampli-tude distribution. Solid line shows the error for thewhole ADC, dashed line shows the error for the levelsin the middle.

in the ADC while Figure 2.17b shows the RMSE for the 2n/8 centermostlevels. These plots show, as expected, that a lot of data is needed to geta good result with the normalized criterion functions, VNMSE and VNMAE.The other two criterion functions, VMSE and VMAE, show quite similarperformance. With the mean square error criterion function it is easier tocalculate the gradient analytically. Since the performance is quite similarwe hereinafter use VMSE for minimization.

Figure 2.18 shows the convergence of the minimization algorithm. An8-bit ADC without subranging has been simulated. In this plot we can seethat the criterion function decreases with approximately a factor of 10 whenthe number of iterations is increased 100 times.

2.5 Simulations 55

101

102

103

104

105

106

107

10−2

10−1

100

101

Number of data

Mea

n er

ror

of e

stim

ate

a. The whole range of levels

101

102

103

104

105

106

107

10−3

10−2

10−1

100

101

Number of data

Mea

n er

ror

of e

stim

ate

b. The centermost levels

Figure 2.17 RMSE of parameter estimate for different criterionfunctions. VMSE (solid), VNMSE (dashed), VMAE (*),VNMAE (o).


100

101

102

103

104

10−11

10−10

10−9

10−8

10−7

10−6

10−5

10−4

Iteration number

Crit

erio

n fu

nctio

n

Figure 2.18 Convergence as a function of the number of iterations.Dashed line shows the criterion function with initial-ization Θ = 0. Solid line shows the criterion functionwith initialization Θ = fY/fU− 1.

Performance with Gaussian input signal

The histogram is here calculated from 108 samples from a Gaussian distri-bution. The estimate has been calculated by initialization and 100 itera-tions. The errors has been randomly generated in the interval [−0.1, 0.1].Figure 2.19a shows the theoretical Gaussian distribution. In Figure 2.19bthe measured amplitude distribution is shown and in Figure 2.19c the mea-sured amplitude distribution compensated with the estimated parametersis shown. We can see from these plots that the compensation works well, atleast in the parts of the ADC where the excitation is high. In Figure 2.20athe original errors, Θ0, are shown and Figure 2.20b shows the estimationerrors, Θ0− Θ. These plots show that there is still too little data to get agood estimate near the edges of the ADC. In the middle of the ADC theimprovement is however very good. The levels in the middle are also themost important ones to correct, since most of the samples are in that range.

2.5 Simulations 57

0 50 100 150 200 250 3000

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

Level number

Am

plitu

de d

ensi

ty

a. Theoretical Gaussian distribution.

0 50 100 150 200 250 3000

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

Level number

Am

plitu

de d

ensi

ty

b. Measured amplitude distribution.

0 50 100 150 200 250 3000

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

Level number

Am

plitu

de d

ensi

ty

c. Compensated measured amplitudedistribution.

0 50 100 150 200 250 3000

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

Level number

Am

plitu

de d

ensi

ty

d. Theoretical (solid), measured(dashdotted) and compensated(dotted) amplitude distribution.

Figure 2.19 Amplitude distribution functions, Gaussian input sig-nal.


0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude

a. Error before estimation, Θ∗.

0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude

b. Error after estimation, Θ − Θ∗.

Figure 2.20 Error vector before and after estimation with Gaussianinput.

2.5 Simulations 59

To avoid that the improvement in signal quality is destroyed by bad esti-mates in the parts where the excitation is low, the parameters can be fixedto zero where the excitation is lower than some limit.

Two important measures of the signal quality in communication systemsare the Signal to Noise and Distortion Ratio (SNDR) and the SpuriousFree Dynamic Range (SFDR), see Chapter 1 for definitions. Sinusoidalsignals with different amplitudes have been generated and converted in asimulated A/D converter with the error Θ∗. The SNDR and SFDR havebeen calculated before and after correction both with the true errors, Θ∗,and with the estimated errors, Θ. Correction with the true errors gives thetheoretical lower bound of how much the signal quality can be improved.Figure 2.21a shows the SNDR before and after correction with Θ∗ and Θrespectively. In Figure 2.21b the SFDR is shown. The peak improvementis about 4dB for SNDR and 18dB for SFDR. Near the edges of the ADC,the number of samples in each interval is quite low, between 1 and 10. Thisis hard to see from the histogram in Figure 2.19b, but can be seen if it iszoomed in. The deterioration in performance near the edges of the ADC iscaused by the low excitation from the estimation data.

Performance with sinusoidal input

For a sinusoidal signal the amplitude distribution looks like a bathtub. Fig-ure 2.22 shows the theoretical, measured and compensated histogram. Be-cause of the bathtub shape with high peaks near the edges the histogramis very sensitive to amplitude changes in the input signal. Therefore theaccuracy near the edges might not be very good with real (not simulated)signals. In the middle of the ADC the histogram is, however, quite con-stant, so these parameters should be possible to calculate quite accurately.Figure 2.23 shows the errors before and after correction with sinusoidal in-put. The improvement after estimation is here very good, even near theedges. This is also seen in the plots of SNDR and SFDR before and aftercorrection, Figure 2.24. The improvement is here close to the theoreticallimit for both SNDR and SFDR for the whole range of the ADC. The peakimprovement is 4dB for SNDR and 18dB for SFDR.


−14 −12 −10 −8 −6 −4 −2 025

30

35

40

45

50

55

Signal power [dBFS]

SN

DR

[dB

]

a. SNDR

−14 −12 −10 −8 −6 −4 −2 035

40

45

50

55

60

65

70

Signal power [dBFS]

SF

DR

[dB

]

b. SFDR

Figure 2.21 Solid line shows the signal quality before correction,dashed line after correction with Θ and dotted lineafter correction with Θ∗. The estimation is here donewith Gaussian input signal.

2.5 Simulations 61

0 50 100 150 200 250 3000

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

Level number

Am

plitu

de d

ensi

ty

a. Theoretical Sinusoidal distribu-tion.

0 50 100 150 200 250 3000

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

Level number

Am

plitu

de d

ensi

ty

b. Measured amplitude distribution.

0 50 100 150 200 250 3000

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

Level number

Am

plitu

de d

ensi

ty

c. Compensated measured amplitudedistribution.

0 50 100 150 200 250 3000

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

Level number

Am

plitu

de d

ensi

ty

d. Theoretical (solid), measured(dashdotted) and compensated(dotted) amplitude distribution.

Figure 2.22 Amplitude distribution functions, Sinusoidal inputsignal.


0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude


0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude


Figure 2.23 Error vector before and after estimation with Sinu-soidal input.

2.5 Simulations 63

−14 −12 −10 −8 −6 −4 −2 025

30

35

40

45

50

55

Signal power [dBFS]

SN

DR

[dB

]

a. SNDR

−14 −12 −10 −8 −6 −4 −2 035

40

45

50

55

60

65

70

Signal power [dBFS]

SF

DR

[dB

]

b. SFDR

Figure 2.24 Solid line shows the signal quality before correction,dashed line after correction with Θ and dotted lineafter correction with Θ∗. The estimation is here donewith Sinusoidal input signal.


Performance with uniformly distributed input

A uniformly distributed input is in a way the perfect signal for estimationfor two reasons:

• The excitation is constant and high at all levels of the ADC.

• The estimate is easily calculated analytically with very few operations.

The good performance can be seen in the parameter error plots before andafter correction, Figure 2.25. Since this is an analytical solution the re-maining errors are only caused by low excitation which we can see still existdespite the large amount of data. The amount of data is however goodenough to get an indistinguishable difference in signal quality from correc-tion with the true errors, Figure 2.26. The peak improvement is here 5dBfor SNDR and 19dB for SFDR.

2.5.2 Unknown Amplitude Distribution

The algorithm for estimation with unknown input amplitude distributionis here evaluated on simulated data. The error parameters and the signaltypes are the same as for the case with known input amplitude distributionin Section 2.5.1 to make the results from the two methods comparable.

Performance with Gaussian input distribution

Figure 2.27a shows the errors before compensation and Figure 2.27b showsthe errors after compensation with estimated parameters. The correctionhas been done with data from a Gaussian distribution. These figures showthat most of the errors that change quickly between adjacent levels are elim-inated, some of the slow varying errors are however still left. This is causedby errors in the estimation of the amplitude distribution, slow variations inthe errors can not be distinguished from variations in the true amplitudedistribution since only smoothness is assumed. The errors near the edges ofthe ADC are not eliminated becsause of the poor excitation in this region.Figure 2.28 shows the signal quality before and after correction with esti-mated error parameters. Correction with the true errors are also plotted forcomparison. The signal quality is measured as SNDR and SFDR. The peakimprovement is 3dB for SNDR and 8dB for SFDR. The improvement is notas good as for the case with known input distribution since the estimationof the amplitude distribution is not perfect.

2.5 Simulations 65

0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude


0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude


Figure 2.25 Error vector before and after estimation with Uni-formly distributed input.


−14 −12 −10 −8 −6 −4 −2 025

30

35

40

45

50

55

Signal power [dBFS]

SN

DR

[dB

]

a. SNDR

−14 −12 −10 −8 −6 −4 −2 035

40

45

50

55

60

65

70

Signal power [dBFS]

SF

DR

[dB

]

b. SFDR

Figure 2.26 Solid line shows the signal quality before correction,dashed line after correction with Θ and dotted lineafter correction with Θ∗. The estimation is here donewith a uniformly distributed input signal.

2.5 Simulations 67

0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude


0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude


Figure 2.27 Error vector before and after estimation with Gaussiandistributed input.


−14 −12 −10 −8 −6 −4 −2 025

30

35

40

45

50

55

Signal power [dBFS]

SN

DR

[dB

]

a. SNDR

−14 −12 −10 −8 −6 −4 −2 035

40

45

50

55

60

65

70

Signal power [dBFS]

SF

DR

[dB

]

b. SFDR

Figure 2.28 Solid line shows the signal quality before correction,dashed line after correction with Θ and dotted lineafter correction with Θ∗. The estimation is here donewith a Gaussian input signal.

2.5 Simulations 69

Sinusoidal distribution

The results for sinusoidal input signals are quite similar to the Gaussiancase, the estimation most accurate in the middle of the ADC. The reasonfor the bad performance near the edges is however quite different in thiscase. Here the excitation is very high near the edges, but the amplitudedistribution has an abrupt change near the edges. Therefore the estimationof the amplitude distribution near the edges is not good enough. The errorsbefore and after estimation are shown in Figure 2.29. The signal qualityis comparable to the Gaussian case, see Figure 2.30. The SFDR is evenbetter with estimation from sinusoidal input than with Gaussian input.This is however done with a full range sinusoid and the performance woulddecrease with a lower amplitude. The peak improvement is here 3dB forSNDR and 10dB for SFDR.

Uniform distribution

The uniformly distributed input is again the perfect signal for estimation,although it is more of an academical example used for comparison sincereal signals are never uniformly distributed. Since the distribution is notknown in the algorithm the initialization does not give exactly the correctresult here but the algorithm converges in one or two iterations. The result isshown in Figure 2.31. Here we can see that the estimation is quite good evenclose to the edges since we do not have any of the problems with the edgeswhich we had in the Gaussian and the sinusoidal case. The signal qualityimprovement is also much better in this case, see Figure 2.32. The peakimprovement is here 4dB for SNDR and 15dB for SFDR. The performanceis here almost as good as for the case with known input distribution.

2.5.3 Subranging ADC

Here a subranging ADC with mismatch is simulated. The ADC has threesubranging stages with 4, 4, 5 bits respectively in the three stages. The A/Dconverter is simulated with only mismatch errors, i.e., each subranging stageis linear. The ADC has been simulated with a mismatch of about 1% be-tween the first and second stage and 3% between the second and third stage.Figure 2.33a shows the simulated histogram. 150 million samples have beencollected to generate this histogram. Figure 2.33b shows the estimated am-plitude distribution of the input signal. We can see that the largest dipsin the measured histogram are not entirely eliminated. The improvement


0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude


0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude


Figure 2.29 Error vector before and after estimation with a Sinu-soidal input.

2.5 Simulations 71

−14 −12 −10 −8 −6 −4 −2 025

30

35

40

45

50

55

Signal power [dBFS]

SN

DR

[dB

]

a. SNDR

−14 −12 −10 −8 −6 −4 −2 035

40

45

50

55

60

65

70

Signal power [dBFS]

SF

DR

[dB

]

b. SFDR

Figure 2.30 Solid line shows the signal quality before correction,dashed line after correction with Θ and dotted lineafter correction with Θ∗. The estimation is here donewith Sinusoidal input signal.


0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude


0 50 100 150 200 250 300−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1

Level number

Err

or m

agni

tude


Figure 2.31 Error vector before and after estimation with Uni-formly distributed input.

2.5 Simulations 73

−14 −12 −10 −8 −6 −4 −2 025

30

35

40

45

50

55

Signal power [dBFS]

SN

DR

[dB

]

a. SNDR

−14 −12 −10 −8 −6 −4 −2 035

40

45

50

55

60

65

70

Signal power [dBFS]

SF

DR

[dB

]

b. SFDR

Figure 2.32 Solid line shows the signal quality before correction,dashed line after correction with Θ and dotted lineafter correction with Θ∗. The estimation is here donewith Uniformly distributed input signal.


0 1000 2000 3000 4000 50000

0.2

0.4

0.6

0.8

1x 10

−3

Level number

Cod

e de

nsity

a. Output histogram.

0 1000 2000 3000 4000 50000

1

2

3

4

5

6

7

8x 10

−4

Level number

Cod

e de

nsity

b. Estimated amplitude distribution of input.

Figure 2.33 Histograms from simulated subranging ADC.

2.6 Measurements 75

after estimation and compensation is evaluated with a sinusoidal input sig-nal. The SNDR before and after compensation is shown in Figure 2.34a. InFigure 2.34b the SFDR before and after correction is shown. We have herea great improvement over a wide range of input power (70dB). The peakimprovement is 13dB for SFDR and 11dB for SNDR.

2.6 Measurements

The algorithm for blind equalization with unknown input signal distributionis here evaluated on a real A/D converter.

2.6.1 ADC Description

The A/D converter that was used is a three stage subranging SA-ADC, [69,18], see Figure 2.35. The three subranging stages have 4, 4, 5 bits precisionrespectively. If all these levels were used the digital output would be formedas

y = (a · 16+ b) · 32+ c (2.36)

where a ∈ {0, . . . , 15}, b ∈ {0, . . . , 15}, c ∈ {0, . . . , 31} are the output fromstage one, two and three, respectively. Now, all levels are not used due tothe redundancy. The digital output, y, is here formed as

y = (a · 12+ b) · 24+ c (2.37)

With this configuration, the output will have the possible values: y ∈{0, . . . , 4711}.

2.6.2 Algorithm Modification

The number of levels in the A/D converter (4712) is very large. Because ofthis the error estimate takes very long time to calculate. It also takes verylong time to generate and measure data to get enough excitation for all theerrors in the ADC. The excitation is, however, enough for the mismatcherrors which are much larger. A modification of the algorithm that onlyestimates large errors is therefore suggested here. This modification alsoreduces the amount of computations significantly.


−80 −70 −60 −50 −40 −30 −20 −10 00

10

20

30

40

50

60

70

Signal power [dBFS]

SN

DR

[dB

]

a. SNDR

−80 −70 −60 −50 −40 −30 −20 −10 010

20

30

40

50

60

70

80

Signal power [dBFS]

SF

DR

[dB

]

b. SFDR

Figure 2.34 Solid line shows the signal quality before correctionand dashed line after correction with Θ. The estima-tion is here done with Gaussian input signal.

2.6 Measurements 77

+_

V1 ⋅ a

C1 C2 C3va

Sampling Comparator

Binarysearch

Switch

Test chip MATLAB

algorithm

Calculateparameters

,HE Θ

AccumulatehistogramHM

Equation (2)

D

CalculateAddress

A CLook-uptableLUT(A)

Generatecorrecteddata

a=0

a=15

Stage 1

V2 ⋅ bb=0

b=15

Stage 2

V3 ⋅ cc=0

c=31

Stage 3control

Figure 2.35 Structure of test setup.

Selection of large errors

The parameters corresponding to large errors can be found by comparing themeasured amplitude distribution, fY(k), with the estimated input amplitudedistribution, fZ(k, 0). The levels where the relative difference is larger thana threshold, h, is denoted

L = {k :|fY(k) − fZ(k, 0)|

fZ(k, 0)> h} (2.38)

The parameters corresponding to large errors, {θk : k ∈ L}, are free param-eters subject to minimization. The rest of the parameters in Θ are fixedto the relative mean deviation between the measured and the estimatedamplitude distribution.

θk6∈l =∑i6∈L

fY(i) − fZ(i)

fY(i)(2.39)

This is done to keep the sum of the parameters close to zero to avoid thatthe amplitude of the signal is changed.

Extrapolation

Since usually only the mismatch errors are handled in this algorithm, theerrors can be assumed to approximately have a repetitive structure. Thiscan be used to estimate the errors by extrapolation near the edges wherethe excitation is too low even to estimate the mismatch errors.


2.6.3 Data Acquisition

A sequence of Discrete Multi Tone (DMT) symbols, see Chapter 1, was usedas input signal to the ADC when calculating the histogram. In Figure 2.36,an example with 5 · 106 samples is shown. The input signal was generated

2000 2200 2400 2600 2800 30000

2000

4000

6000

8000

10000

12000

code number

code

den

sity

Histogram of output signal

Figure 2.36 Measured histogram

in MATLAB and D/A converted before measuring it in the ADC. The D/Aconverter has much higher accuracy than the A/D converter. This meansthat the analog input signal can be assumed to be correct.

2.6.4 Evaluation

In Figure 2.37 the correction parameters are shown. The large correctionvalues (close to −1) occurs with an interval of 24 levels and comes frommismatch between the two last stages. The peaks occur with an interval of288 = 24∗12 and come from the mismatch between the two first subrangingstages. Here the true errors are unknown. Therefore the performance ismeasured by signal quality before and after correction only. The correctionalgorithm has been evaluated with sinusoidal signals. The signal powerhas been varied and the Signal to Noise and Distortion Ratio (SNDR) and

2.6 Measurements 79

0 1000 2000 3000 4000 5000−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

Figure 2.37 Estimated error parameters.

Spurious Free Dynamic Range (SFDR) have been measured before and aftercorrection, see Figure 2.38. The subranging stages are clearly seen as twodips in the signal quality before correction. These dips are almost eliminatedafter correction. The deterioration in signal quality improvement at highsignal powers is caused by the extrapolation that does not give perfect result,since the errors are not exactly periodical. The peak improvement is about8dB for SNDR and 14dB for SFDR.

2.6.5 Implementation Aspects

The algorithms was tested as post processing in MATLAB of measureddata. The cost of implementing them in hardware is of great importancefor the usefulness and is therefore investigated. Table 2.1 shows the numberof operations and an estimate of required area and power, which is neededto do an implementation in a 0.25 µm CMOS process. Only the collectionof the histograms and the look-up table access are done at the samplingfrequency. The correction algorithms are calculated batch wise and thusseveral millions of clock periods are available. This part can be implementedas a very small processor, which also can handle the control. The processorneeds only 0.5mm2 of the chip area and can easily be integrated on the


−80 −70 −60 −50 −40 −30 −20 −10 00

10

20

30

40

50

60

70

80

Signal Power [dBFullScale]

SN

DR

(+),

SF

DR

(o)

[dB

]

Signal quality

compensated not compensated

Figure 2.38 Signal quality before and after correction. Solid lineindicates corrected and dashed line indicates not cor-rected. The theoretical limit for SNDR (quantization)is drawn as a solid line. + indicates the SNDR and oindicates the SFDR.

chip. The memory might however be too large to be suitable for integrationon the chip.

2.7 Conclusion

The simulations show that the estimation method works well. The perfor-mance is summarized in Table 2.2. This table shows that if the amplitudedistribution of the input signal is known, the improvement is as good aswith known error parameters, Θ∗, independent of what distribution we have.With unknown amplitude distribution the SNDR improvement is almost asgood as with known amplitude distribution while the SFDR improvementis slightly decreased. The two last rows, with subranging A/D converters,

2.7 Conclusion 81

Operation Implementation cost UnitsHistogram 64K bits of RAM

1 mm2

0.3 mW/(MSamples/s)Additions 1M

Multiplications 1M

Divisions 1k

HW including 20k Gatescontrol 0.5 mm2

0.1 mW/(MSamples/s)Memory for 1M bits of RAMcalculations 15.6 mm2

0.3 mW/(MSamples/s)Look-up table 182K bits of RAM

2.9 mm2

0.3 mW/(MSamples/s)Total area 20 mm2

Total power 1 mW/(MSamples/s)

Table 2.1 Implementation cost for integration of the estimation al-gortihm on chip.

cannot be compared to the other simulations since it is not the same A/Dconverter structure. But we can see that we have a good improvement, bothin simulations and in measurements.

Since the estimation with known amplitude distribution gives such goodresults, some knowledge about the amplitude distribution could be utilizedto improve the estimate, even if the amplitude distribution is not exactlyknown. If we know, for example, that the input is a DMT signal, theamplitude distribution is close to Gaussian according to the central limittheorem. A Gaussian distribution, parameterized in mean and standarddeviation, can then be adjusted to the measured histogram. This has notbeen evaluated yet but there is a potential improvement in using moreprior knowledge about the input signal. In the applications where the A/Dconverters are used, for example xDSL modems, the signal shapes are alwaysthe same and therefore we usually have some prior knowledge about thesignal.


Estimation Estimation SNDR SFDRmethod signal peak peak

type improvement improvementKnown Gaussian 4dB 18dB

input Sinusoidal 4dB 18dB

distribution Uniform 5dB 19dB

Unknown Gaussian 3dB 8dB

input Sinusoidal 3dB 10dB

distribution Uniform 4dB 15dB

Correction withtrue Θ 5dB 19dB

Unknowninput,subrangingADC Gaussian 11dB 13dB

Unknowninput,measurements DMT 8dB 14dB

Table 2.2 Signal quality improvement for different estimationmethods and different A/D converter structures.

3Equalization of Dynamic

Distortion in S/H

In this chapter, equalization of the sample-and-hold circuit is discussed. Thesample-and-hold circuit is a critical component in the ADC. It should havethe same gain over a wide frequency band. It should also be linear to avoiddistortion of the signal. In for example radio applications, where we have arelatively narrow signal band around a high frequency carrier, the conversioncan be done at lower frequency by using undersampling. The sample-and-hold circuit must, however, still be fast enough to track the high frequencycarrier. A perfect sample-and-hold circuit is impossible to construct, therewill always be some distortion. To improve the performance the errors in thesample-and-hold circuit could be compensated for afterwards, in the outputsignal. One problem with the sample-and-hold circuit is that the outputsignal is not directly measurable. A quantized, discrete time, version ofthe output signal is however available. The compensation must thereforebe done after the digitization. This means the conversion step must beaccurate, or compensated for first.

3.1 The Sample-and-Hold Operation

In this section a description of how the sample-and-hold circuit works fol-lows. The sample-and-hold circuit is required in most A/D converter con-figurations to keep the analog input signal at a constant level during the

83

84 Chapter 3 Equalization of Dynamic Distortion in S/H

conversion. If the sample-and-hold circuit was not used in for example aSuccessive Approximation ADC, the signal might be in the upper half ofthe ladder during the comparison to the middle level and then change to thelower half for the rest of the search. That could lead to a situation wherethe digital value could not be found.

3.1.1 The Ideal Sample-and-Hold Circuit

An ideal sample-and-hold circuit should track the signal until the sampletime and then keep it constant until the conversion is finished, see Figure 3.1

y(t) =

{u(t) during track modeu(kT) during hold mode

(3.1)

see Figure 3.1. Here u(t) denotes the input signal to the sample-and-holdcircuit and y(t) denotes the output, that still is an analog signal. If thesample rate is the same but the signal frequency is much higher, i.e., under-sampling is used, the sample-and-hold circuit must still be fast enough totrack the input signal, see Figure 3.2. This ideal behavior is, however, notpossible to implement in reality. Especially for high frequency signals, thesample-and-hold circuit is too slow to track the signal and it also introducesnonlinear distortion. Therefore there are errors in the sampled signal, seeFigure 3.3.

3.1.2 The NMOS Transistor

The sample-and-hold cicuit is implemented with NMOS transistors and ca-pacitances. The NMOS transistors have a nonlinear behaviour that causesdistortion in the sampled signal. The nonlinear properties of the NMOStransistor are described in this subsection. In the next subsection, the im-plementation of the sample-and-hold cicuit is described. More detailed in-formation about transistor characteristics can be found in for instance [56].The terminals of the NMOS transistor are denoted Gate, Source and Drain,see Figure 3.4. The gate voltage, VG, controls the transistor. The MOStransistor is symmetric, this means that which one of the terminals thatis drain and source respectively is defined by the voltage on the respectiveterminals.

VD > VS (3.2)

where VD and VS are the voltages on drain and source. The simplest modelof the transistor is a switch. This means that the transistor is conducting

3.1 The Sample-and-Hold Operation 85

0 100 200 300 400 500 600 700−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

Time

Figure 3.1 Ideal behaviour of sample-and-hold cicuit. Dashed lineindicates the input signal u(t) and the solid line is theoutput signal y(t).

0 100 200 300 400 500 600 700−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

Time

Figure 3.2 Ideal behaviour of sample-and-hold cicuit using under-sampling. Dashed line indicates the input signal u(t)

and the solid line is the output signal y(t).


0 100 200 300 400 500 600 700−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

Time

Figure 3.3 Nonideal behaviour of sample-and-hold cicuit, the cir-cuit is too slow to track the input signal between sam-pling instants. Dashed line indicates the input signalu(t) and the solid line is the output signal y(t).

when the gate voltage is larger than a threshold voltage and nonconductingotherwise, see Figure 3.5. In this ideal case, the resistance in the transistoris zero when it is conducting, i.e., the voltage drop over the transistor VD−

VS = 0. This simple model is however not enough to describe the propertiesin a real trasistor. The transistors are here supposed to be in triode modewhich occurs when

VD− VS� VG− VS− VTH (3.3)

where VTH is a threshold voltage that is the smallest voltage required to getthe transistor conducting. VTH depend on the source voltage

VTH = VT0+ γ(√VS+ 2ΦF−

√2ΦF) (3.4)

VT0, γ and ΦF are parameters that depends on the manufacturing process.When the transistor is conducting, it can be modeled as a non-linear, signaldependent, resistance

RON =1

µnCoxWL

(VG− VS− VTH)(3.5)


Gate

Source Drain

VG

VS VD

Figure 3.4 The NMOS transistor.

VS VD

VG < VTH

Figure 3.5 A simple model of the transistor. The transistor is con-ducting when VG > VTH where VTH is a threshold volt-age.

where W and L are the length and width of the transistor. µn and Cox areprocess parameters.

3.1.3 The Bottom Plate Sampler

The implementation of the sampling circuit that is studied here is called thebottom plate sampler. The bottom plate sampler consists of three NMOStransistors and a capacitance [16, 17], see Figure 3.6. The input signal,u0(t), is biased with a constant signal ubias so that the input to the sample-and-hold circuit u(t) = u0(t)+ubias. The bias is applied to guarantee thatthe voltage on the input node always is positive. The three transistors aredenoted M1, M2 and M3. The capacitance is denoted CH and the voltageover CH which is the output signal is denoted y(t).

Track mode

During the track mode, or acquisition phase, the transistors M1 and M3 areopen and M2 is closed. In track mode the transistor M2 does not effect thecircuit since it is short-circuited. The capacitance CH is charged by u(t).


VCu(t)

y(t)

M1

M2

M3

CH

Figure 3.6 The bottom plate sampler. u(t) is the analog inputsignal, y(t) is the sampled signal.

The sample-and-hold circuit can then be modeled as a capacitance in serieswith two non-linear resistances, see Figure 3.7. With Kirchoff’s voltage lawthe output signal can be calculated

u(t) − RON3i(t) − y(t) − RON1i(t) = 0 (3.6)

y(t) =1

CH

∫ t0

i(τ) +Q0

CH

Eliminating i(t) from (3.6) gives

u(t) − RON3CHy(t) − y(t) − RON1CHy(t) = 0 (3.7)

Since the terminal voltages of the transistors decide which one of the ter-minals that is drain and source, the sample-and-hold model will split intotwo discrete modes for each transistor. The transistor M1 is connected toground and all the terminals always have positive voltage. Therefore M1

always is in the same mode. M3 on the other hand can switch betweenthe modes. This means that the sample-and-hold model has two discretemodes. The transistor M1 always has its source terminal connected toground. Therefore M1 has a constant threshold voltage

VTH1 = VT0 (3.8)


u(t)

y(t)

CH

RON1

RON3

Figure 3.7 A model of the bottom plate sampler in track mode.

and also a constant resistance, i.e., is only dependent on the gate voltage

RON1 =1

µnCoxWL

(VG− VT0)(3.9)

When the input signal, u(t), is larger than the voltage VC, see Figure 3.6,u(t) > VC the source of the transistor M3 is connected to the capacitanceand the source voltage is

VS = VC = RON1i(t) + y(t) = RON1CHy(t) + y(t) (3.10)

The threshold voltage for M3 is therefore dependent on both y(t) and y(t)

VTH3 = VT0+ γ(√RON1CHy(t) + y(t) + 2ΦF−

√2ΦF) (3.11)

and the resistance in M3 becomes

RON3 =1

µnCoxWL

(VG− VC− VTH3)(3.12)

When u(t) < VC the source terminal is connected to the input and thesource voltage is therefore easy to calculate

VS = u(t) (3.13)

The threshold voltage is in this mode

VTH3 = VT0+ γ(√u(t) + 2ΦF−

√2ΦF) (3.14)


and the resistance is

RON3 =1

µnCoxWL

(VG− u(t) − (VT0+ γ(√u(t) + 2ΦF−

√2ΦF)))

(3.15)

Figure 3.8 shows a block diagram of the sample-and-hold circuit. To sum-

Mode 1

Mode 2

u(t)

y(t)

y(t)u > VC

u < VC

Figure 3.8 Block diagram of the sample-and-hold circuit in track-mode.

marize the track mode model for the sample-and-hold circuit we have

• Mode 1, u(t) > VC


RON1 =1

µnCoxWL

(VG− VT0)

RON3 =1

µnCoxWL

(VG− VC− VTH3)

VC = RON1CHy(t) + y(t)

VTH3 = VT0+ γ(√RON1CHy(t) + y(t) + 2ΦF−

√2ΦF)


• Mode 2, u(t) < VC


RON1 =1

µnCoxWL

(VG− VT0)

RON3 =1

µnCoxWL

(VG− u(t) − VT0+ γ(√u(t) + 2ΦF−

√2ΦF))

Another transistor model that is based on real measurements and used inSPICE simulations is given in [11].

Transition from track to hold mode

In the transistion from track to hold mode the switching transistors shouldbe opened so that the capacitance is isolated from the input signal and theground. This is done in three steps. At the sampling instant, the “samplingswitch”, M1, is first opened. This isolates the capacitance from the inputsignal. After that the dummy transistor M2 is closed to cancel some ofthe charge injected by M1. Without the transistor M2, some of the chargefrom the transistor M1 would go to the capacitance which would lead to anerror in the capacitance voltage. Finally M3 is open and the transition fromtrack to hold mode is completed. There are, however, some disturbancesthat influences the charge in CH.

• Thermal noise from the switches contributes with a noise charge

Qn =√kBTC (3.18)

• Clock-Feedthrough (CFT): The clock-signal contributes to the chargeby a capacitance between the clock signal and the switch [58]. Thiscan be reduced by a differential circuit [33].

• Charge injection: When the transistors are closing, charge from thechannel in the transistor will move to the capacitance. If the clocksignal switches fast enough this disturbance is however quite small [59].Some of the injected charge is also cancelled by the dummy transistorM2.

When the transition from track to hold mode is completed, the capacitanceshould hold a constant voltage during the conversion. Because of leakagecurrents the voltage slowly decreases. Therefore the conversion should nottake too long time.


3.2 Problem Formulation

We will here only study the track mode of the sample-and-hold circuit.The non-linear dynamic behavior of the sample-and-hold circuit deterio-rates the dynamic range of the A/D converter. The performance could beincreased a lot if these errors could be compensated for. A lot of work oncompensation methods for dynamic errors has been done. In [57] a correc-tion table based on current and previous sample is proposed for correction.The table has one entry for each combination of current and previous sam-ple, uk = f(yk, yk−1). This means that a 2n× 2n table is required for ann-bit ADC. This method works for low precision A/D converters, but forhigh precision A/D converters the table would be too large. To improvethe accuracy the table could be based on the slope of the input signal in-stead of the previous sample. The slope can either be measured with extrahardware [53] or estimated from the output by a digital filter [35, 26]. Thisimproves the accuracy since the derivative is measured more accurately, butthe size of the table is still too large to be used in high precision A/D con-verters. In [36] the table size is reduced by approximating the table withtriangle basis functions and in [3] a neural network is used to reduce thememory requirements. All these methods require a calibration with knowninput signals to fill the table with correction values. Since the errors dependon both slope and amplitude, many different signals must be used in thecalibration process to fill the whole table. Calibration is time consumingand costs a lot of money, therefore a correction method that does not re-quire calibration is desirable. In [43] a method based on sinusoid histogramsis used for estimation of dynamic errors. Two histograms are used, one fornegative slopes and one for positive slopes. The amplitude distribution ofthe input signal must be known in this approach, and a slope detector mustbe used to find out if the slope is positive or negative. One way of esti-mating the dynamic errors blindly could be to estimate the true histogramsas in chapter 2. This method is not yet investigated. Here we will use anequalization method based on a model of the sample-and-hold circuit. Thismethod is described in the next section.

3.3 Model Based Equalization of Sample-and-Hold

Nonlinearities

The idea here is to use the physical model of the sample-and-hold circuit,described in Section 3.1, to equalize the sample-and-hold nonlinearities. The

3.3 Model Based Equalization of Sample-and-Hold Nonlinearities 93

goal is to construct an equalizer based on previous samples, i.e., with noextra hardware for slope detection. Here ideas from the RAM-based equal-izers [44, 45] can be used. In the RAM-based equalizers a Random AccessMemory (RAM) is continuously updated with data and used to equalizenonlinear communication channels.

We will here investigate how a table with fixed size, M, should be filled,assuming that both the output signal, y, and the output signal derivative,y, is known, see Figure 3.9. We assume here that the output and its deriva-

Sample−and−hold circuit

Look−up−table,

u(t)y(t)

y(t)u(t)

ddt

f(y, y)

Figure 3.9 Sample-and-hold circuit and equalizer.

tive are directly measurable, i.e., there is no amplitude quantization. Thissituation is far from the realistic case where the derivative is not availableand the output is quantized, but it gives a hint of how far we can reach witha model based look-up table approach. Assume that we have a table withM entries. This table should be used to approximate the ideal equalizationfunction, f(y, y), that is the inverse function of the sample-and-hold modeldescribed in Section 3.1. The model equations are hard to invert analyti-cally. The equations for mode 1 are easily inverted, but a problem here isthat we cannot easily determine which mode the transistor is in from onlythe output signal and its derivative. Therefore a table with local models ineach entry is used instead. The coefficents in the table are found by min-imizing the mean square error between input and output,

∫(u(t) − u(t))2.

Four equalization functions, all locally affine in the signals y and y areinvestigated.

1. fij(y, y) = y+ aij, mn ≤M

2. fij(y, y) = y+ aij+ bijy, 2mn ≤M

3. fij(y, y) = y+ aij+ cijy, 2mn ≤M

4. fij(y, y) = y+ aij+ bijy+ cijy, 3mn ≤M

We will investigate how well different table configurations, see Table 3.1,approximates the inverse model. The parameters aij, bi,j, cij are coefficients


y < y2 a11, b11, c11 a12, b12, c12 · · · a1n, b1n, c1ny2 ≤ y < y3 a21, b21, c21 a22, b22, c22 · · · a2n, b2n, c2n

......

.... . .

...ym ≤ y am1, bm1, cm1 am2, bm2, cm2 · · · amn, bmn, cmn

y < y2 y2 ≤ y < y3 · · · yn ≤ y

Table 3.1 Sample-and-hold equalizer configurations.

for different model inversion approximations. More complex models reducesthe number of entries in the table since the total table size should be con-stant. The question here is which model works best for fixed M and how m

and n should be chosen. Another question is how the interval limits, yi andyi should be chosen. Here we use uniform intervals and leave this questionto later investigations.

3.4 Simulations

In this section a sample-and-hold circuit is simulated and a table for eachinversion model, f(y, y), is estimated from simulated data. A table withfixed number of entries, M = 100, is used in all simulations. The root meansquare error (RMSE) is calculated after compensation with each table. TheRMSE is for each kind of table plotted for different values of m, i.e., thepartitioning in y. The partitioning in y is calculated such that the totalnumber of entries in the table is constant, M. In Figure 3.10 the RMSEafter compensation with fij(y, y) = y + aij is shown. Figure 3.11 showsthe RMSE after compensation with fij(y, y) = y + aij + bijy. Figure 3.12shows the RMSE after compensation with fij(y, y) = y + aij + cijy andFigure 3.13 shows the RMSE after compensation with fij(y, y) = y+ aij+

bijy+ cijy. These plots show that it is important to include the derivativein the model. We can also see that if the derivative is included in the model,the performance is almost independent of the partitioning of the table. Ifthe derivative is not included in the model, however, it is important tohave a fine partitioning of the derivative in the table. This indicates thatknowledge of the output derivative is quite important.

3.5 Conclusion 95

0 20 40 60 80 10010

−3

10−2

10−1

100

RMSE for model uhat=y+aij

Nr of y entries

RM

SE

Figure 3.10 RMSE after compensation with fij(y, y) = y+aij as afunction of m wheremn = 100. Dashed line shows theRMSE before compensation. We have optimal perfor-mance for m = 1 and n = 100

3.5 Conclusion

In this chapter we have summarized a mathematical model of the sample-and-hold circuit. An equalization method is suggested based on the model.Simulations show a great improvement of the performance after equaliza-tion. The simulations are however done for a simplified situation where moreknowledge is available about the output signal than in a realistic situation.More work must be done in this field to find out how robust the equalizationmethod is to model errors. In a realistic situation the derivative must beestimated since it is not directly measurable. The effects of this derivativeapproximation must be investigated.


0 10 20 30 40 5010

−3

10−2

10−1

100

RMSE for model uhat=y+aij+b

ij*y

Nr of y entries

RM

SE

Figure 3.11 RMSE after compensation with fij(y, y) = y + aij +

bijy as a function of m where 2mn = 100. Dashedline shows the RMSE before compensation. We haveoptimal performance for m = 1 and n = 50.

0 10 20 30 40 5010

−4

10−3

10−2

10−1

100

RMSE for model uhat=y+aij+c

ij*yp

Nr of y entries

RM

SE


cijy as a function of m where 2mn = 100. Dashedline shows the RMSE before compensation.

3.5 Conclusion 97

0 5 10 15 20 25 30 3510

−4

10−3

10−2

10−1

100

RMSE for model uhat=y+aij+b

ij*y+c

ij*yp

Nr of y entries

RM

SE


bijy + cijy as a function of m where 3mn = 100.Dashed line shows the RMSE before compensation.

4Equalization of Static Jitter in

Parallel ADC

4.1 Background

When we are reaching the limit of how fast an A/D converter can be madeat reasonable cost, we have to look at other ways of increasing the samplingrate. One way of increasing the speed is to use several A/D convertersin parallel [39], see Figure 4.1. Each ADC works at 1/Mth of the desiredsampling frequency fs. The ADC’s are interleaved in time so that the kthADC takes samples at time instants (k + nM)Ts, n = 0, 1, . . . where Ts =

1/fs is the sampling interval. This is achieved by a delay line from theclock to each ADC. With many ADC’s in parallel the sampling rate can beincreased a lot. There are however some things that limit the maximumnumber of ADC’s and the signal quality. The maximum number of parallelADC’s is limited by the sample-and-hold circuits which must be fast enoughto track the high frequency parts of the input signal. Even if the sample-and-hold signal is fast and good enough the signal quality will deteriorate ina time-interleaved ADC architecture. One reason for this is different offsetsin the different ADC’s, i.e., the zero level is not the same for all converters.This causes spurious harmonics in the output signal. Figure 4.2 shows theDFT of a sinusoid sampled with two parallel ADC’s with an amplitude offsetof 5%. Another reason is errors in the delay lines to the different ADC’s, i.e.,the signal will be non-uniformly sampled [54, 38, 37]. This non-uniformity

99

100 Chapter 4 Equalization of Static Jitter in Parallel ADC

samplingclock

delay

ADC1

ADC2

ADC3

ADCM

u

y

Figure 4.1 M parallel time-interleaved ADC’s

0 0.2 0.4 0.6 0.8 110

1

102

103

104

105


Figure 4.2 DFT of sinusoid sampled with amplitude offsets in eachADC in Figure 4.1.

4.1 Background 101

is however periodic since the sampling interval for one of the ADC’s isalways MTs. The timing errors caused by the interleaving structure is heredenoted static jitter. Figure 4.3 shows the DFT of a sinusoid sampled withtwo parallel ADC’s with a timing error of 10% of the nominal samplingtime. The static jitter should not be confused with the random jitter that

0 0.2 0.4 0.6 0.8 110

1

102

103

104

105


DFT of nonuniformly sampled sinusoid

Figure 4.3 DFT of sinusoid sampled with static jitter caused bydifferent time delays to each ADC in Figure 4.1.

occurs in a sample-and-hold circuit which gives a random timing error [60].The estimation of amplitude offsets is solved in [20]. A random chopper isused to whiten the input signal before conversion and the amplitude offsetscan then be estimated as the mean value from each A/D converter. Thereare also methods for estimation of the timing errors [40, 12], but thesemethods require a special calibration signal to be used in the estimation.It is expensive to generate good calibration signals, therefore it should beavoided.

In this chapter a method is presented for blind estimation of timingerrors in an interleaved A/D converter structure. The estimation method isalso presented in [24]. The problem of compensating for the timing errorsis also discussed.


4.2 Notation

The analog input signal is denoted u(t). Ts denotes the nominal samplingtime, that we would have without any errors. M is the number of AD con-verters in the parallel structure. The time offset for the ith AD converter isdenoted ti. The output from the ith AD converter is denoted yi[k] wherek is the kth sample from that AD converter. Each AD converter form asubsequence, yi[k] = u((kM + i)Ts+ ti). The sample period for each suchsubsequence is exactly MTs. These subsequences are merged to the outputsignal y[m] = y(mmodM)[bmMc], where b·c denotes integer part. The differ-ence between samples from AD converter i−1 and AD converter i is denoted∆yi[k] = yi[k] − y{(i−1) mod M}[k]. We hereinafter omit mod M, for sim-plicity, when no confusion can occur. We denote the number of data pointsfrom each AD converter by N. We assume that the same number of samplesis taken from all the AD converters so that NM is the total number of data.We use the notation E(s(t)) = limn→∞ 1

n

∑nt=1E(s(t)) for quasistationary

signals [48], where the expectation is taken over possible stochastic partsof s(t). The mean square difference between adjacent samples is denotedRNi,i−1[0], where N is the number of samples that it is calculated from andi, i− 1 are the A/D converters that it is calculated from. The argument, 0,denotes that the samples are taken at the same time index.

4.3 Timing Error Estimation Algorithm

We will, in the presentation of the estimation method, first assume thatthe A/D converters are perfect sampling units. This means that there isno amplitude quantization and also that there are no other errors in eachADC, such as random jitter or static nonlinearities. We also assume that theamplitude offsets are zero. We will then study the effect of the amplitudequantization on the estimation performance.

4.3.1 Timing Error Estimation in Interleaved Perfect Sam-pling Units

Although the estimation method is blind, we need an assumption on theinput signal. The input signal must have most of its energy in a low passband, below approximately 1/3 of the Nyquist frequency. This restrictionis not limiting the usage of the estimation method since oversampling isusually used and an analog anti-aliasing filter is required anyway. Theestimation method is based on the assumption that the signal changes more

4.3 Timing Error Estimation Algorithm 103

on average if the time between adjacent samples is longer than the nominalsampling interval and that it changes less on average if the time is shorter.This means that we have to assume that the signal changes slowly enoughcompared to the sampling interval, i.e., that it has a low enough bandwidth.We look at the difference, ∆yi[k], between the samples from two adjacentA/D converters and make a Taylor expansion around the nominal samplingtime of A/D converter i− 1.

∆yi[k] = yi[k] − yi−1[k] (4.1)= u(kMTs+ iTs+ ti) − u(kMTs+ (i− 1)Ts+ ti−1)

≈ u(kMTs+ (i− 1)Ts) + (Ts+ ti)u′(kMTs+ (i− 1)Ts)

− u(kMTs+ (i − 1)Ts) + ti−1u′(kMTs+ (i− 1)Ts)

≈ (Ts+ ti− ti−1)u′(kMTs+ (i− 1)Ts), i = 2, . . . ,M

The mean value of this difference will tend to zero as the number of samplesgoes to infinity since the input signal is assumed to be limited.

1

N

N∑k=1

∆yi[k] = (Ts+ ti− ti−1)1

N

N∑k=1

u ′(kMTs+ (i− 1)Ts) (4.2)

→ (Ts+ ti− ti−1)E(u ′(t)) = 0

We calculate the mean squared difference between samples from two adja-cent A/D converters:

RNi,i−1[0] =1

N

N∑k=1

{∆yi[k]}2 (4.3)

= (Ts+ ti− ti−1)2 1

N

N∑k=1

{u ′(kMTs+ (i− 1)Ts)}2

→ (Ts+ ti− ti−1)2E{(u ′(t))2}, N→∞

Assume that the variance of the input signal derivative, E(u ′(t)), is knownand that the timing error of the first A/D converter is zero, t1 = 0. Thenwe can calculate the timing errors of the other A/D converters using equa-tion (4.3).

ti =

i∑j=2

(

√RNj,j−1

[0]

E{(u ′(t))2}− Ts), i = 2, . . . ,M (4.4)


The mean value of (u ′(t))2 is however usually unknown. Therefore we haveto estimate it from the sampled data. E(u ′(t))2 can be estimated as anaverage over all the AD-converters:

1

M

M∑i=1

RNi,i−1[0] =1

NM

N∑k=1

M∑i=1

(yi[k] − yi−1[k])2

≈ 1

NM

N∑k=1

M∑i=1

(Ts+ ti− ti−1)2(u ′(kMTs+ (i − 1)Ts))

2

→ 1

M

M∑i=1

(Ts+ ti− ti−1)2E{(u ′(t))2}

= (T2s +2

M

M∑i=1

t2i −2

M

M∑i=1

titi−1)E{(u ′(t))2} (4.5)

From equation (4.5) it seems like we have to know the time offset to calcu-late the estimate of E{(u ′(t))2}. We can however get a crude estimate byassuming that 2

M

∑Mi=1 t

2i − 2

M

∑Mi=1 titi−1 is small compared to T2s . This

is a quite reasonable assumption if the timing offset errors are small on av-erage compared to the nominal sampling time. Using this estimate we cancalculate a crude estimate of the time offsets using equation (4.4):

t(0)

i =

i∑j=2

(

√√√√ RNj,j−1[0]

1MT2s

∑Mi=1 R

Ni,i−1

[0]− Ts), i = 2, . . . ,M (4.6)

With this estimate of the timing errors we can improve the estimate ofE{(u ′(t))2} using equation (4.5). With this improved estimate of E{(u ′(t))2}the timing error estimates can be improved iteratively, using equation (4.5)and fixed-point iteration [6]:

t(l)

i =

i∑j=2

(

√√√√ RNj,j−1

[0]

1

a(l−1)

∑Mi=1 R

Ni,i−1[0]

− Ts), i = 2, . . . ,M (4.7)

where a(l)= M(T2s +

2

M

M∑i=1

(t(l)

i )2−2

M

M∑i=1

t(l)

i t(l)

i−1)

This iteration is repeated until the timing error estimates change slowenough.


If we instead sum over the square root of RNi,i−1[0], the unknown timingerrors cancel

1

M

M∑i=1

√RNi,i−1[0] (4.8)

→ 1

M

M∑i=1

(Ts+ ti− ti−1)

√E{(u ′(t))2} = Ts

√E{(u ′(t))2}

If we take the square root of (4.3) and insert the new estimate (4.8), we getM equations linear in ti

RNi,i−1[0] = (Ts+ ti− ti−1)1

MTs

M∑j=1

√RNj,j−1

[0], i = 1, . . . ,M (4.9)

This means that we just have to solve a linear equation system to calculatethe timing errors

1 0 0 · · · −1

−1 1 0 · · · 0

0 −1 1 · · · 0...

. . . . . ....

0 0 0 · · · 1

t1t2t3...tM

=

RN1,M[0]

RN2,1[0]

RN3,2[0]...

RNM,M−1[0]

1

σu′− Ts

σu′ =1

MTs

M∑j=1

√RNj,j−1[0] (4.10)

Although this equation system is easier to solve than the nonlinear equationsdescribed earlier, both methods are useful. As we will see in the next section,it is easier to compensate for noise in the first description.

4.3.2 Noise Sensitivity

The algorithm in the previous section is based on the assumption that ad-jacent samples are correlated, i.e., that the signal is band-limited. We willin this section discuss how the estimation is affected by an additive noiseterm at the output of the AD converter:

yi[k] = u((kM + i)Ts+ ti) + ei[k], ei[k] ∈ N(0, λ) (4.11)

From equation (4.1) we now have

∆yi[k] ≈ (Ts+ ti− ti−1)u′(kMTs+ (i− 1)Ts) + ei[k] − ei−1[k] (4.12)


Since we assume that the noise is independent of u(t) and the differentnoise sources are independent of each other the cross terms disappear andwe have from equation (4.12):

RNi,i−1 =1

N

N∑k=1

{∆yi[k]}2 (4.13)

=1

NM

N∑k=1

M∑i=1

(Ts+ ti− ti−1)2(u ′(kMTs+ (i − 1)Ts))

2

+1

NM

N∑k=1

M∑i=1

(e2i [k] + e2i−1[k] − 2ei[k]ei−1[k])

+1

NM

N∑k=1

M∑i=1

((ei[k] − ei−1[k])u′(kMTs+ (i − 1)Ts))

→ (Ts+ ti− ti−1)2E{(u ′(t))2} + 2λ, N→∞

With (4.13) in (4.11) we can see that the noise will cause an error in thetime error estimates:

t(0)

i =

i∑j=2

(

√√√√ (RNj,j−1

)y0 + 2λ

1MT2s

∑Mi=1(R

Ni,i−1)y0 + 1

T2s2λ

− Ts) (4.14)

t(l)

i=

i∑j=2

(

√√√√ (RNj,j−1)y0 + 2λ

1

a(l−1)

∑Mi=1(R

Ni,i−1

)y0 + M

a(l−1) 2λ− Ts)

i = 2, . . . ,M

a(l) = M(T2s +2

M

M∑i=1

(t(l)

i)2−

2

M

M∑i=1

t(l)

it(l)

i−1)

l = 1, . . .

Here (RNi,i−1)y0 = 1N

∑Nk=1{∆y

0i [k]}

2, where y0i [k] denotes the noise-free partof yi[k]. From the equation above we can see that the estimates are moreaccurate when the signal is varying quickly (the derivatives get larger). Theaccuracy of the first order Taylor expansion approximation decreases how-ever when the signal is fast varying. This means that if we can choose thefrequency content in the input signal there is a trade-off between accuracyof the Taylor approximation and accuracy of the time estimation algorithmin the noise corrupted case. If the noise variance, λ, is known, we can com-pensate for the noise in the algorithm by subtracting 2λ in equation (4.13).


4.3.3 Quantization Effects

So far we have assumed that the A/D converters do not have any amplitudequantization. This is of course not true in a real A/D converter. Denote byqi[k] the quantization error from the ith A/D converter at the kth sample.We can then calculate the output

yi[k] = u((kM + i)Ts+ ti) + qi[k] (4.15)

This looks similar to the noisy case, but the quantization noise is non-whiteand correlated with the input signal. The mean square difference calculatedfrom equation (4.15) will therefore have two additional terms consisting ofthe correlation between the quantization noise from adjacent A/D convertersand the correlation between quantization and input signal derivative.

RNi,i−1[0] =1

N

N∑k=1

{∆yi[k]}2 (4.16)

=1

NM

N∑k=1

M∑i=1

(Ts+ ti− ti−1)2(u ′(kMTs+ (i − 1)Ts))

2

+1

NM

N∑k=1

M∑i=1

(q2i [k] + q2i−1[k] − 2qi[k]qi−1[k])

+1

NM

N∑k=1

M∑i=1

2((qi[k] − qi−1[k])u′(kMTs+ (i − 1)Ts))

For most signals, however, these terms converge to zero since the correla-tion is very weak. The exception is very slowly varying signals. This can beunderstood in an “ad-hoc” manner by the following example. Consider asignal varying slowly enough so that many adjacent samples will be roundedto the same quantization level, see Figure 4.4. Figure 4.4a shows the sam-pled (not quantized) input signal along with the quantization levels (dashedline). Assume that the signal is rounded to the nearest quantization level.Then we will have quantization errors as shown in Figure 4.4b. Here we havemany adjacent quantization errors with the same sign and the product ofadjacent quantization errors is therefore more often positive than negative,as seen in Figure 4.4c. Therefore the correlation between quantization errorsfrom adjacent samples will give a positive contribution in equation (4.16).The correlation between quantization and and input signal derivative will,however, usually be close to zero. This can be understood from Figure 4.5


0 10 20 30 40 50 600

0.5

1

1.5

2

2.5

3

3.5

4

Time

Am

plitu

de le

vel

a. Slowly varying input signal and itssampling points.

0 10 20 30 40 50 60−0.5

−0.4

−0.3

−0.2

−0.1

0

0.1

0.2

0.3

0.4

0.5

Time

Qua

ntiz

atio

n er

ror

b. The quantization errors of the sam-pled signal.

0 10 20 30 40 50 60−0.25

−0.2

−0.15

−0.1

−0.05

0

0.05

0.1

0.15

0.2

0.25

Time

c. The product of adjacent quantiza-tion errors.

Figure 4.4 Quantization effects of a slowly varying signal.

where (qi[k] − qi−1[k])u′(kMTs+ (i − 1)Ts) is shown. This term will have

the same sign for long intervals, but the transitions between positive andnegative quantization errors give a large contribution of the opposite signthat cancels the built-up bias.

For fast varying signals we do not have this effect. In Figure 4.6 thequantization effects for a fast varying signal are shown. In Figure 4.6a thesignal is shown at its sampling points without quantization. Figure 4.6bthe quantization errors are shown and here the quantization errors look


0 10 20 30 40 50 60−0.02

0

0.02

0.04

0.06

0.08

0.1

Time

Figure 4.5 Correlation between quantization error difference be-tween adjacent samples and input signal derivative.

more like noise. We can also see in Figure 4.6c that the product betweenquantization errors between adjacent samples will have a mean value closeto zero. Also the product of signal slope and quantization errors will looklike noise, see Figure 4.7.

The interleaved A/D converter structure is used for high frequency sig-nals and we normally do not have too much oversampling. This means thatthe estimation method normally should work well also on a quantized signal.We have from equation (4.16), for an interleaved A/D converter structurewith quantization noise variance λ

RNi,i−1[0] =1

N

N∑k=1

{∆yi[k]}2 (4.17)

→ (Ts+ ti− ti−1)2E{(u ′(t))2} + 2λ, N→∞

The same estimation algorithm as for the noisy case can here be used. Thequantization noise variance can here also be calculated analytically

λ =

∫qs/2−qs/2

x21

qsdx =

q2s12

(4.18)

where qs is the quantization step.


0 10 20 30 40 50 600

50

100

150

200

250

300

Time

Am

plitu

de le

vel

a. Fast varying input signal at its sam-pling points.

0 10 20 30 40 50 60−0.5

−0.4

−0.3

−0.2

−0.1

0

0.1

0.2

0.3

0.4

0.5

Time

Qua

ntiz

atio

n er

ror

b. The quantization errors of the sam-pled signal.

0 10 20 30 40 50 60−0.25

−0.2

−0.15

−0.1

−0.05

0

0.05

0.1

0.15

0.2

0.25

Time

c. The product of adjacent quantiza-tion errors.

Figure 4.6 Quantization effects of a fast varying signal.

4.3.4 Noise estimation Algorithm

Usually the noise variance is unknown. With a high noise variance theestimation accuracy deteriorates a lot as we can see from equation (4.14). Tokeep the estimation accuracy with noisy data we therefore have to estimatethe noise variance. The measurement from each ADC can be described as


0 10 20 30 40 50 60−100

−80

−60

−40

−20

0

20

40

60

80

Time

Figure 4.7 Correlation between quantization error difference be-tween adjacent samples and input signal derivative.

a regression of old measurements plus some noise:

yi[k] =

l∑j=1

ai,jy[(k− 1)M + i− j] + ei[k], i = 1, ...,M (4.19)

This model can be used to predict the signal part of the next measurement:

y0i [k] =

l∑j=1

ai,jy[(k− 1)M + i− j], i = 1, ...,M (4.20)

The ai,j coefficients can be estimated from data by minimizing a loss func-tion, the mean square error:

Vi(ai,j, j = 1, ..., l) =

N∑k=1

(yi[k] − yi[k])2 (4.21)

(ai,j, j = 1, ..., l) = argminVi(ai,j, j = 1, ..., l)


From the model (4.19) we can see that

Vi(a∗i,j, j = 1, ..., l) =

N∑k=1

(y0i [k] − yi[k])2 (4.22)

=

N∑k=1

(ei[k])2 = λ

where a∗i,j are the true parameters. ai,j is an estimate of a∗i,j and thereforeVi(ai,j, j = 1, ..., l) is an estimate of the noise variance λ. This means thatλ can be estimated from data before the timing error estimation and theestimated value can be subtracted as described in section 4.3.2.

4.4 Error compensation

The timing errors are more difficult to compensate for than the other typesof errors described in this thesis. All the other errors can be corrected bya look-up table when they are known. For the timing errors other tech-niques must be used. In [49, 50] a filter bank approximating the ideal timedelay, ejωti , is used. This technique gives a good approximation but ismore suitable if the timing errors are known in advance since calculation ofthe optimal approximation filter given the timing errors is rather complex.In [65] a recursive filter design is suggested for interpolation of nonuniformlysampled signals. Iterative methods are suggested in [51, 40]. These methodsare less computationally demanding and therefore more suitable for onlineimplementation.

4.5 Simulations

In this section a parallel time-interleaved A/D converter structure is sim-ulated. The timing errors have been randomly generated between −10%and 10% of the nominal sampling interval. The nominal sampling intervalis Ts = 1 in all simulations.

4.5.1 Timing error estimation

Here we assume that the A/D converters do not have any quantization inamplitude. In the following examples 10 time interleaved A/D convertershave been simulated. A total of 100000 samples have been used for theestimation, i.e., 10000 samples from each A/D converter. In Figure 4.8 an

4.5 Simulations 113

estimation example is shown. The timing errors have here been estimated

0 2 4 6 8 10−0.1

−0.05

0

0.05

0.1

ADC number

actual time offsets estimated time offsets

Figure 4.8 Estimated and true timing errors, estimated from sinu-soidal signal with input frequency f=0.02Hz.

from a sinusoidal signal with frequency f=0.02Hz. The true errors and theestimated errors are in this plot indistinguishable. Figure 4.9 shows the rootmean square error of the estimated timing errors for different frequencies ofthe sinusoidal signal. This plot shows that the estimation is improved whenthe signal frequency is decreased. This can be explained by the linearizationaround a sample point, that is a better approximation at lower frequencies.The fixed point iteration, equation (4.7), gives a significant improvement inestimation accuracy. Figure 4.10 shows the estimated timing errors beforeand after one iteration. In Figure 4.11 the RMSE estimation error is shownas a function of number of iterations. This plot shows that only one or twoiterations are needed, after that the estimates do not improve. From nowon we therefore use 2 iterations. Figure 4.12 shows the estimation errorfor different initial errors. Here we can see that the estimation improveswith smaller initial errors. This means that we always get the same relativeimprovement after estimation even if the errors are small from the begin-ning. So far we have used the same amount of data for all estimations.In Figure 4.13 we can see the estimation accuracy for different amount ofdata. The estimation accuracy improves with more data as expected, butthe improvement is very slow when we have more than 106 samples. It


10−3

10−2

10−1

100

10−6

10−5

10−4

10−3

10−2

10−1

Input signal frequency, fin

/fs

Roo

t mea

n sq

uare

err

or

After estimation Before estimation

Figure 4.9 Root mean square estimation error for different sinu-soidal input signal frequencies.

is also interesting to see how the estimation accuracy varies with differentnumber of A/D converters in the interleaved structure, this is shown in Fig-ure 4.14. The amount of data for each ADC is here kept constant and wecan see that the accuracy is almost constant independently of the numberof ADC’s. These simulations indicate that the estimation method workswell for sinusoidal signals. The next step is to verify that it also works forother input signals. In Figure 4.15 RMSE after estimation with bandlimitedwhite noise is shown. The RMSE is plotted for different bandwidth of thenoise signal. Note that the estimation improves the RMSE even when thebandwidth goes above the Nyquist frequency. In Figure 4.16 the timingerrors are estimated from a DMT signal.

4.5.2 Noise compensation

In the previous subsection the estimation method was verified for differentsignals but without noise. Here we will study how noise affects the estima-tion accuracy. With additive noise on a sinusoidal signal, the estimationaccuracy decreases, especially for low frequency signals. In Figure 4.17 theRMSE after estimation is shown for different frequencies, the Signal-to-NoiseRatio is here 60dB. We can see here that for noisy signals there is an opti-

4.5 Simulations 115

0 2 4 6 8 10−0.15

−0.1

−0.05

0

0.05

0.1

ADC number


a.

0 2 4 6 8 10−0.1

−0.05

0

0.05

0.1

ADC number


b.

Figure 4.10 Estimated errors before iteration (a) and after one it-eration(b).


0 0.5 1 1.5 2 2.5 3 3.5 410

−4

10−3

10−2

Number of iterations

RM

SE

afte

r es

timat

ion

Figure 4.11 Estimation accuracy for different number of iterations.

10−3

10−2

10−1

100

10−6

10−5

10−4

10−3

Initial RMSE

RM

SE

afte

r es

timat

ion

Figure 4.12 Root mean square error after estimation with differentsize of the initial error.

4.5 Simulations 117

101

102

103

104

105

106

10−4

10−3

10−2

10−1

Number of data

RM

SE

afte

r es

timat

ion

Figure 4.13 Root mean square estimation error for differentamount of data.

0 20 40 60 80 1001

2

3

4

5

6

7

8

9

10x 10

−4

RM

SE

afte

r es

timat

ion

Number of ADCs

Figure 4.14 Root mean square estimation error for different num-ber of ADC’s.


10−2

10−1

100

101

10−4

10−3

10−2

10−1

Input signal bandwidth, fc/f

s

Roo

t mea

n sq

uare

err

or

After estimation Before estimation

Figure 4.15 RMSE after estimation with bandlimited white noise.

1 2 3 4 5 6 7 8 9 10−0.1

−0.08

−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

0.1actual time offsetsestimated time offsets

Figure 4.16 RMSE after estimation with DMT signal.

4.5 Simulations 119

10−3

10−2

10−1

100

10−4

10−3

10−2

10−1

Input signal frequency, fin

/fs

Roo

t mea

n sq

uare

err

or After estimation Before estimation

Figure 4.17 RMSE after estimation from noisy sinusoidal signal,SNR=60dB.

mal frequency for estimation. There is a trade off between variance for highfrequencies and bias from the noise for low frequencies. This estimation wasdone without noise estimation. If the noise variance is estimated the accu-racy is improved. In Figure 4.18 the estimation accuracy is compared withand without noise estimation. Figure 4.18a shows the true and estimatedtiming errors are shown without noise compensation. In Figure 4.18b theestimates are compensated with the true noise variance, λ. In Figure 4.18cthe timing error estimates are compensated with estimated noise variance.We can see that the estimation accuracy is almost as good with estimatednoise variance as with true noise variance. Figure 4.19 shows the RMSEafter timing error estimation compensated with λ estimated with differentregression lengths. This plot shows that a regression length of about 100 to150 is required to get a good estimate of the noise variance.

4.5.3 Quantization effects

In this subsection we will study how the quantization influences the esti-mation accuracy. In Figure 4.20 the RMSE after estimation is shown fordifferent number of quantization levels. The errors are here estimated froma sinusoidal signal at 1/2 of the Nyquist frequency. As expected from Sec-


0 2 4 6 8 10−0.5

0

0.5

ADC number


a. Timing error estimation withoutnoise compensation

0 2 4 6 8 10−0.5

0

0.5

ADC number


b. Timing error estimation compen-sated with true noise variance.

0 2 4 6 8 10−0.5

0

0.5

ADC number


c. Timing error estimation with esti-mated noise variance.

Figure 4.18 Timing error estimation with and without noise vari-ance compensation.

4.5 Simulations 121

0 50 100 150 200 2500

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Regression length

Est

imat

ion

erro

r

Figure 4.19 RMSE after estimation from noisy sinusoidal signal,SNR=60dB.

0 2 4 6 8 10 12 14 1610

−2

10−1

Quantizaiton (Number of bits)

RM

SE

afte

r es

timat

ion

Figure 4.20 Estimation accuracy with different number of quanti-zation levels. The input signal is sinusoidal with fre-quency 0.25Hz.


tion 4.5.3 the estimation accuracy is the same independent of the numberof quantization levels. If the frequency is decreased by a factor of 10, seeFigure 4.21, the accuracy is decreased when the signal is quantized to a fewlevels. Only about 8 bits precision is however required to get the same accu-

0 2 4 6 8 10 12 14 1610

−4

10−3

10−2

10−1


RM

SE

afte

r es

timat

ion


racy as without quantization. If the input frequency is further decreased bya factor of ten, about 20 bits is needed to get the same accuracy as withoutquantization, see Figure 4.22. Such high oversampling rates are howevernever used in reality, so the quantization is not a problem in a real system.

4.5.4 Implementation Aspects

The estimation algorithm should be used online on an A/D converter chip.Therefore it is interesting to know how much calculations that are neededto calculate the timing error estimate. Calculation complexity is presentedin Table 4.1 for estimation from 10000 samples from each A/D converter.

4.5 Simulations 123

0 2 4 6 8 10 12 14 1610

−6

10−5

10−4

10−3

10−2

10−1


RM

SE

afte

r es

timat

ion


Timing error Noise variance TotalOperation estimation estimationMultiplications 10k 60k 70k

Additions 20k 80k 100k

Divisions 10 20k 20k

Memory 160kbit 160kbit

Square root 3 0 3

Table 4.1 Calculation complexity for estimation of timing errors.The number of operations is calculated for each ADC.With M parallel ADCs the figures should be multipliedby M.


4.6 Conclusion

The simulations show that the estimation method works well. The restric-tion that the signal must be bandlimited is not limiting to the performancesince an anti-aliasing filter must be used before the A/D converter anyway.The anti-aliasing filter must, in a practical application, have lower cut-offfrequency than fs/2 since an ideal low-pass filter cannot be constructed.Therefore some oversampling is always used in practice. The next step hereis to test the estimation algorithm on a real time-interleaved A/D converter.This also requires implementation of an interpolation algorithm to correctthe non uniformly sampled data, since the true timing errors are unknownin this case.

5Conclusions

In this chapter we summarize the content and the results of this thesis. Thechapter ends with suggestions for future work to improve the equalizationmethods for A/D converters.

5.1 Summary

In Chapter 1, an introduction to A/D converters was given. Different A/Dconverter structures was described and advantages and disadvantages withthe different A/D converters were discussed. Specifications and performancemeasures for A/D converters was also described. The chapter continuedwith a description of two applications for high speed A/D converters, soft-ware radio and xDSL modems. We also stated the problems discussed inthis thesis.

Chapter 2 treated static nonlinear errors in A/D converters. The causeof these static errors was described for one type of A/D converter, the SA-ADC. Two methods for equalization of these errors were proposed. The firstmethod requires knowledge about the amplitude distribution of the inputsignal while the second method only requires that the amplitude distributionis smooth. The equalization methods show improved performance, both insimulations and for real measurements. The SFDR was increased by up to15dB and SNDR by 8dB in measurements on a real A/D converter with

125

126 Chapter 5 Conclusions

unknown input signal distribution. Simulations show that we get almost asgood performance with unknown input signal distribution as with knowninput signal distribution.

In Chapter 3 nonlinear dynamic errors in the sample-and-hold circuitof an A/D converter were treated. A model of the sample-and-hold circuitwas developed and an equalization method was proposed. The equalizationmethod was tested in simulations under simplified conditions, with moreknowledge about the signal than in a realistic situation. These simulations,however, showed improved performance after equalization.

In Chapter 4 timing errors in parallel time interleaved A/D converterswere discussed. The cause of the errors were described and a method forblind estimation of the errors were proposed. The estimation method wasevaluated in simulations and showed significantly increased performance.The only requirement on the input signal is that most of its energy shouldlie in a low pass frequency band.

5.2 Further Work

During the completion of this thesis, many new ideas of how to improvethe equalization methods have evolved. Some of these ideas are listed here,divided into four parts.

Blind Equalization of Static Nonlinearities

The equalization of static nonlinearities works well but can still be improved.Some suggestions follow here:

• The amplitude distribution estimation algorithm could be improvedwith partial knowledge about the input signal amplitude distribution.The amplitude distribution of a DMT signal for instance can be ap-proximated with a Gaussian distribution parameterized in µ and σ.For soft radio, the limited number of carriers in the input spectra canbe utilized for instance using AR-models. Possible improvements fromthat should be investigated.

• The gradient search in Chapter 2 could be improved by optimizing thestep length, µ, for each level, i.e., use a vector µ optimized for eachparameter.

• The levels with low excitation could be better excited if samples arecollected during a longer time. A longer collection time would result

5.2 Further Work 127

in overflow in the histogram memory since it has a limited number ofbits. This could be handled by a weighting function that smoothlyflattens the measured histogram.

• Detection of abrupt changes in the amplitude distribution could im-prove the amplitude distribution estimation, for instance when theinput signal is sinusoidal.

Analytical Equalization of Nonlinear Sample-and-hold Circuit

The equalization of nonlinearities in the sample-and-hold circuit is the partthat requires most further development.

• The equalization method should be tested for robustness against errorsin the model. The model parameters are quite inaccurate and to avoidcalibration the method must work even if there are errors in the model.

• The derivative of the output signal must be estimated in a realisticsituation. Therefore the estimation method must work even if thereare errors in the derivative. The robustness to these errors should beinvestigated.

• The influence of amplitude quantization should be investigated.

• With some assumptions on the input signal it might be possible touse a RAM-based equalizer that is continuously updated, estimatedusing the techniques from Chapter 2.

• Finally, if the method works in simulations, the method should alsobe tested on a real A/D converter.

Equalization of Static Jitter

• The influence of random jitter on the performance of the estimationmethod should be investigated.

• Different interpolation methods should be investigated. Is a linearor polynomial interpolation enough, or do we need more complicatedmethods?

• The estimation method should be tested on a real time-interleavedA/D converter. This also requires implementation of an interpolationalgorithm to measure the performance since the true timing errors areunknown in this case.

128 Chapter 5 Conclusions

General

All three equalization methods described in this thesis should be used to-gether. An open question here is in which order the equalization methodsshould be applied. This requires knowledge about how robust each methodis to the other kinds of errors.

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