Question Bank OF ELC-2041).pdf · Q.40 Design MOD 6 synchronous counter by using J-K Flip-Flop....
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Question Bank OF ELC-204 Faculty Name: Er.Anand K. Gupta and Preeti Singh Subject: Digital Electronics Course code: ELC-204
Transcript of Question Bank OF ELC-2041).pdf · Q.40 Design MOD 6 synchronous counter by using J-K Flip-Flop....
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Question Bank OF ELC-204
Faculty Name: Er.Anand K. Gupta and Preeti Singh
Subject: Digital Electronics
Course code: ELC-204
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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Created by Cam Scanner(Manya Technologies).
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SET-D
Q.1 Explain the working of JK flip-flop. How can you convert the J- K flip-flop into D flip-
flop?
Q.2 What is flip-flop? Explain R-S flip-flop using NAND gates.
Q.3 What is race around condition in JK flip-flop? Explain how it is avoided in JK
master slave FF.
Q.4 What is the difference between synchronous & asynchronous sequential circuit
Q.5 What are the types of shift register ? Explain PISO shift register in detail.
Q.6 Draw a circuit diagram of 3-bit serial-in serial-out shift register and explain
its working.
Q.7 What are the four modes of Shift Register? Which is fastest of them? Why?.
Q.8 Explain the working of 4 bit ripple counter with the help of circuit and timing
diagram.
Q.9 What is a counter? What are the two important types of counters? Explain
the working of a 3-bit counter of any one type with suitable diagram and input –
output wave forms.
Q.10 Draw neat diagram of 3-bit asynchronous up-down counter and explain its
working.
Q.11 Explain R-2R ladder type digital to analog converter ?
Q.12 Give the classification of logic families
Q.13Mention the classification of saturated bipolar logic families.
Q.14 Mention the important characteristics of digital IC’s?
Q.15 Define Fan-out?
Q.16 What is propagation delay?
Q.17 Define noise margin?
Q.18 Define fan in?
Q.19 What are the types of TTL logic?
Q.20 Draw the circuit diagram TTL NAND gate.
Q.21 Draw the circuit diagram RTL NAND gate.
Q.22 Draw the circuit diagram TTL NOT gate.
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Q.23 Draw the circuit diagram TTL NAND gate.
Q.24 Compare the performance of TTL, CMOS and ECL logic.
Q.25 What are the precautions taken while using CMOS ICs?
Q.26 Explain with diagram the working of DTL. State the advantage of DTL over DCTL.
Q.27 Explain briefly the operation of TTL NAND gate in tristate output configurations.
Q.28 Explain the ECL circuit.
Q.29 State the specifications of standard TTL family.
Q. 30 Explain briefly the operation of TTL NAND gate in Totem-Pole Configurations.
Q.31 Explain the working of dual slope analog to digital converter.
Q.32 Explain the working of CMOS NAND circuit.
Q.32 Determine the conversion time of a dual slope 8 bit ADC.Assume analog input voltage
is 5V,reference voltage is 10 volt and clock frequency is 50Khz.What is the maximum
sampling frequency of the converter.
Q.33 Design MOD 10 Ripple counter and also draw the timing diagram of it.
Q. 34 Design a synchronous counter by using T Flip-Flop with an irregular binary count
sequence of 1, 2, 5 & 7.
Q.35 Explain the working of Ring counter.
Q.36 Explain the working of Johnson counter.
Q.37 . Design a PLA structure for the following functions.
a) F1 =∑m(1,2,3,5,7,8,10,12,14)
b) F2 =∑m(7,11,13,14,15)
Q.38 Design a PLA structure for the following functions.
c) F1 =∑m(0,1,2,3,4,7,8,11,12,15)
d) F2 =∑m(2,3,6,7,8,9,12,13)
e) F3 =∑m(1,3,7,8,11,12,15)
f) F4=∑m(0,1,,4,8,11,12,15)
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Q.39 Implement f1(x2,x1)=∑m(0,3), f2(x2,x1)=�� ����������� and f3(x2,x1)=IIM(1) with a 4X3 ROM.
Q.40 Design MOD 6 synchronous counter by using J-K Flip-Flop.
Q.41 Explain the working of Master Slave JK flip-flop.
Q.42 Explain Universal shift Register.
Q.43 Design a synchronous counter by using J-K Flip-Flop with an irregular binary count
sequence of 1, 3, 4, 5 & 7.
Q.44 Design a BCD Decade counter.
Q45. State advantages and disadvantages of TTL
Q.46 Draw the logic diagram for SR latch using two NOR gates.
Q.47 Working of clocked RS flip-flop.
Q.48 What are T and D types of flip flops ?
Q.49 What is the difference between combinational and Sequential Circuit.
Q.50 Design Mod -6 asynchronous counter.
