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NOEL
Extending CMOS:
Quantum Functional Circuits
Using Si-Based
Resonant Interband Tunnel Diodes
Paul R Berger
Department of Electrical and Computer Engineering
Department of Physics
Ohio State University
Columbus, OH 43220 USA
Berger (Si-Based RITDs) September 20, 2017
NOEL
Collaborators
Naval Research Laboratory
Glenn Jernigan, Phillip E. Thompson, Karl Hobart,
and Brad Weaver
IMEC
Roger Loo, Ngoc Duy Nguyen (now Univ-Liege), Shotaro Takeuchi
(now Covalent Silicon), and Matty Caymax
Rochester Institute of Technology
Sean L. Rommel, Santosh K. Kurinec, and Karl D. Hirschman
University of California, Riverside
Roger Lake
NIST, Gaithersberg
David Simons
Berger (Si-Based RITDs) September 20, 2017
NOEL
Students
Current Graduate Students & Researchers
Dr. Tyler Growden & Parastou Fakhimi
Former Graduate Students
Ms. Anisha Ramesh (Ph.D. 2012)
Si-Young Park (Master’s Thesis 2006, Ph.D. 2009)
Ronghua Yu (Ph.D. 2007)
Sung-Yong Chung (Master's Thesis 2002, Ph.D. 2005)
Sandro Di Giacomo (Master's Thesis 2005)
Niu Jin (Master's Thesis 2001, Ph.D. 2004)
Anthony Rice (Master's Thesis 2003)
Sean L. Rommel (Ph.D. 2000)
Berger (Si-Based RITDs) September 20, 2017
Present Day
CMOS Challenges
Moore’s law
Motivation: Extending CMOS?
2000 2002 2004 2006 2008 2010 2012 2014 2016 2018
1
10
100
1000
1E-3
0.01
0.1
22283545607090130
0.002
Source: 2001 ITRS Roadmap
Co
st
(µcen
ts/t
ran
sis
tor)
Production Year
0.347
En
erg
y p
er
Sw
itch
(fJ
/Devic
e)
1.66
107
Year
Node Size (nm)
No Known Solutions
NOEL
CMOS cannot be scaled indefinitely.
Solutions: either replace or augment scaled CMOS
Tunnel diodes married with CMOS offer enhancements
Berger (Si-Based RITDs) September 20, 2017
Intel’s Core i7
6T SRAM cache memory dominates footprint
and power consumption, operates about 1 volt
(→ 8T SRAM)
Power consumption related to voltage squared
(~1 volt state-of-the-art)
NOEL Berger (Si-Based RITDs) September 20, 2017
Let’s Enter the
Quantum World
Cu
rre
nt
Voltage
“N-shaped”
negative differential
resistance (NDR)
• How to characterize tunnel diode?
– Peak-to-valley current ratio
PVCR = Ip / Iv
– Peak current density
Jp = Ip / Area
– Speed index
s = Jp / Cj
• Why use TD with transistors?
– Increases circuit speed
– Reduces circuit complexity
– Lowers circuit power
– Simple integration with transistor
Introduction to Advantages of
Tunnel Diodes
NOEL
Ip
Iv
Berger (Si-Based RITDs) September 20, 2017
Three Interband TD Current Components
From Sze, Physics of Semiconductor Devices, pg. 517 (1981).
Desired: optimize
structure for efficient
quantum mechanical
tunneling
Undesired: excess
current comprised
partially of defect related
tunneling
Thermal diffusion
current eventually takes
over at higher biasesBasic TD Figure-of-Merit
• Peak-to-valley current ratio (PVCR) = Ip/Iv
• Peak current density (PCD or Jp )= Ip/A, where A is the diode area
NOEL Berger (Si-Based RITDs) September 20, 2017
• Band-to-band tunneling current
– PVCR, PCD, and speed
• Excess tunneling current
– PVCR and Standby power dissipation
• Thermal diffusion current
)(24/exp2/32/1 VVqEmW big
png
xx VVeeVE
eWD (6.0
2exp
5.0
From Sze
Goal: Increase band-to-band current and minimize excess current.
Physics Based Model for RITDs
1 kTqV
oth eJJ
Band-to-band tunneling current
Excess current
Thermal current
Cu
rren
t
Voltage
NOEL Berger (Si-Based RITDs) September 20, 2017
Excess Current of an Esaki DiodeFigure adapted from Sze, Physics of Semiconductor Devices, pg. 528 (1981).
•Excess current limits PVCR.
•Excess current is a
tunneling phenomena via
defect or midgap states
For more info see Chynoweth et al.,
Phys. Rev., vol. 121, p. 684, (1961).
NOEL Berger (Si-Based RITDs) September 20, 2017
The Opportunity
Opportunity: Tunnel Diode Memory
• One Transistor 2-Tunnel Diode SRAM (1T TSRAM)
• Robust operation at low voltages
• Refresh-free – Low active and standby power Consumption
• J. P. A. van der Wagt, A. C. Seabaugh, and E. A. Beam, III, “RTD/HFET low standby power SRAM
gain cell,” IEEE Electron Dev. Lett. 19, pp. 7-9 (1998).
• J. P. A. van der Wagt, “Tunneling-Based SRAM,” Proc. of IEEE, 87, pp. 571-595 (1999).
NOEL Berger (Si-Based RITDs) September 20, 2017
NOEL
2005 ITRS – Emerging Research Devices
• Monolithic Integration of Si-based tunnel
diodes with Si-based transistors
Berger (Si-Based RITDs) September 20, 2017
NOEL 2005 ITRS – Emerging Research Devices
NOEL
More computational power per unit area
Fewer devices required
Faster circuits and systems
Reduced power consumption
The Payoff: TDs Integrated with Transistors
Result: Extension of CMOS if a
Si-Based TD is available that is
compatible with CMOS!
Berger (Si-Based RITDs) September 20, 2017
Now Let’s Apply Quantum
Mechanics
Solid State Electronic Devices, Seventh EditionBen G. Streetman | Sanjay Kumar Banerjee
Copyright ©2015, 2006 by Pearson Education, Inc.All rights reserved.
Figure 3–13 Energy band discontinuities for a thin layer of GaAs sandwiched between layers of wider band gap AIGaAs. In this case, the GaAs region is so thin that quantum states are formed in the valence and conduction bands. Electrons in the GaAs conduction band reside on “particle in a potential well” states such as E1 shown here, rather than in the usual conduction band states. Holes in the quantum well occupy similar discrete states, such as Eh.
Quantum well
Solid State Electronic Devices, Seventh EditionBen G. Streetman | Sanjay Kumar Banerjee
Copyright ©2015, 2006 by Pearson Education, Inc.All rights reserved.
Figure 2–6 Quantum mechanical tunneling: (a) potential barrier of height V0 and thickness W; (b) probability density for an electron with energy E < V0, indicating a nonzero value of the wavefunction beyond the barrier.
Tennis Ball
“tunnels” through
barrier
Basic Physics: Esaki Tunnel Diode
(Interband)
Degenerate Doping Required – Difficult with conventional epitaxy
For more info see L. Esaki, “New phenomenon in narrow Germanium p-n junctions,” Phys. Rev., vol. 109, p. 603, 1958.
V
V
V
I I I I
V
I
(a) (b) (d) (e) (f)
VV
V V
PeakTunneling current
Excess current
Thermal diffusion current
p(E)
EE
n(E)
I
(c)
V
p(E)
EE
n(E)
V
p(E)
E
n(E)
n(E)
p(E)p(E)
E
E
E
n(E)
n(E) p(E)
EE
Tunneling current
V
E
E
Prior Art: Lack of Si-Based TDs that can be Monolithically
Integrated with Si transistors
Ge Esaki Diode Si Esaki Diode
• Vintage 1960’s alloy technology prevents large-scale batch processing
• Discrete Esaki diodes are ideal for niche applications.
• However the alloy process does not lend itself to an integrated circuit.
Basic Physics: Resonant
Tunneling Diode (Intraband)
Large Band Offset Required
Si/SiGe heterojunction has limited band offset
without a thick relaxed buffer
Alternative barriers (i.e. SiO2) present difficult
heteroepitaxy of single crystal Si quantum well
atop amorphous barrier
For more info see L. L. Chang, L. Esaki
and R. Tsu, “Resonant tunneling in
semiconductor double barriers,” Appl.
Phys. Lett., vol. 24, pp. 593-595, 1974.
V
(c) (d)(a)
V V
intrinsic
I
(b)
V
I
V
I
V
I
V
emitter collectorTunneling current Excess current Thermal diffusion current
I I I
V
I
(a) (b) (c) (d)
V V V
V
V
V
n -delta doping
p- delta doping
Tunneling current Excess current Thermal diffusion current
Basic Physics: Resonant Interband
Tunneling Diode
δ-doping to form quantum wells;
eliminates need for degenerately
doped junctions
For more info see M. Sweeny and J. Xu,
“Resonant interband tunnel diodes,” Appl. Phys.
Lett., vol. 54, pp. 546-548, 1989.
100 nm n+ Si
Sb-delta doping plane
1 nm undoped Si
4 nm undoped Si0.5Ge0.5
1 nm undoped Si
B-delta doping plane
100 nm p+Si
p+ Si substrate
MBE Heterostructure
• Low growth temperature (320 oC)
• CMOS process compatibility
World’s First Si-Based Resonant Interband
Tunnel Diode (1998)
“Room Temperature Operation of Epitaxially Grown
Si/Si0.5Ge0.5/Si Resonant Interband Tunneling Diodes,"
Sean L. Rommel, Thomas E. Dillon, M. W. Dashiell, H.
Feng, J. Kolodzey, Paul R. Berger, Phillip E.
Thompson, Karl D. Hobart, Roger Lake, Alan C.
Seabaugh, Gerhard Klimeck, and Daniel K. Blanks,
Appl. Phys. Lett., 73, pp. 2191-2193 (1998).
0.0 0.2 0.4 0.6 0.80
5
10
300 K
Peak to Valley Current Ratio : 1.4
Peak Current Density : 2.8 kA/cm2
NRL 80424.2
4 nm i-SiGe spacer
1 nm -dope offsets
700 0C, 1 min anneal
18 m diameter
6 adjacent devices
Cu
rre
nt
(mA
)
Voltage (V)
NOEL
Si/Si0.6Ge0.4/Si RITDs
Grown at 320 oC
High Peak-to-Valley Current Ratios
100 nm n+ Si
P -doping plane
4 nm undoped Si
4 nm undoped Si0.6Ge0.4
B -doping plane
1 nm p+ Si0.6Ge0.4
100 nm p+ Si
p+ Si substrate
MBE Heterostructure
Tu
nn
el
Barr
ier
Greater defect annihilation leads to less excess
current in valley region and therefore higher PVCRs
0.0 0.2 0.4 0.6 0.8 1.00
1
2
3
4
5
6
7
OSU/NRL RITDs (#050322.2)
800 oC, 1-min anneal
etched by HBr
PVCR: 4.03
PCD: 142 A/cm2
Cu
rre
nt (m
A)
Voltage (V)
NOEL
-1.5
-1
-0.5
0
0.5
1
45 50 55 60
Ene
rgy
(eV
)
Position (nm)
V = 0.4VX
zX
xy
HHLH
SO
|Xxy
>
|Xz>
|HH>|LH> Courtesy
R. Lake (UC
Riverside)
Berger (Si-Based RITDs) September 20, 2017
NOEL
First Si-Based Resonant Interband Tunnel Diodes
Front page of the Wall
Street Journal
(October 1, 1998).
Approach
EC
(eV)
Upper
Barrier
Crystalline
Quantum
Well
Crystalline
Lower
Barrier
Crystalline
Production
PotentialStatus
SiO2/a-Si/SiO2 3.2 No No No High Abandoned - High scattering in quantum,
no room temperature PVR
CaF2/Si/CaF2 2 Yes Yes Yes Low Abandoned - Tendency for island growth,
defect-assisted transport below 10 nm
ZnS/Si/ZnS 1 Yes Yes Yes Med. ZnS on Si growth established, Si quantum well
growth under study
SiO2/Si/SiO2
Lateral overgrowth
3.2 No Yes No Med. Process for forming oxide islands established,
overgrowth process under development
ZnS/Si/ZnS
Lateral overgrowth
1 Yes Yes Yes Med. ZnS islands have been prepared for first
overgrowth experiments
SiO2/SiGe(C)/SiO2
Lateral overgrowth
3.2 No Yes No Med. Oxide islands have been prepared for first
overgrowth experiments
SSii//SSiiGGee
rreessoonnaanntt iinntteerrbbaanndd
ttuunnnneell ddiiooddee
-- -- -- -- HHiigghh WWoorrlldd’’ss ffiirrsstt ddeemmoonnssttrraattiioonn oonn SSii;;
rroooomm tteemmppeerraattuurree ppeeaakk--ttoo--vvaalllleeyy
ccuurrrreenntt rraattiioo ooff 11..66
980505
A paradigm shift from other approaches was spearheaded
by a team of researchers lead by Berger (then at the
University of Delaware), Naval Research Laboratory and
Raytheon Systems.
• DARPA Award of Excellence (1998)
• Late News at International Electron Devices Meeting
(1998)
• Best Science/Engineering Dissertation (2000)
• Special Invitation to 2003 ITRS Meeting
• IEEE Fellow (2011)
Berger (Si-Based RITDs) September 20, 2017
5 Key Features of the Original RITD Design
A pair of δ-doping planes of B and P (or Sb) provide highly degeneratedoping levels which can confine quantum states in potential energy wells.The gap between δ-doping planes is assumed the tunneling distance.
An intrinsic layer is used as the central tunneling spacer, which reducescarrier scattering. Both Si and Si/Si1-xGex composite spacers have beenexplored. The addition of Ge provides greater momentum mixing andtherefore higher current densities.
Fixed offsets between the δ-doping planes and the tunneling spacerwere introduced in some SiGe designs to minimize the outdiffusion ofdopants and impurity accumulation into the central tunneling spacer.
Samples were epitaxially grown by low-temperature molecular beamepitaxy (LT-MBE) to allow for greater dopant incorporation and abruptinterfaces minimizing segregation and diffusion.
Short post growth rapid thermal annealing (RTA) heat treatments wereintroduced to reduce the point defect density associated with lowtemperature growth. Diffusion during annealing may decrease the spacerthickness and reduce as-grown δ-doping levels.
“Si-Based Resonant Interband Tunneling Diodes,” Paul R. Berger, Sean L. Rommel, Phillip E.
Thompson, Karl D. Hobart, and Roger Lake, [Issued on October 12, 2004, U. S. Patent #6,803,598].
“Method of Making Interband Tunneling Diodes,” Paul R. Berger, Sean L. Rommel, Phillip E.
Thompson, Karl D. Hobart, and Roger Lake, (U. S. Patent #7,303,969).
NOEL Berger (Si-Based RITDs) September 20, 2017
Isothermal Annealing Effects with Cladding
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
25
50
75
100
125
150
175
200
225
250
275
300
325
350
RITD 042 CLAD
PVCR = 3.6
RITD 042
PVCR = 3.0
RITD 141
PVCR = 1
Cu
rre
nt
De
nsity (
A/c
m2)
Voltage (V)
“Diffusion Barrier Cladding in Si/SiGe Resonant
Interband Tunneling Diodes And Their Patterned
Growth on PMOS Source/Drain Regions,” Niu Jin,
Sung-Yong Chung, Anthony T. Rice, Paul R.
Berger, Phillip E. Thompson, Cristian Rivas,
Roger Lake, Stephen Sudirgo, Jeremy J.
Kempisty, Branislav Curanovic, Sean L. Rommel,
Karl D. Hirschman, Santosh K. Kurinec, Peter H.
Chi and David S. Simons, Special Issue on
“Nanoelectronics” in IEEE Trans. Elect. Dev., vol.
50, pp. 1876-1884 (September 2003).
Diffusion barrier cladding
surrounding the δ-doping
spike raises the process
thermal budget and allows for
greater defect annihilation
before interdiffusion becomes
serious
Annealed 825 oC for 1 minute
NOEL Berger (Si-Based RITDs) September 20, 2017
Very High Peak Current Densities
100 nm n+ Si
P -doping plane
1 nm undoped Si
2 nm undoped Si0.6Ge0.4
B -doping plane
1 nm undoped Si0.6Ge0.4
100 nm p+ Si
p+ Si substrate
Tu
nn
el
Barr
ier
0.0 0.2 0.4 0.6 0.8 1.00
50
100
150
Measured RITDExtracted Intrinsic RITD
Voltage (V)
OSU/NRL Si/SiGe RITD
(2nm Si0.6
Ge0.4
/1nm Si)
Sharpened P peak
5 m diameter diode
575oC, 1 min anneal
Cu
rre
nt
De
nsity (
kA
/cm
2)
Si/Si0.6Ge0.4/Si RITDs
Grown at 320 oC
By reducing tunnel barrier, over 150 kA/cm2 current density!
High current densities valuable for fast switching and RF Mixed Signals
“151 kA/cm2 Peak Current Densities in Si/SiGe
Resonant Interband Tunneling Diodes for High-
Power Mixed-Signal Applications,” Niu Jin, Sung-
Yong Chung, Anthony T. Rice, Paul R. Berger,
Ronghua Yu, Phillip E. Thompson, and Roger
Lake., Appl. Phys. Lett., 83, 3308 (2003).
NOEL Berger (Si-Based RITDs) September 20, 2017
Tailorable Peak Current Densities
Current densities can be
engineered over ~8 orders of
magnitude by controlling RITD
spacer thickness between the δ-
doping pair from 1 nm up to 16 nm.
By widening spacer, below 20 mA/cm2 current density!
Low current densities valuable for memory and low power consumption
0.0 0.2 0.4 0.6 0.8 1.010
-4
10-3
10-2
10-1
100
101
102
103
104
15 nm
14 nm
825oC annealed, 1 min
16 nm
12 nm
10 nm
8 nm
Cu
rre
nt D
en
sity (
A/c
m2)
Voltage (V)
NOEL
0 2 4 6 8 10 12 14 1610
-2
10-1
100
101
102
103
104
105
Pe
ak C
urr
en
t D
en
sity (
A/c
m2)
Spacer Thickness (nm)
Red data points
indicated occur at
maximum PVCRMixed signal
Logic
Memory
Berger (Si-Based RITDs) September 20, 2017
Results highlighted here demonstrate the highest reported peak current density
for Si-based interband tunnel diodes that is 3 times larger than the previous world
record. A high current density is needed to generate large amounts of microwave
power output for radio transmission in small distributed sensor networks
0.0 0.2 0.4 0.6 0.8 1.00
50
100
150
Measured RITDExtracted Intrinsic RITD
Voltage (V)
OSU/NRL Si/SiGe RITD
(2nm Si0.6
Ge0.4
/1nm Si)
Sharpened P peak
5 m diameter diode
575oC, 1 min anneal
Cu
rre
nt
De
nsity (
kA
/cm
2)
Requirement for Memory or Logic Function ( PVCR ≥ 2 )
Requ
irem
en
t for H
igh
sp
ee
d o
r Mix
ed
-Sig
na
l
Circ
uitry
( Jp
>1
0 k
A/c
m2
)
1 2 3 4 5 6
100
1k
10k
100k
RTA/Esaki
(Wang, 2003)
CMOS/RITD
(Sudirgo, 2003)
Si/SiGe RITD (Jin-APL, 2003)
SiGe RITD
(Rommel-APL,
1998)
Esaki Diode
(Dashiell, 2000)
SiGe RITD
(Jin-Eastman,
2002)
SiGe RITD
(Rommel-IEDM
1998)
RITD (Duschl, 2001)
Si-only RITD (Rommel-EDL, 1999)
Esaki Diode
(Jorke, 1993)
Pe
ak
Cu
rre
nt
De
nsi
ty (
A/c
m2)
Peak-to-Valley Ratio (PVCR)
RITD (Duschl, 2000)
Solid circles () indicate prior work by Berger group,
open squares () indicate prior work by other groups,
and stars (*) indicate recent work by Berger group.
RF Mixed Signal Applications Enabled
“151 kA/cm2 Peak Current Densities in
Si/SiGe Resonant Interband Tunneling
Diodes for High-Power Mixed-Signal
Applications,” Niu Jin, Sung-Yong Chung,
Anthony T. Rice, Paul R. Berger, Ronghua
Yu, Phillip E. Thompson, and Roger
Lake., Appl. Phys. Lett., 83, 3308 (2003).
NOEL Berger (Si-Based RITDs) September 20, 2017
Microwave Performance of RITDs
STRUCTURE Uniqueness
• Additional P -doped layer wasinserted for better ohmic contact.
• Ni silicide was formed.
• Minimum space thickness (2.5 nm)with the highest Ge fraction (55 %)was tried.
• 218 kA/cm2 peak current density.
• 20.2 GHz cutoff frequency.
• 35.9 mV/ps of speed index.
P -doping plane
B -doping plane
P -doping plane
1 nm undoped Si
1 nm p+ Si0.45Ge0.55
p Si Substrate (3000-8500 ·cm)
1.5 nm undoped Si0.45Ge0.55
104 nm n+ Si
5 nm n+ Si
264 nm p+ Si
NOEL Berger (Si-Based RITDs) September 20, 2017
Ground
Signal
Ground
Air bridge
DUT
Device Fabrication
For RF measurement
• 1 metal & 2 etching processes havebeen developed, resulting in 0.34m2 sized RITDs.
• Air-bridge is formed to isolate aactive device from huge pad.
• Ni silicidation through P -dopedquantum well by rapid thermalsintering at 430 oC for 30 seconds,resulting in a specific contactresistivity of 5.3×10-7 -cm2, whichis extracted from RF measurement.
Metal (Signal)Metal (Ground)
Forward biased RITD under test
p- Si substrate (3000~8000 Ω-cm)
p++
n++n++
p++
Reverse biased parasitic RITD
NOEL Berger (Si-Based RITDs) September 20, 2017
1 2 3 4 5 610m
100m
1
10
100
1k
10k
100k
1M
SiGe ITD
(Stoffel, 2005)
Si Esaki Diode
(Oehme, 2010)
SiGe RITD, TED 2006
SiGe RITD, EL 2006
SiGe RITD, EDL 2006
RITD
(Duschl, 1999)
RITD (Duschl, 2000)
Esaki Diode
(Dashiell, 2000)
SiGe RITD
(TED, 2005)
SiGe RITD (APL 2003)
SiGe RITD
(APL, 1998)SiGe RITD
(IEEE-TED, 2003)
SiGe RITD
(IEDM, 1998)
Si-only RITD
(EDL, 1999)
Esaki Diode
(Jorke, 1993)
Pe
ak C
urr
en
t D
en
sity (
A/c
m2)
Peak-to-Valley Ratio (PVCR)
Si-based Interband Tunnel Diode
Technology (PCD & PVCR)
Technology Availability
PVCR up to 4
PCD: 20 mA/cm2 to 218 kA/cm2
“Si/SiGe Resonant Interband Tunnel
Diode with fr0 20.2 GHz and Peak Current
Density 218 kA/cm2 for K-band Mixed-
Signal Applications,” Sung-Yong Chung,
Ronghua Yu, Niu Jin, Si-Young Park,
Paul R. Berger, and Phillip E. Thompson,
IEEE Electron Device Letters 27, pp. 364-
367 (May 2006).
NOEL Berger (Si-Based RITDs) September 20, 2017
Si-based Interband Tunnel
Diode Technology (Speed)
0.1 1 10 100 10000.1
1
10
100
0.1
1
10
100 Cut-off freq.
Peak Current Density (JP, kA/cm
2)
Speed Index (
mV
/ps)
Cut-
off fre
quency
(GH
z) Chung, EDL 2006
Jin, 2005
Jin, 2005
Yan, 2004
Dashiell, 2002
Auer, 2001
Speed Index
Technology Availability
fT: up to 20.2 GHz
Switching Speed: ~ 36 mV/ps
“Si/SiGe Resonant Interband Tunnel
Diode with fr0 20.2 GHz and Peak Current
Density 218 kA/cm2 for K-band Mixed-
Signal Applications,” Sung-Yong Chung,
Ronghua Yu, Niu Jin, Si-Young Park,
Paul R. Berger, and Phillip E. Thompson,
IEEE Electron Device Letters 27, pp. 364-
367 (May 2006).
NOEL Berger (Si-Based RITDs) September 20, 2017
260 nm p+ Si0.8Ge0.2
4 nm i Si0.4Ge0.6 spacer
Si0.8Ge0.2 substrate
1 nm p+ Si0.4Ge0.6
2 nm i Si spacer
100 nm n+ Si0.8Ge0.2
B δ-doping layer
P δ-doping layer
2 nm n+ Si
17.5 nm Cap Si
260 nm p+ Si0.8Ge0.2
4 nm i Si0.4Ge0.6 spacer
1 nm p+ Si0.4Ge0.6
100 nm n+ Si0.8Ge0.2
B δ-doping layer
P δ-doping layer
2 nm i Si0.8Ge0.2 spacer
Si0.8Ge0.2 substrate
17.5 nm Cap Si
Tensile Strain on Virtual SiGe
• SiGe virtual substrates utilized for higher Ge content in the spacer toincrease tunneling probability
• Thin tensilely strained Si layer cladding around P δ-doping spike acting asa P diffusion inhibitor
Structure ‘A’ Structure ‘B’
NOEL Berger (Si-Based RITDs) September 20, 2017
“Strain Engineered
Si/SiGe Resonant
Interband Tunneling
Diodes Grown on
Si0.8Ge0.2 Virtual
Substrates,” N. Jin
et.al., IEEE EDL, 29,
599 (2008)
900 1000 1100 1200
-1
0
1
260nm
Si 0
.8G
e0
.2
100nm
Si 0
.8G
e0
.2
1nm
Si 0
.4G
e0
.6
4nm
Si 0
.4G
e0
.6
2nm
Si 0
.8G
e0
.2
B
-dopin
g
P
-dopin
g
Si 0
.8G
e0
.2 S
ubstr
ate
Surf
ace
EV
EC
Ene
rgy (
eV
)
Depth (A)
EF
900 1000 1100 1200
-1
0
1
100nm
Si 0
.8G
e0
.2
260nm
Si 0
.8G
e0
.2
2nm
Si
2nm
Si
1nm
Si 0
.4G
e0
.6
4nm
Si 0
.4G
e0
.6
B
-dopin
g
P
-dopin
g
Si 0
.8G
e0
.2 S
ubstr
ate
Surf
ace
EV
EF
Ene
rgy (
eV
)Depth (A)
EC
Deepened P-well
Tensile Strain on Virtual SiGe
Structure ‘B’Structure ‘A’
“Strain Engineered Si/SiGe Resonant Interband Tunneling Diodes Grown on Si0.8Ge0.2 Virtual Substrates,”
N. Jin et.al., IEEE EDL, 29, 599 (2008)
NOEL Berger (Si-Based RITDs) September 20, 2017
750 775 800 825 8501.0
1.5
2.0
2.5
3.0
Annealing Temperature (oC)
PVCR: Structure B (P-cladding)
PVCR: Structure A (control)
PV
CR
0.0 0.2 0.4 0.6 0.80
30
60
90
120
Voltage (V)
Cu
rre
nt
De
nsity (
A/c
m2)
Structure A,
800 oC annealed
Structure B,
835 oC annealed
• Increase in optimal annealing temperature due to reduced P diffusion• 1.8x increase in PVCR
Tensile Strain on Virtual SiGe
“Strain Engineered Si/SiGe Resonant Interband Tunneling Diodes Grown on Si0.8Ge0.2 Virtual Substrates,” N. Jin et.al.,
IEEE EDL, 29, 599 (2008)
NOEL Berger (Si-Based RITDs) September 20, 2017
260 nm p+ Si0.8Ge0.2
4 nm i Si0.5Ge0.5 spacer
Si0.8Ge0.2 substrate
1 nm p+ Si0.5Ge0.5
1 nm i Si spacer
2 nm p+ Si
100 nm n+ Si0.8Ge0.2
2 nm n+ Si0.5Ge0.5
B delta doping layer
P delta doping layer
2 nm n+ Si
260 nm p+ Si0.8Ge0.2
4 nm i Si0.5Ge0.5 spacer
Si0.8Ge0.2 substrate
1 nm p+ Si0.5Ge0.5
1 nm i Si spacer
100 nm n+ Si0.8Ge0.2
B delta doping layer
P delta doping layer
2 nm n+ Si
Outside Barriers
• Tensilely strained p-type and compressively strained Si0.5Ge0.5 n-type added.
NOEL Berger (Si-Based RITDs) September 20, 2017
“Strain Engineered
Si/SiGe Resonant
Interband Tunneling
Diodes with Outside
Barriers Grown on
Si0.8Ge0.2 Virtual
Substrates,” A. Ramesh
et.al., APL, 93, 102113
(2008).
Outside Barriers
0 5 10 15 20 25 30
-1.0
-0.5
0.0
0.5
1.0
1.5
Ev = 0.2 eV
Ev
EfEne
rgy (
eV
)
Distance (nm)
Ec
Ec = 0.2 eV
0 5 10 15 20 25 30-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
Ev = 0.26 eVE
v
Ef
En
erg
y (
eV
)
Distance (nm)
Ec
Ec = 0.28 eV
• Electron and hole quantum well deepened.
“Strain Engineered Si/SiGe Resonant Interband Tunneling Diodes with Outside Barriers Grown on Si0.8Ge0.2 Virtual
Substrates,” A. Ramesh et.al., APL, 93, 102113 (2008).
NOEL Berger (Si-Based RITDs) September 20, 2017
It is shown that outside barriers can enhance the Jp while reduce the Jv.
The QW is deepened due to the accumulation of bandgap offset (Enhance Jp)
The barrier can block the non-resonant tunneling current (Reduce Jv)
Device Results
800 810 820 830
PV
CR
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
Annealing Temperature (oC)
PVCR: w/o outside bariers
PVCR: w/ outside barriers
800 810 820 830
0
50
100
150
200
250
300
350
400
Cu
rre
nt
De
nsity(A
/cm
2)
Jp: w/o outside barriers
Jv: w/o outside barriers
Jp: w/ outside barriers
Jv: w/ outside barriers
Annealing Temperature (oC)
“Strain Engineered Si/SiGe Resonant Interband Tunneling Diodes with Outside Barriers Grown on Si0.8Ge0.2 Virtual
Substrates,” A. Ramesh et.al., APL, 93, 102113 (2008).
NOEL Berger (Si-Based RITDs) September 20, 2017
Technology Transfer: RITD
0.0 0.2 0.4 0.6 0.8 1.00
1
2
3
4
5
6
7
OSU/NRL RITDs (#050322.2)
800 oC, 1-min anneal
etched by HBr
PVCR: 4.03
PCD: 142 A/cm2
Cu
rre
nt (m
A)
Voltage (V)
0.0 0.2 0.4 0.6 0.8 1.00
5
10
15
20
25
Si/Si0.6
Ge0.4
CVD RITD
6 nm barrier (Si=2, SiGe=4)
PVCR = 5.21, Jp = 20 A/cm
2
10 m
15 m
30 m
40 m
Cu
rrent D
ensity (
A/c
m2)
Voltage (V)
MBE Prototype CVD Tech Transfer *
* Grown on a standard ASM reactor (200 mm) at IMEC
NOEL Berger (Si-Based RITDs) September 20, 2017
“High 5.2 Peak-to-Valley Current Ratio in Si/SiGe Resonant Interband Tunnel Diodes Grown by Chemical Vapor
Deposition,” A. Ramesh et.al., APL, 100, 092104 (2012).
Fabrication Technology Developed
100 nm p+ Si
100 nm n+ Si
X nm i-Si
Y nm i-Si0.6Ge0.4
1 nm p+ Si0.6Ge0.4
Implanted p+ Si
P -plane
B -plane
X+Y nm i-layer
n-well
n-Si substrate
~~
~~
~~
SiO2
TEOS
p-welln-well
implanted p+ n+ n+
TEOSAl
n+
polyTD TD
NFETBack-to-back
Si/SiGe RITD
~~
• Over 80 major steps
• LOCOS isolation
• Double well technology
• n+ polysilicon gate
• Self-aligned S/D
• Low Temperature Molecular
Beam Epitaxy (NRL)
• Post Growth Rapid Thermal
Anneal (OSU)
• Al(1%Si) Metalization
"NMOS/SiGe Resonant Interband Tunneling Diode Static Random Access Memory," S. Sudirgo,
et al., Proceedings of the Device Research Conference (State College, PA, USA, 2006), p. 265..
SEM Micrograph Gallery
10 μm
PMOS
NMOS Si/SiGe
RITD
PWord
PBit
NBit
NWord
VSN
Ground
N-Well
Contact
P-Well
Contact 051003.3
4-State CMOS AMV-TSRAM
RITD Load
RITD Drive
NFET
Word
Bit
VSN
VDD
Ground
20 m
Binary 2TD-1T
051003.320 m
Binary 2T-1TD
051003.3
051003.3
VSN
GroundNFET
10 μm
WordBit
VDD
5-State 4TD-1T
"NMOS/SiGe Resonant Interband Tunneling Diode Static Random Access Memory," S. Sudirgo,
et al., Proceedings of the Device Research Conference (State College, PA, USA, 2006), p. 265..
Integrated CMOS and Si/SiGe RITD
-5 -4 -3 -2 -1 0 1 2 3 4 50.0
5.0
10.0
15.0
20.0
25.0
30.0
-2.5V
NFET
3.0V
3.5V
4.0V
4.5V
VG = 5V
-3.0V
-3.5V
-4.0V
-4.5V
|ID
S| (
m)
VDS
(V)
VG = -5V 051003-D4 R3C2
LMask
= 4m
PFET
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710
0
101
102
1.90
1.90
2.03
1.92
12 nm
10 nm
8 nm
Cu
rren
t D
ensi
ty (
A/c
m2)
Voltage (V)
Integrated Si/SiGe RITDs
051003 D2, D4, D5, D6
6 nm
Device PVCR
6 nm
8 nm
10 nm
12 nm
• Integrated NMOS exhibits a typical VT around 3.0 V.
• Integrated PMOS has VT around -2.65 V.
• Si/SiGe RITDs with various i-layer thicknesses: 6, 8, 10, and 12 nm.
• JP ranges from 10-100 A/cm2, and PVCR up to 2.3.
"NMOS/SiGe Resonant Interband Tunneling Diode Static Random Access Memory," S. Sudirgo,
et al., Proceedings of the Device Research Conference (State College, PA, USA, 2006), p. 265..
The First Integrated Si/SiGe TSRAM
0.0 0.1 0.2 0.3 0.4 0.5 0.60.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
VDD
=
0.57V
I Dri
ve,
I Lo
ad (
mA
)
VSN
(V)
IDrive
ILoad
0.51003.D4
R3C5 CN1-12
0.13V 0.43V
PVCR = 1.87
JP = 52 A/cm
2
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.1
0.2
0.3
0.4
0.5
0.6
0.78V0.57V0.47V
0.36V
VH = 0.59V
0.12V0.13V
0.0V - 1.0V
1.0V - 0.0V
VL
= 0.21V
VS
N (
V)
VDD
(V)
0.51003.D4
R3C5 CN1-12
0.44V
0.2 0.4 0.60.0
0.1
0.2
0.3
0.4
0.5
WH
0.30 V
0.43 V
"1"
Time (sec)
VS
N (
V)
"0" "0"
"1"
0.13 V
0.0
1.0
2.0
3.0 WL SB WL
Word
(V
)
WLWH SBSB
0.0
0.2
0.4
0.6
0.8
1.0
SB
Bit
(V
)
VDD
= 0.57V
• Low voltage operation down to 0.37 V
and %VSWING up to 53.5%.
"NMOS/SiGe Resonant Interband Tunneling Diode Static Random Access Memory," S. Sudirgo,
et al., Proceedings of the Device Research Conference (State College, PA, USA, 2006), p. 265..
Si-Based RITD Results Summary
•High PVCR (5.2)
•High PCD (≥ 218 kA/cm2)
•Low PCD (≤ 20 mA/cm2)
• Vertically stacked back-to-back RITDs for
symmetric NDR
• Tri-state logic with vertically stacked RITDs
• Low voltage MOBILE latches (CMOS-RITD)
NOEL
Device Optimization Hybrid Circuit Prototyping
Device Integration Monolithic Circuits
•Monolithic integration with CMOS
•Monolithic Integration with SiGe HBTs
•CVD Integration
•Low power/low voltage TSRAM
•Low power/low voltage MOBILE
•Adjustable PVCR (HBT-RITD)
Berger (Si-Based RITDs) September 20, 2017
For Further Reading
Paul R. Berger, Anisha Ramesh “Negative Differential Resistance Devices and Circuits” in
Comprehensive Semiconductor Science and Technology, Elsevier, Volume 5, Chapter 13, pp.
176–241 (2011).
A. C. Seabaugh, B. Brar, T. Broekaert, G. Frazier, and P. van der Wagt, “Resonant tunneling
circuit technology: has it arrived?” 1997 GaAs IC Symposium, pp. 119-122.
A. Seabaugh and R. Lake, “Tunnel diodes,” Encyl. Appl. Phys., vol. 22, pp. 335-359 (1998).
J.P. Sun, G.I. Haddad, P. Mazumder, J.N. Schulman, “Resonant tunneling diodes: Models and
properties,” Proc. of IEEE, vol. 86, pp. 641-661 (1998).
P. Mazumder, S. Kulkarni, Bhattacharya M, J.P. Sun, G.I. Haddad, “Digital circuit applications of
resonant tunneling devices, Proc. IEEE, vol. 86, pp. 664-686 (1998).
J. P. A. van der Wagt, “Tunneling-Based SRAM,” Proc. of IEEE, vol. 87, pp. 571-595 (1999).
A. Seabaugh, B. Brar, T. Broekaert, F. Morris, P. van der Wagt, and G. Frazier, “Resonant-
tunneling mixed-signal circuit technology,” Solid State Electronics, vol. 43 pp. 1355-1365 (1999).
K. Maezawa, T. Akeyoshi, and T. Mizutani, “Flexible and reduced-complexity logic circuits
implemented with resonant tunneling transistors,” International Electron Devices Meeting
Technical Digest, pp. 415-418 (1993).
NOEL Berger (Si-Based RITDs) September 20, 2017