Qualkitdo Rptgenext Qualificationreport SDD Logic
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SDD_logic.slxDesign DescriptionThe MathWorks, Inc.
SDD_logic.slx
2
SDD_logic.slx: Design DescriptionThe MathWorks, Inc.
Publication date 13-Aug-2015 03:57:39Copyright © 2015
For Internal Distribution Only
iii
Table of Contents1. Model Version ................................................................................................................ 12. Root System ................................................................................................................... 2
Description ................................................................................................................. 2Blocks ....................................................................................................................... 2
Parameters ......................................................................................................... 2Block Execution Order ......................................................................................... 5
3. Subsystems ..................................................................................................................... 7Increment Real World .................................................................................................. 7
Blocks ............................................................................................................... 7LimitedCounter ......................................................................................................... 10
Blocks ............................................................................................................. 10Repeating Sequence Stair ............................................................................................ 12
Blocks ............................................................................................................. 12Wrap To Zero ........................................................................................................... 15
Blocks ............................................................................................................. 154. System Design Variables ................................................................................................. 18
Design Variable Summary ........................................................................................... 18Design Variable Details .............................................................................................. 18
5. System Model Configuration ............................................................................................ 20
iv
List of Figures2.1. SDD_logic ................................................................................................................... 23.1. SDD_logic/Repeating Sequence Stair/LimitedCounter/Increment Real World ............................ 73.2. SDD_logic/Repeating Sequence Stair/LimitedCounter ........................................................ 103.3. SDD_logic/Repeating Sequence Stair .............................................................................. 123.4. SDD_logic/Repeating Sequence Stair/LimitedCounter/Wrap To Zero .................................... 15
v
List of Tables2.1. "and" Parameters ........................................................................................................... 22.2. "bitand" Parameters ....................................................................................................... 32.3. "CombLogic" Parameters ................................................................................................ 32.4. "Pulse Generator" Parameters .......................................................................................... 32.5. "Pulse Generator1" Parameters ........................................................................................ 42.6. "Pulse Generator2" Parameters ........................................................................................ 42.7. "Pulse Generator3" Parameters ........................................................................................ 52.8. "relop" Parameters ......................................................................................................... 53.1. "FixPt Constant" Parameters ........................................................................................... 73.2. "FixPt Data Type Duplicate" Parameters ........................................................................... 83.3. "FixPt Sum1" Parameters ............................................................................................... 83.4. "u" Parameters .............................................................................................................. 93.5. "y" Parameters .............................................................................................................. 93.6. "Data Type Propagation" Parameters ............................................................................... 103.7. "Force to be scalar" Parameters ...................................................................................... 103.8. "Output" Parameters .................................................................................................... 113.9. "y" Parameters ............................................................................................................ 113.10. "Force to be scalar" Parameters .................................................................................... 123.11. "Out" Parameters ....................................................................................................... 133.12. "Output" Parameters ................................................................................................... 133.13. "Vector" Parameters ................................................................................................... 143.14. "y" Parameters .......................................................................................................... 143.15. "Constant" Parameters ................................................................................................ 153.16. "FixPt Data Type Duplicate1" Parameters ...................................................................... 163.17. "FixPt Switch" Parameters ........................................................................................... 163.18. "U" Parameters .......................................................................................................... 163.19. "Y" Parameters .......................................................................................................... 174.1. Functions used in Design Variable Expressions ................................................................. 185.1. SDD_logic Configuration Set ......................................................................................... 205.2. SDD_logic Configuration Set.Components(1) .................................................................... 205.3. SDD_logic Configuration Set.Components(2) .................................................................... 215.4. SDD_logic Configuration Set.Components(3) .................................................................... 225.5. SDD_logic Configuration Set.Components(4) .................................................................... 235.6. SDD_logic Configuration Set.Components(5) .................................................................... 265.7. SDD_logic Configuration Set.Components(6) .................................................................... 275.8. SDD_logic Configuration Set.Components(7) .................................................................... 275.9. SDD_logic Configuration Set.Components(8) .................................................................... 285.10. SDD_logic Configuration Set.Components(9) .................................................................. 305.11. SDD_logic Configuration Set.Components(8).Components(1) ............................................. 315.12. SDD_logic Configuration Set.Components(8).Components(2) ............................................. 32
1
Chapter 1. Model VersionVersion: 1.54
Last modified: Wed Mar 13 06:37:59 2013
Checksum: 3044426783 2346909945 3236893000 3782843288
2
Chapter 2. Root System
Table of ContentsDescription ......................................................................................................................... 2Blocks ............................................................................................................................... 2
Parameters ................................................................................................................. 2Block Execution Order ................................................................................................. 5
Figure 2.1. SDD_logic
Copyright 2009-2011 The MathWorks , Inc.
This model should conta in a ll blocks in the Logic and Bit Opera tions libra ry tha t a ren't actua lly masked subsys tems .
==
re lop
BitwiseAND0x3
bita ndAND
a nd
Repea tingSequence
S ta ir1
Repea tingSequence
Sta ir
P ulseGenera tor3
P ulseGenera tor2
P ulseGe ne ra tor1
P ulseGenera tor
Simulink Report Generator (SDD Report) Test ModelSDD_logic
CombLogic
DescriptionSimulink Report Generator (SDD Report) Test Model
BlocksParameters
"and" (Logic)
Table 2.1. "and" Parameters
Parameter ValueOperator AND
Root System
3
Parameter ValueNumber of input ports 2Icon shape rectangularRequire all inputs and ou-tput to have the same datatype
off
Output data type booleanSample time (-1 for inhe-rited)
-1
"bitand" (S-Function)
Table 2.2. "bitand" Parameters
Parameter ValueSimulinkmasksOperator-_MP
AND
SimulinkmasksUseBitM-ask_MP
on
SimulinkmasksNumber-OfInputPorts_MP
1
SimulinkmasksBitMask_-MP
bin2dec('0000011')
SimulinkmasksTreatMas-kAs_MP
Stored Integer
"CombLogic" (CombinatorialLogic)
Table 2.3. "CombLogic" Parameters
Parameter ValueTruth table [0;1]Sample time (-1 for inhe-rited)
-1
"Pulse Generator" (DiscretePulseGenerator)
Table 2.4. "Pulse Generator" Parameters
Parameter ValuePulse type Time basedTime (t) Use simulation time
Root System
4
Parameter ValueAmplitude boolean(1)Period (secs) 2Pulse Width (% of perio-d)
50
Phase delay (secs) 0Sample time 1Interpret vector paramet-ers as 1-D
on
"Pulse Generator1" (DiscretePulseGenerator)
Table 2.5. "Pulse Generator1" Parameters
Parameter ValuePulse type Time basedTime (t) Use simulation timeAmplitude 1Period (secs) .1Pulse Width (% of perio-d)
50
Phase delay (secs) 0Sample time 1Interpret vector paramet-ers as 1-D
on
"Pulse Generator2" (DiscretePulseGenerator)
Table 2.6. "Pulse Generator2" Parameters
Parameter ValuePulse type Time basedTime (t) Use simulation timeAmplitude 1Period (secs) 1Pulse Width (% of perio-d)
50
Phase delay (secs) 0Sample time 1Interpret vector paramet-ers as 1-D
on
Root System
5
"Pulse Generator3" (DiscretePulseGenerator)
Table 2.7. "Pulse Generator3" Parameters
Parameter ValuePulse type Time basedTime (t) Use simulation timeAmplitude 1Period (secs) 2Pulse Width (% of perio-d)
50
Phase delay (secs) 0Sample time 1Interpret vector paramet-ers as 1-D
on
"relop" (RelationalOperator)
Table 2.8. "relop" Parameters
Parameter ValueRelational operator ==Require all inputs to havethe same data type
off
Output data type booleanEnable zero-crossing det-ection
on
Sample time (-1 for inhe-rited)
-1
Block Execution Order1. Pulse Generator [3] (DiscretePulseGenerator)2. CombLogic [3] (CombinatorialLogic)3. Pulse Generator1 [4] (DiscretePulseGenerator)4. Pulse Generator2 [4] (DiscretePulseGenerator)5. and [2] (Logic)6. Pulse Generator3 [5] (DiscretePulseGenerator)7. Data Type Propagation (S-Function)8. FixPt Data Type Duplicate (DataTypeDuplicate)9. FixPt Constant (Constant)10. Output (UnitDelay)
Root System
6
11. FixPt Sum1 (Sum)12. FixPt Data Type Duplicate1 (DataTypeDuplicate)13. Constant (Constant)14. FixPt Switch (Switch)15. Vector (Constant)16. Output (MultiPortSwitch)17. Out (SignalConversion)18. relop [5] (RelationalOperator)19. Data Type Propagation [10] (S-Function)20. FixPt Data Type Duplicate [8] (DataTypeDuplicate)21. FixPt Constant [7] (Constant)22. Output [11] (UnitDelay)23. FixPt Sum1 [8] (Sum)24. FixPt Data Type Duplicate1 [15] (DataTypeDuplicate)25. Constant [15] (Constant)26. FixPt Switch [16] (Switch)27. Vector [14] (Constant)28. Output [13] (MultiPortSwitch)29. Out [13] (SignalConversion)30. bitand [3] (S-Function)
7
Chapter 3. Subsystems
Table of ContentsIncrement Real World .......................................................................................................... 7
Blocks ....................................................................................................................... 7LimitedCounter ................................................................................................................. 10
Blocks ..................................................................................................................... 10Repeating Sequence Stair .................................................................................................... 12
Blocks ..................................................................................................................... 12Wrap To Zero ................................................................................................................... 15
Blocks ..................................................................................................................... 15
Increment Real WorldFigure 3.1. SDD_logic/Repeating Sequence Stair/LimitedCounter/Increment RealWorld
1
y
S a meDT
1
1
u
Blocks
Parameters
"FixPt Constant" (Constant)
Table 3.1. "FixPt Constant" Parameters
Parameter ValueConstant value 1Interpret vector paramet-ers as 1-D
on
Output minimum []
Subsystems
8
Parameter ValueOutput maximum []Output data type Inherit: Inherit via back propagationLock output data type se-tting against changes bythe fixed-point tools
off
Sample time infFrame period inf
"FixPt Data Type Duplicate" (DataTypeDuplicate)
Table 3.2. "FixPt Data Type Duplicate" Parameters
Parameter ValueNumber of input ports 3
"FixPt Sum1" (Sum)
Table 3.3. "FixPt Sum1" Parameters
Parameter ValueIcon shape rectangularList of signs ++Sum over All dimensionsDimension 1Require all inputs to havethe same data type
on
Accumulator data type Inherit: Inherit via internal ruleOutput minimum []Output maximum []Output data type Inherit: Inherit via back propagationLock data type settingsagainst changes by the fi-xed-point tools
on
Integer rounding mode FloorSaturate on integer overf-low
off
Sample time (-1 for inhe-rited)
-1
Subsystems
9
"u" (Inport)
Table 3.4. "u" Parameters
Parameter ValuePort number 1Port dimensions (-1 forinherited)
-1
Sample time (-1 for inhe-rited)
-1
Minimum []Maximum []Data type Inherit: auto
"y" (Outport)
Table 3.5. "y" Parameters
Parameter ValuePort number 1Icon display Port numberMinimum []Maximum []Data type Inherit: autoLock output data type se-tting against changes bythe fixed-point tools
off
Output as nonvirtual busin parent model
off
Port dimensions (-1 forinherited)
-1
Variable-size signal InheritSample time (-1 for inhe-rited)
-1
Source of initial outputvalue
Dialog
Output when disabled heldInitial output []
Subsystems
10
LimitedCounterFigure 3.2. SDD_logic/Repeating Sequence Stair/LimitedCounter
1
yWrap To Zero
z
1V++
IncrementRea l World
D:1
Force to be sca la r
Re f1
Ref2
PropData Type
Propaga tion
BlocksParameters
"Data Type Propagation" (S-Function)
Table 3.6. "Data Type Propagation" Parameters
Parameter ValueSimulinkmasksx1Propag-atedDataType_MP
Specify via dialog
Simulinkmasksx11Propa-gatedDataTypeegFixdt1-16Fixdtsingle_MP
uint(nbits)
Simulinkmasksx2Propag-atedScaling_MP
Specify via dialog
Simulinkmasksx21Prop-agatedScalingSlopeEg29-OrSlopeBiasEg1253_MP
1
"Force to be scalar" (SignalSpecification)
Table 3.7. "Force to be scalar" Parameters
Parameter ValueMinimum []
Subsystems
11
Parameter ValueMaximum []Data type Inherit: autoLock output data type se-tting against changes bythe fixed-point tools
off
Require nonvirtual bus offDimensions (-1 for inher-ited)
1
Variable-size signal InheritSample time (-1 for inhe-rited)
-1
"Output" (UnitDelay)
Table 3.8. "Output" Parameters
Parameter ValueInitial condition 0.0Input processing InheritedSample time (-1 for inhe-rited)
tsamp
State name must resolveto Simulink signal object
off
"y" (Outport)
Table 3.9. "y" Parameters
Parameter ValuePort number 1Icon display Port numberMinimum []Maximum []Data type Inherit: autoLock output data type se-tting against changes bythe fixed-point tools
off
Output as nonvirtual busin parent model
off
Port dimensions (-1 forinherited)
-1
Variable-size signal Inherit
Subsystems
12
Parameter ValueSample time (-1 for inhe-rited)
-1
Source of initial outputvalue
Dialog
Output when disabled heldInitial output []
Repeating Sequence StairFigure 3.3. SDD_logic/Repeating Sequence Stair
1
y
OutValues
Vector
0
Output
Out
lim
LimitedCounte r
D:1
Force to be sca la r
BlocksParameters
"Force to be scalar" (SignalSpecification)
Table 3.10. "Force to be scalar" Parameters
Parameter ValueMinimum []Maximum []Data type Inherit: autoLock output data type se-tting against changes bythe fixed-point tools
off
Require nonvirtual bus offDimensions (-1 for inher-ited)
1
Variable-size signal Inherit
Subsystems
13
Parameter ValueSample time (-1 for inhe-rited)
-1
"Out" (SignalConversion)
Table 3.11. "Out" Parameters
Parameter ValueOutput Signal copyData type Inherit: autoExclude this block from'Block reduction' optimi-zation
off
"Output" (MultiPortSwitch)
Table 3.12. "Output" Parameters
Parameter ValueData port order Zero-based contiguousNumber of data ports 1Data port indices (e.g. {1,[2,3]})
{1,2,3}
Data port for default case Last data portDiagnostic for default ca-se
Error
Require all data port inp-uts to have the same datatype
off
Output minimum OutMinOutput maximum OutMaxOutput data type Inherit: Inherit via internal ruleLock output data type se-tting against changes bythe fixed-point tools
off
Integer rounding mode FloorSaturate on integer overf-low
off
Sample time (-1 for inhe-rited)
tsamp
Allow different data inp-ut sizes (Results in varia-ble-size output signal)
off
Subsystems
14
"Vector" (Constant)
Table 3.13. "Vector" Parameters
Parameter ValueConstant value OutValuesInterpret vector paramet-ers as 1-D
on
Output minimum OutMinOutput maximum OutMaxOutput data type OutDataTypeStrLock output data type se-tting against changes bythe fixed-point tools
off
Sample time infFrame period inf
"y" (Outport)
Table 3.14. "y" Parameters
Parameter ValuePort number 1Icon display Port numberMinimum OutMinMaximum OutMaxData type Inherit: autoLock output data type se-tting against changes bythe fixed-point tools
off
Output as nonvirtual busin parent model
off
Port dimensions (-1 forinherited)
-1
Variable-size signal InheritSample time (-1 for inhe-rited)
-1
Source of initial outputvalue
Dialog
Output when disabled heldInitial output []
Subsystems
15
Wrap To ZeroFigure 3.4. SDD_logic/Repeating Sequence Stair/LimitedCounter/Wrap To Zero
U(k)1
Y
> 4
S a meDT
0
1
U
Blocks
Parameters
"Constant" (Constant)
Table 3.15. "Constant" Parameters
Parameter ValueConstant value 0Interpret vector paramet-ers as 1-D
on
Output minimum []Output maximum []Output data type Inherit: Inherit via back propagationLock output data type se-tting against changes bythe fixed-point tools
off
Sample time infFrame period inf
Subsystems
16
"FixPt Data Type Duplicate1" (DataTypeDuplicate)
Table 3.16. "FixPt Data Type Duplicate1" Parameters
Parameter ValueNumber of input ports 3
"FixPt Switch" (Switch)
Table 3.17. "FixPt Switch" Parameters
Parameter ValueCriteria for passing firstinput
u2 > Threshold
Threshold ThresholdRequire all data port inp-uts to have the same datatype
off
Output minimum []Output maximum []Output data type Inherit: Inherit via back propagationLock output data type se-tting against changes bythe fixed-point tools
off
Integer rounding mode FloorSaturate on integer overf-low
off
Enable zero-crossing det-ection
off
Sample time (-1 for inhe-rited)
-1
Allow different data inp-ut sizes (Results in varia-ble-size output signal)
off
"U" (Inport)
Table 3.18. "U" Parameters
Parameter ValuePort number 1Port dimensions (-1 forinherited)
-1
Subsystems
17
Parameter ValueSample time (-1 for inhe-rited)
-1
Minimum []Maximum []Data type Inherit: auto
"Y" (Outport)
Table 3.19. "Y" Parameters
Parameter ValuePort number 1Icon display Port numberMinimum []Maximum []Data type Inherit: autoLock output data type se-tting against changes bythe fixed-point tools
off
Output as nonvirtual busin parent model
off
Port dimensions (-1 forinherited)
-1
Variable-size signal InheritSample time (-1 for inhe-rited)
-1
Source of initial outputvalue
Dialog
Output when disabled heldInitial output 0
18
Chapter 4. System Design Variables
Table of ContentsDesign Variable Summary ................................................................................................... 18Design Variable Details ...................................................................................................... 18
Design Variable SummaryTable 4.1. Functions used in Design Variable Expressions
Function Na-me
Parent Blocks Calling string
bin2dec bitand [3] bin2dec('0000011')
boolean Pulse Generator [3] boolean(1)
Design Variable Details
BitMask. 3
Used by Blocks:
• SDD_logic/bitand [3]
Resolved in: mask workspace (SDD_logic/bitand)
BitMaskRealWorld. 2
Used by Blocks:
• SDD_logic/bitand [3]
Resolved in: mask workspace (SDD_logic/bitand)
NumInputPorts. 1
Used by Blocks:
• SDD_logic/bitand [3]
Resolved in: mask workspace (SDD_logic/bitand)
UseBitMask. 1
Used by Blocks:
• SDD_logic/bitand [3]
System Design Variables
19
Resolved in: mask workspace (SDD_logic/bitand)
logicop. AND
Used by Blocks:
• SDD_logic/bitand [3]
Resolved in: mask workspace (SDD_logic/bitand)
20
Chapter 5. System Model ConfigurationSource: ModelSource Name: SDD_logic
Table 5.1. SDD_logic Configuration Set
Property ValueDescription Components [SDD_logic Configuration Set.Components(1) [-
20], SDD_logic Configuration Set.Componen-ts(2) [21], SDD_logic Configuration Set.Com-ponents(3) [22], SDD_logic Configuration Se-t.Components(4) [23], SDD_logic Configurat-ion Set.Components(5) [26], SDD_logic Conf-iguration Set.Components(6) [27], SDD_logicConfiguration Set.Components(7) [27], SDD-_logic Configuration Set.Components(8) [28],SDD_logic Configuration Set.Components(9) [-30]]
Name ConfigurationSimulationMode normal
Table 5.2. SDD_logic Configuration Set.Components [20](1)
Property ValueName SolverDescription Components StartTime 0.0StopTime 10AbsTol autoFixedStep autoInitialStep autoMaxNumMinSteps -1MaxOrder 5ZcThreshold autoConsecutiveZCsStepRelTol 10*128*epsMaxConsecutiveZCs 1000ExtrapolationOrder 4NumberNewtonIterations 1MaxStep autoMinStep auto
System Model Configuration
21
MaxConsecutiveMinStep 1RelTol 1e-3SolverMode AutoEnableConcurrentExecution offConcurrentTasks offSolver ode45SolverName ode45SolverType Variable-stepSolverJacobianMethodControl autoShapePreserveControl DisableAllZeroCrossControl UseLocalSettingsZeroCrossAlgorithm NonadaptiveSolverResetMethod FastPositivePriorityOrder offAutoInsertRateTranBlk offSampleTimeConstraint UnconstrainedInsertRTBMode Whenever possibleSampleTimeProperty
Table 5.3. SDD_logic Configuration Set.Components [20](2)
Property ValueName Data Import/ExportDescription Components Decimation 1ExternalInput [t, u]FinalStateName xFinalInitialState xInitialLimitDataPoints onMaxDataPoints 1000LoadExternalInput offLoadInitialState offSaveFinalState offSaveCompleteFinalSimState offSaveFormat ArraySignalLoggingSaveFormat ModelDataLogsSaveOutput onSaveState offSignalLogging on
System Model Configuration
22
DSMLogging onInspectSignalLogs offVisualizeSimOutput onStreamToWorkspace offStreamVariableName streamoutSaveTime onReturnWorkspaceOutputs offStateSaveName xoutTimeSaveName toutOutputSaveName youtSignalLoggingName logsoutDSMLoggingName dsmoutOutputOption RefineOutputTimesOutputTimes []ReturnWorkspaceOutputsName outRefine 1LoggingIntervals [-inf, inf]
Table 5.4. SDD_logic Configuration Set.Components [20](3)
Property ValueName OptimizationDescription Components BlockReduction offBooleanDataType onConditionallyExecuteInputs onDefaultParameterBehavior TunableInlineParams offUseDivisionForNetSlopeComputation offUseFloatMulNetSlope offDefaultUnderspecifiedDataType doubleUseSpecifiedMinMax offInlineInvariantSignals offOptimizeBlockIOStorage onBufferReuse onGlobalBufferReuse onGlobalVariableUsage NoneStrengthReduction offAdvancedOptControl
System Model Configuration
23
EnforceIntegerDowncast onExpressionFolding onBooleansAsBitfields offBitfieldContainerType uint_TEnableMemcpy onMemcpyThreshold 64PassReuseOutputArgsAs Structure referencePassReuseOutputArgsThreshold 12FoldNonRolledExpr onLocalBlockOutputs onRollThreshold 5StateBitsets offDataBitsets offActiveStateOutputEnumStorageType Native IntegerUseTempVars offZeroExternalMemoryAtStartup onZeroInternalMemoryAtStartup onInitFltsAndDblsToZero onNoFixptDivByZeroProtection offEfficientFloat2IntCast offEfficientMapNaN2IntZero onOptimizeModelRefInitCode offLifeSpan infEvaledLifeSpan InfMaxStackSize Inherit from targetBufferReusableBoundary onSimCompilerOptimization offAccelVerboseBuild off
Table 5.5. SDD_logic Configuration Set.Components [20](4)
Property ValueName DiagnosticsDescription Components RTPrefix errorConsistencyChecking noneArrayBoundsChecking noneSignalInfNanChecking noneSignalRangeChecking none
System Model Configuration
24
ReadBeforeWriteMsg UseLocalSettingsWriteAfterWriteMsg UseLocalSettingsWriteAfterReadMsg UseLocalSettingsAlgebraicLoopMsg warningArtificialAlgebraicLoopMsg warningSaveWithDisabledLinksMsg warningSaveWithParameterizedLinksMsg noneCheckSSInitialOutputMsg onUnderspecifiedInitializationDetection ClassicMergeDetectMultiDrivingBlocksExec noneCheckExecutionContextPreStartOutputMsg offCheckExecutionContextRuntimeOutputMsg offSignalResolutionControl TryResolveAllWithWarningBlockPriorityViolationMsg warningMinStepSizeMsg warningTimeAdjustmentMsg noneMaxConsecutiveZCsMsg errorMaskedZcDiagnostic warningIgnoredZcDiagnostic warningSolverPrmCheckMsg noneInheritedTsInSrcMsg warningMultiTaskDSMMsg warningMultiTaskCondExecSysMsg noneMultiTaskRateTransMsg errorSingleTaskRateTransMsg noneTasksWithSamePriorityMsg warningSigSpecEnsureSampleTimeMsg warningCheckMatrixSingularityMsg noneIntegerOverflowMsg warningInt32ToFloatConvMsg warningParameterDowncastMsg errorParameterOverflowMsg errorParameterUnderflowMsg noneParameterPrecisionLossMsg warningParameterTunabilityLossMsg warningFixptConstUnderflowMsg noneFixptConstOverflowMsg noneFixptConstPrecisionLossMsg noneUnderSpecifiedDataTypeMsg none
System Model Configuration
25
UnnecessaryDatatypeConvMsg noneVectorMatrixConversionMsg noneInvalidFcnCallConnMsg errorFcnCallInpInsideContextMsg UseLocalSettingsSignalLabelMismatchMsg noneUnconnectedInputMsg warningUnconnectedOutputMsg warningUnconnectedLineMsg warningSFcnCompatibilityMsg noneFrameProcessingCompatibilityMsg errorUniqueDataStoreMsg noneBusObjectLabelMismatch warningRootOutportRequireBusObject warningAssertControl UseLocalSettingsEcho EnableOverflowDetection offAllowSymbolicDim offModelReferenceIOMsg noneModelReferenceVersionMismatchMessage noneModelReferenceIOMismatchMessage noneModelReferenceCSMismatchMessage noneModelReferenceSimTargetVerbose offUnknownTsInhSupMsg warningModelReferenceDataLoggingMessage warningModelReferenceSymbolNameMessage warningModelReferenceExtraNoncontSigs errorStateNameClashWarn warningSimStateInterfaceChecksumMismatchMsg warningSimStateOlderReleaseMsg errorInitInArrayFormatMsg warningStrictBusMsg ErrorLevel1BusNameAdapt WarnAndRepairNonBusSignalsTreatedAsBus noneSFUnusedDataAndEventsDiag warningSFUnexpectedBacktrackingDiag warningSFInvalidInputDataAccessInChartInitDiag warningSFNoUnconditionalDefaultTransitionDiag warningSFTransitionOutsideNaturalParentDiag warningSFUnconditionalTransitionShadowingDiag warning
System Model Configuration
26
SFUndirectedBroadcastEventsDiag warningSFTransitionActionBeforeConditionDiag warningSFOutputUsedAsStateInMooreChartDiag errorIntegerSaturationMsg warning
Table 5.6. SDD_logic Configuration Set.Components [20](5)
Property ValueName Hardware ImplementationDescription Components ProdBitPerChar 8ProdBitPerShort 16ProdBitPerInt 32ProdBitPerLong 32ProdBitPerLongLong 64ProdBitPerFloat 32ProdBitPerDouble 64ProdBitPerPointer 32ProdLargestAtomicInteger CharProdLargestAtomicFloat NoneProdIntDivRoundTo UndefinedProdEndianess UnspecifiedProdWordSize 32ProdShiftRightIntArith onProdLongLongMode offProdHWDeviceType 32-bit GenericTargetBitPerChar 8TargetBitPerShort 16TargetBitPerInt 32TargetBitPerLong 32TargetBitPerLongLong 64TargetBitPerFloat 32TargetBitPerDouble 64TargetBitPerPointer 32TargetLargestAtomicInteger CharTargetLargestAtomicFloat NoneTargetShiftRightIntArith onTargetLongLongMode offTargetIntDivRoundTo Undefined
System Model Configuration
27
TargetEndianess UnspecifiedTargetWordSize 32TargetTypeEmulationWarnSuppressLevel 0TargetPreprocMaxBitsSint 32TargetPreprocMaxBitsUint 32TargetHWDeviceType SpecifiedTargetUnknown offProdEqTarget on
Table 5.7. SDD_logic Configuration Set.Components [20](6)Property ValueName Model ReferencingDescription Components UpdateModelReferenceTargets IfOutOfDateOrStructuralChangeSkipRefExpFcnMdlSchedulingOrderCheck offEnableRefExpFcnMdlSchedulingChecks onCheckModelReferenceTargetMessage errorEnableParallelModelReferenceBuilds offParallelModelReferenceErrorOnInvalidPool onParallelModelReferenceMATLABWorkerInit NoneModelReferenceNumInstancesAllowed MultiPropagateVarSize Infer from blocks in modelModelDependencies ModelReferencePassRootInputsByReference onModelReferenceMinAlgLoopOccurrences offPropagateSignalLabelsOutOfModel offSupportModelReferenceSimTargetCustomCode off
Table 5.8. SDD_logic Configuration Set.Components [20](7)Property ValueName Simulation TargetDescription Components SimCustomSourceCode SimCustomHeaderCode SimCustomInitializer SimCustomTerminator SimReservedNameArray
System Model Configuration
28
SimUserSources SimUserIncludeDirs SimUserLibraries SFSimEnableDebug offSFSimOverflowDetection onSFSimEcho onSimBlas onSimCtrlC onSimExtrinsic onSimIntegrity onSimUseLocalCustomCode offSimParseCustomCode onSimBuildMode sf_incremental_buildSimDataInitializer SimGenImportedTypeDefs off
Table 5.9. SDD_logic Configuration Set.Components [20](8)
Property ValueName Code GenerationSystemTargetFile grt.tlcTLCOptions CodeGenDirectory GenCodeOnly offMakeCommand make_rtwGenerateMakefile onPackageGeneratedCodeAndArtifacts offPackageName TemplateMakefile grt_default_tmfPostCodeGenCommand Description GenerateReport offSaveLog offRTWVerbose onRetainRTWFile offProfileTLC offTLCDebug offTLCCoverage offTLCAssert offProcessScriptMode Default
System Model Configuration
29
ConfigurationMode OptimizedProcessScript ConfigurationScript ConfigAtBuild offRTWUseLocalCustomCode offRTWUseSimCustomCode offCustomSourceCode CustomHeaderCode CustomInclude CustomSource CustomLibrary CustomInitializer CustomTerminator Toolchain Automatically locate an installed toolchainBuildConfiguration Faster BuildsCustomToolchainOptions IncludeHyperlinkInReport offLaunchReport offPortableWordSizes offGenerateErtSFunction offCreateSILPILBlock NoneCodeExecutionProfiling offCodeExecutionProfileVariable executionProfileCodeProfilingSaveOptions SummaryOnlyCodeProfilingInstrumentation offSILDebugging offTargetLang CIncludeERTFirstTime onGenerateTraceInfo offGenerateTraceReport offGenerateTraceReportSl offGenerateTraceReportSf offGenerateTraceReportEml offGenerateCodeInfo offGenerateWebview offGenerateCodeMetricsReport offGenerateCodeReplacementReport offRTWCompilerOptimization offObjectivePriorities
System Model Configuration
30
RTWCustomCompilerOptimizations CheckMdlBeforeBuild OffCustomRebuildMode OnUpdateDataInitializer Components [SDD_logic Configuration Set.Components(8).C-
omponents(1) [30], SDD_logic ConfigurationSet.Components(8).Components(2) [32]]
Table 5.10. SDD_logic Configuration Set.Components [20](9)
Property ValueDescription Simulink Coverage Configuration ComponentComponents Name Simulink CoverageRecordCoverage onCovPath /CovSaveName covdataCovCompData CovMetricSettings rwCovFilter CovHTMLOptions CovNameIncrementing offCovHtmlReporting onCovForceBlockReductionOff onCovEnableCumulative onCovSaveCumulativeToWorkspaceVar onCovSaveSingleToWorkspaceVar onCovCumulativeVarName covCumulativeDataCovCumulativeReport offCovReportOnPause onCovModelRefEnable OffCovModelRefExcluded CovExternalEMLEnable offCovSFcnEnable onCovBoundaryAbsTol 1.0000e-05CovBoundaryRelTol 0.0100CovUseTimeInterval offCovStartTime 0CovStopTime 0
System Model Configuration
31
Table 5.11. SDD_logic Configuration Set.Components(8).Components [30](1)
Property ValueName Code AppearanceDescription Components ForceParamTrailComments offGenerateComments onCommentStyle AutoIgnoreCustomStorageClasses onIgnoreTestpoints offIncHierarchyInIds offMaxIdLength 31PreserveName offPreserveNameWithParent offShowEliminatedStatement offOperatorAnnotations offIncAutoGenComments offSimulinkDataObjDesc offSFDataObjDesc offMATLABFcnDesc offIncDataTypeInIds offPrefixModelToSubsysFcnNames onMangleLength 1CustomSymbolStr $R$N$MCustomSymbolStrGlobalVar $R$N$MCustomSymbolStrType $N$R$M_TCustomSymbolStrField $N$MCustomSymbolStrFcn $R$N$M$FCustomSymbolStrFcnArg rt$I$N$MCustomSymbolStrBlkIO rtb_$N$MCustomSymbolStrTmpVar $N$MCustomSymbolStrMacro $R$N$MCustomSymbolStrUtil $N$CCustomCommentsFcn DefineNamingRule NoneDefineNamingFcn ParamNamingRule NoneParamNamingFcn SignalNamingRule None
System Model Configuration
32
SignalNamingFcn InsertBlockDesc offInsertPolySpaceComments offSimulinkBlockComments onMATLABSourceComments offEnableCustomComments offInternalIdentifier ShortenedInlinedPrmAccess LiteralsReqsInCode offUseSimReservedNames offReservedNameArray
Table 5.12. SDD_logic Configuration Set.Components(8).Components [30](2)
Property ValueName TargetDescription Components IsERTTarget offTargetFcnLib ansi_tfl_tmw.matTargetLibSuffix TargetPreCompLibLocation GenFloatMathFcnCalls NOT IN USETargetLangStandard C89/C90 (ANSI)TargetFunctionLibrary NOT IN USECodeReplacementLibrary NoneUtilityFuncGeneration AutoERTMultiwordTypeDef System definedERTMultiwordLength 256MultiwordLength 2048GenerateFullHeader onInferredTypesCompatibility offGenerateSampleERTMain offGenerateTestInterfaces offModelReferenceCompliant onParMdlRefBuildCompliant onCompOptLevelCompliant onConcurrentExecutionCompliant onIncludeMdlTerminateFcn onCombineOutputUpdateFcns off
System Model Configuration
33
CombineSignalStateStructs offSuppressErrorStatus offERTFirstTimeCompliant offIncludeFileDelimiter AutoERTCustomFileBanners offSupportAbsoluteTime onLogVarNameModifier rt_MatFileLogging onMultiInstanceERTCode offCodeInterfacePackaging Nonreusable functionSupportNonFinite onSupportComplex onPurelyIntegerCode offSupportContinuousTime onSupportNonInlinedSFcns onSupportVariableSizeSignals offParenthesesLevel NominalCastingMode NominalGenerateClassInterface offModelStepFunctionPrototypeControlCompliant offCPPClassGenCompliant onGRTInterface onGenerateAllocFcn offUseToolchainInfoCompliant onGenerateSharedConstants onExtMode offExtModeStaticAlloc offExtModeTesting offExtModeStaticAllocSize 1000000ExtModeTransport 0ExtModeMexFile ext_commExtModeMexArgs ExtModeIntrfLevel Level1RTWCAPISignals offRTWCAPIParams offRTWCAPIStates offRTWCAPIRootIO offGenerateASAP2 offMultiInstanceErrorCode Error