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Q8. Explain the 8288 Bus controller.For reasons of simplicity, flexibility, and low cost, mostmicrocomputers,including those involving multiprocessor configurations, are built

around aprimary system bus which connects all of the major components in thesystem. In

order to obtain a foundation while designing its products, amicrocomputermanufacturer makes assumptions about the bus that is tobe used to connect its devices together

Frequently, these assumptionsbecome formalized and constitute what is referred to as abus standard

The Intel MULTIBUS has gained wide industrial acceptance and severalmanufacturers offerMULTIBUS-compatible modules. This bus is designedto support both 8-bit and 16-bit

devices and can be used in multiprocessor systems in which several processors can

be masters. At any point in time,only two devices may communicate with each other overthe bus, onebeing the master and the other the slave. The master/slave relationship isdynamic

with bus allocation being accomplished through the bus allocation(i.e., request/grant) control

signals. The MULTIBUS has been physicallyimplemented on an etched backplane boardwhich is connected to eachmodule using two edge connectors, denoted PI and P2, I shown inFig.9.13. The connector P1 consists of 86 pins which provide-the major bussignals, and P2 is an

optional connector consisting of 60 auxiliary lines,primarily used for power failure detection

and handling.

Fig. 9.13: Illustration of a module being plugged into MULTIBUS

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The P1 lines can be divided into the following groups according to their functions:1. Address

lines.2. Data lines.3. Command and handshaking lines.4. Bus access control lines.5. Utilitylines.T h e M U L T I B U S h a s 2 0 a d d r e s s l i n e s , l a b e l e d t h r o

u g h , w h e r e t h e numeric suffix represents the address bit in hexadecimal. The address

linesare driven by the bus master to specify the memory location or I/O portbeing accessed..The MULTIBUS standard calls for all single bytes to becommunicated over only the lower 8

bits of the bus; therefore, any 16-bitinterface must include a swap byte buffer so that only thelower data linesare used for all byte transfers. (It should be pointed out that because

an8086 expects a byte to be put on the high-order byte of the bus when isactive, onemay want to permit nonstandard MULTIBUS transfers betweenmemory and an 8086.)The

two inhibit signals are provided for overlaying RAM, ROM, andauxiliary ROM in a common

address space. For example, a bootstraploader may be stored in an auxiliary ROM and amonitor in a ROM.Because the loader is needed only after a reset, and could both beactivated

while the loader is executing.Then, when the monitor is in

control,could be raised while remains low. If control is passed to the user,and could both be deactivated, thus allowing the RAM to fill theentire memory space during normaloperation.T h e r e a r e 1 6 b i d i r e c t i o n a l d a t a l i n e s ( -

) , o n l y e i g h t o f w h i c h a r e used in an 8-bit system. Data transfers on

the MULTIBUS bus areaccomplished by handshaking signals in a manner similar to thatdescribedi n t h e p r e c e d i n g s e c t i o n s .

T h e m e m o r y r e a d ( ) , m e m o r y w r i t e ( ) ,

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I / O r e a d ( ) , a n d I / O w r i t e ( ) l i n e s a r e d e f i n e d

t o b e t h e s a m e a s t h e y were in the discussion of the 8288 buscontroller. There is an acknowledge() s i g n a l w h i c h s e r v e s t h e s a m e

p u r p o s e a s t h e R E A D Y s i g n a l i n t h e discussion of the bus controllogic, i.e., to verify the end of a transfer. In ageneral setting it may be received by bus

master. Because a master mustwait to be notified of the completion transfer, the duration of abus cyclevaries depending on the speed of the bus master and the slave. Thisasynchronousnature enables the system to handle slow devices withoutpenalizing fast devices