PWM - matrix.senecacollege.cageorge.vande-belt/MCO556/PDFs/PWM.pdfMCO556 - 2 – Seneca College –...
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MCO556 - 1 – Seneca College – School of Information and Communications Technology - 113 Slide 1 MCO556 Pulse Width Modulation ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ____________________________________________________________________
Transcript of PWM - matrix.senecacollege.cageorge.vande-belt/MCO556/PDFs/PWM.pdfMCO556 - 2 – Seneca College –...
MCO556
- 1 – Seneca College – School of Information and Communications Technology - 113
Slide 1
MCO556
Pulse Width Modulation
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MCO556
- 2 – Seneca College – School of Information and Communications Technology - 113
Slide 2
2
PWM
Pulse width modulation (PWM) is a method
of varying the average voltage of a square
wave by varying the duty cycle.
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MCO556
- 3 – Seneca College – School of Information and Communications Technology - 113
Slide 3
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PWM
Period = Low_Time + High_Time
Frequency = 1 / Period
Duty_Cycle = 100% x High_Time/Period
Average_Voltage = Duty_Cycle x (High_Voltage
- Low_Voltage) + Low_Voltage
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MCO556
- 4 – Seneca College – School of Information and Communications Technology - 113
Slide 4
4
1 kHz 50% Duty Cycle
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MCO556
- 5 – Seneca College – School of Information and Communications Technology - 113
Slide 5
5
1 kHz 50% Duty Cycle
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MCO556
- 6 – Seneca College – School of Information and Communications Technology - 113
Slide 6
6
1 kHz 50% Duty Cycle
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MCO556
- 7 – Seneca College – School of Information and Communications Technology - 113
Slide 7
7
1 kHz 25% Duty Cycle
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MCO556
- 8 – Seneca College – School of Information and Communications Technology - 113
Slide 8
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PWM with Filtering
PWM with filtering acts like a D/A converter.
This type of D/A conversion has a step
response that is a function of the RC
filtering time constant.
The tradeoff is that with more filtering, the
step response is slower.
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MCO556
- 9 – Seneca College – School of Information and Communications Technology - 113
Slide 9
9
HCS12 PWM
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MCO556
- 10 – Seneca College – School of Information and Communications Technology - 113
Slide 10
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Configure 7 Registers
PWMPRCLK - clock B and clock A prescale_factor
PWMPOL - output or low / high at start of
PWMCAE - left or centre aligned
PWMCTL - halt PWM clock in wait or freeze modes
PWMPER0 - period;
PWMDTY0 - duty cycle
PWME - enable PWM channel
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MCO556
- 11 – Seneca College – School of Information and Communications Technology - 113
Slide 11
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RegistersPWM Prescale Clock Select Register (PWMPRCLK)
PWM Polarity Register (PWMPOL)
PWM Center Align Enable Register (PWMCAE)
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MCO556
- 12 – Seneca College – School of Information and Communications Technology - 113
Slide 12
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Registers
PWM Control Register (PWMCTL)
PWM Channel Period Registers (PWMPERx)
PWM Channel Duty Registers (PWMDTYx)
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MCO556
- 13 – Seneca College – School of Information and Communications Technology - 113
Slide 13
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PWME
PWMEn — Pulse Width Channel n Enable
1 = channel n enabled. Output on PORT P.n
0 = channel n disabled.
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MCO556
- 14 – Seneca College – School of Information and Communications Technology - 113
Slide 14
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PWMPRCLK
PCKB2 - PCKB0 : Prescaler Select for Clock B
PCKA2 - PCKA0 : Prescaler Select for Clock A
Clock x Prescaler Selects
PCKx2 PCKx1 PCKx0 Value of Clock x
0 0 0 bus clock
0 0 1 bus clock / 2
0 1 0 bus clock / 4
0 1 1 bus clock / 8
1 0 0 bus clock / 16
1 0 1 bus clock / 32
1 1 0 bus clock / 64
1 1 1 bus clock / 128
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MCO556
- 15 – Seneca College – School of Information and Communications Technology - 113
Slide 15
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PWMPOL
PPOL7 — Pulse Width Channel n Polarity
1 = output is high at beginning
goes low when the duty count is reached.
0 = output is low at beginning
goes high when the duty count is reached.
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MCO556
- 16 – Seneca College – School of Information and Communications Technology - 113
Slide 16
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PWMCAE
1 = Center Aligned Output Mode.
0 = Left Aligned Output Mode.
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MCO556
- 17 – Seneca College – School of Information and Communications Technology - 113
Slide 17
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PWM Left Aligned Output
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MCO556
- 18 – Seneca College – School of Information and Communications Technology - 113
Slide 18
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PWM Center Aligned Output
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MCO556
- 19 – Seneca College – School of Information and Communications Technology - 113
Slide 19
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PWMCTL
CONxy — Concatenate channels x and y
1 = Channels x and y are concatenated to create one 16-bit PWM channel. Channel x becomes the high order byte and channel y becomes the low order byte. Channel y output pin is used as the output for this 16-bit PWM
Channel y bits determine the clock, polarity, output enable, and center aligned mode
0 = Channels x and y are separate 8-bit PWMs.
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MCO556
- 20 – Seneca College – School of Information and Communications Technology - 113
Slide 20
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PWME
PWMEn — Pulse Width Channel n Enable
1 = Pulse Width channel n is enabled. The PWM
signal becomes available at PORT Pn
0 = Pulse Width channel n is disabled.
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MCO556
- 21 – Seneca College – School of Information and Communications Technology - 113
Slide 21
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Example Lab PWM
#include <hidef.h> /* common defines and macros */
#include “derivative.h” /* derivative information */
/* clock A, channel 0 (pin P0) PWM) */
/* change duty cycle in main() by changing PORTH dip switches */
void PWM0open(unsigned char prescale_factor, unsigned char period, unsigned char init_duty);
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MCO556
- 22 – Seneca College – School of Information and Communications Technology - 113
Slide 22
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Example Lab PWM
void main(void)
{DDRH=0x00; /* data direction register PORTH as input */
PERH=0xFF; /* set pull up/down on PORTH */
DDRB=0xFF; /* enable output for LEDs */
PWM0open(0x03,255,0); /* initialize PWM */
/* prescale to divide by 8 results in 1MHz clock or 1 usec per pulse */
/* period of 255 is 255 usec */
while(1)
{PWMDTY0=PTH; /* set duty cycle using PORTH (PTH) dip switches */
PORTB=~PWMDTY0;
}
}
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MCO556
- 23 – Seneca College – School of Information and Communications Technology - 113
Slide 23
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Example Lab PWM/* clock A, channel 0 (pin P0) PWM) */
void PWM0open(unsigned char prescale_factor, unsigned charperiod, unsigned char init_duty)
{PWMPRCLK = prescale_factor; /* choose 8-bit PWM, and set clock A
prescaler to prescale_factor */
PWMPOL |= 0x01; /* channel 0 polarity high then low */
PWMCAE &= ~0x01; /* select left-aligned */
PWMCTL = 0x80; /* 8 bit counter, allow clock to continue in wait mode and PWM to continue in freeze mode*/
PWMPER0 = period; /* set period of PWM 0 to 2.55 ms,
1/(bus clock / prescale_factor) * period */
PWMDTY0 = init_duty; /* set duty cycle to init_duty/period *100% */
PWME |= 0x01; /* enable PWM channel 0 */
}
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