7/30/2019 Put Ecs301 Mm

1/2

Name: Roll No: ..

ABES Institute of Technology

(ECS-301 DIGITAL LOGIC DESIGN)

2ND YEAR (11CS & 11IT)

PRE UNIVERSITY EXAMINATION (ODD SEMESTER 2012-13)

Time: 3.00 hrs. Max. Marks: 100

Note: The question paper contains three Sections. All Sections are compulsory.

PART A

(2 10= 20)

Attempt all questions. All questions carry equal marks.

1. 1. Perform the BCD Operations : (i) 954 + 463 (ii) 8936472. How is 2s complement representation advantageous for adder circuit design.3. 3.Determine Base X for the equality : (211)X = (152)84. Implement EX-OR gate with NAND gates only.5. Convert (i) (82.35)10 to Base 4 number system and (ii) (0.625)10 to a binary number.6. Explain the difference between a latch and a flip-flop.7. Design a Full Adder using NOR gates.8. 8.What is Race Around Condition. Explain in brief.9. Explain briefly how the ASM chart differs from the conventional flow chart.10.Briefly describe the various types of ROMs.

PART B

(6 5 = 30)

Attempt All questions. All questions are of equal marks.

11.What are the different techniques for representing signed numbers. Explain giving examples.12.Design a two digit BCD adder using 4-bit binary adders.13.What are hazards. Explain static 0 , static 1 and dynamic hazards with examples. How can

we remove hazards.14.Draw a bi directional shift register and explain its functioning.15.Design a Mod 13 Parallel counter using JK Flip Flops.

7/30/2019 Put Ecs301 Mm

2/2

PART C

(5 10= 50)

Attempt all the five questions. All questions are of equal marks.

16.Design a Gray to BCD code converter using 1:16 demultiplexer (active low output).OR

(i) Design a 16 X 8 memory using a 16 X 4 memory units.(ii) Differentiate between Programmable Array Logic (PAL) and Programmable Logic

Arrays (PLA)

17.What is the difference between encoder and decoder. Design a 4bit priority encoder with inputs as given table. Here D0 has thehighest priority and D3 has the Lowest priority.

OR

Convert (i) a D FF into a JK FF and (ii) a T FF into a D FF

18.Discuss the race around condition and its solution. Also discussthe state reduction technique. OR

Derive the transition table and output map for the asynchronous sequential circuit describedby the following functions Y = X1X2 + (X1 + X2)Y Z = Y. also describe in words the

behavior of the circuit.

19.what are critical and non critical races. How can they be avoided. Design an JK Flip FlopAsynchronous sequential circuit having two inputs and a single output. The circuit is requiredto give an output of1 if and only if the same input variable changes two or more times

consecutively.

OR(i) design a full subtractor using a 1:8 demultiplexer.

(ii) design a 2 bit magnitude comparator.

20.(i) Distinguish between static and dynamic RAM. Also draw Static RAM cell.(ii) Implement the Boolean function using 8:1 multiplexer. F(A,B,C) = m(0,2,4,6,7,11,13)

OR

Design a circuit that implements the state diagram shown using JK flip flops.