PSG / PSBU / Wide Format

P09141

Satellite Thermal Heater ControllerDetailed Design Review Package Electrical

Document Revision: 03

Document Date: 02/12/2009

Table of Contents

2Table of Contents

31Introduction

31.1Vision

31.2Background

31.3Objectives

31.4Deliverables

31.5Expected Project Benefits

31.6Core Team Members

42Strategy & Approach

42.1Assumptions & Constraints

42.2Issues & Risks

53System Level Architecture

74Communications

74.1Interface Board

154.1Protocol

175Microcontroller Programming

196Slave to HHC Interface

1 Introduction

1.1 Vision

The mission of this project is to design, build and test a scalable prototype of a thermal heater controller for the Space Systems Division of ITT. The controller will be subsystem in future satellite-imaging systems.

1.2 Background

The Satellite Thermal Heater Controller (STHC) is a single master multiple slave system that can be arrayed in a distributed fashion with centralized control. The system can be described as a group of distributed, autonomous thermal control units that share the same power input, which will also serve for communication. This controller may be used in satellite applications to control the temperature of critical optical subsystems.

1.3 Objectives

1. Demonstrate an enhancement to ITT's current distributed autonomous thermal controller.

2. Create a more competitive thermal controller that is lightweight, scalable, modular, reliable, cost effective and power efficient.

3. Demonstrate the ability to thermally control, stabilize and enable critical optical subsystems.

4. Selecting components that will minimize power consumption, weight and cost, respectively.

5. Achieve communications between the master and slaves through the DC power line.

6. Program DSP for efficient communication between master and slaves.

7. Connect DSP to heater controller to communicate between slaves and heater controllers.

8. Design HHC enclosure to meet vibration, thermal conductivity, EMI, and venting specs.

1.4 Deliverables

1. Interface electronics to send information between the master and slave DSP board over heater power bus.

2. PC interface that communicates with master over serial line.

3. Programming of master to accept requests from the PC and pass them on to slave

4. Programming of slave to control HHC and send status back to master.

5. PC GUI to monitor and control the temperature and state of (2) heater controllers.

1.5 Expected Project Benefits

1. The STHC shall be used as a basis for future heater control systems launched and deployed in space by ITT to regulate the temperature of a variety of satellite payloads.

2. The STHC might be used by other groups that are involved in satellite imaging applications.

3. Reinforce the engineering programs at RIT.

1.6 Core Team Members

1. Anthony Berwin

2. Scott Rioux

3. Greg Pawlowski

4. Sarmad Abedin

5. John Scipione

2 Strategy & Approach

2.1 Assumptions & Constraints

1. There is a time constraint of 22 weeks where the project must be completed.

2. Lead times for parts components and materials. Incorporate lead times into scheduling.

3. Lead time for printed circuit boards. Incorporate lead times into scheduling.

4. Controller from the Texas Instruments (28x family).

5. Access to the Hybrid Heater Controller (HHC) Specifications.

2.2 Issues & Risks

Acquiring DSP

Must have by February 23, 2009 Buy one ourselves, msp430,

Acquiring HHC

Must have by February 23, 2009

Acquiring Equipment specs

Must have by February 23, 2009

Programming Difficulty

Consultation with faculty and advisors

Protocol Communication difficulty

Consultation with faculty and advisors

Hardware modulation

Consultation with Professionals

Equipment Failure

Buy new stuff

Changes in customer req

Customer Interaction

Time constraints

Customer Interaction

Testing equipment

Replacing and using new equipment, understand specs

Wake/Sleep Programming

Research and trial and error.

Code Composer Complications

Farther Research and training

Analog to Digital Converter Programming Complications

Further Research and training

Pulse Width Modulator Programming Complications

Further Research and training

3 System Level Architecture

DC POWER

SUPPLY

HEATER POWER BUS 28V +/-8V DC

MASTER

2808 EZDSP

2808 EZDSP2808 EZDSP

Heater Controller

SLAVE1SLAVE2

Interface

Electronics

Interface

Electronics

Interface

Electronics

PC User

Interface

HEATERTHERMISTERTHERMISTERHEATER

Heater Controller

22 AWG wire, 50ft max

25°C +/-0.3°C25°C +/-0.3°C

Serial Cable

Interface

Electronics

Interface

Electronics

Figure 3.1: System Level Architecture

Project Mission

PC User interface to control and monitor the operations of the master from a desktop computer.

Interface electronics to utilize the 28V +/- 8V DC Power bus line and apply a carrier of 10mV RMS AC signal via an FSK modulator and demodulator connected to a line-driver and transformer.

Interface electronics between the slave and heater controller.

Not responsible for creating the DC Power supply, the AC/DC Converter, the 2808 EZDSPs, the heater power bus, the AC Power Bus, the heater controllers, the thermister, the heater, or the payload.

4 Communications

In this section communication between the master and slave microcontrollers is examined.

4.1 Interface Board

Relavent Specs:

Spec No.

Source

Description

Unit of Measure

Marginal Value

Ideal Value

2

3.2, 3.3

Bus voltage

V

20 to 36

28

4

3.3

Master slave measurement time

ms

1 to 20

1

5

3.3

Time to wake slave

ms

1 to 20

1

15

3.3

Communications bandwidth

Hz

<300K

12804 to 100K

16

3.3

Bit error rate

%

0 to 1e-4

0

17

3.3

S/N Ratio

dB

-40

>-40

18

3.3

Transmitted signal amplitude over the power bus

mV RMS

1 to 10

1

19

3.3

Power bus wire thickness

AWG

22+

22

20

3.3

Power bus wire length

ft

<50

20

21

3.7.2, 3.8.1

EMI leak threshold

KHz

<100

<100

U1

OPAMP

+

-

OUT

0

0

R1

1k

R2

1k

C1

4.1n

V1

FREQ = 200k

VAMPL = 10m

VOFF = 0

0

C2

2.05n

U2

OPAMP

+

-

OUT

R4

100

R5

15kk

V2

5

U3

OPAMP

+

-

OUT

0

R3

1k

R7

1k

C3

1.5n

C4

.75n

0

U5

OPAMP

+

-

OUT

R10

100

R12

10

0

R11

100

R13

5.6k

R14

1k

U4

OPAMP

+

-

OUT

0

R8

1k

R9

1k

C5

1.1n

C6

.55n

V

V

V

U1

OPAMP

+

-

OUT

0

0

R1

1k

R2

1k

C1

4.1n

V1

FREQ = 200k

VAMPL = 10m

VOFF = 0

0

C2

2.05n

U2

OPAMP

+

-

OUT

R4

100

R5

15kk

V2

5

U3

OPAMP

+

-

OUT

0

R3

1k

R7

1k

C3

1.5n

C4

.75n

0

U5

OPAMP

+

-

OUT

R10

100

R12

10

0

R11

100

R13

5.6k

R14

1k

U4

OPAMP

+

-

OUT

0

R8

1k

R9

1k

C5

1.1n

C6

.55n

V

V

V

Figure 4.1.1 Demodulator (Receive) Electronics

This is the receive side of the interface board. It uses a sixth-order butterworth filter to filter out any high frequency noise in the signal. Then there is a gain stage of 150 which leads to an 1.5V DC offset stage to go to the analog to digital converter.

Time

0s50us100us150us200us250us300us350us400us

V(U4:OUT)V(R2:1)

-10mV

0V

10mV

V(U5:OUT)

0V

1.0V

2.0V

3.0V

SEL>>

Figure 4.1.2 Waveforms of the Received Signal with a 20 kHz frequency (logic level 0)

Figure 4.1.2 shows the waveforms entering the receive stage and exiting the filter stage on the bottom and shows the waveform of the output after amplification and 1.5V DC offset.

Time

0s50us100us150us200us250us300us350us400us

V(U4:OUT)V(R2:1)

-10mV

0V

10mV

V(U5:OUT)

0V

1.0V

2.0V

3.0V

SEL>>

Figure 4.1.3 Waveforms of the Received Signal with a 30 kHz frequency (logic level 1)

Figure 4.1.3 Shows the same thing for 30kHz input signal

Time

0s5us10us15us20us25us30us35us40us45us50us

V(U4:OUT)V(R2:1)

-10mV

0V

10mV

V(U5:OUT)

1.4V

1.6V

1.8V

SEL>>

Figure 4.1.4 Waveforms of the Received Signal with a 200 kHz frequency

Figure 4.1.4 shows the same thing for a 200kHz input signal. After filtering and amplification and offset the signal is less than 10mVpp RMS.

R8

4.7k

R10

4.7k

C7

2.5n

C8

2.5n

0

C9

1n

V

V

V

U1

OPAMP

+

-

OUT

0

R1

1k

R2

1k

C1

4.1n

0

C2

2.05n

U3

OPAMP

+

-

OUT

0

R3

1k

R7

1k

C3

1.5n

C4

.75n

U4

OPAMP

+

-

OUT

0

R9

1k

R11

1k

C5

1.1n

C6

.55n

V1

TD = 0.1p

TF = 0.1p

PW = 5u

PER = 10u

V1 = 3.3v

TR = 0.1p

V2 = 0

R12

1k

0

R8

4.7k

R10

4.7k

C7

2.5n

C8

2.5n

0

C9

1n

V

VV

U1

OPAMP

+

-

OUT

0

R1

1k

R2

1k

C1

4.1n

0

C2

2.05n

U3

OPAMP

+

-

OUT

0

R3

1k

R7

1k

C3

1.5n

C4

.75n

U4

OPAMP

+

-

OUT

0

R9

1k

R11

1k

C5

1.1n

C6

.55n

V1

TD = 0.1p

TF = 0.1p

PW = 5u

PER = 10u

V1 = 3.3v

TR = 0.1p

V2 = 0

R12

1k

0

Figure 4.1.5 Modulator (Transmit) Electronics

Figure 4.1.5 shows the transmit electronics. The input comes from the PWM from the DSP and goes through a passive low-pass filter to generate a sinusoidal signal which then goes through a set of low-pass filter to filter out any harmonics.

Time

0s50us100us150us200us250us300us350us400us450us500us550us600us

V(C9:1)

-80mV

-40mV

0V

40mV

V(V1:+)V(R2:2)

0V

2.0V

4.0V

SEL>>

Figure 4.1.6 Waveforms of the Transmitted Signal with a 20 kHz frequency (logic level 0) from the PWM

The top graph shows the PWM signal and then the sinusoidal after going through the passive low pass filter. The bottom graph shows the output signal after active filtering.

Time

0s50us100us150us200us250us300us350us400us450us500us550us600us

V(C9:1)

-50mV

0V

50mV

V(V1:+)V(R2:2)

0V

2.0V

4.0V

SEL>>

Figure 4.1.7 Waveforms of the Transmitted Signal with a 30 kHz frequency (logic level 1) from the PWM

The top graph shows the PWM signal and then the sinusoidal after going through the passive low pass filter. The bottom graph shows the output signal after active filtering.

ADC

PWM

S2

D2

In1

Vdd

GND

In2

D1

S1

ADG823

5Vdd

u

u

Tx

Rx

V1

28Vdc

C2

.1u

TX2

0

0

0

ADC

PWM

S2

D2

In1

Vdd

GND

In2

D1

S1

ADG823

5Vdd

u

u

Tx

Rx

V1

28Vdc

C2

.1u

TX2

0

00

Figure 4.1.8 Modulator/Demodulator switching circuit

Figure 4.1.8 shows the modulator/demodulator switching circuit that will switch from Rx to Tx when In1 and In2 (tied together) are switch from 0 to 1. If the input is 0 the signal is modulated and when it is 1 the signal is demodulated.

The only path of communication between the master and slave electronics is through the 22AWG heater power bus that is used to power the heater controllers. It is marked as HEATER POWER BUS on the System Level Block Diagram (Figure 3.1) above. It is impossible to directly send the DC voltage levels over the power bus because it would interfere with the operation of the heater controller, would be extremely slow, and would be highly susceptible to line noise. Instead, FSK modulation is used to encode the bits into carrier frequencies which is send over the power bus. Provided that the signal generated is kept at an amplitude less than 10mVpp RMS there will be no interference with the heater electronics. In order to modulate and demodulate the communication signal an interface board is necessary to take the TTL logic levels coming from the microcontrollers and convert them into the appropriate FSK frequencies and vice-versa.

The 28V DC power source on the left in Figure 4.1 above represents the power supply for the heater controllers marked DC Power Supply in Figure 3.1. Capacitor C2 blocks the DC voltage and only allows AC signals to pass. The TX2 transformer is a 0.4mH coupling transformer that in conjunction with C2 yields a 25KHz pass-band filter. The pass-band filter will filter out any frequencies that are not in the bandwidth needed for the signal frequencies. The AC signal filtered out by the coupling transformer and capacitor goes into the ADG823 CMOS switch which will switch between transmit and receive signals coming from the master and slave microcontrollers. The input marked ‘u’ represents inputs coming the microcontrollers. Op-Amps U1 and U3 act as low-pass filters that filters out any frequencies above 20KHz. Op-Amp U2 acts as an inverting amplifier which amplifies the 10mVpp RMS amplitude into a 0V to 3V amplitude needed for the ADC.

0

V1

28Vdc

R8

1k

0

0

V2

FREQ = 25000

VAMPL = 10m

VOFF = 0

R9

100

R11

100

C5

5.627nf

C6

10.25nf

U3

OPAMP

+

-

OUT

V

V

V

C1

.1u

C2

.1u

R1

100

TX1

TX2

R4

100

0

0

R5

100

C3

5.627nf

C4

10.25nf

R10

10

U1

OPAMP

+

-

OUT

R12

10

U2

OPAMP

+

-

OUT

R6

100

R7

27k

0

V1

28Vdc

R8

1k

0

0

V2

FREQ = 25000

VAMPL = 10m

VOFF = 0

R9

100

R11

100

C5

5.627nf

C6

10.25nf

U3

OPAMP

+

-

OUT

VV

V

C1

.1u

C2

.1u

R1

100

TX1

TX2

R4

100

0

0

R5

100

C3

5.627nf

C4

10.25nf

R10

10

U1

OPAMP

+

-

OUT

R12

10

U2

OPAMP

+

-

OUT

R6

100

R7

27k

Figure 4.1.9 Test Circuit for Simulations

Time

0s50us100us150us200us250us300us350us400us450us500us550us

V(U3:OUT)V(R1:1)

-20mV

0V

20mV

V(R8:2)

-4.0V

0V

4.0V

SEL>>

Figure 4.1.10 Graph of Transmit and Receive

The capacitor C1 and C2 and the transistors TX1 and TX2 of figure 4.1.6 form a band pass filter, with a cut off frequency of 25 kHz. This frequency was chosen because it is the average of the two signals being sent to the power bus to represent 0 and 1. The bottom graph of figure 4.1.7 shows the transmitted signal which is 10 mV peak to peak; the received signal is slightly higher than the 10 mV. The top graph of figure 7 shows the amplified signal which is almost at 4 volts, this is larger than the ADC’s full scale output. The transmit frequencies will be filtered by the LC filter.

Time

0s50us100us150us200us250us300us350us400us450us500us550us

V(U3:OUT)V(R1:1)

-20mV

0V

20mV

V(R8:2)

-4.0V

0V

4.0V

SEL>>

Figure 4.1.11 Waveforms of Transmit and Receive for 20 kHz

Figure 4.1.8 shows the transmitted and received signals. The transmitted signal is the 10mV signal of the bottom graph. The other signal on the bottom graph is on the receive side; it is slightly smaller in amplitude as the transmitted signal and the amplified signal is at about 3.0V.

Time

0s50us100us150us200us250us300us350us400us450us500us550us

V(U3:OUT)V(R1:1)

-20mV

0V

20mV

V(R8:2)

-4.0V

0V

4.0V

SEL>>

Figure 4.1.9 Waveforms of Transmit and Receive for 30 kHz

Figure 4.1.9 shows the transmitted and received signals. The transmitted signal is the 10mV signal of the bottom graph. The other signal on the bottom graph is on the receive side; you can see it has a smaller amplitude, and then the amplified signal is at about 2.4V.

4.2 Protocol

Relavent Specs:

Spec No.

Source

Description

Unit of Measure

Marginal Value

Ideal Value

4

3.3

Master slave measurement time

ms

1 to 20

1

5

3.3

Time to wake slave

ms

1 to 20

1

6

3.3.4

Communication protocol length

bits

24 to 64

24

Master-Slave Communication Protocol Explanation for the STHC, 32-bit wide

Note: S=from Slaves point of view

M=from Masters point of view

Bits

Description

Values

B0-B1

Start indicator

B0 and B1 must both be zero in order for the transmission to begin.

B2-B9

Slave ID number

00000000 to 11111111 (256) (The master receives the Slave ID number to indicate which slave is contacting it).

B10

Tx/Rx bit

S:’1’= Another slave is talking to master (discard Msg); ’0’=master talking to the slave (ID number in B2-B9). M:’1’= slaves response to a given order; ‘0’= Msg received by slave.

B11

Zone

‘1’: Zone 1 of HHC is initiated; ‘0’: Zone 2 is initiated

B12

Read/Set

Read=’0’ Set=’1’

B13

Temp/Heater State

’1’= Read/set Temp;’0’= Read telemetry* or set Heater state

B14

Read what?

‘1’=Read telemetry; ‘0’=Read both (telemetry/ temp)

B15

Vdd state(telemetry(tlm) pin)

’1’= on; ’0’= off (slave reads the V on assigned pin and reports back to the master)

B16

Bus voltage(tlm pin)

’1’= on; ’0’= off (slave reads the V on assigned pin and reports back to the master)

B17

Heater state (tlm pin)

’1’= on; ’0’= off (slave reports whether the heater is ‘on’ or ‘off’)

B18

Thermistor (tlm pin)

’1’= driving the thermister with a new voltage to turn heater on; ’0’=no operation

B19

Transistor gate(telemetry pin)

’1’= on; ’0’= off (reads the state of the transistor, can be used for debugging issues. If this pin is ‘0’ and heater is still on then there is a problem in between the transistor and the heater itself)

B20-B31

Temp Value

-40C to 55C res=0.0232C

B32-B37

Checksum

Contains the number of ‘1’s that should be in the msg. This value is compared with a counter which counts the number of 1’s in the msg. If they are equal then the message is correct, otherwise the msg is discarded.

B38

Stop bit

Must be ‘0’ or the message will be discarded.

Table 4.2: Communication Protocol

Communication is bidirectional, but only the master or slave can communicate at any time (half-duplex). The master sends out requests to a slave and then waits for a response for 2ms. If it does not receive a response from the slave in the response time window that probably means there was an error so it resends the message to the slave and waits another 2ms for a response. The slave never sends to the master unless asked first. The master will continue to send messages out to the slave until it gets a response. However, if the master sends five consecutive messages to the slave and does not get a response than it assumes that the slave is not working. The master cannot reset the slave so at this point the slave is effectively dead.

In order to send a message the master or slave first waits for a start indicator of 00. When the master or slave receive a start indicator than the master or slave store the next 36 bits into some registers. B38 is checked to make sure that it is set to ‘0’ which indicates a complete message was received. B2-B9 are checked to see if the message is intended for the slave of that ID number in the case of a transmit, or indicates the slave number that sent the message in the case of a receive. Then the master/slave checks B10 to see if the message is for them--if B10=0 the message is intended for the slave, if B10=1 the message is intended for the master. Next the checksum is checked. The numbers of ones in B2-B31 are added up and the integer value of the sum is compared against the integer value of the checksum. If the sums match then the signal is valid. B38 is checked next to ensure that the whole message was received (must be zero).

Calculation of the Carrier Frequency:

Given: 20mS is the time limit in which the master must send and receive back the appropriate data.

(Eq. 1 (to find the total number of bits that are being transferred))

(Eq.2 (in order to find sec/bit))

(Eq.3 (doubling ‘0’s carrier freq.))

Carrier frequency for a ‘0’ bit= 20KHz (must be a multiple of 5 KHz)

Carrier frequency for a ‘1’ bit= 30KHz (must be a multiple of 5 KHz)

5 Microcontroller Programming

In this section microcontroller programming is discussed.

The master and each slave are controlled by a TI3200F2808 Microcontroller. The TI3200F2808 microcontroller contains 16 PWM used to do modulation and demodulation. Each slave microcontroller is connected to a heater controller (HHC) and is responsible for reading and setting temperature and state information on that heater. The protocol detailed in section 4.2 above is utilized to command the heater to perform the designated task.

The code used in for this task comes from

Using PWM Output as a Digital-to-Analog Converter on a

TMS320F280x Digital Signal Controller

David M. Alter DSP Applications – Semiconductor Group

http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractName=spraa88a

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6 Slave to HHC Interface

EzDSP

VG1

VG2

+PWR_MON

VDD_MON

V2SEST

J3_ID

J3

MicroD 15-P

1

9

2

10

3

11

4

12

5

13

6

14

7

15

8

SHLD

+PWR_RTN

RTHM1

+PWR_RTN

RTHM2

V2COMP+

HTR1_MON

HTR2_MON

V1COMP+

V1SET

P9

Rx1

3

5

7

9

11

13

15

17

19

2

4

6

8

10

12

14

16

18

20

RTHM1

RTHM2

Ref

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

VG1

VG2

HTR1_MON

HTR2_MON

+PWR_MON

VDD_MON

P8

DB9

P10

To PC GUI

+PWR_RTN(4)

+PWR_RTN(12)

Tx

Vset1

Vset2

Vcomp1

Vcomp2

P9 is Analog Interface. Pins 1-19 are all ground pins. 1 and 19 are connected to grounds on the HHC. Pins 2, 4, 6 are all connected to the analog to digital converter. Pin 18 is a reference voltage that comes from the HHC and is used with the analog to digital converter to detect temperature changes. J3 is the analog connector on the HHC.

P8 is the I/O Interface. Pins 5, 6, 7, 8, 10, 12, 13, 22, 23, 25, and 34 are all GPIO pins

P10 is the 2x5 SCI-B Header. It is connected via a serial cable to the PC.

PAGE

1

_1295963619.vsd

Interface Electronics

DC POWER SUPPLY

PC User Interface

HEATER POWER BUS 28V +/- 8V DC

Interface Electronics

MASTER

2808 EZDSP

2808 EZDSP

2808 EZDSP

Heater Controller

Heater Controller

SLAVE1

SLAVE2

InterfaceElectronics

Interface Electronics

InterfaceElectronics

HEATER

HEATER

THERMISTER

�

THERMISTER

22 AWG wire, 50ft max

25°C +/- 0.3°C

25°C +/- 0.3°C

Serial Cable

_1295953399.vsd

EzDSP

P9

Rx

135791113151719

2468101214161820

RTHM1

RTHM2

Ref

13579111315171921232527293133353739

246810121416182022242628303234363840

VG1

VG2

HTR1_MON

HTR2_MON

+PWR_MON

VDD_MON

P8

DB9

P10

To PC GUI

+PWR_RTN(4)

+PWR_RTN(12)

Tx

Vset1

Vset2

Vcomp1

Vcomp2