Prospect and Plan for IRS3B Readout - University of Hawaiiidlab/taskAndSchedule/... · Prospect and...
Transcript of Prospect and Plan for IRS3B Readout - University of Hawaiiidlab/taskAndSchedule/... · Prospect and...
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Prospect and Plan for IRS3B Readout
Toru IijimaAug. 21, 2013 KEKB Steering Committee report
1. Progress on Key Performance Parameters
2. Understanding limitations during LEPS operation
3. Carrier02 Rev. C (with O-E-M improvements)
4. Pre-production tasks/schedule
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IRS3B-based Readout Overview
8k channels1k 8-ch. ASICs
64 SRM “board stacks”
64 DAQ fiber transceivers
32 FINESSE8 COPPER
FTSW clock, trigger, programming
Waveform sampling ASIC
Clock jitter cleaners
64 SRM
8 COPPER
32 FINESSE
UT3 Trigger module
16 FTSW
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Executive Summary• After commissioning/learning period, now obtaining electronics resolutions commensurate with stated minimum requirements (<100ps timing)
• Still room to improve: Processing: timebase cal, leading edge timing extraction Board improvements: sampling timebase, gain, risetime
• Rev. C Carrier boards [improved mechanics, amplifiers, signal coupling] being assembled, testing soon
• IRS3C [extended dynamic range] due this week
• Details in subsequent slides3
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Board Stack #37 single photon timing, no ADC cuts, no modifications from LEPS configuration
106/128 channels(some missing to be added –missed first pass)
<100ps average once CAMAC contribution removed (not relevant for Belle II)
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As understood from simulation
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Channels within same ASIC similar –common timing/timebase issue
If dominated by DAC/VadjN jitter, should see clear dependence…6
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And it is clearly observed
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Example channel
Ensemble distribution, No ADC cuts
Probably a combination of jitter (noise on VadjN) and coarseness of DAC [under study]
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Pedagogical slides about timing…• Space-time correlations
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Beam Test Data
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• For large amplitude, corresponding to the tight cuts applied, and assuming (“120ps” width)…
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About LEPS timing current status… (work in progress)
Sqrt([120ps]2 + [100ps] 2) ~ 156 ps
Electronics contribution
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Performance Requirements (TOP)• Single photon timing for MCP-PMTs
σ ~ 38.4ps
σ <~ 10ps(ideal waveform
sampling)
NIM A602 (2009) 438
σ <= 100ps 1% impact
σ <~ 50ps target
To include T0, clock distrib, timebase ctrl
NOTE: this is single-photon timing, notevent start-time “T0”
σT0 = 25ps
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• 100ps is min. required for Key Performance Parameters (50ps target)
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Electronics contribution
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TOP Electronics Production Schedule
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Install and operate completed modules in Fuji CRT
3+ TOP modules of readout possible(when actual modules ready?)
Window for a “final electro-mech-optical” qualification beam test
Enough ASICs, Rev. C or D (final, dual-stage amp), SCROD Rev. C (?)
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carrier02 revC improvements
received PCBs last weekassembly to begin imminentlywill have assembled boards by end of August
new VadjN/P filtering
new thermal wall connections
new 16 bit DAC with series resistance
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Status and Prospects• Have achieved Key Performance Parameters over entire IRS3B-based readout module used in beam test; this is only minimum, <=50ps looks achievable
•Will fabricate/populate Carrier02 [IRS3B limited] so can have spares and distribute for testing elsewhere – improved thermo-mechanics
• IRS3C drop-in for IRS3B [extended dynamic range]
• Demonstrate true timing limits 14
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Backup
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Development Timeline (next steps)
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HardwareDates Milestone(s)
Summer ‘11 –Winter 12
Spring ‘12 –Winter 12
< Spring ‘11 Prototyping
FNAL beamtest
Semi-infinite reviews
Spring ‘13 –Summer 13
LEPS beamtest
Autumn ‘13 v. 3 IRS3C/IRSX v.1 RT recon FINv2, final boardstack
Phas
e 1
Phas
e 2
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Comparison IRS3B “toy” Monte Carlo
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Vpeak 100 ADCRisetime 2.7 nsSampling rate 2.72 Gsa/snom dT 0.368 nsnom dV 13.617 ADC/sample
sSNR = dV/noise
40% CFD ratio: Applied between 2 points on leading edge that bracket this transition
~44ps for 100mV peak, 2mV noise
Leading Edge time [ns]
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In general, noise ‘fixed’
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40% CFD ratio
Noise 2.4 ADCRisetime 2.7 nsSampling rate 2.72 Gsa/snom dT 0.368 ns
Even in ideal case, for only using 2 points on leading edge, need Vpeak >= 50 ADC to get below 100ps timing
(gain issue)
If no other contributions, would be < 50ps for >100 ADC
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Adding in realistic degradations
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40% CFD ratio
What effects still missing?
• Residual Timebasejitter ?
• Non-linearity on leading edge?
• Something else ?
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Adding in realistic degradations (II)
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What effects still missing?
Modest non-linearity doesn’t make a big difference
Amplifier noise? (doesn’t impact pulser or sine data)
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Ways to improve (short-term)1. Increase gain (straightforward)2. Add Voltage Regulator to amplifier power
3. Increase risetime
4. Add better VdlyN, VdlyP filtering (reduce timebase filter)
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All these to be improved on Carrier02 Thermo-mech prototype (boards have been fabricated, being assembled) Final mechanics after tests with new HV, front/PMT interface (final board-stack w/IRSX)
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One example: improved Risetime
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Vpeak 100 ADCRisetime 1.0 nsSampling rate 2.72 Gsa/snom dT 0.368 nsnom dV 13.617 ADC/sample
40% CFD ratio
Now < 100ps for ADC>30 (with no other changes)
But will boost gain also
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Improvements to carrier02 √ Will populate with improved amplifiers √ add series resistor and capacitors to VadjN/VadjP (10
Ohm+200pF+47nF+2uF) √ exchange SMA connectors for MMCX √ exchange 12 bit external DAC for 16 bit one in same
series √ re-visit c02 wiring to allow powering entire boardstack
with just one cable √ extend width of boards and add holes for new thermal
wall structure concept √ swap ASIC regulator for one with a shutdown featurefull list at http://www.phys.hawaii.edu/~mza/PCB/iTOP/boardstack-v3.html
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Layout of carrier02 revC
design posted at: http://www.phys.hawaii.edu/~mza/PCB/iTOP/carriers/index.html
Improved –pin-tie thermal stack
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2.72 ns risetime 1.45 ns risetime
2-stage prototype Amp
Optimization study ongoing …25
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80fC injected charge
<1 ns risetime
2-stage prototype Amp -- measurements
Some care required to avoid oscillations..
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170mV peak(~250-300 ADC counts)
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new circuit (OPA847, 2.4k feedback)
Simulation indicates -- prior to changing layout radically (2x stage design), can already improve amplitude/risetime by switching to LHM6629 (single stage)
Need to confirm stability – will populate first batch with this circuit
For Rev C Carrier02
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original circuit (OPA846, 6k feedback)
new circuit (OPA847, 2.4k feedback)
2.72 ns risetime 1.45 ns risetime
Optimizing gain, risetime for “drop in” amp
Previous measurements…28
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original circuit (OPA846, 6k feedback)
new circuit (OPA847, 2.4k feedback)
2.72 ns risetime 1.45 ns risetime
Optimizing gain, risetime for “drop in” amp
Optimization study ongoing …29
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Next steps: IRS3C & IRSX ASICsIRS3C = IRS3B + 2 small changes
Exploit lessons learned from TARGET[i] series development, other ASICs
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Example: linearity improvement
IRSX design review (September – if ready)
(in fab – due imminently)
2X dynamic range,Greatly improved linearity
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Expectations – matched to measurements
J-F Genat, G. Varner, F. Tang, H. FrischNIM A607 (2009) 387-393.
G. Varner and L. RuckmanNIM A602 (2009) 438-445.
1GHz analog bandwidth, 5GSa/s
Simulation includes MCP response
• Noise/amplitude• Non-linearity• Timebase non-uniformity
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Simple estimate based upon trigger threshold dependenceUse as cross-check for detailed fit estimate, though robust (insensitive to laser coupling/optical fiber alignment)
Trigger Efficiency estimate
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