Proof of Concept – Full Test Bench
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Proof of Concept – Full Test Bench Description: This is an overview of both full frames sent as well as the partial third frame. Testbench: tb_AZALIA_BLOCK_poc.vhd
description
Proof of Concept – Full Test Bench. Testbench : tb_AZALIA_BLOCK_poc.vhd. Description: This is an overview of both full frames sent as well as the partial third frame. Proof of Concept – SYNC Tags. Testbench : tb_AZALIA_BLOCK_poc.vhd. - PowerPoint PPT Presentation
Transcript of Proof of Concept – Full Test Bench
Proof of Concept – Full Test Bench
Description: This is an overview of both full frames sent as well as the partial third frame.
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – SYNC Tags
Description: The red circles show the SYNC signal’s stream tags.
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – Reset, First SDO, First Tag
Description: The red circles show the initial reset assertion. The white block shows the initial read from SRAM to the output block. The orange block shows the first word output to SDO and first bytes received by SDI0 and SDI1. Also notice the first stream tag in green.
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – First Read, Second Read
Description: Notice the first read from SRAM in the white block. Also seen is the second read in yellow.
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – First non-CORB, first SDI
Description: Notice the final read from SRAM of the last word of CORB data. Notice the first read from SRAM of non-CORB output data. Note in red the first write to SRAM from SDI0 (on left) and SDI1 (on right) [data is to RIRB].
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – SDO vs. SDI
Description: Notice the reads from SRAM to SDO (red) occur twice as often as reads from SDI to SRAM (yellow) [Due to double-pumping of output block]
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – Request Tx Data
Description: Notice the assertion of the REQ_Tx_DATA signal after all SDO data has been read from SRAM. The system, in white, begins reading data from SRAM while the system is not busy after this assertion.
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – Strobe New Tx Data
Description: Notice in white the system beginning to read again from SRAM after the controller is no longer busy. Also, in red, the system strobes the Tx_DATA_STB to indicate it has finished with new transmit data and the system’s response, de-asserting REQ_Tx_DATA.
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – Rx Data End
Description: In red, the system asserts NEW_Rx_DATA after receiving the last of the SDI data. In white, the system reading all SDI data (notice the RIRB AA’s and 55’s). In yellow, the system strobing Rx_DATA_STB and the device’s response by de-asserting NEW_Rx_DATA.
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – Tx/Rx Data End
Description: Notice the reads to/from SRAM by the system in white and yellow. Of particular note (red double-arrow) is the time remaining after all data has been read by the system ( > 1 us ).
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – Begin Frame 2
Description: This is the start of the second frame. In white, the initial SDO data for frame two is read from SRAM. In red, the first SDO data arrives on-time. The error flag (pink) is never strobed.
Testbench: tb_AZALIA_BLOCK_poc.vhd
Proof of Concept – Dropped Packet Errors
Description: Notice in red, if Tx_DATA_STB is never strobed, the dropped packed error is strobed, and the REQ_Tx_DATA signal is de-asserted. In yellow, if RX_DATA_STB is never strobed, the dropped packet error is strobed, and the REQ_Rx_DATA signal is de-asserted.
Testbench: tb_AZALIA_BLOCK_poc.vhd
Long Run – Full Long Test Bench
Description: This is an overview of all 100 full frames sent.
Testbench: tb_AZALIA_BLOCK_longrun.vhd
Long Run – Single Frame
Description: One full frame of IO data.
Testbench: tb_AZALIA_BLOCK_longrun.vhd
