PROGRAM NAME B.Tech ELECTRONICS & COMPUTER … · (1) Learn the Register transfer language used to...
Transcript of PROGRAM NAME B.Tech ELECTRONICS & COMPUTER … · (1) Learn the Register transfer language used to...
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KL University, Guntur
B.Tech – II year, First Semester-2011-12
Date: 28-6-11
PROGRAM NAME : B.Tech ELECTRONICS & COMPUTER ENGINEERING
Course name : COMPUTER ORGANIZATION
Course Coordinator : B.VEERAMALLU
Course Detail : Theory
Lecture Hours : 60
I ELECTRONICS & COMPUTER ENGINEERING PROGRAMME OBJECTIVE:
The main objective of an engineering course in Electronics & Computers is to prove the
technical viability of new technology, together with, as appropriate, its possible economic
advantages. Provides a quality education with emphasis on strong foundation, fostering
creativity and use of modern ICT tools. Demonstration activities are expected to speed up the
innovation of new technologies in the field of computers and electronics.
The above program objective can be broadly defined on five counts as below.
1. Preparation: To prepare students for successful careers both in software and
hardware industry that meet the needs of Indian and Multinational companies and to
prepare students for postgraduate programs in inter-disciplinary streams related to
Electronics and Computers.
2. Core Competence: To provide students with solid foundation in mathematical,
scientific and engineering fundamentals which are necessary to formulate, solve and
analyze engineering problems and also to prepare them for graduate studies.
3. Breadth: To train the students with good engineering skills so as to work as part of
teams in Multi disciplinary projects.
4. Professionalism: The instruction should emphasize the primary purpose of the
profession as being the pursuit of a learned art in the sprit of public service. The sense
of professionalism should convey the responsibility to evaluate the impact of the
opportunity and obligation of the practitioner, to be in concert with peers, guides, and
direct the profession.
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5. Learning Environment: To develop the ability among students to synthesize data
and technical concepts for application to product design. To promote student
awareness of the life – long learning and to introduce them to professional ethics and
codes of professional practice.
II. Program Outcomes:
a. Graduates will demonstrate basic knowledge in mathematics, science and
engineering.
b. Graduates will demonstrate an ability to identify, formulate and solve
Electronics and Computer Engineering problems.
c. Graduates will demonstrate the ability to design Electronic circuits and develop
programs under different operating systems.
d. Graduates will demonstrate the ability to design the Embedded System and
application software that meets the desired specifications and requirements.
e. Graduates will demonstrate the ability to visualize and work in both electronic
and software industry, involving Multidisciplinary tasks.
f. Graduate will demonstrate skills to use modern engineering tools, software and
equipment to analyze problems.
g. Graduates will demonstrate knowledge of professional and ethical
responsibilities.
h. Graduate will be able to communicate effectively in both verbal and written
form.
i. Graduate will show the understanding of impact of engineering solutions on the
society and also will be aware of contemporary issues.
j. Graduate will develop confidence for self education and ability for life – long
learning.
k. Graduate who can participate and succeed in competitive examinations like
GATE, PGECET, IES, GRE etc.
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Mapping of Electronics & Computers Program Objectives (I-V) with Program
Outcome (a-k)
Program
Educational
Objectives
Program Outcomes
a b c d e f g h i j k
I X X X X X
II X X X X X
III X X X X
IV X X X X X
V X X
III COURSE DESCRIPTION:
This course provides basic Knowledge necessary to understand the hardware
operation of digital computers and covers the three subjects associated with computer
hardware.It describes Physical organization of a particular computer including its
registers,dataflow,Micro operations and control Function by means of a hardware description
language.
IV COURSE OBJECTIVES
After In detailed Learning of Computer Organization the student will be able to:
(1) Learn the Register transfer language used to express the microoperations in symbolic
form.
(2) Knows the organization and design of a basic digital computer.
(3) Understand the concept of microprogramming used in the design of the control unit.
(4) Learn about the Central Processing Unit which consists of the ALU,Control unit and
memory.
(5) Understand the arithmetic algorithms implemented at the hardware level.
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(6) Learn the techniques that computers use to communicate with input and output devices.
(7) Understand the concept of memory hierarchy.
V COURSE OUTCOMES
At the end of the course the student will be able to
a) Be familiar with the Von Neumann architecture.
b) Be familiar with the functional units of the processor such as the register file and
Arithmetic logical unit.
c) Be familiar with the basics of systems topics: single‐cycle (MIPS), multi‐cycle (MIPS),
parallel, pipelined, superscalar, and RISC/CISC architectures.
d) Be familiar with the cache subsystem.
e) Be familiar with the representation of data, addressing modes, instructions sets.
f) Be familiar with the basic knowledge the design of digital logic circuits and apply to
computer organization.
g) Be familier with the hardware and software implementation of control unit.
Mapping of Course Objectives with Programme Outcomes
Program Outcomes
a b c d e f g h i j k
Course Objectives
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VI SYLLABUS:
UNIT I:
REGISTER TRANSFER & MICRO-OPERATIONS: Register Transfer Language,
Register Transfer, Bus&memory Transfers, Arithmetic Micro-operations, Logic Micro
Operations, Shift Micro-operation, Arithmetic Logic Shift Unit.
UNIT II:
BASIC COMPUTER ORGANISATION AND DESIGN: introduction codes, Computer
Registers, Computer instructions, Timing and Control, Instruction Cycle, Memory-Reference
Instruction, Input-Output and interrupt, Design of Basic Computer, Design of accumulator
Logic, MICRO PROGRAMMED CONTROL: Control Memory, Address Sequencing,
Micro-Program example, Design of Control Unit.
UNIT III:
CENTRAL PROCESSING UNIT: General registers Organization, Stack Organization,
Instruction Formats, Addressing Modes, Data Transfer and Manipulation,
Program Control, Reduced instruction Set Computer (RISC).COMPUTER ARITHMETIC:
Addition and Subtraction, Multiplication Algorithms, Division Algorithms Floating-point Arithmetic
Operations.
UNIT IV:
MEMORY ORGANIZATION: Memory Hierachy,Main Memory, Auxiliary memory, Associative
Men Cache Memory, Virtual Memory, Memory Management hardware.
UNIT V:
INPUT-OUTPUT ORGANISATION: Peripheral Devices, input-Output interface,
Asynchronous Data Tranfer, Modes of Transfer, Priority interrupt, Direct Memory Access
(DMA), input –output Processor, serial Communication.
TEXT BOOKS:
1.Morris M.Mano,”Computer Systems Arichitecture”,3rd
Edition.
REFERENCE BOOKS:
1. John P Hayes,” Computer Arichitecture and Organization”2nd
Edition.
2. V.Carl Hamacher et.al,”Computer Organization”2nd
Edition.
3. Computer architecture and organization by Raja Raman and Radha Krishna-PHI
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VII UNIT WISE RATIONALIZATION:
UNIT-I: This unit is designed to describe the micro operations between registers and to
represent them with register transfer language.
The rationale of this unit is to enable the students to understand the register
transfer language and Arithmetic and logical micro operations.
UNIT-II: Basic computer organization is used to design a computer system with given
instruction set and the micro programmed control unit is used to describe the
software implementation of the computer.
This unit emphasizes the need for understanding the instructions and the
designing of basic computer and the micro instructions used to implement
control unit.
UNIT-III: Central Processing Unit is the part of the computer that performs the bulk of data
processing operations computer arithmetic provides various procedures for
implementing arithmetic operations with digital hardware.
In this unit the student will be able to understand stack organization,
instruction formats, addressing modes and different arithmetic operations such
as addition, subtraction, multiplication and division.
UNIT-IV: The Memory unit is an essential component in any digital computer since it is
needed for storing programs and data.
This unit explains Memory hierarchy and different types of memories and
memory management hardware.
UNIT-V: The Input-Output subsystem of a computer provides an efficient mode of
communication between the central system and the outside environment.
This unit describes about Peripheral devices,various I/O interface,different
modes of transfer Serial Communication.
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VIII. SESSION PLAN
S.No Unit Session Content Learning objective Methodology Faculty
Approach
Student approach Learning
outcome
1 I 1. Computer
organization
introduction Chalk & talk Explains,
demonstrates
Listens and
participate
Understand
2 I 2. Register transfer
language
Register transfer language Chalk & talk Explains Listen Remember
3 I 3. Register transfer . Register transfer, Control
Transfer.
Chalk & talk Explains,
demonstrates
Listen and Practice Understand
4 I 4. Bus and memory
transfers
Three state Bus Buffers,
Memory transfer
Chalk & talk Explains,
demonstrates
Listen and Practice Understand and
Analyze
5 I 5. Arithmetic micro
operations
Binary Adder, Binary
Adder-Subtractor, Binary
incrementer, Arithmetic
Circuit.
Chalk & talk Explains,
demonstrates
Listen Understand and
Analyze
6 I 6. Logic micro
operations
List of Logic micro
operations.
Chalk & talk Explains,
demonstrates
Listen Understand and
Analyze
7 I 7. Logic micro
operations
Hardware Implementation
,Some applications
ppt Explains,
demonstrates
Listens Remember
8 I 8. Shift micro
operations
Hardware Implementation Chalk & talk Explains Observe and
comprehend
Understand
9 I 9. Arithmetic Logic
Shift Unit
Arithmetic Logic Shift Unit Chalk & talk Explains Listens and
Participate
Understand
10 II 10. Co & design introduction Chalk & talk Explains Listens Remember and recall
11 II 11. Instruction codes Stored program
Organization, Indirect
Address
Chalk & talk Explains Listen and Practice Remember and
recall
12 II 12. Computer Registers,
Computer
Instructions
Common Bus System,
Instruction set completeness
Chalk & talk Explains Listen Understand
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13 II 13. Timing &Control,
Instruction cycle
Fetch & Decode, determine
the type of Instruction,
Register Reference
Instruction
ppt
Facilitates,
conducts
Listens,
participates
Understand and
remember
14 II 14. Memory reference
Instruction
AND to AC,ADD to AC,
LDA: Load to AC,.
ppt Explains, narrates Listen, Observes,
participates
Understand and
remember
15 II 15. Memory reference
Instruction
STA,BUN,BSA,ISZ Chalk & talk Explains,
Demonstrates
Listens ,Observes Understand and
remember
16 II 16. Input-Output and
Interrupt
I/O Configuration, I/O
Instructions,
Chalk & talk Explains Listens, Observes Evaluate
17 II 17. Input-Output and
Interrupt
Program Interrupt, Interrupt
cycle.
Chalk & talk Explains,
demonstrates
Listen Understand and
remember
18 II 18. Design of Basic
Computer
Control Logic gates, control
of registers and memory
Chalk & talk Explains Listen Evaluate and apply
19 II 19. Design of Basic
Computer
Control of single flip-flop,
control of common bus.
Chalk & talk Explains Listens, Participates
Evaluate and apply
20 II 20. Design of
accumulator logic
Control of AC register,
adder and logic circuit
Chalk & talk Explains Observe Understand
21 II 21. Control Memory Control Memory
Chalk & talk Explains Listens, Observe Understand
22 II 22. Addressing
Sequencing
Conditional Branching,
mapping of instructions, sub
Routines
Chalk & talk Explains Listens, Observes Understand
23 II 23. Micro Program
Example
Computer configuration,
Micro instruction format,
Symbolic micro instruction,
Chalk & talk Explains Listen Understand and
remember
24 II 24. Micro Program
Example
the fetch routine, binary
micro program
Chalk & talk Explains Listens, Practices Remember &
Apply
25 II 25. Design of Control
Unit
Micro program Sequencer. Chalk & talk Explains Listen Understand and
remember
26 III 26. Cpu introduction Chalk & talk Explains Listens,
Participates
Remember &
Apply
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27 III 27. General Register
Organization
Control Word, Examples of
micro operations
Chalk & talk Explains Listens,
Participates
Comprehend &
Apply
28 III 28. *Stack Organization Register stack, memory
stack, reverse polish
notation, Evolution of
arithmetic expression.
Chalk & talk Explains,
demonstrates
Listen Remember
29 III 29. Instruction Format Three- address, two
addresses, one address, zero
address RISC instructions.
Chalk & talk Explains Listen Understand and
remember
30 III 30. Addressing Modes Immediate ,Register,
Register indirect, implied,
Auto Increment decrement,
Chalk & talk Explains Comprehend, Observes
Understand and remember
31 III 31. Addressing Modes direct, indirect, relative,
indexed addressing modes
Chalk & talk Explains Listen, Participates Remember &
Apply
32 III 32. Data Transfer
manipulation
Data Transfer &
Manipulation instructions
arithmetic instruction
logical and bit manipulation
instruction
Chalk & talk Explains Listen Understand and
Remember
33 III 33. Program Control Status bit conditions,
conditional branch
instructions subroutine call
and return,
Chalk & talk Explains,
Facilitates
Listen, participates Remember &
Apply
34 III 34. Program Control Programs interrupt types of
interrupts.
Chalk & talk Explains Listen Understand and
remember
35 III 35. Reduced Instruction
Set Computer(RISC)
CISC Characterstics,Risc
Characteristics
Chalk & talk Explains Listen Remember and
apply
36 III 36. Arithmetic addition
&Subtraction
Algorithm
Addition, Subtraction with
signed magnitude data with
signed two’s complement
data, Hardware
Chalk & talk Explains Listen Remember and
apply
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implementation. 37 III 37. Multiplication
Algorithms
Signed Magnitude data,
Hardware implementation,
booth Multiplication
algorithm, array multiplier.
Chalk & talk Explains Listen Understands
38 III 38. Division Algorithms Hardware implementation
for signed magnitude data,
Divide overflow, Hardware
algorithm
Chalk & talk Explains Listens, Observe Understand
remembers and
comprehends
39 III 39. Floating Point
Arithmetic
Operation
Basic Conditions, Register
configuration, addition and
subtraction.
Chalk & talk Explains,
demonstrates
Listens,
participates
Apply
40 III 40. Floating Point
Arithmetic
Operation
Multiplication & division Chalk & talk Explains,
demonstrates
Listen Understand and
Analyze
41 IV 41. *Memory
organization
introduction Chalk & talk Explains,
demonstrates
Listens Remember
42 IV 42. Memory hierarchy Auxiliary Memory, cache
memory,
multiprogramming,
Chalk & talk Explains Listen Understand and
comprehends
43 IV 43. Main Memory RAM and ROM Chips,
Memory Address Map,
Memory connection CPU.
Chalk & talk Explains Listen, participates understand
44 IV 44. Auxiliary Memory Magnetic disk, Magnetic
tape
Chalk & talk Explains Listen Understand
45 IV 45 Associative and
cache Memory
Associative Mapping
,direct, set-Associative
Mapping,
Chalk & talk Explains Listen Understand and
comprehends
46 IV 46 Associative and
cache Memory
writing into cache ,cache
initialization
Chalk & talk Explains Listen Understands
47 IV 47 Virtual Memory Address space and Memory
Space, Address mapping
Chalk & talk Explains Listens, Observe Understand
remembers and
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using pages, comprehends
48 IV 48 Virtual Memory Associative memory page
table, page Replacement
Chalk & talk Explains,
demonstrates
Listens,
participates
Apply
49 IV 49 Memory
Management
Hardware
Segmented page Mapping,
Memory Protection
Chalk & talk Explains,
demonstrates
Listen Understand and
Analyze
50 V 50 i/o organization introduction Chalk & talk Explains,
demonstrates
Listens Remember
51 V 51 *Peripheral Devices Peripheral. Monitor and
keyboard, printer, Magnetic
tape, magnetic Disk.
Chalk & talk Explains Listen Understand and
comprehends
52 V 52 Input-Output
Interface
I/O Bus and interface
Module, I/O versus memory
buses,.
Chalk & talk Explains Listen, participates understand
53 V 53 Input-Output
Interface
isolated versus Memory
mapped I/O
Chalk & talk Explains Listen Understand
54 V 54 Asynchronous data
transfer
Strobe control, Hand
shaking.Asynchronous
serial transfer,
Asynchronous
communication interface,
FIFO Buffer.
Chalk & talk Explains Listen Understand and
comprehends
55 V 55 Modes of Transfer Programmed I/O, Interrupt
initiated I/O
Chalk & talk Explains Listen Understands
56 V 56 Priority Interrupt Daisy chining priority,
parallel priority interrupt,
Priority encoder, interrupts
cycle.
Chalk & talk Explains Listens, Observe Understand
remembers and
comprehends
57 V 57 Direct Memory
Access
DMA Controller, DMA
Transfer
Chalk & talk Explains, demonstrates
Listens, participates
Apply
58 V 58 *Input-Output
Processor
CPU-IOP Communication,
Intel 8089 IOP
Chalk & talk Explains,
demonstrates
Listen Understand and
Analyze
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59 V 59 Serial
Communication
Character oriented protocol
,
Chalk & talk Explains,
demonstrates
Listens Remember
60 V 60 Serial
Communication
Data Transparency, Bit
oriented Protocol
Chalk & talk Explains Listen Understand and
comprehends
IX.SELF STUDY MATERIAL:
Unit Topic Source
I Binary adder subtractor Morris M.Mano,”Computer Systems
Arichitecture”,3rd
Edition
I Digital computers Morris M.Mano,”Computer Systems
Arichitecture”,3rd
Edition
II Adder and logic circuit Morris M.Mano,” Computer Systems
Arichitecture”,3rd
Edition.
II Logical operations Morris M.Mano,”Computer Systems
Arichitecture”,3rd
Edition
II Computer instructions Morris M.Mano,”Computer Systems
Arichitecture”,3rd
Edition
III Data manipulation
instructions
V.Carl Hamacher et.al,”Computer
Organization”2nd
Edition
III Computer instructions Morris M.Mano,”Computer Systems
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Arichitecture”,3rd
Edition
IV General registers Morris M.Mano,”Computer Systems
Arichitecture”,3rd
Edition
V RISC Computer Oraganization by William Stallings
V interrupt Morris M.Mano,”Computer Systems
Arichitecture”,3rd
Edition
V CPU-IOP communication Computer architecture and organization by
Raja Raman and Radha Krishna-PHI
Software tool for Computer Organization.
Logic Aid 3.0 (CAD software for logic design)
HDL(Hardware Description Language)
Evaluation Pattern :
Internal Marks : 40
External Marks : 60
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EVALUATION SCHEME Sl.
No.
Nature of
examination
Marks
%
Type of examination and
mode of Assessment Scheme of examination
1 *Theory
60 Semester end examination
(external evaluation)
This examination question paper
in theory subjects will be for a
maximum of 60 marks
40
20
Test – 1 2 mid – exams each for 20 marks
and of 1½ hr duration are to be
conducted. For a total of 20
marks, 75% of better of the two
and 25% of the other are added
and reported.
Test - 2
5 Assignment Test
6 Question to be released in
advance. 2 Questions allotted by
Examiners choice to be
answered. Duration 45 min.
5 Home Assignments Average of Home Assignments
minimum 2 per subject
5 Surprise Quiz A maximum of two surprise
quizzes per subject
5 Attendance / Class notes 5 marks are allotted for
attendance and class notes
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Attendance Weightage 05 Marks
Attendance of 75 % and above but less than 80 % 01 Mark
Attendance of 80 % and above but less than 85 % 02 Marks
Attendance of 85 % and above but less than 90 % 03 Marks
Attendance of 90 % and above but less than 95 % 04 Marks
Attendance of 95 % and above 05 Marks
GRADES
After successful completion of the Course work and all the internal and external examinations, a student will graded as follows
Letter Qualitative Meaning Grade Point Attached
X - Excellent 10
A - Very Good 8
B - Good 7
C - Fair 6
D - Satisfactory 4
F - Fail 0
NOTICES
ALL notices regarding this subject are displayed on the e-learning site only
COURSE COORDINATOR
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Signature of course Co-ordinator