Prof. Dr. Matthias Sturm HTWK Leipzigmicrocontroller basics a description based on TI‘s MSP430...

Prof. Dr. Matthias Sturm HTWK Leipzigmicrocontroller basics

microcontroller basicsa description based on TI‘s MSP430

author and speaker

Prof. Dr. Matthias Sturm

based on TI‘s design seminar MSP430


topics architectural overview memory configuration instruction set and addressing modes software development stack and subroutines interrupt process system clock generator periphery

parallel ports basic timer 1 LCD driver module ADC 8-bit interval timer / counter timer / port module watchdog timer module


typically microcontroller applications for the MSP430 family

Handheld Measurement Air Flow measurement Alcohol meter Barometer Data loggers Emission/Gas analyser Temperature measurement Weight scales

Medical Instruments Blood pressure meter Blood sugar meter Breath measurement EKG system

Home environment Air conditioning Control unit Thermostat Boiler control Shutter control White goods (Washing machine,..)

Misc. Smart card reader Taxi meter Smart Batteries

Utility Metering Gas Meter Water Meter Heat Volume Counter Heat Cost Allocation Electricity Meter Sports equipment Bike computer Diving watches

Security Glass break sensors Door control Smoke/fire/gas detectors


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

architectural overview: configuration ‘320


CPU register

R4 universal registerR0 programm counter PC

R1 stack pointer SP R2 statur register SR

R3 const. generator CG2

R5 universal register











special register universal register

16 bit

16 bit


CPU register
















16 bit

16 bit

15 1 0

0

R0 programm counter


CPU register
















16 bit

16 bit

15 1 0

0

R1 stack pointer


CPU register


R1 stack pointer SP







16 bit

R2 statur register SR








16 bit15 9 8 7 6 5 4 3 2 1 0

V SCG1 SCG0 OSCoff CPUoff GIE N Z C

R2 status register


formats of numbers

0000h0001hFFFFh

7FFFh8000h

4000hC000h

0

1

16384

32767

32768

49152

65535

+

unsigned

C


formats of numbers

0000h0001hFFFFh

7FFFh8000h

4000hC000h

0

1

16384

32767

-32768

-16384

-1

+

signed

-

V


Flags

Flags are set or cleared in dependence of logic or arithmetic instructions.Flags are used to control the program flow.

Z-Flag (zero) set, if the result of a logic or arithmetic instruction is zero,otherwise cleared.

N-Flag (negative)set, if the result of a logic or arithmetic instruction is negative,otherwise cleared.The N-Flag is a copy of the most significant bit (MSB)


Flags

C-Flag (carry) set, if the result of a logic or arithmetic instruction produced a carry, otherwise cleared.

V-Flag (overflow)set, if the result of an arithmetic instruction overflows the signed variable range, otherwise cleared.

positiv + positive = negativenegativ + negative = positivepositive - negative = negativenegative - positive = positive


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

memory configuration MSP430P325


memory model MSP430P325

interrupt vectors

16 kB OTP

512 Byte RAM

16 bit periphery

8 bit periphery

special function register

FFFFhFFE0hFFDFh

C000h

03FFh0200h01FFh0100h00FFh0010h000Fh0000h

unused

RAM

Word access Byte access

OTP EPROM


MSP430P325 starter kit

The board



interrupt vectors

monitor

16 kB OTP

512 Byte RAM

16 bit periphery

8 bit periphery


FFFFhFFE0hFFDFhEA00h

C000h


unused

OTP EPROM

RAM

pre-programmed in starter kit



interrupt vectors

identification bit pattern

stack used by application

stack needed from monitor, 50 Bytes

user address range3DCh - 214h

(do not set the stack pointer)

RAM-area for monitor

3FEh3E0h3DFh

3DCh

214h212h200h

RAM

RAM-area in starter kit


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

instruction set and addressing modes


fifty-one instructions twenty-seven basic instructions RISC twenty-four emulated instructions CISC

byte and word processing

seven address modes for source

four address modes for destination

all instructions appropriate for all modules

instruction set


Format I Format II Format III

source,destination source or destination +/- 9bit offset ( Word )

ADD(.B) CALL JMPADDC(.B) PUSH(.B) JCAND(.B) RETI JNCBIC(.B) RRA(.B) JEQBIS(.B) RRC(.B) JNEBIT(.B) SWPB JGECMP(.B) SXT JLDADD(.B) JNMOV(.B)SUB(.B)SUBC(.B)XOR(.B)

12 instructions 7 instructions 8 instructions1 .. 6 cycles 1 .. 5 cycles 2 cycles1 .. 3 word 1 .. 2 word 2 word

instruction set - basic instructions


emulated instructions are: basic instruction to the user replaced with a basic instruction by the assembler

emulated instructions benefits: increased processing speed increased ROM code efficiency supply users with familiar instructions no additional effort in CPU:

RISC with CISC-like instruction set

instruction set - emulated instructions


Arithmetic Logical Data Program Flow

ADC(.B) INV(.B) CLR(.B) BR

DADC(.B) RLA(.B) CLRC DINT

DEC(.B) RLC(.B) CLRN EINT

DECD(.B) CLRZ NOP

INC(.B) POP(.B) RET

INCD(.B) SETC

SBC(.B) SETN

SETZ

TST(.B)

7 instructions 3 instructions 9 instructions 5 instructions




How to emulate instructions?

emulated instruction basic instruction

INC.B dst increment destination ADD.B #1,dstINCD.B dst double-incr. destination ADD.B #2,dstCLRN clear negative bit BIC #4,SREINT enable interrupt BIS #8,SRINV dst invert destination XOR #0FFFFh,dst

The trick is to take constant numbers in basic instructionsby using special registers, the constant generators.


CPU register
















16 bit

16 bit

15 0

R3 constant register

Under different addressing modes:

0 0 0 1

0 0 0 2

F F F F

0 0 0 0



R2 statur register SR





CPU register


R1 stack pointer SP








16 bit


15 9 8 7 6 5 4 3 2 1 0


R2 status register

Under different addressing modes:

0 0 0 0

0 0 0 4

0 0 0 8


instruction table (example)

source form operand operation status bits

V N Z C

ADD src, dst src+dst->dst * * * *

::

::

::

::

MOV src, dst src -> dst - - - -

instruction set


orthogonal instruction set

Orthogonality is, when

all instructionswith

all address modesare valid for

all operands

Orthogonality in MSP430…

all single operand instructions useall seven address modes.

and

all double operand instructions use all seven source address modes andall four destination address modes

AddressModesSource

AddressModesDestination

Instructions

AddressModesSource

AddressModesDestination

Instructions

Example: Orthogonality for two operand instructions

Example: Non-Orthogonality for two operand instructions


seven address modes for source four address modes for destination

mode source destination

register mode

indexed mode

symbolic mode

absolute mode

indirect mode

indirect autoincrement mode

immediate mode

address modes


register addressing mode

ADD R7,R8 ; ( R7 ) + ( R8 ) ( R8 )

MOV R5,R6 ; ( R5 ) ( R6 )

CLR R5 ; #0 ( R5 )

XOR #1,R9 ; Toggle Bit 0 in R9

The operand is contained in one of the registers R0 to R15.

This is the fastest addressing mode and needs the least memory .

address modes


address modes

indexed addressing mode

MOV 2(SP),R7 ; Move 2nd item of Stack to R7

MOV.B R5,9(R10) ; LSByte (R5) ((R10)+9)

ADDC -2(R5),4(R7) ; ((R5)-2)+((R7)+4)+C ((R7)+4)

The address of the operand is the sum of the index and the contents of the register.

The indexed mode with index zero may used for “indirect register addressing” of the destination operand.

BIS #8,0(R4) ; Set Bit 3 at address (R4)


symbolic addressing mode (PC relative addressing)

ADD EDE,TONI ; (EDE) + (TONI) (TONI)

MOV TONI,EDE ; Move (TONI) to (EDE)

MOV R5,TONI ; (R5) (TONI)

MOV EDE,R8 ; (EDE) (R8)

The content of the words EDE / TONI is used for the operation.

Any address in the 64k memory space is addressable both as a source and as a destination.

address modes


address modes

absolute addressing mode

ADD &CCR1,&CCR2 ; (CCR1) + (CCR2) (CCR2)

MOV &P1IN,&P2OUT ; Move (P1IN) to (P2OUT)

MOV R5,&ACTL ; (R5) (ADC Control Register)

MOV &TACTL,R8 ; (TACTL) (R8)

The contents of the fixed addresses are used for the operation.

Used for hardware peripheral modules that are located at an absolute address; used for Position Independent Code.


address modes

indirect register addressing mode

ADD @R8,R9 ; ((R8)) + (R9) (R9)

MOV @R10,0(R12) ; ((R10)) ((R12)+0)

MOV @R5,&ACTL ; ((R5)) (ADC Control Register)

MOV.B @R4,R8 ; Byte addressed by R4 (R8)

The registers are used as a pointer to the operand.

The registers are not modified. Only for the source operand addressing.


ADD @R8+,R9 ; ((R8)) + (R9) (R9), (R8)+2 (R8)

MOV @R10+,0(R12) ; ((R10)) ((R12)+0) , (R10)+2 (R10)

MOV @R5+,&ACTL ; ((R5)) (ADC Register), (R5)+2 (R5)

MOV.B @R4+,R8 ; Byte ((R4)) (R8) , (R4)+1 (R4)

indirect register addressing with autoincrement

The registers are used as a pointer to the operand.

The registers are incremented accordingly afterwards. Only for the source operand addressing.

address modes


immediate register addressing mode

BIT #0100h,4(R9) ; Test Bit 8=1 ? in the 3rd word of a table ; starting at (R9)

MOV.B #01Fh,0(R12) ; 01Fh ((R12)+0)

MOV #0010,&ACTL ; 0Ah (ADC Control Register)

ADD #0A00h,R8 ; 0A00h + (R8) (R8)

Any immediate 8 or 16 bit constant can be used with the instruction.

Only for the source operand.

address modes


editor

assembler

simulator

hardware

success?

success?

success?

start

end

yesno

yesno

yesno

debugger(monitor)

• editor

• assembler

• simulator

• debugger

steps of software development

tools for software development


source code line

software development

Label instruction operand(s) ; comment

start mov #0FC17h, R15 ; load the ; value #0FC17h ; in register R15


software development

assembler directives .sect

.sect defines initialized named sction and associates subsequent code or data with this section

example: .sect “INIT”,0214h

.set and .equ .set and .equ directives set a constant value to symbol

example: LCDCTL .equ 030h

.byte and .word .byte places one or more 8-bit values into consecutive bytes of current section .word places one or more 8-bit values into consecutive bytes of current section

.end .end teminates assembly, should be the last source statement


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

programming techniques - stack and subroutines


stack and subroutine

mainprogram

instruction A

instruction B

instruction C

instruction D

instruction B

instruction C

instruction E

instruction B

instruction C

instruction F

instruction B

instruction C

instruction A

CALL subroutine

instruction D

CALL subroutine

instruction E

CALL subroutine

instruction F

CALL subroutine

instruction B

instruction C

instruction G

mainprogram

instruction G RETURN

subroutine



instruction Ainstruction B

instruction C

instruction D

stack

R0 program counter

instruction B

instruction C

instruction B

instruction Binstruction C

instruction C

instruction F

stack stack areaR1 stack pointer

mainprogram

memory


R2 flag register

instruction E

MP

register area

stack

instruction G JMP MP

No subroutine

main process

low address

high address



instruction C

instruction D

stack

R0 program counter

instruction B

instruction C

instruction B

instruction Binstruction C

instruction C

instruction F


mainprogram

memory


R2 flag register

instruction E

MP

register area

stack


instruction G JMP MP

No subroutine

main process

low address

high address


instruction ACALL SR

instruction D

CALL SR

stack

R0 program counter

instruction E

CALL SR

CALL SR

instruction CRET

instruction G

instruction B


mainprogram

memory


R2 flag register

instruction F

MP

register area

stack


JMP MPSR

subroutine

subroutine process

low address

high address



instruction D

CALL SR

stack

R0 program counter

instruction E

CALL SR

CALL SR

instruction CRET

instruction G

instruction B

address of instruction D stack areaR1 stack pointer

mainprogram

memory


R2 flag register

instruction F

MP

register area

stack


JMP MPSR

subroutine

subroutine process

low address

high address



instruction D

CALL SR

stack

R0 program counter

instruction E

CALL SR

CALL SR

instruction CRET

instruction G

instruction B

Address of instruction D stack areaR1 stack pointer

mainprogram

memory


R2 flag register

instruction F

MP

register area

stack


JMP MPSR

subroutine

subroutine process

low address

high address



instruction D

CALL SR

stack

R0 program counter

instruction E

CALL SR

CALL SR

instruction CRET

instruction G

instruction B

stack areaR1 stack pointer

mainprogram

memory


R2 flag register

instruction F

MP

register area

stack


JMP MPSR

subroutine

address of instruction D

subroutine process

low address

high address



instruction D

CALL SR

stack

R0 program counter

instruction E

CALL SR

CALL SR

instruction CRET

instruction G

instruction B


mainprogram

memory


R2 flag register

instruction F

MP

register area

stack


JMP MPSR

subroutine


subroutine process

low address

high address



instruction D

CALL SR

stack

R0 program counter

instruction E

CALL SR

CALL SR

instruction CRET

instruction G

instruction B

stack


mainprogram

memory


R2 flag register

instruction F

MP

register area

stack


JMP MPSR

subroutine


subroutine process

low address

high address



instruction D

CALL SR

stack

R0 program counter

instruction E

CALL SR

CALL SR

instruction CRET

instruction G

instruction B


mainprogram

memory


R2 flag register

instruction F

MP

register area

stack


JMP MPSR

subroutine

address of instruction E

subroutine process

low address

high address


stack and data

Save data on the stack

• before you save data on the stack you need to initiate the stack by writing the stack address to the stack pointer (R1)

• to push data on the stack use the PUSH instruction• to pop data from the stack use the POP instruction

• function: last-in first-out

• the stackpointer uses always two Bytes of stack space

remember: • be careful not to demage addresses on the stack• avoid underflow and overflow of the stack



Conclusion

• before you call a subroutine you need to initiate the stack by writing the stack address to the stack pointer (R1)

• to call a subroutine use the CALL instruction• to return from subroutine use the RET instruction

• before a subroutine call the microcontroller saves the following instruction address on the stack

remember: • the stack location have to be RAM• the stack is growing to lower addresses• the stack pointer points to the latest used stack address


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

programming techniques - interrupts


interrupt

An interrupt request (usually called an interrupt)

is generated by an interrupt source.

An interrupt need to be served by a special program,

the interrupt service routine (ISR).

An interrupt can take place every time

independent of program flow (in difference to subroutine calls).

Interrupts can be maskable or non-maskable.

Different interrupt sources have different priority.

To react on an interrupt the most microcontroller

containing a vector interrupt system.

generally


interrupt sources

int. source 1 / local enable


instruction C

instruction D

stack

instruction E

instruction X

instruction Z

instruction Winterrupt vector ISR1

instruction U

instruction V

stack stack area

mainprogram

memory

R0 program counterR1 stack pointer


R2 flag register

instruction Y

MP

register area

stack

interrupt vector ISR2

JMP MP

interrupt service routine 1

ISR1

RETI

RETI

ISR2 interrupt service routine 2

interrupt vector table

interrupt logic

global interrupt enableGIE

priority check hard wired


interrupt

interrupt process

low address

high address


interrupt sources



instruction C

instruction D

stack

instruction E

instruction X

instruction Z


instruction U

instruction V

instruction D address stack area

mainprogram

memory



R2 flag register

instruction Y

MP

register area

stack


JMP MP


ISR1

RETI

RETI



interrupt logic




interrupt

interrupt process

low address

high address


interrupt sources



instruction C

instruction D

flag register

instruction E

instruction X

instruction Z


instruction U

instruction V

instruction D address stack area

mainprogram

memory



R2 flag register

instruction Y

MP

register area

stack


JMP MP


ISR1

RETI

RETI



interrupt logic




interrupt

interrupt process

low address

high address


Int. Source Int. Flag system Int. Word address mirror address priority

power-up RSTI reset 0FFFEh 03FEh 15, highestexternal resetwatchdog WDINMI NMIIFG nonmaskable 0FFFCh 03FCh 14Oscillator fault OFIFGdedicated I/O P0.0IFG maskable 0FFFAh 03FAh 13dedicated I/O P0.1IFG maskable 0FFF8h 03F8h 12

watchdog timer WDTIFG maskable 0FFF4h 03F4h 10

ADC ADCIFG maskable 0FFEAh 03EAh 5timer port flags located in maskable 0FFE8h 03E8h 4 module register

basic timer BTIFG maskable 0FFE2h 03E2h 1I/O port 0 P0.2..7IFG maskable 0FFE0h 03E0h 0, lowest

interrupt



interrupt

programming interruptsprogram structure

initiate

main program

Interrupt service routine 1



Priority falling


interrupt

program steps initiate stack and stack pointer resources of the main program resources of interrupt subroutines local interrupt enable global interrupt enable

main program instructions of main program loop inside the main program

interrupt subroutine 1 instructions of the interrupt subroutine end ISR with RETI instruction

interrupt subroutine 2 instructions of the interrupt subroutine end ISR with RETI instruction

Don’t forget to initiate the interrupt vector table !


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

system clock generator



features

One crystal - no external components stable processor frequency - no accumulating error fast start up

Low power Oscillatorfor 32.768 kHz crystal

ACLKAuxiliary Clock

PUCFLL

fMCLK = ( N + 1 ) * fACLKMCLKMain System Clock(fSystem)

XIN

XOUT



: ( N + 1 )

synchro-

nizer-

+ACLK

CLK

U/D Reset

Enable

frequency integrator

10 bit

modulator

5

digitally controlled oscillator (DCO)

DC Gen

MCLKfSystem

OscOff, SCG0, SCG1

set interrupt flag in SFR’s

29 28 27 26 25 24 23 22

5

... 21 20

… FN_4 FN_3 FN_2 ...

SCFI0

SCFI1 SCFI0

M 26 25 24 23 22 21 20

SCFQCTL

N

PUC

Control ofoperation mode

frequency locked loop



three register used for control system clock frequency control register SCFQCTL

0052h system clock frequency integrator 0 register SCFI0 0050h system clock frequency integrator 1 register SCFI1 0051h

osc. fault interrupt flag OFIFG IFG 1.1 0002h osc. Fault interrupt enable OFIE IE 1.1 0000h

use byte instructions

MCLK = f(System) = ( N + 1 ) f(crystal)

N in the range of 3 .. 127

MCLKmax = f(System)max = 3.3 MHz

system clock frequency


mode crystal DC DCO loop comments typ. current osc. generator control at Vcc=3V

fsys.=1MHz

active on on on on conditions after PUC 3000µA (400µA/C325)

LPM1 on on on off loop control off CPU off 70µA

LPM2 on on off off DCO and loop control off 6µA

LPM3 on off off off only crystal osc. On 1.3µA

LPM4 off off off off all functions disabled 0.1µAfsystem=0Hz


system clock operation modes

15 9 8 7 6 5 4 3 2 1 0


R2 status register


CL

POR

Q0 Q1CBSEL1

CBSEL0

0

1

2

3MCLK

ACLK

XBUF

CBE


crystal buffer output

7 6 5 4 3 2 1 0

CBSEL1 CBSEL0 CBE

CBCTL crystal buffer control register


program example

configures the system clock to 1.05MHz by crystal frequency of 32768Hz

START mov.b #1Fh,&SCFQCTL ; set multiplication; factor of PLL to 32



MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

periphery


interrupt vectors

monitor

16 kB OTP

512 Byte RAM

16 bit periphery

8 bit periphery


FFFFhFFE0hFFDFhEA00h

C000h


unused

OTP EPROM

RAM

periphery

periphery register


512 Byte RAM

16 bit periphery

8 bit periphery



RAM

periphery register / special function register

: :0007h reserved0006h reserved0005h module enable 2 ME2.20004h module enable 1 ME1.10003h interrupt flag register 2 IFG2.x0002h interrupt flag register 1 IFG1.x0001h interrupt enable 2 IE2.x0000h interrupt enable 1 IE1.x


512 Byte RAM

16 bit periphery

8 bit periphery



RAM

periphery register / Byte modules

: : :0080h - 008Fh reserved0070h - 007Fh USART register0060h - 006Fh reserved0050h - 005Fh system clock generator register0040h - 004Fh basic timer, 8-Bit timer/counter, timer/port register0030h - 003Fh LCD register0020h - 002Fh digital I/O port P3 and P4 control register0010h - 001Fh digital I/O port P0, P1 and P2 control register


512 Byte RAM

16 bit periphery

8 bit periphery



RAM

periphery register / Word modules

: : :0180h - 018Fh reserverd0170h - 017Fh timer_A0160h - 016Fh timer_A0150h - 015Fh reserved0140h - 014Fh reserved0130h - 013Fh multiplier0120h - 012Fh watchdog timer0110h - 011Fh analog-to-digital converter0100h - 010Fh reserved


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

general port P0 / parallel ports


general port P0

8 Bit parallel port bit programmable individual function select interrupt source selection

(three interrupt vectors)

features

P0BIT.4

P0DIR.4

P0.4

P0BIT.3

P0DIR.3

P0.3

P0BIT.2

P0DIR.2

P0.2

P0BIT.1

P0DIR.1

P0.1

P0BIT.0

P0DIR.0

P0.0

P0BIT.5

P0DIR.5

P0.5

P0BIT.6

P0DIR.6

P0.6

P0BIT.7

P0DIR.7

P0.7


six register used for control

input register P0IN 0010h output register P0OUT 0011h direction register P0DIR 0012h interrupt flags P0IFG 0013h interrupt edge select P0IES 0014h interrupt enable P0IE 0015h


general port P0


general port P0

schematic of bits P0.7 to P0.3

output buffer

input

interrupt flaginterrupt edge select

Pad logic

P0.x

P0IE.xP0IFG.x

P0IRQ.x

P0IN.x

P0OUT.x

P0DIR.x

P0IES.x

P0BIT.x


bic.b #018h,&P0DIR ; set P0.3 and P0.4 to inputsmain clr R15 ; clear R15

bit.b #008h,&P0IN ; check pin P0.3jnc P04 ; if not pressed -> check pin P0.4mov.b #015h,R15 ; if pressed -> load pattern R15

P04 bit.b #010h,&P0IN ; check pin P0.4jnc next ; if not pressed -> goto nextmov.b #016h,R15 ; if pressed -> load pattern R15

next nop

general port P0

program example

configures P0.3 and P0.4 as input and checks the pins


TP.3TPD.3

TPE.3

TP.4TPD.4

TPE.4

TP.1TPD.1

TPE.1

TP.2TPD.2

TPE.2

TP.0TPD.0

TPE.0

TP.5TPD.5

TPE.5

timer / port module

parallel port feature

five outputs one bidirectional channel

two register used for control TP O/P data register TPD 004Eh TP data enable register TPE 004Fh



timer / port module

program example

configures TP0 .. TP5 as output and writes a pattern

mov.b #0FFh,&TPE ; enable outputs of Timer/Portmov.b #015h,R15 ; load pattern R15

OUT mov.b R15,&TPD ; output pattern


AIN.3

AEN.3

AIN.4

AEN.4

AIN.1

AEN.1

AIN.2

AEN.2

AIN.0

AEN.0

A.3

A.4

A.1

A.2

A.0

A.5 AIN.5

AEN.5

parallel port feature

six inputs

two register used for control input data register AIN 0110h input enable register AEN 0112h

use word instructions

ADC


ADC

program example

configures all AD-pins as inputs and checks two pins

mov #0FFh,&AEN ; all AD-pins dig.inputsMAIN bit #01h,&AIN ; check pin AIN.0

jnc A1 ; if LO -> check pin AIN.1mov.b #015h,R15 ; if HI -> load pattern R15

A1 bit #02h,&AIN ; check pin AIN.1jnc next ; if LO -> goto nextbis.b #02Ah,R15 ; if HI -> add pattern to R15

next nop


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

basic timer 1


DIVSSEL

0

1

2

3

CLK1BTCNT1

Q4 Q5 Q6 Q7

FRFQ1FRFQ0

ACLK / 256

fLCD

ACLK

MCLK

EN1

DIVHold

Q4 Q5 Q6 Q7Q3Q2Q1Q0

Set_Int._Flag

Hold

CLK2BTCNT2

IP2IP1IP0

EN2

Three functions of the Basic Timer 1

LCD driver frequency

basic timings

real-time clock

basic timer 1


basic timer 1

three register used for control basic timer1control register BTCTL 0040h basic timer1 counter 1 register BTCNT1 0046h basic timer1 counter 2 register BTCNT2 0047h

basic timer interrupt flag BTIFG IFG2.7 0003h basic timer interrupt enable BTIE IE2.7 0001h


7 6 5 4 3 2 1 0

SSEL Hold DIV FRFQ1 FRFQ0 IP2 IP1 IP0

BTCTL basic timer1 control register


Q4 Q5 Q6 Q7Q3Q2Q1Q0

Set_Int._Flag

Hold

CLK2BTCNT2

IP2IP1IP0

EN2

204816384 8192 4096 5121024 256 128

ACLK / 256

ACLK

MCLK

CLK2 Interrupt frequency [Hz]

864 32 16 24 1 0.5

depends on MCLK

simple generation of timings

basic timer 1 - examples

LCD timing

example MUX4

LCD data sheetfframing=100Hz..30Hz

ACLK=32768Hz

FRFQ:fLCD=8x100Hz..8x30HzfLCD=800Hz..240Hz

select fLCD

1024Hz/512Hz/256Hz/128Hz

fLCD=256HzFRFQ1=1 / FRFQ2=0


mov.b #050h,&BTCTL ; set up Basic Timer; for LCD operation

bis.b #BTME,&ME2 ; enable Basic Timer

mov.b #0FFh,&LCDCTL ; set up LCD drivermov #0008h,R7 ; clear display

LOOP clr.b LCDM-1(R7)dec R7jnz LOOP

program example

configures basic timer1 as clock source for LCD module

basic timer 1


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

LCD driver module


different driving methodsstatic2MUX3MUX4MUX

memory structure for the segment bits up to 30 segment lines per module up to 15 digits in 4MUX mode On/ Off of analog generator capability select groups of segment/ digital outputs


LCD driver module

features


i

Display

Memory

15 8 bit

Segment

Output

Control

Mux

Mux

Mux

Mux

••••••

••••••

Timing Generator

Analog Voltage

Multiplexer

LCD Control & Mode Register

R23R13R03

COM0

COM2COM1

R33

COM3

S0

S2 / O2S1

S29 / O29 / CMPI

Common Output Control

LCD ModuleLCD Module

Basic Timer 1 Basic Timer 1 ModuleModule

fLCD

•••

LCD driver module

MSP430


a

b

c

d

e

f g

h

a

b

c

d

e

f g

h

COM0 COM1 COM2 COM3

segment n segment n+1

LCD driver module

7 segment display

4MUX modeA digit consists of sevensegments driven from two segment and four common lines.


LCD driver module

MDB BIT 7 6 5 4 3 2 1 0 COM 3 2 1 0 3 2 1 0

MAB 003Fh a b c h f g e d digit 15003Eh a b c h f g e d digit 14003Dh a b c h f g e d digit 13003Ch a b c h f g e d digit 12003Bh a b c h f g e d digit 11003Ah a b c h f g e d digit 100039h a b c h f g e d digit 90038h a b c h f g e d digit 80037h a b c h f g e d digit 70036h a b c h f g e d digit 60035h a b c h f g e d digit 50034h a b c h f g e d digit 40033h a b c h f g e d digit 30032h a b c h f g e d digit 20031h a b c h f g e d digit 1

segm. n+1 segm. n

a

b

c

d

e

f g

h

COM0 COM1 COM2 COM3


Display memory, 4MUX drive


LCD_TYPE

;STK/EVK LCDa .equ 01hb .equ 02hc .equ 10hd .equ 04he .equ 80hf .equ 20hg .equ 08hh .equ 40h

;--- character definitions

LCD_Tab .byte a+b+c+d+e+f ; displays "0" .byte b+c ; displays "1" .byte a+b+d+e+g ; displays "2" .byte a+b+c+d+g ; displays "3" .byte b+c+f+g ; displays "4" .byte a+c+d+f+g ; displays "5" .byte a+c+d+e+f+g ; displays "6" .byte a+b+c ; displays "7" .byte a+b+c+d+e+f+g ; displays "8" .byte a+b+c+d+f+g ; displays "9" .byte a+b+c+e+f+g ; displays "A" .byte c+d+e+f+g ; displays "B" b .byte a+d+e+f ; displays "C" .byte b+c+d+e+g ; displays "D" d .byte a+d+e+f+g ; displays "E" .byte a+e+f+g ; displays "F"

COM0 COM1 COM2 COM3

a

b

c

d

e

f g

h


MDB BIT 7 6 5 4 3 2 1 0 COM 3 2 1 0 3 2 1 0

MAB 0037h e h f c g d b a digit 70036h e h f c g d b a digit 60035h e h f c g d b a digit 50034h e h f c g d b a digit 40033h e h f c g d b a digit 30032h e h f c g d b a digit 20031h e h f c g d b a digit 1

segm. n segm. n+1

LCD of the starter kitMSP430


one register used for control

LCD control and mode register LCDCTL 0030h

Use word instructions and absolute address mode.

LCD driver module

7 6 5 4 3 2 1 0

LCDM7 LCDM6 LCDM5 LCDM4 LCDM3 LCDM2 LCDM1 LCDM0

LCDCTL LCD control and mode register

segment selection mode selection


LCD driver module

mov.b #0FFh,&LCDCTL ; set up LCD drivermov #0008h,R7 ; clear display

LOOP clr.b LCDM-1(R7)dec R7jnz LOOP

MAIN mov &NUMBER,R6 ; load value of NUMBER in R6clr R7 ; register R7 := 00h

PRINT mov R6,R8 ; move R6 to R8and #000Fh,R8 ; keep lower 4 bitsmov.b LCD_Tab(R8),LCDM(R7) ; display digit on LCDrra R6 ; rotate right four timesrra R6rra R6rra R6inc R7cmp #04h,R7 ; all 4 digits onejne PRINT ; no -> go to next digitnop

program example


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

ADC


AVSS1000h

SVCC

A

D

C

B

0

Range

A/D-C Value

2000h3000h 4000h

0.75*SVCC

0.50*SVCC

0.25*SVCC

Programmable 12bit or 14 bit resolution Four programmable ranges Conversion time <100µsec,

96(12 bit) / 132(14 bit) ADCLK cycles Sample&Hold Eight Analog/Digital inputs Programmable current source Ratiometric or Absolute measurement Low current consumption, typ. 200µA Power-Down feature

to stop current consumption Large supply voltage range, 2.5V ..... 5.5V external or internal reference supply

ADC

features


analog

SVCC

Rext

A0A1A2A3A4A5A6A7

Input Buffer AIN

Input Buffer Enable AEN

AVCC

ACTL6ACTL7

ACTL1ACTL12

ACTL8

0.75 * SVCC

SVCC 2

Ran

ge

MU

X

Cap

acit

or

AR

RA

Y

Inp

ut

MU

X

Current MUX

ACTL2ACTL3ACTL4ACTL5

Successive ApproximationRegister

: 12

MDB, 16 bit

: 1: 2: 3:4

ADCLK/12

Res

isto

r D

eco

de

Conversion Result ADAT

Int. flag

AC

TL

13A

CT

L 14

AVSS

AC

TL1

4A

CT

L13

AC

TL1

2A

CT

L11

AC

TL1

0A

CT

L9A

CT

L8A

CT

L7A

CT

L6A

CT

L5A

CT

L4A

CT

L3A

CT

L2A

CT

L1A

CT

L0

Control RegisterACTL

AC

TL1

0A

CT

L9

ACTL0ACTL11

MCLK

C

B

A

D

ACTL10ACTL9

ADCLK

5

dela

y

7 2

128

128

128

128

digi

tal

16 1688

MSP430x32x

ADC


0V

DVSS

AVSS

SVCC

A1 MSP430x325

Ri

DVCC

+5.5V ... +2.5V

AVCC

R2

R1

N = 214 / [R2/(R2+R1)]

N = 214 * 0.25 * R1 / R2

0V

DVSS

AVSS

SVCC

A1 MSP430x325

Ri

DVCC

+5.5V ... +2.5V

AVCC

R2

R1

ADC

radiometric measurement


DVSS

AVSS

SVCC

A1 MSP430x325

Ri

DVCC AVCC

voltage regulator

supplyinput

Analoginput

SVCC ~ AVCCSVCC switch closed

0V

DVSS

AVSS

SVCC

A1 MSP430x325

Ri

DVCC

+5.5V ... +2.5V

AVCC

voltage regulator

supplyinput

Analoginput

0 < SVCC < AVCCSVCC switch open

ADC

absolute measurement


ADC

four register used for control input register AIN 0110h input enable register AEN 0112h ADC control register ACTL 0114h ADC data register ADAT 0118h

end-of-conversion flag ADIFG IFG2.2 0004h

clear by software


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 ADCLK Pd range select c. source AD input sel. Vref CS

ACTL ADC control register


mov #0900h,&ACTL ; set up ADC :; - external reference; - ADC input A0; - no current source; - automatic range select; - power on, ADCLK = MCLK

bis.b #020h,&P0DIR ; switch on externalbis.b #020h,&P0OUT ; on-board reference

MAIN bis #CS,&ACTL ; start conversionEOC bit.b #ADCIFG,&IFG2 ; wait for end of

; conversionjnc EOCbic.b #ADCIFG,&IFG2 ; clear flagmov &ADAT,R6 ; load conv. result in R6

program example

ADC

configures the ADC and works as converter


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

8-bit interval timer / counter



features

three major functionsserial communication or data exchangepulse counting or pulse accumulationtimer

three register used for control T/C control register TCCTL 0042h pre-load register TCPLD 0043h counter register TCDAT 0044h

P0.1 or counter interrupt flag P0IFG IFG1.3 0002h P0.1 or counter interrupt enable P0IE.1 IE1.3 0000h P0.1 interrupt edge select P0IES.1 P0IES 0014h




8

CLK2 Counter TCDAT

Load RC

SSEL0 1

SS

EL

0S

SE

L1

ISC

TL

EN

CN

TR

XA

CT RX

DT

XD TX

E

Interrupt request IRQP0.1

P0IE.1

IRQA

ISCTL

1

0

P0IES.1P0.1

Q0 ...Q7

EN

'Write' to TCDAT

Clear

D+ Q

ACLK

MCLK

RXD_FF

TXD_FFPUC

TXD

ENCNT

RXD

RXACT

Set

Clear

Q1

0

123

0

Set

D Q

PUC

Set

D Q

P0.2Output control

P0O

UT

.2

P0D

IR.2

TX

E

T/C Control Reg.TCCTL

Pre-load Register TCPLD

interrupt logicP0.1 and 8bit T/C

counter, preloadand control register

serial communication support


D0 D1 D2 D3 D4 D5 D6 D7

LSB MSB

start bit

eight data bits

stop bit

high

low

t


serial asynchronous data format


D0 D1 D2 D3 D4 D5 D6 D7

LSB MSB

start bit

eight data bit

stop bit

high

low

t

begin of frameis the falling

edge of start bit

level detection in the middle

of the bit


serial asynchronous data format (reading)


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

timer / port module


timer / port module

features

six tri-state output ports (one bidirectional) precision comparator CMPI for slope A/D conversion

or standard digital input CIN

two 8-bit counters, cascadable for 16-bit counter three clock sources for counting up the counter three interrupt sources



EnableControl

Set_EN1FG

ENB ENA

CMP

MCLKACLK

TPSSEL1 TPSSEL0

0123

CPON

CIN

CMPI

VCC/4

TPSSEL001

EN1

CLK1

EN2

Set_RC1FG

CLK2

RC1

RC2

Set_RC2FG

TP.3 TPD.3

TPE.3

TP.4 TPD.4

TPE.4

TP.1 TPD.1

TPE.1

TP.2 TPD.2

TPE.2

TP.0 TPD.0

TPE.0

TP.5 TPD.5

TPE.5

CMP

MCLKACLK

TPSSEL3 TPSSEL2

0123

TPIN.5

TP

IN.5

TPIN.5

B16

TP

SE

L1

TP

SE

L0

EN

BE

NA

EN

1R

C2F

GR

C1F

GE

N1F

G

B16

CP

ON

TP

D.5

TP

D.4

TP

D.3

TP

D.2

TP

D.1

TP

D.0

Control RegisterTPCTL

Data RegisterTPD

TP

SE

L3

TP

SE

L2

TP

E.5

TP

E.4

TP

E.3

TP

E.2

TP

E.1

TP

E.0

Data Enable Register TPE

Timer/Port

timer / port module


five register used for control TP control register TPCTL 004Bh TP counter 1 register TPCNT1 004Ch TP counter 2 register TPCNT2 004Dh TP O/P data register TPD 004Eh TP data enable register TPE 004Fh

timer/port interrupt enable TPIEIE2.3 0001h


timer / port module


mov.b #060h,&TPCTL ; set clock for TPCNT1 enable TPCNT1 with TP.5-INmov.b #00h,&TPE ; disable outputsmov.b #080h,&TPD ; select 16-bit modeclr.b &TPCNT2 ; set timer start valuesclr.b &TPCNT1bis.b #TPIE,&IE2 ; enable Timer/Port interrupteint ; global interrupt enable

MAIN jmp MAIN ; infinite loop

; Timer/Port Interrupt Service Routine

TPISR bit.b #EN1FG,&TPCTL ; detect interrupt sourcejnc TPI_EX ; jump if source = overflowclr R5 ; prepare counter resultmov.b &TPCNT2,R5 ; read high part of counter resultswpb R5 ; swap low- and high partclr R6 ; prepare counter resultmov.b &TPCNT1,R6 ; read low part of counterbis R6,R5 ; build the counter result by logic OR

OUT ... ; print counter result to LCD

clr.b &TPCNT2 ; set timer start valuesclr.b &TPCNT1

TPI_EX bic.b #(RC2FG+EN1FG),&TPCTL ; clear interrupt flagsreti ; return from interrupt

program example pulse with measurement with timer / port

timer / port module


MAB

MDBBus conv.

I/OPort

LCD

ADC12+2 bit

Watch

BasicTimer

TimerPort

8 bitTimer

RAMROM

CPU

FLLPowerJTAG

watchdog timer module



features

eight software selectable time intervals two operation modes

watchdog

expiration of time interval generates a system reset interval timer

expiration of time interval generates a interrupt request

write the watchdog control register is only possible using a password


CLK

Q6

16-bit Counter

WDT Control Register

MDB, LowByte

HOLD

NMIES

NMI

TMSEL

CNTCL

SSEL

IS1

IS0

SSEL

ACLK

MCLK

Q9 Q13 Q15

0

1

IS1

IS0012

Password Compare

MDB, HighByte

3

HOLD

R/W

EN

CNTCL

Clear

IE1.0

PUC

Clear

WDTIE

IFG1.0

PORIRQA

Clear

WDTIFG

IRQTMSEL

S

Resetwd2

Resetwd1

Power-up

V

EQU

RST/NMI____

POR

WDTQn TMSEL

NMI

PUC

CC

Circuitry

PUC

EQU

IRQ:IRQA:

Interrupt RequestInterrupt Request Accepted

timer/counter and interrupt logic

power-on reset POR and power-up clear PUC logic

WDT control register with protection

Read: HighByte is 069h

Write: HighByte is 05Ah, otherwise

security key is violated




one register used for control watchdog timer control register WDTCTL 0120h


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 0 1 0 0 1 HOLD NMIES NMI TMSEL CNTCL SSEL IS1 IS0

WDTCTL watchdog control register (read)

Password (69h)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 1 1 0 1 0 HOLD NMIES NMI TMSEL CNTCL SSEL IS1 IS0

WDTCTL watchdog control register (write)

Password (5Ah)


program example

disables the watchdog timer

WDTCTL .equ 0120hWDTHold .equ 80hWDT_wrkey .equ 05A00h

Marke mov #(WDTHold+WDT_wrkey),&WDTCTL ; stop Watchdog



MSP430 roadmap

Price

Complexity

x310

x320

x330

with LCDdriver

without LCDdriver

x11xMore to come

CPU,Timer/Port

CPU,A/D converterTimer/Port

CPU,H/W MPYUSART,Timer_ATimer/Port


MAB

MDBBus conv.

I/OPort

I/OPort

I/OPort

I/OPort

LCD

TimerA

WatchMUL

BasicTimer

TimerPort

8 bitTimer

Univ.USART

RAMROM

CPU

FLLPowerJTAG

architectural overview: configuration ‘330


microcontroller basicsa description based on TI‘s MSP430

author and speaker

Prof. Dr. Matthias Sturm

based on TI‘s design seminar MSP430

Special thanks for listening the

Prof. Dr. Matthias Sturm HTWK Leipzigmicrocontroller basics a description based on TI‘s MSP430...

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Transcript of Prof. Dr. Matthias Sturm HTWK Leipzigmicrocontroller basics a description based on TI‘s MSP430...