Prof. Dae Hyun Kim School of Electrical Engineering …daehyun/teaching/2015_EE582/ppt/02...Prof....
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EE582 Physical Design Automation of VLSI Circuits and Systems
Prof. Dae Hyun Kim
School of Electrical Engineering and Computer Science Washington State University
Partitioning
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2 Physical Design Automation of VLSI Circuits and Systems
What We Will Study
• Partitioning – Practical examples – Problem definition – Deterministic algorithms
• Kernighan-Lin (KL) • Fiduccia-Mattheyses (FM) • h-Metis
– Stochastic algorithms • Simulated-annealing
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3 Physical Design Automation of VLSI Circuits and Systems
Example
Source: http://upload.wikimedia.org/wikipedia/commons/3/37/Dolby_SR_breadboard.jpg
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4 Physical Design Automation of VLSI Circuits and Systems
Example
• ASIC Placement
Source: Nam, “Modern Circuit Placement”
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5 Physical Design Automation of VLSI Circuits and Systems
VLSI Circuits
• # interconnections – Intra-module: many – Inter-module: few
Source: David, “A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) – Part I: Derivation and Validation,” TCAD’98
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6 Physical Design Automation of VLSI Circuits and Systems
Problem Definition
• Given – A set of cells: T = {c1, c2, …, cn}. |W|=n. – A set of edges (netlist): R = {e1, e2, …, em}. |R|=m. – Cell size: s(ci) – Edge weight: w(ej) – # partitions: k (k-way partitioning). P = {P1, …, Pk} – Minimum partition size: b ≤ s(Pi) – Balancing factor: max(s(Pi)) – min(s(Pj)) ≤ B – Graph representation: edges / hyper-edges
• Find k partitions
– P = {P1, …, Pk}
• Minimize – Cut size: ∑ 𝑤𝑤(𝑒𝑒)∀𝑒𝑒(𝑢𝑢1,…,𝑢𝑢𝑢𝑢)∈𝑝𝑝(𝑢𝑢𝑢𝑢)≠𝑝𝑝(𝑢𝑢𝑢𝑢)
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7 Physical Design Automation of VLSI Circuits and Systems
Problem Definition
• A set of cells – T = {c1, c2, …, cn}. |W|=n
c1
c2
c3
c4
c5
c6
c7
c8
e1
e2
e3
e4
e6
e5
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8 Physical Design Automation of VLSI Circuits and Systems
Problem Definition
• A set of edges (netlist, connectivity) – R = {e1, e2, …, em}. |R|=m
c1
c2
c3
c4
c5
c6
c7
c8
e1
e2
e3
e4
e6
e5
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9 Physical Design Automation of VLSI Circuits and Systems
k-way Partitioning
• k=2, |Pi|=4
c1
c2
c3
c4
c5
c6
c7
c8
c1
c2
c3
c4
c5
c6
c7
c8
P1 = {c1, c2, c3, c4}
P2 = {c5, c6, c7, c8}
P1 = {c1, c2, c3, c5}
P2 = {c4, c6, c7, c8}
Cut size = 3 Cut size = 3
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10 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Problem definition – Given
• A set of vertices (cell list): V = {c1, c2, …, c2n}. |T|=2n. • A set of two-pin edges (netlist): E = {e1, e2, …, em}. |E|=m. • Weight of each edge: w(ej) • Vertex size: s(ci) = 1
– Constraints
• # partitions: 2 (two-way partitioning). P = {A, B} • Balanced partitioning: |A| = |B| = n
– Minimize
• Cutsize
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11 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Cost function: cutsize = ∑ 𝑤𝑤(𝑒𝑒)𝑒𝑒∈𝜓𝜓 – Ψ: cut set = {e2, e4, e5} – Cutsize = w(e2) + w(e4) + w(e5)
e1
e2 e3
e4
A={c1, c2, c3}
c1
c2
c3 c6
c4
c5
B={c4, c5, c6}
e5
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12 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Algorithm
Find an initial solution
Improve the solution
Best? Keep the best one.
No more improvement?
Yes
No
End
Yes
No
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13 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Iterative improvement
Current Optimal
A B A* B*
X Y Y X
How can we find X and Y?
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14 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Iterative improvement – Find a pair of vertices such that swapping the two vertices
reduces the cutsize.
ca
cb
Cutsize = 4
ca cb
Cutsize = 3
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15 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Gain computation – For each cell a
• External cost = Ea =∑𝑤𝑤(𝑒𝑒𝑒𝑒𝑒𝑒) for all v∈B = ∑𝑤𝑤(external edges) • Internal cost = Ia = ∑𝑤𝑤(𝑒𝑒𝑒𝑒𝑒𝑒) for all v∈A = ∑𝑤𝑤(internal edges) • D-value (a) = Da = Ea – Ia
– For each pair (a, b)
• Gain = gab = Da + Db – 2w(eab)
– gab = {(Ea – w(eab)) – Ia}+ {(Eb – w(eab)) – Ib} = Da + Db – 2w(eab)
a
b
A B
Ea = 4 Ia = 2 Da = 2
Eb = 1 Ib = 0 Db = 1
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16 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Find a best-gain pair among all the gate pairs
c1 c2
c5
c6
c3
c4
A B
Ea Ia Da
c1 1 0 1 c2 1 2 -1 c3 0 1 -1 c4 2 1 1 c5 1 1 0 c6 1 1 0
g12 = 1 – 1 – 2 = -2 g13 = 1 – 1 – 0 = 0 g14 = 1 + 1 – 0 = +2 g52 = 0 – 1 – 0 = -1 g53 = 0 – 1 – 0 = -1 g54 = 0 + 1 – 2 = -1 g62 = 0 – 1 – 0 = -1 g63 = 0 – 1 – 0 = -1 g64 = 0 + 1 – 2 = -1
gab = Da + Db – 2w(eab)
Cutsize = 3
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17 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Swap and Lock – After swapping, we lock the swapped cells. The locked cells will
not be moved further.
c4 c2
c5
c6
c3
c1
A B
Ea Ia Da
c1 1 0 1 c2 1 2 -1 c3 0 1 -1 c4 2 1 1 c5 1 1 0 c6 1 1 0
Cutsize = 1
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18 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Update of the D-value – Update the D-value of the cells affected by the move.
• Dx’ = Ex’ – Ix’ = {Ex – w(exb) + w(exa)} – {Ix + w(exb) – w(exa)} = (Ex – Ix) + 2w(exa) – 2w(exb) = Dx + 2w(exa) – 2w(exb)
• Dy’ = (Ey – Iy) + 2w(eyb) – 2w(eya) = Dy + 2w(eyb) – 2w(eya)
ca
cb
x
y
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19 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Update
Da Da’ c1 1 c2 -1 -1 + 2 – 2 = -1 c3 -1 -1 c4 1 c5 0 0 + 0 – 2 = -2 c6 0 0 + 0 – 2 = -2
Dx’ = Dx + 2*w(exa) – 2*w(exb) Dy’ = Dy + 2*w(eyb) – 2*w(eya)
c1 c2
c5
c6
c3
c4
A B
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20 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Gain computation and pair selection
Da’ c1
c2 -1 c3 -1 c4
c5 -2 c6 -2
g52 = -2 – 1 – 0 = -3 g53 = -2 – 1 – 0 = -3 g62 = -2 – 1 – 0 = -3 g63 = -2 – 1 – 0 = -3
gab = Da + Db – 2w(eab)
c4 c2
c5
c6
c3
c1
A B
Cutsize = 1
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21 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Swap and update
Da Da’ c1
c2 -1 -1 + 2 – 0 = +1 c3 -1 c4
c5 -2 -2 + 2 – 0 = 0 c6 -2
Dx’ = Dx + 2*w(exa) – 2*w(exb) Dy’ = Dy + 2*w(eyb) – 2*w(eya)
c4 c2
c5
c6
c3
c1
A B
Cutsize = 1
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22 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Swap and update
Da
c1
c2 +1 c3
c4
c5 0 c6
Dx’ = Dx + 2*w(exa) – 2*w(exb) Dy’ = Dy + 2*w(eyb) – 2*w(eya)
c4 c2
c5 c6
c3 c1
A B
Cutsize = 4
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23 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Gain computation
Da
c1
c2 +1 c3
c4
c5 0 c6
g52 = +1 + 0 – 0 = +1
gab = Da + Db – 2w(eab)
c4 c2
c5 c6
c3 c1
A B
Cutsize = 4
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24 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Swap
c4
c2
c5
c6
c3 c1
A B
Cutsize = 3
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25 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Cutsize – Initial: 3
• g1 = +2 – After 1st swap: 1
• g2 = -3 – After 2nd swap: 4
• g3 = +1 – After 3rd swap: 3
c4 c2
c5
c6
c3
c1
A B
Cutsize = 1
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26 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Algorithm (a single iteration) 1. V = {c1, c2, …, c2n} {A, B}: initial partition 2. Compute Dv for all v ∈ V queue = {}, i = 1, A’=A, B’=B 3. Compute gain and choose the best-gain pair (ai, bi). queue += (ai, bi), A’ = A’-{ai}, B’=B’-{bi} 4. If A’ and B’ are empty, go to step 5. Otherwise, update D for A’ and B’ and go to step 3. 5. Find k maximizing G=∑ 𝑔𝑔𝑖𝑖𝑘𝑘
𝑢𝑢=1
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27 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Algorithm (overall) 1. Run a single iteration. 2. Get the best partitioning result in the iteration. 3. Unlock all the cells. 4. Re-start the iteration. Use the best partitioning result for the
initial partitioning of the next iteration.
• Stop criteria – Max. # iterations – Max. runtime – Δ Cutsize between the two consecutive iterations. – Target cutsize – …
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28 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Complexity analysis 1. V = {c1, c2, …, c2n} {A, B}: initial partition 2. Compute Dv for all v ∈ V queue = {}, i = 1, A’=A, B’=B 3. Compute gain and choose the best-gain pair (ai, bi). queue += (ai, bi), A’ = A’-{ai}, B’=B’-{bi} 4. If A’ and B’ are empty, go to step 5. Otherwise, update D for A’ and B’ and go to step 3. 5. Find k maximizing G=∑ 𝑔𝑔𝑖𝑖𝑘𝑘
𝑢𝑢=1
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29 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Complexity of the D-value computation – External cost (a) = Ea =∑𝑤𝑤(𝑒𝑒𝑒𝑒𝑒𝑒) for all v∈B – Internal cost (a) = Ia = ∑𝑤𝑤(𝑒𝑒𝑒𝑒𝑒𝑒) for all v∈A – D-value (a) = Da = Ea – Ia
a
b
A B
Ea = 4 Ia = 2 Da = 2
Eb = 1 Ib = 0 Db = 1
For each cell (node) a For each net connected to cell a Compute Ea and Ia
Practically O(n) n: # nodes
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30 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Complexity of the gain computation – gab = Da + Db – 2w(eab)
For each pair (a, b) gab = Da + Db – 2w(eab)
Complexity: O((2n – 2i + 2)2)
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31 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Complexity of the D-value update for swapping a and b – Dx’ = Dx + 2w(exa) – 2w(exb) – Dy’ = Dy + 2w(eyb) – 2w(eya)
For a (and b) For each cell x connected to cell a (and b) Update Dx and Dy
Practically O(1)
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32 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Complexity analysis 1. V = {c1, c2, …, c2n} {A, B}: initial partition 2. Compute Dv for all v ∈ V queue = {}, i = 1, A’=A, B’=B 3. Compute gain and choose the best-gain pair (ai, bi). queue += (ai, bi), A’ = A’-{ai}, B’=B’-{bi} 4. If A’ and B’ are empty, go to step 5. Otherwise, update D for A’ and B’ and go to step 3. 5. Find k maximizing G=∑ 𝑔𝑔𝑖𝑖𝑘𝑘
𝑢𝑢=1
O((2n-2i+2)2)
Loop. # iterations: n
Overall: O(n3)
O(n)
O(1)
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33 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Reduce the runtime – The most expensive step: gain computation (O(n2))
• Compute the gain of each pair: gab = Da + Db – 2w(eab) – How to expedite the process
• Sort the cells in the decreasing order of the D-value – Da1 ≥ Da2 ≥ Da3 ≥ … in partition A – Db1 ≥ Db2 ≥ Db3 ≥ … in partition B
• Keep the max. gain (gmax) found until now. • When computing the gain of (Dal, Dbm)
– If Dal + Dbm < gmax, we don’t need to compute the gain for all the pairs (Dak, Dbp) s.t. k>l and p>m.
– Practically, it takes O(1).
– Complexity: O(n*logn) for sorting.
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34 Physical Design Automation of VLSI Circuits and Systems
Kernighan-Lin (KL) Algorithm
• Complexity analysis 1. V = {c1, c2, …, c2n} {A, B}: initial partition 2. Compute Dv for all v ∈ V queue = {}, i = 1, A’=A, B’=B 3. Compute gain and choose the best-gain pair (ai, bi). queue += (ai, bi), A’ = A’-{ai}, B’=B’-{bi} 4. If A’ and B’ are empty, go to step 5. Otherwise, update D for A’ and B’ and go to step 3. 5. Find k maximizing G=∑ 𝑔𝑔𝑖𝑖𝑘𝑘
𝑢𝑢=1
O(n log n)
Overall: O(n2 log n)
O(n) Loop. # iterations: n
O(1)
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35 Physical Design Automation of VLSI Circuits and Systems
Questions
• Can the KL algorithm handle – hyperedges? – unbalanced partitions? – fixed cells (e.g., cell k should be in partition A)? – …
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36 Physical Design Automation of VLSI Circuits and Systems
Questions
• Intentionally left blank
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37 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Handles – Hyperedges
– Imbalance (unequal partition sizes) – Runtime: O(n)
• Idea
– Move a cell instead of swapping two cells.
edge hyperedge
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38 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Algorithm
Find an initial solution
Improve the solution
Best? Keep the best one.
No more improvement?
Yes
No
End
Yes
No
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39 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Definitions – Cutstate(net)
• uncut: the net has all the cells in a single partition. • cut: the net has cells in both the two partitions.
– Gain of cell: # nets by which the cutsize will decrease if the cell
were to be moved.
– Balance criterion: To avoid having all cells migrate to one block. • r·|V| - smax ≤ |A| ≤ r·|V| + smax • |A| + |B| = |V|
– Base cell: The cell selected for movement.
• The max-gain cell that doesn’t violate the balance criterion.
Max cell size
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40 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Definitions (continued) – Distribution (net): (A(n), B(n))
• A(n): # cells connected to n in A • B(n): # cells connected to n in B
– Critical net • A net is critical if it has a cell that if moved will change its cutstate.
– cut to uncut – uncut to cut
• The distribution of the net is (0,x), (1,x), (x,0), or (x,1).
Distribution (n1) = (1, 1) Distribution (n2) = (0, 1) Distribution (n3) = (0, 2) Distribution (n4) = (2, 1) Distribution (n5) = (1, 1) Distribution (n6) = (2, 0)
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41 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Critical net – Moving a cell connected to the net changes the cutstate of the
net.
A B A B A B A B
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42 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Algorithm 1. Gain computation
• Compute the gain of each cell move
2. Select a base cell (a max-gain cell)
3. Move and lock the base cell and update gain.
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43 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Gain computation – F(c): From_block (either A or B) – T(c): To_block (either B or A)
– gain = g(c) = FS(c) – TE(c)
• FS(c): |P| s.t. P = {n | c ∈ n and dis(n) = (F(c), T(c)) = (1, x)} • TE(c): |P| s.t. P = {n | c ∈ n and dis(n) = (F(c), T(c)) = (x, 0)}
A B
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44 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Gain computation
A B
c1
c2
c3
c4
c5
c6
m
q
k
j
p
gain = g(c) = FS(c) – TE(c) FS(c): # nets whose dis. = (F(c), T(c)) = (1, x)} TE(c): # nets whose dis. = (F(c), T(c)) = (x, 0)}
Distribution of the nets (A, B) m: (3, 0) q: (2, 1) k: (1, 1) p: (1, 1) j: (0, 2) Gain g(c1) = 0 – 1 = -1 g(c2) = 2 – 1 = +1 g(c3) = 0 – 1 = -1 g(c4) = 1 – 1 = 0 g(c5) = 1 – 1 = 0 g(c6) = 1 – 0 = +1
For each net n connected to c if F(n) = 1, g(c)++; if T(n) = 0, g(c)--;
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45 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Select a base (best-gain) cell.
A B
c1
c2
c3
c4
c5
c6
m
q
k
j
p
Gain g(c1) = 0 – 1 = -1 g(c2) = 2 – 1 = +1 g(c3) = 0 – 1 = -1 g(c4) = 1 – 1 = 0 g(c5) = 1 – 1 = 0 g(c6) = 1 – 0 = +1
Size: 3
S: 2
S: 4
S: 1
S: 3
S: 5
Balance factor: 0.4
S(A) = 9, S(B) = 9 Area criterion: [0.4*18-5, 0.4*18+5] = [2.2, 12.2]
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46 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Before move, update the gain of all the other cells.
A B
c1
c2
c3
c4
c5
c6
m
q
k
j
p
Size: 3
S: 2
S: 4
S: 1
S: 3
S: 5
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47 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Original code for gain update – F: From_block of the base cell – T: To_block of the base cell – For each net n connected to the base cell
• If T(n) = 0 – gain(c)++; // for c ∈ n
• Else if T(n) = 1 – gain(c)--; // for c ∈ n & T
• F(n)--; • T(n)++; • If F(n) = 0
– gain(c)--; // for c ∈ n • Else if F(n) = 1
– gain(c)++; // for c ∈ n & F
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48 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Gain update (reformulated) – F: From_block of the base cell – T: To_block of the base cell – For each net n connected to the base cell
• If T(n) = 0 – gain(c)++; // for c ∈ n
• Else if T(n) = 1 – gain(c)--; // for c ∈ n & T
• If F(n) = 1 – gain(c)--; // for c ∈ n
• Else if F(n) = 2 – gain(c)++; // for c ∈ n & F
• F(n)--; • T(n)++;
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49 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Gain update
F T
base cell
F T
g: -1 g: +1
F T
g: -1 g: -1
F T
g: 0 g: 0
Case 1) T(n) = 0
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50 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Gain update
F T
base cell
F T
g: +1 g: -1
F T
g: 0 g: +1
F T
g: +1 g: 0
Case 2) T(n) = 1
F T
g: 0 g: +1
F T
g: 0 g: 0 g: 0
g: 0
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51 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Instead of enumerating all the cases, we consider the following combinations.
F(n) = 1 T(n) = 0
F(n) = 2 T(n) = 1
F(n) ≥ 3 T(n) ≥ 2
(2) (3)
(4)
(5)
(6) (7)
(8)
(9)
Δg(c) in F Δg(c) in T F(n) T(n)
(1) (2) -2 1 1 (3) -1 1 ≥ 2 (4) +2 2 0 (5) +1 -1 2 1 (6) +1 2 ≥ 2 (7) +1 ≥ 3 0 (8) -1 ≥ 3 1 (9)
(1)
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52 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Conversion from the table to a source code.
Δg(c) in F Δg(c) in T F(n) T(n)
(1) (2) -2 1 1 (3) -1 1 ≥ 2 (4) +2 2 0 (5) +1 -1 2 1 (6) +1 2 ≥ 2 (7) +1 ≥ 3 0 (8) -1 ≥ 3 1 (9)
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53 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Conversion from the table to a source code.
Δg(c) in F Δg(c) in T F(n) T(n)
(1) (2) -2 1 1 (3) -1 1 ≥ 2 (4) +2 2 0 (5) +1 -1 2 1 (6) +1 2 ≥ 2 (7) +1 ≥ 3 0 (8) -1 ≥ 3 1 (9)
T(n) = 0 : g(c)++; // c ∈ n & F
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54 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Conversion from the table to a source code.
Δg(c) in F Δg(c) in T F(n) T(n)
(1) (2) -2 1 1 (3) -1 1 ≥ 2 (4) +2 2 0 (5) +1 -1 2 1 (6) +1 2 ≥ 2 (7) +1 ≥ 3 0 (8) -1 ≥ 3 1 (9)
T(n) = 1 : g(c)--; // c ∈ n & T
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55 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Conversion from the table to a source code.
Δg(c) in F Δg(c) in T F(n) T(n)
(1) (2) -2 1 1 (3) -1 1 ≥ 2 (4) +2 2 0 (5) +1 -1 2 1 (6) +1 2 ≥ 2 (7) +1 ≥ 3 0 (8) -1 ≥ 3 1 (9)
F(n) = 1 : g(c)--; // c ∈ n & T
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56 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Conversion from the table to a source code.
Δg(c) in F Δg(c) in T F(n) T(n)
(1) (2) -2 1 1 (3) -1 1 ≥ 2 (4) +2 2 0 (5) +1 -1 2 1 (6) +1 2 ≥ 2 (7) +1 ≥ 3 0 (8) -1 ≥ 3 1 (9)
F(n) = 2 : g(c)++; // c ∈ n & F
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57 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Gain update – F: From_block of the base cell – T: To_block of the base cell – For each net n connected to the base cell
• If T(n) = 0 – gain(c)++; // for c ∈ n
• If T(n) = 1 – gain(c)--; // for c ∈ n
• If F(n) = 1 – gain(c)--; // for c ∈ n
• If F(n) = 2 – gain(c)++; // for c ∈ n
• F(n)--; • T(n)++;
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58 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Before move, update the gain of all the other cells.
A B
c1
c2
c3
c4
c5
c6
m
q
k
j
p
Size: 3
S: 2
S: 4
S: 1
S: 3
S: 5
Δg(c) in F Δg(c) in T F(n) T(n) (2) -2 1 1
(3) -1 1 ≥ 2
(4) +2 2 0
(5) +1 -1 2 1
(6) +1 2 ≥ 2
(7) +1 ≥ 3 0
(8) -1 ≥ 3 1
Gain (before move) g(c1) = 0 – 1 = -1 g(c2) = 2 – 1 = +1 g(c3) = 0 – 1 = -1 g(c4) = 1 – 1 = 0 g(c5) = 1 – 1 = 0 g(c6) = 1 – 0 = +1
Gain (after move) g(c1) = -1 + 1 = 0 g(c3) = -1 + 1 + 1 = +1 g(c4) = 0 – 1 = -1 g(c5) = 0 – 2 = -2 g(c6) = 1 – 2 = -1
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59 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Move and lock the base cell.
A B
c1
c2
c3
c4
c5
c6
m
q
k
j
p
Size: 3
S: 2
S: 4
S: 1
S: 3
S: 5
Gain (after move) g(c1) = -1 + 1 = 0 g(c3) = -1 + 1 + 1 = +1 g(c4) = 0 – 1 = -1 g(c5) = 0 – 2 = -2 g(c6) = 1 – 2 = -1
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60 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Choose the next base cell (except the locked cells). • Update the gain of the other cells. • Move and lock the base cell. • Repeat this process.
• Find the best move sequence.
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61 Physical Design Automation of VLSI Circuits and Systems
Fiduccia-Mattheyses (FM) Algorithm
• Complexity analysis 1. Gain computation
• Compute the gain of each cell move
2. Select a base cell
3. Move and lock the base cell and update gain.
For each net n connected to c if F(n) = 1, g(c)++; if T(n) = 0, g(c)--;
Practically O(# cells or # nets)
O(1)
Practically O(1)
# iterations: # cells
Overall: O(n or c)
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62 Physical Design Automation of VLSI Circuits and Systems
Simulated Annealing
• Borrowed from chemical process
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63 Physical Design Automation of VLSI Circuits and Systems
Simulated Annealing
• Algorithm T = T0 (initial temperature) S = S0 (initial solution) Time = 0
repeat Call Metropolis (S, T, M); Time = Time + M; T = α · T; // α: cooling rate (α < 1) M = β · M; until (Time ≥ maxTime);
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64 Physical Design Automation of VLSI Circuits and Systems
Simulated Annealing
• Algorithm Metropolis (S, T, M) // M: # iterations
repeat NewS = neighbor(S); // get a new solution by perturbation Δh = cost(NewS) – cost(S); If ((Δh < 0) or (random < e-Δh/T)) S = NewS; // accept the new solution M = M – 1;
until (M==0)
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65 Physical Design Automation of VLSI Circuits and Systems
Simulated Annealing
• Cost function for partition (A, B) – Imbalance(A, B) = Size(A) – Size(B) – Cutsize(A, B) = Σwn for n ϵ ψ – Cost = Wc · Cutsize(A, B) + Ws · Imbalance(A, B)
• Wc and Ws: weighting factors
• Neighbor(S)
– Solution perturbation • Example: move a free cell.
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66 Physical Design Automation of VLSI Circuits and Systems
hMetis
• Clustering-based partitioning – Coarsening (grouping) by clustering – Uncoarsening and refinement for cut-size minimization
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67 Physical Design Automation of VLSI Circuits and Systems
hMetis
• Coarsening
c3
c6
c4
c1
c2
c8
c7
c5
c3
c6
c4'
c8
c7
c5
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68 Physical Design Automation of VLSI Circuits and Systems
hMetis
• Coarsening – Reduces the problem size
• Make sub-problems smaller and easier. – Better runtime – Higher probability for optimality
– Finds circuit hierarchy
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69 Physical Design Automation of VLSI Circuits and Systems
hMetis
• Algorithm 1. Coarsening 2. Initial solution generation
- Run partitioning for the top-level clusters. 3. Uncoarsening and refinement
- Flatten clusters at each level (uncoarsening). - Apply partitioning algorithms to refine the solution.
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70 Physical Design Automation of VLSI Circuits and Systems
hMetis
• Three coarsening methods.
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71 Physical Design Automation of VLSI Circuits and Systems
hMetis
• Re-clustering (V- and v-cycles) – Different clustering gives different cutsizes.
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72 Physical Design Automation of VLSI Circuits and Systems
hMetis
• Final results
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73 Physical Design Automation of VLSI Circuits and Systems
hMetis
• Final results