Production Readiness Review

Mar-04 E.Ladygin, L.Kurchaninov 1

Production Readiness Review

E. LadyginJoint Institute for Nuclear Research, Dubna,

RussiaL. Kurchaninov

Max-Planck-Institut für Physik, Munich, Germany

Tower Driver Board for the ATLAS Hadronic End-Cap and Forward Calorimeters


1. Design review and follow-up

All power inputs are to be fused, with large safety factors (at least a factor of 2) for the current limits. The fuse should be soldered to the board.

The usage of voltage regulators is required in all front-end boards. In particular, the TDB circuits biased with +5.2V and –5.2V produced from external +7.0V and –7.0V respectively.

Voltages on the power lines of the LARG front-end crate fixed to +7.0V (line 4) and -7.0V (line 9). The TDB has to be modified to use these values.

The TDB will not employ a cooling plate in order to have adequate room on the front panel for the six cable connectors. The resulting off-loading of power to neighbouring boards in the crate has to be measured.

The Level 1 trigger cables have line impedance of 88, this value should be used when considering resistance values for back termination of the cable.

TDB has been reviewed in June 2002 with following comments:



The wiring of grounds in TDB should follow the scheme used in tower builder board.

To study saturation waveforms to insure that there are no surprises.

Although the pre-selection tests for the AD8001 have been made, ATLAS rules require that radiation tests have to be carried out for the batch of chips used in production.

It would be prudent to verify that there are no high-frequency oscillations by measuring the spectrum up to 1GHz with a spectrum analyzer.

Connector shields must be installed (i.e. the holes provided for this installation). This is essential to preserve electromechanical integrity of the Front End Crate, by providing balanced forces on the spring contact for adjacent boards.

Comments:



As a follow-up of the design review, the prototype boards have been studied in the HEC-specific front-end crate test in February-March 2003.

After the pinout of negative voltage regulator was fixed, the TDB has been re-designed taking into account all other requirements and recommendations.

One pre-production board has been produced and tested in laboratory conditions in the fall 2003.


2. HEC trigger architecture

The trigger tower is formed by analog sum of signals from longitudinal segments of the same , location.

In the both Forward and HEC calorimeters the summing is performed on the front-end boards (FEB):

for HEC – by Linear Mixer

for FCAL – by Linear Mixer and Layer Sum Board

The function of Tower Driver Board is to produce differential signals and to drive 70-m trigger cables.


2. HEC trigger architecture

One HEC FEB delivers 32 trigger signals, so in total there are 192 trigger channels per quadrant. These signals are collected to two TDB, so each board has 96 channels.

FE B 1 FE B 2

FE B 3

FE B 5

FE B 4

FE B 6

TDB 2

TDB 1

bins

O

bins ()

D E

bins (12...15)

HEC trigger towers


1.TDB has the same dimensions as other front-end boards: WxLxH = 490x409.5x20.3 mm

2.Power supply from the front-end crate power bars 4 (+7V) and 9 (-7V) similar to the tower builder board

3.Power dissipation is less then 15 W. It allows do not use the cooling plates

4.Input impedance is 50 5%

5.High frequency band. Integrating time constant is less than 2 ns

6.Gain as a ratio of the output differential to input unipolar amplitudes is close to 1 for ~88 output load

TDB specification requirements

3. TDB specification requirements


3. TDB specification requirements

7.Gain variation from channel to channel (RMS) not more than 1%

8.Integral nonlinearity less than 1% for the range of amplitudes up to 3V

9.Noise level is low enough so that its contribution to the total noise is less than 5%. For typical noise level at the LSB output it leads to ~300 V of the noise RMS at the TDB output

10.Crosstalk is not more than 1%

11.Output impedance in each line is 44 5%

12.Radiation stability up to -dose of 397 Gy and neutron fluence of 2.91012

n/cm2

TDB specification requirements


4. TDB design

TDB contains 96 channels

with elements placed

on one side of PCB.

Board Layout


4. TDB design

The TDB module is

shielded by the

simple aluminium

sheet.

Board Layout


4. TDB design

Amplifiers of AD8001 are chosen because all pre-selection tests have been already made for the Tower Builder Board.

TDB channel scheme


4. TDB design

The crate baseplane has common ground, connected to

ground pins of the input connectors, to special “power”

plugs, and to the connector spring contacts.

Like all the front-end boards, the TDB ground is connected to

the baseplane common ground through these three paths.

Therefore, TDB will be equipped with “power” pins and

shields, covering input connector.

Grounding


4. TDB design

Ll

Grounding


4. TDB design

The output ground connections are organized in the same way as in the Tower Builder Board.

All ground shields are connected to the board ground by soldered connector pins. The front panel is connected to the PCB ground via metal cleats.

Grounding

+-

1234567891 01 11 21 31 41 5

SUB D 37c connector

Pair shield 8 to 11

Global shield

Pair shield 12 to 15

Pair shield 0 to 3 .

Pair shield 4 to 7

1 9 1 61 71 8

2 02 22 9 2 8 2 7 2 6 2 5 2 4 2 3 2 13 03 23 7 3 6 3 5 3 4 3 3 3 1

123456789101112131415 0

Pair number

Pin number


4. TDB design

The consuming power is very important for the TDB since the usage of standard cooling plates is problematic. Practically all the front panel space is occupied by the output connectors so, there is not enough room for the water plugs.

A small heat, produced by TDB will be taken out by the cooling plates of the neighbouring front-end boards.

The total dissipating power including regulators is 14.8 W which is distributed over big area of the board. No warming is expected under these conditions, so a special cooling is not needed, that was confirmed by dedicated test.

Power distribution


4. TDB design

The required bias of +5.2V and –5.2V is produced by using radiation-hard voltage regulators LHC4913 (positive) and LHC7913 (negative).

Two independent channels have been selected in order to increase the safety factor of board and decrease the power dissipation of a single voltage regulator.

Power distribution


4. TDB design

According to the general rules of RF shielding, the front panel is connected to the FEC mass through screws and completes the Faraday cage. The connection of the front panel to the board ground is provided through the aluminium support cleats.

For the TDB we intend to use LARG standard front-end panel equipped with side spring gaskets.

The element side of TDB is covered by aluminium shield for mechanical protection of components and to conduct the heat from voltage regulators. Thermal contact between voltage regulator packages and shield is provided by special thermal contact foam.

Front panel and side shield


5. Tests of prototype boards

The tests of the HEC half-crate have been carried out within the common LARG-wide activity for validation of the front-end electronics.

The tests have been performed in the HEC testbeam environment using of 3 Module-0 front-end boards equipped with final versions of preshapers, shapers and LSBs. Two prototype TDBs were connected to L1 receiver board with 70-m L1 trigger cables. The trigger signals are read out by a commercial digitizer.

HEC FEC tests in 2003



HEC specific front-end crate test setup

HEC FEC tests in 2003



The temperature variations in the crate have been studied with nominal positions of TDB1 FEB2 and FEB3 in FEC. Two temperature sensors

of each FEB have bean read out

each 12 seconds during two hours.

It can be seen that there is practically

no effect of TDB heating on the

boards in neighbouring slots.

Temperature conditions.

0 20 40 60 80 100 120

time, minutes

-1.6

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

T v

aria

tio

n, C

TDB ONTDB ON TDB OFF

FEB2 T1FEB2 T2FEB3 T1FEB3 T2



The signal waveforms have been taken by applying calibration signal of different amplitudes and delay.

In this particular measurement the signal is saturated in LSB at amplitude of about 3.0V. This value is less than expected for final FEB due to lower LSB bias voltages used in the Module-0 FEB.

Signals saturation.

0 20 40 60 80 100dac

0

500

1000

1500

2000

2500

3000

3500

ADC measuredADC predictedPRES predictedLSB predicted

Saturation level

amp

litu

de,

mV LSB saturation

100 200 300 400 500 600 700 800time, ns

-500

0

500

1000

1500

2000

dac 020dac 025dac 030dac 035dac 040dac 045dac 060dac 080dac 100

sig

na

l, m

V



The amplification factors of trigger channels have to be chosen such that amplitudes for ET = 250 GeV are between 1250 mV and

2500 mV in order to fit the range gain adjustment in receiver.

TDB input amplitudes

calculated for

Et= 250 GeV

(from Design Review)

Amplitude vs. pseudorapidity.

2 4 6 8 10 12 14 bin

1400

1600

1800

2000

2200

2400

2600

2800

3000

3200

TD

B in

pu

t, m

V

FEB1,2

LM = 1.2LSB = 2

LM = 1.2LSB = 1

FEB5,6

LM = 3.84

LSB = 1

FEB3,4



REC output amplitudes for the LAr conditions:

Et=250GeV Rpa = 0.75 k Gps = 6.1/12.4 Gmix = 1.20/3.84 Glsb = 1.0/2.0 Grec = 1.70 Sum of 3 HEC

segments

The last -bin produces low signal because a significant part of energy is deposited in FCAL.

Amplitude vs. pseudorapidity.

2 4 6 8 10 12 14 bin

800

1000

1200

1400

1600

1800

2000

2200

2400

2600

RE

C o

utp

ut,

mV

2500 mV

1250 mV


6. Tests of pre-production board

The pre-production board functionality has been evaluated in laboratory conditions. The gain and integration time constant were determined by measuring step response, applying signal from rectangular pulse generator.

Design gain value = 0.98

Functional tests

0.97 0.98 0.99 1.00

Gain

0

5

10

15

20

Mean: 0.983Std Dev.: 0.003

0.4 0.5 0.6 0.7 0.8 0.9 1.0

Ti, ns

0

5

10

15

20

Mean: 0.68Std Dev.: 0.08



The measured crosstalk between neighbouring channels is less than 1%.The typical linearity range is about 3.15V. The nonlinearity in this range is less then 0.1%.

Functional tests

0 1 2 3 4Vin, V

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06Nonlinearity, %

0 1 2 3 4Vin, V

0

1

2

3

Vout, V



The TDB responses in the linear and saturation ranges are different, but no surprising effects are observed.

Functional tests

0 50 100 150 200 250 300time, ns

0

500

1000

1500

2000

2500

3000

3500 LSB out 1.0VLSB out 2.0VLSB out 3.2VLSB out 4.0VLSB out 5.0VLSB out 6.0VT

DB

ou

tpu

t, m

V



The TDB noise performance has been studied with prototype board both in laboratory conditions and in HEC testbeam setup. No evident excess noise was detected.

The typical intrinsic noise is 100-200V.

Nevertheless, the dedicated measurements have been performed with pre-production TDB to study the noise performance in different loading conditions.

Noise studies



It was found that few channels are sensitive to the input load.

Noise studies

0 20 40 60 80 100

channel #

0

100

200

300

400

RMS, Vteminated inputopen input

Ch31Ch75



Oscillograms for channel 75.Here is some periodic structure of base line at the positive output when its input is open.

Noise studies

0 500 1000 1500 2000

Time, ns

-1

0

1

2

3

Vout, mVopen inputterminated input



The noise structure has been also studied with HP 4195 spectrum analyzer (500 MHz).

Noise studies

106 107 108

f, Hz

10-5

10-4

10-3

10-2

V²/Hzterminatedopen inputpower Off

106 107 108

f, Hz

10-5

10-4

10-3

10-2

V²/Hzterminatedopen inputpower Off

“good” channel “bad” channel (ch75)



The behaviour of excess noise has been studied while the serial resistor is added to non-inverting input of positive branch.

Noise studies



The noise is effectively damped already for small value. At the same time the rise time and amplitude are practically not changed.

In FEC the TDB inputs are loaded by 50 serial resistors at LSB outputs, so the excess noise is not expected in ATLAS. For a safety margin, a serial resistor of 100 will be added.

Noise studies

30 32 34 36 38 40

Time, ns

-200

300

800

1300

1800

2300

Vout, mV

0100180300

Rin,

0 100 200 300

Rin,

0.1

0.2

0.3

0.4RMS, mV

terminatedopen input



Radiation tests

ATLAS Radiation Hardness Assurance for the front-end crate:

TDB has only one active component - AD8001. These amplifiers have been tested by the Tower Builder Board group and pre-selection tests gave the satisfactory results. The doses achieved in those tests were 3.21013 n/cm2 for neutrons and 2180 Gy for

Simulated

doseSF sim

SF ldr

SF lot

RTC

, Gy 5.67 3.5 5 4 397

n/cm2 1.451011 5 1 4 2.91012


7. TDB production schedule

Production volume and plans

Provisional schedule:

Date Task Quantity Responsibility

1 February-March 2004

Final PCB design JINR

2 March-September

2004

Production of:- PCB

-Front panel-Side shield

-Cleat -Spacer

23232392

299

JINRMPI (BNL?)

MPIMPI (BNL?)

MPI

3 October-December

2004

QC tests 23 MPI

4 January 2005 Delivery to CERN 23 MPI



Quality assurance procedure

The quality assurance procedure includes the following steps: 1. High temperature treatment. Each board will be kept at 100C during 100 hours.

2. Visual inspection. 3. DC-tests. The potentials will be measured in specified points in order to check the working conditions.

4. Functionality tests. All important characteristics will be measured and compared to acceptance window:

- Time constant and amplification factor- Linearity- Crosstalk (few channels from each board)- Noise

Boards, which do not pass the tests, will be rejected and repaired if possible.



Quality assurance procedure

QC setup (exists):- Rectangular pulse generator- Digital oscilloscope- PC and control SW

Production Readiness Review

Documents

Transcript of Production Readiness Review