Reprinted from VMEbus Systems / August 1998 / 1 Copyright 1998 ~ All rights reserved

Today’s short development cycles and program cost con-straints are forcing radar engineers to look for ways to buildradar receivers from commercial-off-the-shelf (COTS)products. In this article Mike and Kevin describe a VMEbus-based, modular, reconfigurable digital radar receiverarchitecture that allows the rapid development of customized,high-performance digital radar systems. It employs off-the-shelf algorithm-specific VMEbus boards that are dynamicallyreconfigurable, allowing the radar system to support differentradar processing modes on a pulse-to-pulse basis.

The real-time signal processing constraints of a radar systemare dictated primarily by two system parameters:■ the time-bandwidth product (TBP)■ the pulse repetition frequency (PRF)

Pulse compression andthe Time Bandwidth Product (TBP)Many radar systems employ a technique known as pulse com-pression. When using this technique, the transmitter sends afinite-length pulse of radiation (called the transmit waveform)towards the targets. When targets are within the range of theradar system, reflections of the transmitted waveform will cre-ate a return signal which is received by the system. The distanceto each target is a function of the time from when the transmit-ter sends a pulse to when a reflection is received back at theradar system.

The receiver continuously convolves the waveform of this re-turn signal with the complex conjugate of the transmit signal,also called the reference waveform. This maximizes the signal-to-noise ratio and produces a sharp peak whenever the wave-form of the returning signal correlates well with the referencewaveform, indicating the presence of a target at that particularrange.

This technique is known as pulse compression because it pro-duces a peak that is considerably narrower than the width of theoriginal transmitted waveform. [1] This narrow pulse providesimproved range accuracy, even though a long-duration transmitwaveform might be used.

In fact, the longer the duration of the transmit waveform, thegreater the aggregate transmitted energy over time, and the bet-ter the signal-to-noise ratio of the peak. Thus, good rangingaccuracy can be obtained, even with fairly low instantaneoustransmitter power.

The ability of pulse compression to produce narrow peaks isdirectly related to the characteristics of the transmit waveform– specifically, its bandwidth and its duration (length). The prod-uct of these two parameters is known as the time bandwidth

product (TBP). For radar systems that transmit a linearly-increasing or linear decreasing FM waveform, the processinggain through the pulse compression filter is proportional to theTBP of the transmit waveform. The compressed pulse width(and thus the range accuracy) is inversely proportional to thebandwidth of the transmitted pulse [2].

So, for radar systems requiring fine range resolution and fairlylow instantaneous transmitting power, a large TBP is needed.But there is a tradeoff – the larger the TBP, the greater the pro-cessing required to implement the pulse compression.

Using SAW filters to implement pulse compressionAnalog filtering techniques, such as Surface Acoustical Wave(SAW) filters, can be used to accomplish the convolutionrequired for pulse compression. SAW filters provide the advan-tages of analog processing, such as extremely low latencies, andcontinuous operation. However, they are also burdened withanalog’s drawbacks:

■ a SAW filter must be customized for a particular referencewaveform, and it typically cannot be used with any otherwaveform. This severely limits the reconfigurability of theradar system.

■ a SAW filter’s performance is vulnerable to temperatureshifts

■ a SAW filter requires frequent recalibration

Using digital technology toimplement pulse compressionWith high performance digital computing, the convolutionoperation required for pulse compression can be done digitally.This digital approach eliminates the calibration requirementsand the limited reconfigurability of analog approaches. Thisdigital processing can be done in either the time domain or inthe frequency domain. Either technique will yield identicalresults, because convolution in the time domain is equivalentto multiplication in the frequency domain.

Processing in the time domainWhen doing the processing in the time domain, a Finite ImpulseResponse (FIR) filter is used to convolve the returning signalwith the reference waveform. The output of this convolutionoperation contains the peaks that represent the targets.

Processing in the frequency domainWhen doing the processing in the frequency domain, a FastFourier Transform (FFT) is used to transform both the referencewaveform and the return signal waveform into the frequencydomain. The complex conjugate of the reference waveform’sFFT is then multiplied (point-by-point) with the returned sig-nal waveform’s FFT. The result is transformed back into the timedomain (with an inverse FFT) to produce the output signal, withpeaks that represent the targets.

2 / Reprinted from VMEbus Systems / August 1998 Copyright 1998 ~ All rights reserved

Tradeoffs between time and frequency domain techniques arequite involved, and could be the subject of an entire article, sowe will not present a detailed discussion here. We will simplynote that, for radar systems with TBPs greater than 32, fre-quency domain techniques (which employ FFTs) can be imple-mented more efficiently in hardware than time domainapproaches (which employ FIR filters). [3]

Figure 1 illustrates the concept of frequency domain pulse com-pression. In this example, the returned signal was sampled with atotal of 4096 samples. This return waveform contains 2 overlappedtarget reflections, which are clearly seen in the processed result.

The basic requirements andarchitecture of a radar receiverPulse compression (although undeniably an important piece ofthe radar signal processing puzzle) is not the whole story. A goodradar receiver should be able to support other types of process-ing. For example:

■ The receiver should be able to process the real sample streamfrom a single A/D converter, to produce a stream of complexsamples, where each complex sample contains both instan-taneous amplitude and phase information.

■ Since the frequency response of the analog front end of thereceiver will not be perfectly flat, the receiver should be ableto apply an equalization filter to the sample stream, to flat-ten the effective response, and thus improve the sharpnessof the peaks, and reduce sidelobes in the output.

■ Rectangular-to-polar coordinate transformation might be neededto transform the peaked signal output into a form that is com-patible with various post-processing algorithms or displays.

■ Thresholding might be needed to discard clutter, and othercompression techniques might be needed to facilitate thetransmission of the output data stream to target report pro-cessors and to displays.

Figure 2 shows the processing steps involved in processing asingle channel radar return signal. There are 4 major steps:

■ A/D conversion of the return signal, to produce a digital datastream

■ Digital down conversion of that data stream, to produce alower-sample-rate complex (in-phase and quadrature) signal,which carries both amplitude and phase information

■ Pulse compression, which produces an output data streamwith a peak for each target detected

■ Post processing, to prepare the data stream for the targetreport processors and for displays

Digital down conversionThe digital down conversion transforms the single real datastream into a complex in-phase and quadrature (“I” and “Q”)data stream. This results in a data stream with one half of theoriginal sampling rate, which is then used by the rest of the sys-tem. Note: The system could certainly be designed with analogcircuitry to generate the complex data stream directly from thereturn analog waveform. However, this would require an ana-log 90° phase shifter, which introduces the drawbacks com-monly associated with analog techniques:

■ limited flexibility■ susceptibility to temperature variations■ high maintenance

It would also require two A/D converters per channel, insteadof just one. Note: Another drawback is mismatches between theI and Q channel, resulting in degraded sidelobe performance inthe pulse-compressed output.

Pulse compressionThe complex data stream from the digital down converter flowsinto the pulse compression unit. This unit:

■ performs a time-domain multiplication, to reduce the mag-nitude of the side lobes

■ performs an FFT operation, to transform the time domaincomplex sample stream into a frequency domain represen-tation of the return signal

Figure 2

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Figure 1

Digitalmixer

Low passfilter Decimation

Windowmultiply forsidelobereduction

FFT

Multiply(matched filtercombined with

transverseequalization filter)

IFFT

Digital down conversion Pulse compression

A/DConversion

Postprocessing

Target reportprocessor and

displays

Reprinted from VMEbus Systems / August 1998 / 3 Copyright 1998 ~ All rights reserved

■ performs a single point-by-point multiplication (in the frequencydomain) of the transverse equalization filter coefficients (tocompensate for the non-flat response of the analog receiver onthe front end) and of the conjugated coefficients of the FFT ofthe reference waveform (to detect correlations with the trans-mitted waveform). (We’ll talk more about this later)

■ performs an inverse FFT operation, to generate a timedomain data stream, with peaks that correspond to targets

Post processingThe resulting output data stream (which contains a peak for eachtarget that has been detected) is then routed to a post-process-ing unit, whose job is to process the data stream, so that onlythe significant peaks are passed along to the general purposetarget report processor, and to the display driver. There are twoalgorithms that are typically used for this purpose:

■ Thresholding■ Peak picking

The idea behind thresholding and peak picking is to limitthe amount of data (and hence the required bandwidth) neededto send the data stream to the general-purpose processor.

ThresholdingTo do thresholding, the user specifies a level, or a set of lev-els. If the magnitude of a given sample is greater than thespecified level, the data is routed to the general-purpose postprocessors. If the magnitude is not greater, the data is discarded.

Peak pickingTo do peak picking, the user specifies the number of peaks (N)to be picked. The system then identifies the largest N peaksin each output vector and passes them to the post processors.

You need adequate processing powerIt is vital that the implementation of each of the steps shown inFigure 2 have enough processing power to handle:

■ large TBPs■ high pulse repetition frequencies■ long return vectors, to provide all-range processing

The pulse repetition frequencyThe pulse repetition frequency (PRF) of a radar unit is a mea-sure of the rate at which the system transmits the referencewaveform. In order to keep up with this rate, all processing fromthe previous transmission must be completed before the nexttransmission. Thus, a radar unit with a higher PRF demandsfaster processing, in order to process the return signal within theavailable time. At the system level, higher PRFs:

■ allow the faster display and report update rates that areespecially important in tracking radar systems, which aredesigned to follow the motion of a chosen target

■ allow a Doppler radar to more precisely determine targetvelocities, since the returns are more closely spaced in time.

■ make coherent and non-coherent integration more effective

Note: For coherent and non-coherent integration, the radar sys-tem sums up N returns, and then sends the result to the postprocessor. For example, the tracking loop update rate of a track-ing radar system is limited by the amount of time it takes to dopulse compression on N returns, and then sum them up. With ahigher PRF, the returns are more closely spaced in time, and Nreturns can be processed and summed more quickly. Thus, thetracking loop update rate can be higher.

The data stream nature of a radar system lends itself to the

design of pipelined algorithm-specific processing hardware.This allows the rather demanding level of processing to beaccomplished with a small number of specialized processingnodes, and within a short processing delay. Thus, a pipelinedradar receiver architecture can support higher time-bandwidthproducts (TBPs) and pulse repetition frequencies (PRFs) thanother architectures that are implemented exclusively with gen-eral purpose processor boards.

Implementing the radar receiver systemFigure 3 shows a VMEbus-based radar receiver architecture whichis built from off-the-shelf algorithm-specific boards from CatalinaResearch. It is constructed with 3 specialized types of boards:

■ The Nimble board■ The DIREC board■ The GEMINI board

The Nimble boardFigure 4 shows a Nimble board. It is a 6U, single-slot, 2-channelVMEbus A/D converter board. The A/D conversion is done bymezzanines, which can be chosen to provide a range of options foreach channel, from 14 bits at 10 MHz to 12 bits at 50 MHz. Thedigital data stream from each of these A/D converters is routed outof the Nimble board through a 40-pin front panel ribbon cable.

The DIREC boardFigure 5 shows a DIREC board. It is a 6U, single-slot, 2-channelVMEbus digital receiver board, with reconfigurable processors.Each 32-bit channel flows through:

■ a digital tuner■ a Finite Impulse Response (FIR) filter■ two user-definable field programmable gate arrays (FPGAs)

Data output takes place through a 64-bit-wide front panel par-allel port.

The GEMINI boardFigure 6 shows a GEMINI board. It is a 6U, single-slot VME64xvector processing board, with two algorithm-specific processorsthat have been optimized for frequency domain algorithms. Datainput and output take place through 64-bit-wide front panelparallel ports. (Only 48 bits are actually used on the GEMINIboard.) There are two versions of the GEMINI board: a 60 MHzversion and an 80 MHz version. Table 1 shows the effective FFTand pulse compression processing times and the sustainable con-tinuous throughput for both versions of the GEMINI board.

The VMEbus-based system represented in Figure 3 provides allof the data stream processing, from the initial A/D conversionto the post-processing. One or more general-purpose processorswould be required at the end of the processing stream, to drivethe displays, and to do the target report generation. These gen-eral-purpose processor boards are not shown in the Figure 3,because any high-performance processor boards could be used.The configuration in Figure 3 uses the last DIREC board in thedata flow to perform FPGA-based post-processing. This DIRECboard can be configured to support a Front Panel Data Port(FPDP) VITA standard interface, which is designed to provide160 Mbyte/second point-to-point transfers.

Since many general purpose DSP and RISC/CISC boards acceptdata through a FPDP interface, a system integrator can choosefrom a wide selection of processor boards for target report pro-cessing and display.

If the system integrator prefers to use a RACEway interface totransfer the data from the end of the data flow to the general-

4 / Reprinted from VMEbus Systems / August 1998 Copyright 1998 ~ All rights reserved

purpose processor boards, a CRITIRboard (Figure 7) could be substituted forthe DIREC board (see Figure 8.) When aCRITIR board is used, it and the GEMINIboard are sandwiched together, with aflex cable providing the interconnection,instead of a front panel ribbon cable.

When the GEMINI board and CRITIRboard are sandwiched together in thismanner, the CRITIR board can route thepipeline’s output data stream over theRACEway, which is a crossbar-based ar-chitecture that supports data transfers upto 160 Mbytes/second. The CRITIR’sonboard FPGAs and its Cartesian-to-po-lar coordinate transformation ASIC canalso provide the same post-processingfunctions as the DIREC board.

Using a backplane-basedarchitectureWhen designing a multiple-processor,real-time architecture, some of the mostdifficult design decisions involve:

■ the assignment of the algorithms to thevarious processing nodes

■ the management of the data transfersbetween these processing nodes

Figure 9 shows the data flow and controlflow needed when implementing real-timeprocessing on an array of general-purpose

NIMBLE

SLOT1

CONTROLLER

DIREC

NIMBLE

DIREC

GEMINI

DIREC

Convert clock

Frame start / trigger

CH2

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Digitized raw data from CH1 and CH2 (40-pin ribbon cable)

Digitized raw data from CH3 and CH4 (40-pin ribbon cable)

Complex data passed to GEMINI for pulse

compression(QC64-ribbon cable)

FPDP output to target report

processor and displays

Linear power supplies for

the A/Ds

Figure 3

processor boards, interconnected througha multiported VMEbus backplane bus.Data transfers between boards are accom-plished through DMA controller andshared memory. These DMA controllersmust be set up, controlled, and synchro-nized in some fashion – typically withsemaphores and interrupts.

These techniques almost always involvecontext switching, and the resulting over-head can consume a substantial amount ofMPU processing time. As more proces-sors are added to the array, this overheadgrows, with diminishing returns on eachnew processor.

Using a pipelined hardwarearchitectureThe pipelined radar receiver architecturepreviously presented in Figure 3 mini-mizes these difficulties. Looking again atthe functional data-flow-oriented block

Figure 4

Figure 5

Figure 6 Figure 7

Reprinted from VMEbus Systems / August 1998 / 5 Copyright 1998 ~ All rights reserved

diagram in Figure 2 (which shows the sequential processingsteps required for the radar receiver) we see that each functionmaps directly onto a single board (or a section of a board) asfollows:

■ The A/D conversion maps into two NIMBLE boards (Withtwo A/D converters on each NIMBLE board, this provides4 real input channels.)

■ The digital down conversion maps into the two DIRECboards. (With two down converters on each DIREC board,this provides 4 channels of down conversion.)

■ The pulse compression and related functions map into theGEMINI board.

■ The FPGA-based post-processing maps into DIREC orCRITIR.

With a one-to-one mapping between the processing steps (in thefunctional block diagram) and the physical modules (in the radarreceiver) it’s easy to assign the algorithms to the processing nodes,and to manage the data flow between those processing nodes.

Data movement between boards takes place through the64-bit-wide front panel parallel interfaces, which are calledQuickComm64 (QC64) ports. This QC64 interface can trans-fer data between adjacent slots at rates up to 60 MHz. Thus thepoint-to-point data transfer rate is 60 MHz x 64 bits/sec = 480Mbytes/sec from slot to slot. (The QC64 interface can also sup-port more elaborate arbitration schemes and longer distanceswith lower data transfer rates.)

QC64 also includes an arbitration mechanism that allows:

■ multiple data sources to funnel data into a single destination■ a single data source to broadcast data to multiple destinations

Data transfers are done with synchronous handshaking, betweenthe output FIFO of the data source and the input FIFO of thedestination. Transfers do not rely on application software,except for the initializations that are done by the system soft-ware when the system starts up. Contrast this approach with thatof Figure 9, which imposes significant overhead on both thesupervisory processor and on the system backplane.

After flowing through the algorithm-specific hardware pipeline,the output data stream is routed to one or more general purposeprocessors (for target report generation) and to displays. (Asmentioned earlier in this article, this routing might be donethrough FPDP and RACEway links.)

Because the pipelined processing is done with algorithm-spe-cific hardware, it can process continuous 24-bit complex datastreams (24-bit I, and 24-bit Q) at rates in excess of 50Msamples/sec. With data rates this high, several general purposeprocessors might be needed to handle the output data stream. Itis the responsibility of the DIREC board (or the CRITIR board)at the end of the data stream (which we will call the outputboard) to manage this very high throughput data transfer to thecollection of general-purpose processors.

There are two different methods that the output board can use tokeep the data rate within the limits that the general-purpose pro-cessors can handle:

■ Compression of the data stream■ Thresholding of the data stream

Compression of the data streamThe FPGAs and the ASICs on the output board can be config-ured to convert the data stream to...

■ a 16-bit magnitude data stream■ a 16-bit magnitude stream plus a 16-bit phase data stream■ an 8-bit log magnitude data stream

...and then pack the resulting data stream into 32-bit or 64-bitwords, for more efficient transfer to the general-purpose pro-cessors.

Thresholding of the data streamTo reduce the output data rate, the output board might alsothreshold the data stream, by comparing the magnitude of theeach data value in the data stream to some user-programmablethreshold level:

■ Data below the threshold is simply discarded.■ Data values above that threshold are passed to the general-

purpose processors, along with their cell count.

The cell count indicates where a particular sample resides withina given vector. When thresholding or peak picking, it is criticalto know where that sample was located, because it is very rarefor all the samples in a vector to get passed to the general-purpose post processors.

By using these methods (either separately, or in conjunction withone another) the output board can throttle the data rate flowingout of the radar receiver, into the general-purpose processors.

GEMINI Benchmarks

60 MHz 80 MHz

multiply/FFT multiply/FFT+multiply/IFFT

multiply/FFT multiply/FFT+multiply/IFFT

Vector Size(Complex)

µsec MSPS µsec MSPS µsec MSPS µsec MSPS128 4.5 28.7 9.0 14.4 2.0 63.2 4.0 31.6256 8.1 31.6 16.2 15.8 3.6 70.6 7.2 35.3512 14.5 35.4 29.0 17.7 6.8 75.0 13.6 37.61,024 27.3 37.5 54.6 18.8 13.2 77.4 26.4 38.72,048 70.2 29.2 140.4 14.6 39.0 52.5 78.0 26.34,096 138.9 29.5 277.8 14.8 77.4 52.9 154.8 26.58,192 275.5 29.7 551.0 14.9 154.2 53.1 308.4 26.616,384 548.5 29.9 1,097.0 15.0 307.8 53.2 615.6 26.632,768 1,368.0 24.0 2,736.0 12.0 615.0 53.3 1,230 26.765,536 2,733.7 24.0 5,467.4 12.0 1,639.3 40.0 3,278.6 20.0

Table 1

6 / Reprinted from VMEbus Systems / August 1998 Copyright 1998 ~ All rights reserved

Using the VMEbus backplaneWhile data transfers between the boards take place primarily overthe QC64 link, the system diagnostics, the board initialization, andthe supervisory control are done over the VMEbus backplane.

For example, the VMEbus can be used to write data into any ofthe algorithm-specific boards (the Nimble, the DIREC, theGEMINI, or the CRITIR). This data can then be routed throughone or more stages of processing, and then read back over theVMEbus. This is a welcome feature for troubleshooting, becauseit helps localize problems.

Figure 10 shows the VMEbus-based radar receiver pipeline,implemented in two alternate configurations:

■ One configuration with a RACEway output■ One configuration with a FPDP output

The 64-bit-wide QC64 front panel parallel port can transfer datafrom board to board at rates up to 60 MHz, and at lower ratesover longer distances. It uses 80-conductor ribbon cable. The64-bit-wide VMEbus backplane transfers data at 80 Mbytes/sec,and is used in D32 mode to initialize and configure all of theboards in the system.

The 40-pin ribbon cable interface is used to transfer two16-bit-wide data streams from a NIMBLE board to a DIRECboard, at rates up to 50 MHz.

The VITA standard Front Panel Data Port (FPDP) interface isused to transfer a 32-bit-wide data stream at 40 MHz.

The software modelAlthough this radar receiver architecture is based upon algorithm-specific hardware, the function of each hardware processing

Figure 8

SystemController

Tuner/FIR

Buffer

A/D

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Buffer

Signal Processor

Buffer

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Buffer

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Buffer

Process synchronization, buffer management, and DMA control functionsAlgorithm control parameters

Figure 9

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compression(QC64-ribbon cable)

RACEway output (P2)to target report

processor and displays

Digitized raw datafrom CH1 and CH2

(40-pin ribbon cable)

Digitized raw datafrom CH3 and CH4

(40-pin ribbon cable)

Linear powersupplies for

the A/Ds

Two-boardsandwich

Reprinted from VMEbus Systems / August 1998 / 7 Copyright 1998 ~ All rights reserved

node is not entirely fixed, and can be reconfigured with software.Each board is designed to be programmable within the applica-tion space for which it is designed.

For example, the GEMINI board is completely programmablefor FFT-based applications, while the DIREC board can be con-figured for a wide range of FIR filter and tuning operations.

A set of C-language function calls has been defined to providean application program interface (API). This API allows anapplication program to specify the mode of operation for eachboard, and to pass specialized parameters.

The application program uses the API to configure the pipelineas follows:

■ Initialize all of the boards in the pipeline■ Clear all of the FIFOs■ Configure each board in the pipeline■ Start the data flow

Initializing the pipelineThe application program invokes the appropriate API calls, toinitialize each of the boards.

Clearing all of the FIFOsThe application program invokes the appropriate API calls toclear all the input and output FIFOs on each board, from thefront of the processing pipeline to the back. This purges all datafrom the pipeline, and prepares the QC64 interface for data flow.

Configuring each board in the pipelineOnce all of the boards in the system has been initialized, and thepipeline has been cleared, the application software invokes theappropriate API calls to prepare each of the boards in the pipe-line for processing. This is done from the back of the pipelineto the front, to ensure that the first boards do not begin fillingthe pipeline with data before subsequent boards have been con-figured to receive it. For radar receiver systems the applicationprogram configures the boards as follows:

DIREC or CRITIRset up the proper post-processing mode (coordinate

transform, or log conversion, and/or thresholding)

set the input mode (front panel QC64)set the output mode (FPDP or RACEway)

GEMINIupload processing algorithms (FFTs, pulse compressions, etc.)upload twiddle factors for the FFTupload the transverse equalization filter responseupload the matched filter response for pulse compressions

(one or many)set the input mode (front panel QC64)set the output mode (front panel QC64)

DIRECconfigure the tuner and FIR ASICs for baseband quadra-

ture samplingset the input mode (front panel QC64)set the output mode (front panel QC64)

Nimbleset the sampling mode (continuous or framed data)set the output mode (front panel parallel port)

Starting the data flowThe radar receiver system is now configured to start samplingthe incoming analog signal and to feed the resulting data streaminto the signal processing pipeline, where each algorithm-spe-cific board in the pipeline processes the data stream accordingto its own configuration.

Dynamic reconfigurationThe application program accomplishes all of this board configu-ration at a high level, through the API. During the processing(while the data is flowing through the pipeline) the applicationprogram can also use the API to reconfigure the boards, arbi-trarily switching between FFT sizes, reference waveforms, post-processing modes, and modes of operation, using the VMEbus.

Because mode, program, or reference waveform switching eachtake only a few VMEbus writes, the board reconfigurations canbe done at the pulse rate of most radar applications. The hard-ware on the boards is designed to execute reconfiguration com-mands between pulses, so the discrete data streams for eachpulse are not corrupted or lost due, to the changes.

The application program can also configure the hardware toinsert a configuration header at the beginning of each datastream, at the time the returning signal is being sampled. This

Figure 10

to target reportprocessing,displays, etc.

NimbleA/D

DIRECtuner/FIR

GEMINImult., FFTmult., IFFT

DIRECpost

procesing

Target reportprocessing,displays, etc.

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Configuration with RACEway output

Configuration with FPDP output

8 / Reprinted from VMEbus Systems / August 1998 Copyright 1998 ~ All rights reserved

header can hold information to guide subsequent downstreamprocessing. So, even though the hardware that makes up thispipelined radar receiver is algorithm-specific, it is also program-mable – to the extent that its functionality can be changed on apulse-by-pulse basis.

Applying the radar receiver systemto real-world problemsNow that we have discussed this pipelined radar receiver archi-tecture, let’s see how it might be used to support 3 different typesof radar processing applications:

■ A track-mode radar application■ A search-mode radar application■ A wideband stretch processing radar application

Each of these applications requires us to configure the boardsin a different manner. This will allow us to see how the archi-tecture of this pipelined radar receiver can be reconfigured tosupport these applications.

Note: For all three examples, the last board in the pipeline (ei-ther the DIREC board or the CRITIR board) will perform someform of post-processing on the data stream, as required by theapplication. The resulting data stream is then passed to the tar-get report processors and the display processors over an FPDPlink or a RACEway link.

Example 1: A track mode radarThis first example is a track mode radar. This mode is used totrack a moving target, after that target has been detected. Sincethe target has already been located, its initial range is known,so the range window being scanned will be small, but an accu-rate range and angle measurement is desired.

The pulse compression will be performed in the frequencydomain, using Fast Fourier Transforms. When the range win-dow is small (as in this case) the sample stream is relativelyshort, and so the pulse compression can performed with:

■ a single FFT operation■ a single complex multiply operation■ an inverse FFT (IFFT) operation.

Block DiagramFigure 11 shows the function performed by each of the boardsin the pipeline:

■ Each Nimble board samples two real incoming analog signalsat 15 Msamples/sec. The resulting sample streams are routedthrough the output FIFO to the corresponding DIREC board.

■ The tuner ASIC on the DIREC board performs the digitaldown conversion, and the resulting complex 7.5 Msample/sec data stream is routed through the output FIFO to theGEMINI board.

■ The GEMINI board does (1) a time-domain multiplication,to reduce sidelobes. (2) the FFT (3) multiplication by thetransverse equalization filter, to compensate for the non-flatresponse of the analog front end (4) multiplication by thematched filter multiply (to do the pulse compression) and (5)the inverse FFT. It does this processing for all four channels.

The matched filter is the conjugated FFT of the reference wave-form, which is stored in memory when the radar system is con-figured, and then used during normal operation to implement thepulse compression algorithm.

Note: The transverse equalization filter coefficients can be com-bined with the matched filter coefficients. This allows both filters

to be applied with a single complex vector multiplication. (Thistechnique was not shown in Figure 1.)

System ParametersThe system parameters for this track mode radar are shown inTable 2.

Calculation of the maximum pulse repetitionfrequency, when using the 60 MHz GEMINI boardThe processing power of the radar receiver sets an upper limiton the pulse repetition frequency of the radar system. Giventhe system parameters for our track mode radar, and the per-formance parameters of the boards in the system, we cancompute this maximum pulse repetition frequency as follows:

The Receive Window (Tc ), is the time interval that:

■ starts when the system begins sampling the return signal■ ends when the system stops sampling the return signal

The duration of the Receive Window is determined by...

■ the pulse width (Pw).■ the Range Window (Rw), which is the difference between the

minimum and the maximum distances at which the systemwill look for targets – in this case the Range Window is 2.5Km

...and is computed as follows:

Tc

= Pw + 2(Rw/c)= 10.2 µsec + 2(2.5 Km/c)= 26.9 µsec

During the entire time interval of the Receive Window, theA/D converter is sampling points. Thus, the total number ofpoints sampled (P) each time the reference waveform is trans-mitted will be the product of the duration of the Receive Win-dow (Tc) and the sampling rate (Fb):

P = Tc x Fb= 26.9 µsec x 7.5 Msamples/sec= 202 samples

The time-bandwidth product (TBP) of the radar system will bethe product of the receiver sampling rate (Fb) and the timerequired to transmit the reference waveform, the transmittedpulse width (Pw):

TBP = Fb x Pw= 7.5 Msamples/sec x 10.2 µsec= 77 samples

Note: The TBP dictates the size of the matched filter that willbe needed to adequately implement the convolution necessaryfor pulse compression. The number of points to process is afunction of both the TBP and the number of samples in theReceive Window (P).

The frequency domain implementation is a circular convolution(instead of a linear convolution) so we need to pick an FFT sizethat compensates for this fact. The minimum FFT size (Lc) isequal to the number of samples taken during the Receive Win-dow (P) plus the number of samples taken during the transmit-ted pulse (TBP), minus 1:

Lc

= P + TBP – 1= 202 + 77 – 1= 278 samples

Reprinted from VMEbus Systems / August 1998 / 9 Copyright 1998 ~ All rights reserved

Note: A derivation of this equation can be found in Section 7-3of reference [3].

This convolution of the return waveform with the referencewaveform will actually be done with a point-by-point complexmultiply in the frequency domain, using:

■ the complex conjugate of the FFT of the reference waveform■ the FFT of the return waveform

We want to do the computations in the frequency domain, andwe must have a number of points which is an integer power oftwo, in order to take advantage of the FFT. Since the minimumFFT size (278) given by the previous equation is larger than 256,we will need to choose an FFT size of at least 512 points toperform this convolution in the frequency domain.

Note: The number of samples in the Receive Window and in thereference waveform are zero-padded to 512, before the FFT iscomputed.

Each processor on the 60 MHz GEMINI board can do a 512-point (multiply/FFT/complex multiply/inverse FFT) in Tg = 58.0µsecs.

The total pulse compression processing time (Tp ) is the numberof channels to be processed (4) multiplied by the time requiredto do each 512-point (multiply/FFT/complex multiply/inverseFFT) (Tg) divided by the number of onboard processors (2):

Tp

= (Nc x Tg)/(# of processors on GEMINI)= (4 x 58.0 µsec)/2= 116.0 µsec

This processing time sets a lower limit on the time that must beallowed between transmitted pulses to do this processing, allow-ing us to compute the maximum permissible pulse repetitionfrequency (PRFmax):PRFmax = 1/Tp

= 1/116.0 µsec= 8,620 Hz (pulses/sec)

Calculation of the maximum pulse repetitionfrequency, when using the 80 MHz GEMINI boardEach processor on the 80 MHz GEMINI board can process a512-point (multiply/FFT/complex multiply/inverse FFT) inTg = 27.2 µsecs. Thus the total processing time when using thisboard is:

Tp = (Nc x Tg)/(# of processors on GEMINI)= (4 x 27.2 µsec)/2= 54.4 µsec

This lower limit on the time between transmitted pulses, allowsus to compute the maximum permissible pulse repetitionfrequency (PRFmax):

PRFmax = 1/Tp= 1/54.4 µsec= 18,380 Hz (pulses/sec)

In summary, this track mode radar receiver system can supporta maximum pulse repetition frequency of:

■ 8,620 Hz (pulses/sec) when using a 60 MHz GEMINI board■ 18,380 Hz (pulses/sec) when using an 80 MHz GEMINI

board

Example 2: Search mode radarThis second example is a search mode radar. This mode is usedwhen searching for a target. Since the range to the target isunknown, the Range Window for this mode of operation willbe large, when compared to that of the track mode, where theapproximate distance to the target is already known.

Block DiagramAs before, Figure 11 shows the function performed by each of theboards in the pipeline with the following differences – theGEMINI board processes a single channel (instead of four chan-nels) and only one NIMBLE/DIREC board pair will be used here.

System ParametersThe system parameters for this search mode radar are shown inTable 3.

System ParametersNumber of Channels (Nc) 4

Transmit Pulse width (Pw) 10.2 µsecBaseband Bandwidth (Bw) 6.0 MHzA/D Sampling Rate (Fs) 15.0 MHzBaseband Sampling Rate (Fb)(after DIREC performs digital down conversion)

7.5 MHz

Range Window (Rw) 2.5 Km

Table 2

Figure 11

IF SAMPLE

SampleController

1/2 NIMBLE

DIGITAL DOWN CONVERTER

1/2 DIREC

Input

Clock

Framestart

(tri gger)

N

N

Tuner ASIC

cos(ω f)

sin(ω f)

I

Q

PULSE COMPRESSION

1/4 GEMINI

FFT IFFT

Window(sidelobereduction )

Transverseequalizationand matched

filter

POST- PROCESSOR

DIREC or CRITIR

• Format conversions• Coordinate

conversions• Log conversion• Pack/unpack data• Thresholding• Other . . .

VMEbus

FPDPDIREC)

RACEwayCRITIR)

A/D

LPF

LPF

FIFO

FIFO

FIFOFIFO

Search Mode System ParametersNumber of Channels (Nc) 1

Transmit Pulse width (Pw) 10.2 µsecBaseband Bandwidth (Bw) 6.0 MHzA/D Sampling Rate (Fs) 15.0 MHzBaseband Sampling Rate (Fb)(after DIREC performs digital down conversion)

7.5 MHz

Range Window (Rw) 200 Km

Table 3

10 / Reprinted from VMEbus Systems / August 1998 Copyright 1998 ~ All rights reserved

Calculation of the maximum pulse repetitionfrequency, when using the 60 MHz GEMINI boardSince the range to the target is unknown, the Range Window forthe search mode of operation will be much larger than that forthe track mode. This larger Range Window means a largerReceive Window. As before, we can compute the duration of theReceive Window from the pulse width and the Range Window:

Tc

= Pw + 2(R

w/c)

= 10.2 µsec + 2(200 Km/c)= 1.344 µsec

With a larger Receive Window, we have a larger number ofsample points on which to perform the FFT. We can computethe total number of points sampled (P) by the A/D converter foreach pulse in the same manner as before:

P = Tc x F

b= 1.344 msec x 7.5 Msamples/sec= 10,080 samples

Note: This is a much larger number of samples than the 202samples we had for the track mode radar.

Since the sample rate and the pulse length are the same as forthe track mode radar, the time-bandwidth product (TBP) will bethe same:

TBP = Fb x Pw= 7.5 Msamples/sec x 10.2 µsec= 77 samples

As before, in order to do the computations with a Fast FourierTransform, we must have a number of points which is an inte-ger power of two. Since the number of points in the convolvedoutput is (77 + 10,077 – 1) = 10,153, we choose an FFT size of16,384 points.

While we could theoretically perform an FFT operation on sucha large set of points, the latency of such an approach might betoo long. This latency results from two causes:

■ The larger the set of points, the longer the system must waitbefore starting the FFT operation, since all of the points mustbe available before the processing can begin.

■ The larger the set of points, the more computation is requiredto perform the FFT operation, once it begins.

The latency can be reduced by performing multiple small FFTs,instead of a single large FFT, with each small FFT overlappedby some number of samples with the previous small FFT. Thisis known as sectioned convolution. Sectioned convolution istypically more efficient than processing a single large FFT.

For sectioned convolution the TBP is the minimum overlaprequired which, in this case, is 77 points. The number of pointswe use to compute the FFT is somewhat arbitrary. However, wemust obviously use more than 77 points, in order to ensure thatwe satisfy this minimum overlap. With a 77-point overlap anda 512-point FFT:

■ points 0-511 would be used to perform the 1st FFT■ points 434-946 would be used to perform the 2nd FFT■ points 896-1381 would be used to perform the 3rd FFT■ etc.

Because of the overlap between consecutive FFTs, some of theinput points are processed 2 times. (For this example, each FFTis done with 77 “old” points and 512-77 = 435 “new” points.)

At the output of the (multiply/FFT/multiply/inverse FFT) algo-rithm the overlapped data is discarded, so we “throw away” 77points out of 512. This can be throught of as the “processingoverhead” imposed by sectioned convolution.

The larger the overlap (compared to the FFT size) the more“overhead” processing we will need to do with each FFToperation. To minimize this overhead, we want to choose an FFTsize that will minimize the percentage of overlap. Given theminimum overlap of 77 in this example, if we choose an FFTsize of 512 complex points, we will have a minimum overheadof ( 77 / 512 ) = 15%.

We can obviously reduce this overhead to some arbitrarily smallpercentage by choosing an arbitrarily large FFT size. However,our choice of FFT size should also take into consideration othersystem parameters, such as the longer processing latency oflarge FFTs. The receive window is 10,077 samples long, andeach FFT section is 512 points long, but each is also overlappedby 77 samples. We can compute the number of sections (S) thatmust be processed in the Receive Window as follows:

S = P/(FFT Size - overlap)= 10,077/(512 – 77)= 24 sections

Since each processor on the 60 MHz GEMINI board can pro-cess a 512-point (multiply/FFT/multiply/inverse FFT) in Tg =58.0 µsecs, we can calculate the total processing time for all 24sections as follows:

Tp = S x (Nc x Tg)/(# of processors on GEMINI)= 24 x (1 x 58.0 µsec)/2= 696.0 µsec

This processing time sets a lower limit on the time betweentransmitted pulses, allowing us to compute the maximum per-missible pulse repetition frequency (PRFmax):

PRFmax = 1/Tp= 1/696.0 µsec= 1,437 Hz (pulses/sec)

Calculation of the maximum pulse repetitionfrequency, when using the 80 MHz GEMINI boardSince each processor on the 80 MHz GEMINI board canprocess a 512-point (multiply/FFT/multiply/inverse FFT) inTg = 27.2 µsecs, we can calculate the total processing time forall 24 sections as follows:

Tp = S x (Nc x Tg)/(# of processors on GEMINI)= 24 x (1 x 27.2 µsec)/2= 326.4 µsec

The maximum permissible pulse repetition frequency (PRFmax) is:

PRFmax = 1/Tp= 1/326.4 µsec= 3,063 Hz (pulses/sec)

In summary, this search mode radar receiver system cansupport a maximum pulse repetition frequency of:

■ 1,437 Hz when using a 60 MHz GEMINI board■ 3,063 Hz when using an 80 MHz GEMINI board

Example 3: Wideband stretch processing modeTo further illustrate the flexibility and performance of thisradar receiver system, Example 3 covers wideband stretch

Reprinted from VMEbus Systems / August 1998 / 11 Copyright 1998 ~ All rights reserved

processing. This technique can be used to process large TBPwaveforms that provide very high resolution range measure-ments, with resolutions much better than one meter.

A wideband stretch processing radar system transmits a linear-frequency-modulated pulse. At the time corresponding to therange of interest, a copy of the transmitted waveform (the ref-erence waveform) is mixed with the return signal. The result isa signal whose frequency is equal to the difference between thetransmitted signal’s frequency and the return signal’s frequency.Since the transmitted signal frequency increases linearly withtime, the frequency of this difference signal is proportional tothe distance to the target. When this difference signal is passedthrough an FFT, each amplitude peak in the frequency spectrumcorresponds to a target.

So the pulse compression problem is mapped into a time domaincorrelation problem, followed by a spectral estimation problem.Since the processor no longer needs to implement the matchedfilter necessary for pulse compression (it only needs to implementan FFT) stretch processing allows higher TPBs to be processed.

Block DiagramFigure 12 shows the function performed by each of the boardsin the pipeline:

■ The Nimble board samples the real incoming analog signalat 50 Msamples/sec. The resulting sample stream is routedthrough the output FIFO to the corresponding DIREC board.

■ The tuner ASIC on the DIREC board performs the digital downconversion, and the resulting complex 25 Msample/sec datastream is routed through the output FIFO to the GEMINI board.

■ The GEMINI board does the sidelobe reduction multiplica-tion, the FFT, and the (optional) multiplication by the trans-verse equalization filter (which compensates for the non-flatresponse of the analog front end) and then routes the result-ing frequency vs. magnitude data stream through the outputFIFO to the post processor.

Note: The calculations below assume that the GEMINI boardis performing a (multiply/FFT). Another multiply would be re-quired to implement the transverse equalization filter.

System ParametersThe system parameters for this Wideband stretch processingmode radar are shown in Table 4.

Calculation of the maximum pulse repetitionfrequency for stretch processingAs before, the Receive Window can be computed as follows:

Tc= Pw + 2(Rw/c)= 10 µsec + 2(90 Km/c)= 10.6 µsec

The total number of points sampled (P) during the ReceiveWindow will be the product of the duration of the ReceiveWindow (Tc) and the sampling rate (Fb):

P = Tc x Fb= 10.6 µsec x 25 Msamples/sec= 265 samples

Since we want to do computations with a Fast Fourier Trans-form, we must have a number of points that is an integer powerof two. Since the number of samples required (265) is larger than256, we round up to the next higher power of 2, yielding an FFTsize of 512 points.

Calculation of the maximum pulse repetitionfrequency, when using the 60 MHz GEMINI boardEach processor on the 60 MHz GEMINI board can processa 512-point multiply/FFT in Tg = 29.0 µsecs. The total pro-cessing time (Tp) is the number of channels to be processed(4) multiplied by the time required to process each 512-pointmultiply/FFT (Tg) divided by the number of onboard proces-sors:

Tp = (Nc x Tg)/(# of processors on GEMINI)= (4 x 29.0 µsec)/2= 58.0 µsec

This processing time sets a lower limit on the time betweentransmitted pulses, allowing us to compute the maximum per-missible pulse repetition frequency (PRFmax):

PRFmax = 1/Tp= 1/58 µsec= 17,241 Hz (pulses/sec)

Calculation of the maximum pulse repetitionfrequency, when using the 80 MHz GEMINI boardEach processor on the 60 MHz GEMINI board can process a512-point multiply/FFT in Tg = 13.6 µsecs. The total process-ing time (Tp) is the number of channels to be processed (4)multiplied by the time required to process each 512-point mul-tiply/FFT (Tg) divided by the number of onboard processors:

IF SAMPLE

SampleController

1/2 NIMBLE

BASEBANDQUADRATURE FILTER

LPF

1/2 DIREC

Analog in

Clock

Frame start(tri gger)

N

LPF N

Tuner ASIC

1, 0, -1, 0, 1, . . .

I

Q

PULSE COMPRESSION(STRETCH PROCESSING)

1/4 GEMINI

FFT FIFO

Window(sidelobe

reduction )

Transverseequalization

filter

POST- PROCESSOR

DIREC or CRITIR

• Format conversions• Coordinate

conversions• Log conversion• Pack/unpack data• Thresholding• Other . . .

VMEbus

FPDPDIREC)

RACEwayCRITIR)

IF

WFG RAMP0, 1, 0, -1, 0, . . .

FIFOA/D

FIFO

FIFO

Figure 12

Wideband stretch processing Mode System ParametersNumber of Channels (Nc) 4

Transmit Pulse width (Pw) 10 µsecBaseband Bandwidth (Bw) 20 MHzA/D Sampling Rate (Fs) 50 MHzBaseband Sampling Rate (Fb)(after DIREC performs digital down conversion)

25 MHz

Range Window (Rw) 90 m

Table 4

12 / Reprinted from VMEbus Systems / August 1998 Copyright 1998 ~ All rights reserved

Tp = (Nc x Tg)/# of processors on GEMINI= (4 x 13.6 µsec)/2= 27.2 µsec

The maximum permissible pulse repetition frequency (PRFmax) is:

PRFmax = 1/Tp= 1/27.2 µsec= 36,765 Hz (pulses/sec)

In summary, this wideband stretch processing mode radarreceiver system can support a maximum pulse repetitionfrequency of:

■ 17,241 Hz, when using a 60 MHz GEMINI board■ 36,765 Hz, when using an 80 MHz GEMINI board

Note: For all three system examples, the maximum PRF wascalculated for a particular hardware configuration. Higher PRFs,TBPs, and/or more channels could be supported by scaling thesystem to include more boards.

SummaryThis article has presented a VMEbus-based, pipelined radar re-ceiver architecture that can be used for a wide variety of radarapplications. By employing algorithm-specific hardware, thearchitecture minimizes the board count, while providing highdata transfer rates and high-speed processing. At the same time,it is flexible, scalable, and dynamically reconfigurable, allow-ing it to support many different radar processing modes.

A system integrator can augment the capabilities of this basicradar receiver architecture by inserting either off-the-shelf orcustom designed boards into strategic points in the pipeline, orby simply changing the software.

For example, by modifying the application code, the user couldprogram the GEMINI board in this system to handle pulse Dop-pler processing, instead of just pulse compression. The integra-tor might also add additional GEMINI boards to the system, toincrease the performance, or to support more channels.

Catalina Research has used this pipelined radar receiver systemarchitecture to provide digital signal processing subsystems forleading-edge radar systems around the world. Shown in Figure13 is a photograph of a ship-based radar signal processing sub-system that is being deployed in volume. There is no A/D boardin this subsystem because the A/D conversion is done in anotherchassis, with the resulting digitized data stream being routed into

this system. However, the data flow through the DIREC, theGEMINI, the post-processing DIREC, and the general-purposePowerPC RISC processors (over FPDP) remains true to thearchitecture described in this article. Ω

Michael J. Bonato received a BS degreein Electrical Engineering in 1991 and anMBA in 1993, both from the Universityof Colorado, Boulder. He is currently theDirector of Marketing for CatalinaResearch, which focuses on real-time,low-latency, high-bandwidth digitalsignal processing solutions for radar andsignal intelligence applications. He has

been with Catalina Research since 1993, starting out as amarketing engineer, primarily responsible for mappingcustomer applications into board-level systems solutions.Before he joined Catalina, Mike held the position of Scientist/Engineer at Mission Research Corporation, and worked withlinear systems techniques to process and analyze test data.

Kevin Witt received a BS degree inElectrical Engineering in 1986 from theUniversity of Kentucky and an MSdegree in Electrical Engineering in 1987from Georgia Institute of Technology.As a Principle Engineer at CatalinaResearch, Kevin’s current focus is ondigital receiver/pulse compression systemdesign and digital signal processing

product development. With over 11 years in the electronicsindustry, he previously held a position at MassachusettsInstitute of Technology, Lincoln Laboratory. While at MIT/LL, Kevin designed and implemented multichannel deform-able mirror adaptive optics systems, digital radar receivers,and radar tracking systems. He also served a 4-year tour at theKREMS Radar Tracking site in the Marshall Islands, wherehe was a Systems Engineer and Assistant Sensor Leader at theALCOR and MMW Radars. In addition, Kevin was the GroupLeader of the Systems’ Engineering Group that led theCOTS-based sensor modernization efforts.

TrademarksQuickComm64™ and QC64™ are trademarks of CatalinaResearch, Inc.

References[1] Cook, Charles E., “Pulse Compression – Key to More Effi-

cient Radar Transmission,” Barton Radar Systems VolumeIII , 1960.

[2] Skolnik, Merrill I., Introduction to Radar Systems,McGraw-Hill Book Co., New York, 1962.

[3] Brigham, Oran E., The Fast Fourier Transform, Prentice-Hall, Inc., Englewood Cliffs, NJ, 1974.

[4] Roberts, Phillip, “An Ultra High Speed 1 Mega-Point FastConvolver,” Catalina Research, Inc., Colorado Springs,CO, 1993.

Want more information?If you have questions about this article, or if you would liketo have more information about Catalina Research products,you can contact the authors at:

Catalina Research1321 Aeroplaza DriveColorado Springs, CO 80916Tel: 719-637-0880 • Fax: 719-637-3839Web: www.cri-dsp.com

Figure 13