Product Specification 40&44-pin micro IDE Flash Disk ... Datasheet/Titans series/100...This document...

November 2008

Product Specification

40&44-pin micro IDE Flash Disk

- Titans Series - Doc-No: 100-XMIFSE-03V0

This document is for information use only and is subject to change without prior notice. APRO Co., Ltd. assumes no

responsibility for any errors that may appear in this document, nor for incidental or consequential damages resulting from

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APRO Co., Ltd..

All parts of the APRO documentation are protected by copyright law and all rights are reserved.

APRO and the APRO logo are registered trademarks of APRO Co., Ltd..

Product names mentioned herein are for identification purposes only and may be trademarks and/or registered

trademarks of their respective companies.

© 2008 APRO Corporation. All rights reserved.

Revision History

Revisions before Rev. 1.0 —initial release 2006/11/19

Rev. 2.0 – Part Number, Order Information and Layout updated 2007/05/09

Rev. 2.1– Series Name updated 2008/10/28

Rev. 3.0- Part Number Decoder & Part Number List updated 2008/11/5

CONTENTS

40&44-pin micro IDE Flash Disk Titans Series © 2008 APRO Co., Ltd.

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CONTENTS

1. INTRODUCTION........................................................................................................................................... 1

1.1. SCOPE ...................................................................................................................................................... 2

1.2. SYSTEM FEATURES.................................................................................................................................... 2

1.3. ATA/ATAPI-5 STANDARD.......................................................................................................................... 2

1.4. TECHNOLOGY INDEPENDENCE.................................................................................................................... 2

1.5. FLASH MANAGEMENT TECHNOLOGY .......................................................................................................... 2

2. PRODUCT SPECIFICATIONS ......................................................................................................................... 4

2.1. SYSTEM ENVIRONMENTAL SPECIFICATIONS................................................................................................. 4

2.2. SYSTEM POWER REQUIREMENTS ............................................................................................................... 4

2.3. SYSTEM PERFORMANCE ............................................................................................................................ 4

2.4. SYSTEM RELIABILITY ................................................................................................................................. 5

2.5. PHYSICAL SPECIFICATIONS ........................................................................................................................ 6

2.6. POWER CABLE FOR 40-PIN MIF.................................................................................................................. 9

2.7. CAPACITY SPECIFICATIONS ...................................................................................................................... 10

3. ADVANCED FEATURE SETS........................................................................................................................11

3.1. ULTRA DMA FEATURE SET ...................................................................................................................... 12

3.2. POWER MANAGEMENT FEATURE SET ....................................................................................................... 12

3.3. CFA FEATURE SET.................................................................................................................................. 12

3.4. POWER REGULATOR................................................................................................................................ 12

3.5. RC OSCILLATOR ..................................................................................................................................... 12

4. INTERFACE DESCRIPTION ......................................................................................................................... 12

4.1. PHYSICAL DESCRIPTION .......................................................................................................................... 13

4.2. PIN ASSIGNMENTS................................................................................................................................... 13

4.3. ELECTRICAL DESCRIPTION....................................................................................................................... 14

CONTENTS


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4.4. ELECTRICAL SPECIFICATION .................................................................................................................... 15

4.4.1. ABSOLUTE MAXIMUM RATING ............................................................................................................... 16

4.4.2. RECOMMENDED OPERATING CONDITION ................................................................................................ 16

4.4.3. DC CHARACTERISTICS ......................................................................................................................... 16

4.4.4. AC CHARACTERISTICS ......................................................................................................................... 17

5. INTERFACE REGISTER DEFINITION............................................................................................................. 19

5.1. DEVICE ADDRESS.................................................................................................................................... 19

5.2. I/O REGISTER DESCRIPTIONS................................................................................................................... 19

6. COMMAND DESCRIPTIONS ........................................................................................................................ 21

6.1. COMMAND SET........................................................................................................................................ 21

6.2. DESCRIPTIONS ........................................................................................................................................ 22

7. INSTALLATION PROCEDURE ...................................................................................................................... 30

7.1. BEFORE UNPACKING................................................................................................................................ 30

7.2. ESD PRECAUTIONS................................................................................................................................. 30

7.3. ILLUSTRATION OF 40/44-PIN MIF.............................................................................................................. 31

7.4. CONFIGURATION OF 40/44-PIN MIF .......................................................................................................... 33

7.5. MIF INSERTION AND REMOVING................................................................................................................ 33

7.5.1. MIF INSERTION..................................................................................................................................... 33

7.5.2. MIF REMOVING .................................................................................................................................... 34

7.6. IDE DEVICE SETUP / AUTO-DETECTION .................................................................................................... 34

7.7. PARTITION & FORMAT .............................................................................................................................. 35

APPENDIX A. ORDERING INFORMATION.......................................................................................................... 36

APPENDIX B. LIMITED WARRANTY ................................................................................................................. 41

1. Introduction

APRO Industrial 40-pin/44-pin micro IDE Flash (MIF) Disk products are designed to follow ATAPI-5 (ATA-66) standard.

The main used Flash memories are Samsung NAND Type SLC Flash memory chips. The available Card capacities are

16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB, 2GB, 4GB and 8GB. The operating temperature grade is optional for

commercial level 0°C ~ 70°C and wide temperature level -40°C ~ +85°C. The APRO Industrial 40-pin/44-pin micro IDE

Flash (MIF) Disks are designed electrically complies with the conventional IDE hard disk and support True IDE Mode. The

data transfer modes supports PIO mode-4 or UDMA-4. One of the great advantage designs of MIF is the very flexible

form-factors to meet different mechanical requirement. The options are 40-/44-pin Vertical type (V-type) MIF,

Horizontal-leftward (HL-type) MIF and Horizontal-rightward (HR-type) MIF.

The APRO Industrial 40-pin/44-pin MIF products provide a high level interface to the host computer. This interface allows

a host computer to issue commands to the Flash Disk to read or write blocks of memory. The host addresses the card in

512 byte sectors. Each sector is protected by a powerful 4 bits Error Correcting Code (ECC). APRO Industrial

40-pin/44-pin micro IDE Flash (MIF) Disk ’s intelligent controllers manages interface protocols, data storage and retrieval

as well as ECC, defect handling and diagnostics, power management and clock control.

Figure 1 shows a block diagram of the used high tech Industrial 40-pin/44-pin micro IDE Flash (MIF) Disk controller.

Figure 1: ATA Flash Disk Controller Block Diagram


1

1.1. Scope

This document describes the features and specifications and installation guide of APRO’s Industrial 40-pin/44-pin MIF

disks. In the appendix, there provides order information, warranty policy, RMA/DOA procedure for the most convenient

reference.

1.2. System Features

Optional design with V-type, HL-type and HR-type each for 40-pin and 44-pin MIF.

Non-volatile memory and no moving parts

NAND type SLC flash technology

Disk capacity from 32MB to 4GB

ATA inter face and True IDE mode

Master/Slave Selectable

Write protection by micro switch

Data transfer supports PIO-4 and UDMA-4

Performance up to 25.9MB/sec

Automatic 4 bits error correction and retry capabilities

Supports power down commands and Auto stand-by / sleep modes.

+5 V ±10％ or +3.3 V ±5％ operation

Capacity: Min. 32MB ~ Max.48GB

MTBF > 1,000,000 hours.

LED indicators for Power on and operating status

Shock : 1,500G compliance to MIL-STD-810F

Vibration : 20G compliance to MIL-STD-810F

Rugged environment is working well

Very high performance, very low power consumption

Low weight, Noiseless

1.3. ATA/ATAPI-5 Standard

APRO Industrial 40-pin/44-pin MIF disks are fully compatible with the ATA/ATAPI-5 (ATA-66) standard.

1.4. Technology Independence

With the proprietary method to manage variable kinds of flash in terms of wear-leveling and ECC (Error Code Correction),

it translate the ATA control, address and data bus signals into the management unit of NAND type flash devices and

constitute the IDE flash disk more ideal than the conventional hard disk drives.

1.5. Flash Management Technology

In order to gain the best management for flash memory, AORO Industrial 40-pin/44-pin micro IDE Flash (MIF) Disk

supports an efficient and algorithms to manage the Flash system. The life of flash memory is limited; the management is

to increase the life of the flash product. There are some blocks are reserved in flash memory and these blocks would not


2


3

be used in normal operation. When host writes new file to flash memory, the flash controller will check the status field in

the lookup table firstly and find out the available index which status is unused, less used & stale, or used & stale. Then it

writes the new file into the block pointed by the index filed at the lookup table. All three statuses are available for data

store. All three statuses are available for data store, and the priority for write operation is 1st. un-used; 2nd. Less used &

stale; 3rd. Used & stale. When host updates the old file within the flash memory, the host will read the old file to system

memory ahead. Then flash controller will update such file into the block after check the lookup table to find out the

available blocks with the above three status then write the update data into the corresponding block and mark the

previous block stale at the look up table.

2. Product Specifications

For all the following specifications, values are defined at ambient temperature and nominal supply voltage unless

otherwise stated.

2.1. System Environmental Specifications

Table 1: Environmental Specification

Commercial Grade Industrial Grade

APRO Industrial 40/44-pin MIF (Titans Series) SxMIFxxxx-SECSC Series WxMIFxxxx-SEISI- Series

Temperature Operating:

Non-operating:

0ºC ~ +70ºC

-20ºC ~ +80ºC

-40ºC ~ +85ºC

-50ºC ~ +95ºC

Humidity Operating & Non-operating: 10% ~ 95% non-condensing

Vibration Operating & Non-operating: 20G compliance to MIL-STD-810F

Shock Operating & Non-operating: 1,500 G compliance to MIL-STD-810F

2.2. System Power Requirements

Table 2: Power Requirement

Commercial Grade Industrial Grade

APRO Industrial 40/44-pin MIF (Titans Series) SxMIFxxxx-SECSC Series WxMIFxxxx-SEISI- Series

DC Input Voltage (VCC) 100mV max. ripple(p-p) 5V±10%

Reading Mode : 93.0mA (max.)

Writing Mode : 94.6mA (max.) +5V Current

(Maximum average value) Sleeping Mode : 59.5mA (max.)

2.3. System Performance

Table 3: System Performances

Data Transfer Mode supporting

- PIO-4 mode

- DMA SW Mode: Not supported

- DMA MW Mode:0,1,2

- UDMA-4 mode (Default setting)

Data Transfer Rate To/From Host 16.6Mybtes/sec under PIO-4 mode

66.6Mbytes/sec under UDMA-4 Mode

Average Access Time 0.7 ms(estimated)

Sequential Read 25.9 Mbytes/sec (Max. / with dual flash / 100MB file test) Maximum Performance

Sequential Write 11.9 Mbytes/sec (Max. / with dual flash / 100MB file test)

Note:

(1). All values quoted are typically at 25℃ and nominal supply voltage.


4

2.4. System Reliability

Table 4: System Reliability

MTBF >1000,000 hours

Data Reliability <1 non-recoverable error in 1014 bits read

Wear-leveling Algorithms Dynamic wear-leveling algorithms

ECC Technology Enhanced management 4 bits per 512bytes block

Endurance > 2,000,000 cycles logically contributed by dynamic

wear-leveling and advanced bad sector management algorithms

Data Retention 10 years


5

2.5. Physical Specifications

Refer to Table 5 and see Figures 2 ~ 7 for Industrial 40/44-pin MIF physical specifications and dimensions.

Table 5: Physical Specifications

40-pin MIF

Orientation : Vertical Type Horizontal Type

Length: 28.60 mm 26.50 mm

Width: 57.00 mm 51.85 mm

Thickness: 10.20 mm 8.70 mm

G. W. : 20 gw (0.7oz) 15 gw (0.53oz)

44-pin MIF

Orientation : Vertical Type Horizontal Type

Length: 27.35 mm 27.00 mm

Width: 49.95 mm 45.05 mm

Thickness: 9.90 mm 5.75 mm

G. W. : 15 gw (0.53oz) 10 gw (0.35oz)

Figure 2 - 40-pin Vertical Type MIF


6

Figure 3 – 40-pin Horizontal-leftward Type MIF


7

Figure 4 - 40-pin Horizontal-rightward Type MIF

Figure 5 - 44-pin Vertical Type MIF

Figure 6 - 44-pin Horizontal-leftward Type MIF


8

Figure 7 - 44-pin Horizontal-rightward Type MIF

2.6. Power cable for 40-pin MIF

For 40-pin MIF, it comes with a 2-pin power cable. Figure 8: is the picture of the power cable for 40-pin MIF.

Figure 8 – Power cable for 40-pin MIF


9

2.7. Capacity Specifications

APRO Industrial 40-pin/44-pin micro IDE Flash (MIF) Disks are built-in mainly Samsung NAND Type SLC Flash memory

chips. The Table 6 shows the equipollent part number of applied Samsung Flash memory chips for each card.

Table 6: Card Configuration vs. Samsung NAND SLC part number

Card Capacity Samsung SLC Flash Memory Part Number * Q’TY

32MB Commercial Grade:

Industrial Grade: K9F5608UOA-PCB0 (256Mb) or equipollent * 1 K9F5608UOA-PIB0 (256Mb) or equipollent * 1


Industrial Grade:K9F1208UOA-PCB0 (512Mb) or equipollent * 1 K9F1208UOA-PIB0 (512Mb) or equipollent * 1


Industrial Grade:

K9F1G08U0A-PCB0(1Gb) or equipollent * 1

K9F1G08U0A-PIB0 (1Gb) or equipollent * 1

256MB

Commercial Grade:

Industrial Grade:

K9F2G08U0A-PCB0 (2Gb) or equipollent * 1




512MB

Commercial Grade:

Industrial Grade:

K9F4G08U0M-PCB0 (4Gb) or equipollent * 1

K9F2G08U0A-PCB0 (2Gb) or equipollent * 2


K9F4G08U0M-PIB0 (4Gb) or equipollent * 1



1GB

Commercial Grade:

Industrial Grade:

K9K8G08U0M-PCB0 (8Gb) or equipollent * 1

K9F4G08U0M-PCB0 (4Gb) or equipollent * 2

K9K8G08U0M-PIB0 (8Gb) or equipollent * 1

K9F4G08U0M-PIB0 (4Gb) or equipollent * 2

2GB

Commercial Grade:

Industrial Grade:

K9WAG08U1M-PCB0 (16Gb) or equipollent *1

K9K8G08U0M-PCB0 (8Gb) or equipollent *2

K9WAG08U1M-PIB0 (16Gb) or equipollent *1

K9K8G08U0M-PIB0 (8Gb) or equipollent *2

4GB

Commercial Grade:

Industrial Grade:

K9WAG08U1M-PCB0 (16Gb) or equipollent *2

K9K8G08U0M-PCB0 (8Gb) or equipollent *4

K9WAG08U1M-PIB0 (16Gb) or equipollent *2

K9K8G08U0M-PIB0 (8Gb) or equipollent *4

The table 7 shows the specific capacity for the various models and the default number of heads, sectors/track and

cylinders.


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Table 7: Model Capacity

Unformatted

Capacity

Default

Cylinder

Default

Head Default Sector

Default CHS

Capacity

32MB 496 4 32 32,505,856

64MB 978 4 32 64,094,208

128MB 978 8 32 128,188,416

256MB 978 16 32 256,376,832

512MB 993 16 63 512,483,328

1,024MB 1,985 16 63 1,024,450,560

2.04GB 3,954 16 63 2,040,643,584

4GB 7,889 16 63 4,071,481,344

3. Advanced Feature Sets


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3.1. Ultra DMA Feature Set

The Ultra DMA data transfer protocol is implemented and can be used with the READ DMA and wirte DMA commands.

This protocol applies to the Ultra DMA burst only.

Several signal lines are redefined to provide different functions during an Ultra DMA burst. There signal lines revert back

to the definitions used for non-Ultra DMA transfers upon the negation of DMACK by the host at the termination of an Ultras

DMA burst.

3.2. Power Management Feature Set

This feature set is implemented by the controller permitting the host to modify the behavior of the device in a

manner that reduces the power required to operate. This feature set provides a set of commands to enable

the device to operate in low power consumption modes.

3.3. CFA Feature Set

The CFA Erase Sectors command preconditions the sector for a subsequent CFA Write Sectors Without

Erase or CFA Write Multiple Without Erase command to achieve higher performance during the write

operation. The CFA Translate Sector command provides information about a sector such as the number of

write cycles performed on that sector and an indication of the sector’s erased precondition.

3.4. Power Regulator

There’s a high-current low-voltage regulator implemented in CMOS technology. It can deliver 150mA output current and

an internal band gap voltage as a reference to fixed output voltage at 3.3V. CMOS technology ensures low dropout

voltage and 120μA low quiescent current.

3.5. RC Oscillator

This low power internal RC oscillator is designed to operate under 2.7V ~ 5.5V and 85MHz outputs.

4. Interface Description


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4.1. Physical Description

The pin 1 ~ pin 44 are for IDE interface. The pin A ~ pin D are for option selection via physical jumpers.

Figure 9- Vertical Type 40-pin IDE Connector Figure 10 - Horizontal Type 40-pin IDE Connector

Figure 11 - Vertical Type 44-pin IDE Connector Figure 12 - Horizontal Type 44-pin IDE Connector

4.2. Pin Assignments

Signals whose source is the host is designated as inputs while signals that the Industrial 40-pin/44-pin micro IDE Flash

(MIF) Disk sources are outputs. The pin assignments are listed in below table 8.

Table 8: Pin Assignments

Pin

No. Signal Name Description

Pin

No.Pin Name Description

1 RESET- Drive Reset 2 GND --

3 DD7 Drive data bus bit 7 4 DD8 Drive data bus bit 8








19 GND Ground 20 KEY No pin

21 DMARQ DMA request 22 GND Ground

23 DIOW- Drive I/O Write 24 GND Ground

25 DIOR- Drive I/O Read 26 GND Ground

27 IORDY I/O channel ready 28 CSEL Cable select

29 DMACK- DMA acknowledge 30 GND Ground

31 INTRQ Drive interrupt 32 IOCS16- Drive 16 bit I/O


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33 DA1 Drive address bus bit 1 34 PDIAG- Passed diagnostics

35 DA0 Drive address bus bit 0 36 DA2 Drive address bus bit 2

37 CS0- Chip select 0 38 CS1- Chip select 1

39 DASP- Drive active/slave present 40 GND Ground

41 VCC +5V supply 42 VCC +5V supply

43 GND Ground 44 RESERVED Reserved for future

definition

4.3. Electrical Description

The Industrial 40-pin/44-pin micro IDE Flash (MIF) Disk Titans Series is optimized for operation with hosts. .Table 9:

describes the signals of 50-pin interface.

Table 9: Signal Description

Pin No. Signal Name Type Description

37, 38

CS(1:0)–

(Chip Select) I

These signals are used to select the Command Block or

Control Block registers. When DMACK– is asserted, CS0–

and CS1– shall be negated and transfers shall be 16 bits

wide.

33, 35, 36 DA(2:0)

(Device Address) I

This is the 3-bit binary coded address for host to access a

register or data port in this controller.

39

DASP–

(Device active, device

1 present)

I/O

During the reset protocol, DASP–shall be asserted by Device

1 to indicate that the device is present.

3, 4, 5, 6, 7,

8, 9, 10, 11,

12, 13, 14,

15, 16, 17,

18

DD(15:00)

(Device Data)

I/O

Bi-directional data bus. DD(7:0) are used for 8-bit register

transfers.

25

DIOR–: HDMARDY–:

HSTROBE

(I/O Read: Ultra DMA

Ready: Ultra DMA Data

Strobe)

I

DIOR– is the strobe signal used by the host to read device

registers of the Data port.

When Ultra DMA mode DMA Read is active, HDMARDY–

should be asserted by the host to indicate that the host is

ready to receive Ultra DMA data-in bursts.

HSTROBE receives the data-out strobe signal from the host

for an UDMA burst.

23

DIOW–: STOP

(I/O Write: Stop Ultra

DMA Burst)

I

This pin is the strobe signal used by the host to write device

registers or the Data port.

29 DMACK–

(DMA acknowledge) I

This signal is used by the host in response to DMARQ to

initiate DMA transfers.


14

21

DMARQ

(DMA Request) O

For DMA data transfers, this controller will assert DMARQ

when the controller is ready to transfer data to or from the

host.

31 INTRQ

(Interrupt) O

When this device is selected, this signal is the active high

Interrupt Request to the host.

27

IORDY:DDMARDY:DST

ROBE

(I/O channel ready:

Ultra DMA ready: Ultra

DMA data strobe)

O

The controller will assert this signal to indicate that the device

is ready to receive Ultra DMA data-out bursts.

When Ultra DMA mode DMA Read is active, this signal is the

data-in strobe generated by the controller.

34

PDIAG–:CBLID–

(Passed diagnostics:

Cable assembly type

identifier)

I/O

PDIAG– will be asserted by Device 1 to indicate to Device 0

that Device 1 has completed diagnostics.

1 RESET–

(Hardware RESET) I

This is the hardware RESET pin from the host.

28

CSEL

(Cable select) I

This pin is used to configure this device as Device 0 or

Device 1. When this pin is grounded, this device is

configured as Device 0; When the pin is High, this device is

configured as Device 1.

32

IOCS16–

O

During PIO transfer mode 0, 1 or 2, this pin indicates to the

host that 16-bit data port has be addressed and that the

device is prepared to send or receive a 16-bit data word.

When transferring in PIO mode 3, 4 or above, this signal

should not used by the host, and all transfers will be

16-bit.Whentransferring in DMA mode, the host must use a

16-bit DMA channel and this signal will not be asserted.

02, 19, 22,

24, 26, 30,

40, 43

GND Ground

41,42 Vcc Vcc 5V

Note:

1) NAME- : It means signal active low.

2) Pin type is Input/Output, Output or Input.

4.4. Electrical Specification


15

Table 11, Table 12, and Table 13 defines all D.C. Characteristics for the Industrial 40-pin/44-pin micro IDE Flash (MIF)

Disk . Unless otherwise stated, a condition is as below Table 10:

Table 10: Electrical Condition

Commercial Grade

SPMIFxxxx-SECSC Titans Series

Industrial Grade

WPMIFxxxx-SEISI- Series

Vcc = 5V ±10%

Vcc = 3.3V ± 5%

Ta = 0°C to 70°C

Vcc = 5V ±10%

Vcc = 3.3V ± 5%

Ta = -40°C to 85°C

4.4.1. Absolute Maximum Rating

Table 11: Absolute Maximum Rating

4.4.2. Recommended Operating Condition

Table 12: Recommended Operating Condition

4.4.3. DC Characteristics


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Table 13: DC Characteristics

Note:

1) For the pins, which were driven by Vcc.

2) For the host interface pins only, wgeb Vccq = 4.5V to 5.5V

4.4.4. AC Characteristics


17

(TOPR

= 0°C to 70°C, TOPRI

= -40°C to 85°C, Vcc = 3.0V to 3.6V, Vccq = 4.5V to 5.5V, output

loading=35pF)

(1) PIO Mode Read/Write AC Characteristics

The controller complies with the requirements of max. or min. values specified in ATA-5

Specification.

(2) Multiword DMA Mode Read/Write AC Characteristics


Specification.

(3) Ultra DMA Mode Read/Write AC Characteristics


Specification.

(4) Flash-side AC Timing Characteristics

The controller complies with the timing values required by all NAND Flash devices which are

supported by this controller. Please get the list of supported flash devices by contacting 3S, and

refer to the NAND Flash datasheets from SAMSUNG or TOSHIBA to get an idea of items such as

command write, address write and data write.


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5. Interface Register Definition

5.1. Device Address

This controller receives commands from the host only when it is the selected device by checking the

DEV bit in the Device Register.

This interface is for the host to program and perform commands and return status.

Table 14: Device Address Commands

5.2. I/O Register Descriptions

The Command Block registers are used for the host to send commands to this controller or for this

controller to post status. These registers include the LBA High, LBA Mid, LBA Low, Device, Sector

Count, Command, Status, Features, Error and Data Registers. The Control Block register is used for

device control and to post alternate status. These registers include Device Control and Alternate Status

registers.

For the detail field/bit description of every register, please refer to the ATAPI-5 specification.

(1) Alternate Status Register

This register contains the same information as the Status register in the Command Block.

(2) Command Register

This register contains the command code being sent. This controller begins immediately to execute

the command after receipt of the command

(3) DMA Data Port

This port is only accessed for the host DMA data transfers when DMACK– and DMARQ are

asserted. The data is 16-bits in width.


19

(4) Data Register

This register is accessed for the host PIO data transfer only when DRQ is set to one and DMACK–

is not asserted. The contents of this register are not valid while it is in the Sleep mode. This register

is 16 bits wide.

(5) Device Register

This register is for the host to set bit 4, DEV, of this register to selects the device. Other bis in this

register are command dependent.

(6) Device Control Register

This register allows the host to software reset attached devices and to enable or disable the

assertion of the INTRQ signal by a selected device. When this register is written, the controller will

respond to the write no matter the device is selected or not. And this controller will respond to the

SRST bit when in the SLEEP mode.

(7) Error Register

At command completion of any command, the contents of this register are valid when the ERR bit is

set to one in the Status register.

(8) Feature Register

This register is writing only, If this address is reading by the host, the content read by the host will

be the Error register.

The content of this register is command dependent.

(9) LBA High Register

This register contains the high order bits of logic block address and becomes a command

parameter when Command register is written.

(10) LBA Low Register

This register contains the low order bits of logic block address and becomes a command parameter

when Command register is written.

(11) LBA Mid Register

This register contains bit 15-8 of logic block address and becomes a command parameter when

Command register is written.

(12) Sector Count Register

This register contains the numbers of sectors of data requested to be transferred on a read or write

operation.

(13) Status Register

This register contains the device status. The contents of this register are updated to reflect the

current state of the device.


20

6. Command Descriptions

6.1. Command Set

The following table summarizes the command defined in ATAPI-5 specification and lists the commands

supported by the controller.

Table 15: ATA Commands

21

Notes:

(1) FR：Feature Register

SC：Sector Count Register

SN：Sector Number register


CY：Cylinder Low/High register

DR：Drive bit of Drive/Head register

HD：Head No. (bit0-bit3) of Drive/Head register

LBA：Logical Block Address Mode Supported.

Y：Set up; －：Not set up; C：The register contains command specific data.

6.2. Descriptions

(1) CFA Erase Sector(s) – C0h

This command pre-erases and conditions from 1 to 256 sectors in the Sector Count register. This

command must be issued in advance of CFA Write without Erase or CFA Write Multiple without

Erase command to increase the execution speed of the write operation.

(2) CFA Request Extended Error Code – 03h

This command requests extended error information for the previous command. The extended error

code is returned to the host in the Error Register.

(3) CFA Translate Sector – 87h

This command allows the host a method of determining the exact times a user sector has been

erased and programmed. This controller will respond with a 512-byte buffer of information

containing the desired cylinder, head and sector, including its Logical Address.

(4) CFA Write Multiple w/o Erase – CDh

This command is similar to Write Multiple command with the exception that an implied erase before

write operation is not performed.

(5) Write Sector(s) w/o Erase – 38h

This command is similar to the Write Sector(s) command with the exception that an implied erase

before write operation is not performed.

(6) Check Power Mode – E5h

This command allows the host to determine the current power mode of the device. This command

will not cause this controller to change power mode.

(7) Execute Device Diagnostic – 90h

This command causes the controller to perform the internal diagnostic tests.

(8) Identify Device – ECh

This command enables the host to receive parameter information from the device. The following

table specifies each field in the data returned by Identify Device command.


22

Table 16: Identify Device Commands

23



24

25



25

Notes:

(1) F/V = Fixed/Variable content

F = the content of the word is fixed and does not change.

V = the content of the word is variable and may be changed depending on the state of the device,

commands executed.

X = the content of the word may be fixed or variable.

C = vendor specific data which can be customized before device shipping.

(2) aaaa indicates an ASCII vendor string; x indicates a numeric nibble value.

(9) Idle – E3h

This command allows the host to place the device in the Idle mode and also set the Standby timer.

(10) Idle Immediate – E1h

This command allows the host to immediately place the device in the Idle mode.

(11) Initialize Device Parameters – 91h

This command enables the host to set the number of sectors per track and number of heads per

cylinder.

(12) NOP – 00h

This controller will respond with command abort upon receipt of the NOP command.

(13) Read Buffer – E4h

This command enables the host to read the current contents of the device’s sector buffer.


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(14) Read DMA – C8h

This command allows the host to read data using the DMA data transfer protocol.

(15) Read Multiple – C4h

This command reads the number of sectors specified in the Sector Count register. The number of

sectors per block is defined by the content of word 59 in the Identify Device response. A successful

Set Multiple Mode command has to precede this command.

(16) Read Sector(s) – 20h

This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count

of 0 will be treated as 256 sectors. The transfer begins at the sector specified in the LBA Low, LBA

Mid, LBA High and Device registers.

(17) Read Verify Sector(s) – 40h

This command is identical to Read Sector(s) command, except that DRQ is never set and no data

is transferred to the host.

(18) Seek – 70h

This command allows the host to provide advanced notification that particular data may be

requested by the host in a subsequent command.

(19) Set Features – EFh

This command is used by the host to establish parameters that affect the execution of certain

features. The following table defines all features that are supported by this controller. If any

subcommand input value is not supported or is invalid, this controller will return command aborted.


27

Table 17: Set Feature Commands

(20) Set Multiple Mode – C6h

Upon receipt of this command, the controller will perform Read and Write Multiple operations and

establishes the block count for these commands. This controller will set BSY to 1 and checks the

Sector Register for the number of sectors per block.

(21) Sleep – E6h

Upon receipt of this command, the controller will set BSY and enter Sleep mode, clear BSY and

generate an interrupt.

(22) Standby – E2h

This command will cause the device to enter Standby mode. The value in the Sector Count register

is used to determine the time programmed into the Standby timer.

(23) Standby Immediate – E0h or 94h

This command will cause the device to immediately enter Standby mode.


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(24) Write Buffer – E8h

This command allows the host to overwrite contents of a sector buffer with any data pattern desired.

(25) Write DMA – CAh

This command allows the host to write data using the DMA data transfer protocol.

(26) Write Multiple – C5h

This command is similar to the Write Sector(s) command. Interrupts are not presented on each

sector but on the transfer of a block that contains the number of sectors defined by Set Multiple.

(27) Write Sector(s) – 30h

This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count

of 0 will be treated as 256 sectors. This controller will interrupt for each DRQ block transferred.


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7. Installation Procedure

7.1. Before unpacking

Before unpacking or handling a drive, take all proper electrostatic discharge (ESD) precautions, including

personal and equipment grounding. Before you start to install the 40/44-pin MIF into your system – please

check the following.

If the shipping package appears to be damaged or water stained, notify your dealer.

Remove the disk from its shipping enclosure and inspect it for any damage that may have occurred

during shipment. If any damage is observed, notify your dealer.

Record the disk serial number and shipment date.

Retain the original shipping enclosure and all packing material for re-shipment.

7.2. ESD Precautions

You can prolong the life of your MIF as well as increase its reliability and prevent unnecessary damage by

following the instructions listed below. Failure to follow any of these instructions may void your warranty.

(1) Always take all proper electrostatic discharge (ESD) precautions, including personnel and

equipment grounding.

(2) Always operate the Flash disk within the environmental specifications.

(3) Always use a grounded wrist strap when handling the Flash disk. Drives that are not installed in the

system are sensitive to ESD damage.


30

7.3. Illustration of 40/44-pin MIF

Before plugging in IDE connector on the mainboard, the MIF must be configured. Below figures can help you

to the aspect with illustration to help you correct configuration.

Figure 13 – Illustration of V-type 40-pin MIF

Figure 14 - Illustration of H-type 40-pin MIF


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Figure 15 – Illustration of V-type 44-pin MIF

Figure 16 - Illustration of H-type 44-pin MIF


32

7.4. Configuration of 40/44-pin MIF

(1) Select Master or Slave by Switch

(2) Enable Write Protect function by Switch

(3) For 40-pin MIF, plug-in the power connector on MIF

(4) Find the pin-1 of both MIF and the IDE interface on motherboard, the fool-proof device on MIF can

also help to connect the IDE connector correctly.

7.5. MIF Insertion and Removing

7.5.1. MIF Insertion

The connector of V-type MIF is very tight when plugging in, and it insures the MIF connection to

motherboard properly. However, you have to be very careful to insert the MIF, especially V-type MIF, in

right behavior. Blows are the important points for your attention to insert the MIF.

(1) Check the MIF housing to see if there are any damaged or loose parts and then check the female

connector carefully if they are intact.

(2) Before inserting the MIF, please check each IDE pins on motherboard are perfect and straight.

Figure 17 - Defective IDE male Pins on Motherboard

Figure 18 - Intact IDE male pins on Motherboard


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(3) Any rude or wrong insertion will damage the both connectors of MIF and motherboard.

Figure 19 – Wrong Insertions

(4) When plugging in, make sure pin-1 of MIF matches to pin 1 of IDE socket on motherboard. The two

ends of connectors must be vertically aligned. Press it down gently and swing slightly a few times. If

insertion is not smooth, DO NOT ATTEMPT TO INSERT FORCEFULLY.

7.5.2. MIF Removing

(1) Make sure the power is off before removing.

(2) As they are firmly attached, you can swing gently a few times to remove. DO NOT PULL IT OFF

FORECE.

7.6. IDE Device Setup / Auto-Detection

Most BIOSes have an entry in the Standard Setup menu for each of the four IDE/ATA devices supported in a

system (primary master, primary slave, secondary master, and secondary slave). For each one, you can enter

a value for each setting in this section (type, size, cylinders, etc.).

Virtually all BIOSes now come with IDE device Auto-Detection. This comes in two forms:

Dynamic IDE Auto-Detection: This is the fully automatic mode. You set one or more of the IDE devices

(primary master, primary slave, etc.) on "Auto" and the BIOS will automatically re-detect and set the

correct options for the drive each time you boot the PC. The BIOS will usually display on the screen what

device it finds each time it auto-detects. For most people, this is the best way to go; it ensures that your

BIOS always has the correct information about your hardware, and it removes any possibility of you

installing a new drive but forgetting to set up the CMOS properly, or of changing a parameter by mistake

in the setup program. Not all BIOSes offer this setting but most newer ones do.


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Manual IDE Auto-Detection: This type of Auto-Detection is run from the BIOS setup program. You

select Auto-Detection, and the BIOS will scan the IDE channels, and set the IDE parameters based on

the devices it finds. When you save the BIOS settings, they are recorded permanently. The

disadvantage of this is that if you change devices, you must return to the BIOS to re-auto-detect the new

devices (unlike the dynamic Auto-Detection scheme, which does a fresh Auto-Detection each time you

boot the PC). Virtually every BIOS created in the last 8 to 10 years offers manual Auto-Detection.

When you use dynamic Auto-Detection, the BIOS will normally "lock" the individual device settings that are

being automatically set by the BIOS at boot time. Most systems that provide manual Auto-Detection will not

lock the individual settings; they auto-detect, set the settings, and then let you change them if you want to. In

most cases of course, you will not want to change what the BIOS detects.

Most BIOSes that allow dynamic Auto-Detection also allow manual Auto-Detection; the choice is yours. Using

some sort of Auto-Detection for IDE/ATA devices is strongly recommended. It is the best way to reduce the

chances of disk errors due to incorrect BIOS settings. It also provides immediate feedback of problems; if you

can't auto-detect a drive from the BIOS, you know you have a problem even before you try to boot up.

7.7. Partition & Format

Before you install your operating system, you must first create a primary partition on the MIF on the system,

and then format a file system on that partition. The Fdisk tool is an MS-DOS-based tool that you can use to

prepare (partition) the R2IDF. You can use the Fdisk tool to create, change, delete, or display current

partitions on the MIF, and then each allocated space on the MIF (primary partition, extended partition, or

logical drive) is assigned a drive letter. Disk 1 may contain one extended partition, and a second MIF may

contain a primary or extended partition. An extended partition may contain one or more logical MS-DOS

drives.

After you use the Fdisk tool to partition MIF, use the Format tool to format those partitions with a file system.

The file system File Allocation Table (FAT) allows the MIF to accept, store, and retrieve data. Windows 95

OEM Service Release 2 (OSR2), Windows 98, Windows 98 Second Edition, Windows Millennium Edition

(Me), and Windows 2000 support the FAT16 and FAT32 file systems. When you run the Fdisk tool on a MIF

that is larger than 512 megabytes (MB), you are prompted to choose one of the following file systems:

FAT16: This file system has a maximum of 2 gigabytes (GB) for each allocated space or drive letter. For

example, if you use the FAT16 file system and have a 6-GB MIF, you can have three drive letters (C, D, and E),

each with 2 GB of allocated space.

FAT32: This file system supports drives that are up to 2 terabytes in size and stores files on smaller sections

of the MIF than the FAT16 file system does. This results in more free space on the MIF. The MIF file system

does not support drives that are smaller than 512 MB.

When you run the fdisk and format commands, the Master Boot Record (MBR) and file allocation tables are

created. The MBR and file allocation tables store the necessary disk geometry that allows MIF to accept,

store, and retrieve data.


35

Appendix A. Ordering Information

1. Part Number

40-pin MIF support operating temperature 0ºC ~ 70ºC

Form-factor 40-pin microIDE flash disk

Grade Operating temperature supports 0˚C ~ 70˚C

Product picture Size Type PIO-4 mode UDMA-4 mode

Vertical SPMIF032M-SECSC-0VP SPMIF032M-SECSC-0VU

Right SBMIF032M-SECSC-0RP SBMIF032M-SECSC-0RU 40-pin Vertical Type 32

MB Left SBMIF032M-SECSC-0LP SBMIF032M-SECSC-0LU


Right SBMIF064M-SECSC-0RP SBMIF064M-SECSC-0RU 64





Vertical SPMIF256M-SECSC-0VP SPMIF256M-SECSC-0VU 40-pin Horizontal-right

Type Right SBMIF256M-SECSC-0RP SBMIF256M-SECSC-0RU

256





Vertical SPMIF001G-SECSC-0VP SPMIF001G-SECSC-0VU

Right SBMIF001G-SECSC-0RP SBMIF001G-SECSC-0RU 1

GB Left SBMIF001G-SECSC-0LP SBMIF001G-SECSC-0LU

40-pin Horizontal-left

Type Vertical SPMIF002G-SECSC-0VP SPMIF002G-SECSC-0VU

Right SBMIF002G-SECSC-0RP SBMIF002G-SECSC-0RU

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2




4



44-pin MIF support operating temperature 0ºC ~ 70ºC


Grade Operating temperature supports 0˚C ~ 70˚C



Right SBMIF032M-SECSC-4RP SBMIF032M-SECSC-4RU 44-pin Vertical Type 32








Vertical SPMIF256M-SECSC-4VP SPMIF256M-SECSC-4VU 44-pin Horizontal-right

Type Right SBMIF256M-SECSC-4RP SBMIF256M-SECSC-4RU

256









Type Vertical SPMIF002G-SECSC-4VP SPMIF002G-SECSC-4VU





4



37

40-pin MIF support operating temperature -40ºC ~ 85ºC


Grade Operating temperature supports -40ºC ~ 85ºC


Vertical WPMIF032M-SEISI-0VP WPMIF032M-SEISI-0VU

Right WBMIF032M-SEISI-0RP WBMIF032M-SEISI-0RU 40-pin Vertical Type 32

MB Left WBMIF032M-SEISI-0LP WBMIF032M-SEISI-0LU


Right WBMIF064M-SEISI-0RP WBMIF064M-SEISI-0RU 64





Vertical WPMIF256M-SEISI-0VP WPMIF256M-SEISI-0VU 40-pin Horizontal-right

Type Right WBMIF256M-SEISI-0RP WBMIF256M-SEISI-0RU

256





Vertical WPMIF001G-SEISI-0VP WPMIF001G-SEISI-0VU

Right WBMIF001G-SEISI-0RP WBMIF001G-SEISI-0RU 1

GB Left WBMIF001G-SEISI-0LP WBMIF001G-SEISI-0LU


Type Vertical WPMIF002G-SEISI-0VP WPMIF002G-SEISI-0VU




Right WBMIF004G-SEISI-0RP WBMIF004G-SEISI-0RU

4



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44-pin MIF support operating temperature -40ºC ~ 85ºC


Grade Operating temperature supports -40ºC ~ 85ºC



Right WBMIF032M-SEISI-4RP WBMIF032M-SEISI-4RU 44-pin Vertical Type 32








Vertical WPMIF256M-SEISI-4VP WPMIF256M-SEISI-4VU 44-pin Horizontal-right

Type Right WBMIF256M-SEISI-4RP WBMIF256M-SEISI-4RU

256









Type Vertical WPMIF002G-SEISI-4VP WPMIF002G-SEISI-4VU




Right WBMIF004G-SEISI-4RP WBMIF004G-SEISI-4RU

4



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2. Part Number Decoder

- Part number construction

X1 X2 X3 X4 X5 X6 X7 X8 X9－X11 X12 X13 X14 X15－Y1 Y2 Z1 C

- Decoder Description

X1 : Grade S : Standard Grade – operating temp. 0º C ~ 70 º C W : Industrial Grade – operating temp. -40º C ~ 85 º X2 : The material of case B : Bare (without case) P : Plastic case X3 X4 X5 : Product category MIF : micro IDE Flash (module) X6 X7 X8 X9 : Capacity 032M: 32MB 064M: 64MB 128M: 128MB 256M: 256MB 512M: 512MB 001G: 1GB 002G: 2GB 004G: 4GB

X11 : Controller S : 3S (Titans Series) X12 : Controller version A,B,C…..

X13 : Controller Grade C : Commercial grade I : Industrial grade X14 : Flash IC S : Samsung NAND-SLC Flash IC X15 : Flash IC grade / Type C : Commercial grade I : Industrial grade Y1 Y2 : MIF orient only 0V : 40-pin IDE Vertical MIF 0R : 40-pin IDE Right-oriented MIF 0L : 40-pin IDE Left-oriented MIF 4V : 44-pin IDE Vertical MIF 4R : 44-pin IDE Right-oriented MIF 4L : 44-pin IDE Left-oriented MIF Z1 : Data transfer rate - IDE series is always as fixed disk type P : PIO-4 mode / fixed disk type U : UDMA-4 mode / fixed disk type C : Reserved for specific requirement C : Conformal-coating


40


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Appendix B. Limited Warranty

APRO warrants your Industrial 40-pin/44-pin micro IDE Flash (MIF) Disk against defects in material and workmanship for

the life of the drive. The warranty is void in the case of misuse, accident, alteration, improper installation, misapplication or

the result of unauthorized service or repair. The implied warranties of merchantability and fitness for a particular purpose,

and all other warranties, expressed or implied, except as set forth in this warranty, shall not apply to the products delivered.

In no event shall APRO be liable for any lost profits, lost savings or other incidental or consequential damages arising out

of the use of, or inability to use, this product.

BEFORE RETURNING PRODUCT, A RETURN MATERIAL AUTHORIZATION (RMA) MUST BE OBTAINED FROM

APRO.

Product shall be returned to APRO with shipping prepaid. If the product fails to conform based on customers’ purchasing

orders, APRO will reimburse customers for the transportation charges incurred.

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