Process Bus for Bus Differential – Challenges, Solutions...

25
Process Bus for Bus Differential – Challenges, Solutions, and Opportunities The 72 nd Annual Conference for Protective Relay Engineers

Transcript of Process Bus for Bus Differential – Challenges, Solutions...

Page 1: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

Process Bus for Bus Differential –Challenges, Solutions, and OpportunitiesThe 72nd Annual Conference for Protective Relay Engineers

Page 2: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 2

Busbar protection

• busbars are used to connectelectrical elements likegenerators, transformers, linesor feeders in a switchyard orswitchgear

• there are a lot of different typesof busbars used in our industry

• electrical faults on busbars often occur with high short circuit currents

• fast fault clearing time is required to maintain the stability of the power system

• busbar protection need to be stable in case of external faults because losinga busbar has severe impact to the power system

• busbars are important parts ofthe power system

Page 3: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 3

Basic principle of bus differential protection

• bus differential protection is based onKirchhoff’s current law

• the protected zone of bus differential protection is defined by the location of thecurrent transformer

Bus zone

I1 InI2

...

01

=∑=

n

kkI

• high selectivity is reached and no additional time delay is neededthis guaranties a high speed of bus differential protection

• the availability and the characteristic of the current transformer at the protectedzone have a major impact on the selection of the busbar protection scheme

Page 4: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 4

Comparison of different bus differential schemes

• partial differential overcurrent can be used if CT’s are not available for all buselements

Sel

ectiv

ity

Spe

ed

Sen

sitiv

ity

Sec

urity

CT-

Req

uire

-m

ents

Partial differential overcurrent

- - - - +

Differentially connected overcurrent

+ o o - o

High-impedance differential

+ + + + -

Low-impedance differential

+ + o + +

+ excellent

o good

- not good

• high impedance bus differential protection offers the best performance regardingselectivity, speed, sensitivity and security but needs dedicated CT which must beof same type and CT ratio

• low-impedance differential schemes can reach nearly the same performance withmuch lower CT requirements

Page 5: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 5

Basic principle of low impedance bus differential protection

• the operating quantity Idiff is equal to the magnitude ofthe sum of all currents flowing into the protected zone

• a restraint current Ires is created and a trip command isonly given if the differential current exceeds aminimum differential current setting and a certainportion of the restraint current like shown in the figure

restraint current

differential current

minimum differential

currentrestrain area

operate area slope

∑=

=n

kkdiff iI

1

Bus zone

I1 InI2

...

∑=

=n

kkres iI

1

Page 6: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 6

Two general kinds of bus differential algorithm1. protection based on pure samples

• bus differential protection based on pure samples can generate a trip decision ina few milliseconds using a very short measurement window like shown in figure

I/A

t/s

measurement window

Primary currentSecondary current

∑ ∑= =

=

n

k

m

llkiI

1 1,diff

∑ ∑= =

=

n

k

m

llkiI

1 1,res

k: consecutive number of bay / feedern: total number of bays / feedersl: consecutive number samplem: total number samples

• a trip for this bus fault with high short circuit current can be given before thecurrent transformer starts to saturate

Page 7: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 7

Two general kinds of bus differential algorithm2. protection based on current phasors

k: consecutive number of bay / feedern: total number of bays / feeders

• current phasors are used to form the operatingand restraint quantities ∑

=

=n

kkdiff II

1

∑=

=n

kkres II

1

• using current phasors instead of instantaneous values increases the sensitivitybecause the current phasors only contain the measurements of the fundamentalfrequency

• all transients and the DC component are filteredout of the signal in best case

• bus differential protection based on current phasors needs more time to generatea trip command because it needs at least a cycle of the fundamental frequency tocalculate the current phasors

Page 8: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 8

Architecture of centralized bus differential protection

• in this scheme all data processing is done in the central unit

I1 InI2

...

Central unit• for centralized bus differentialprotection all primary equipmentlike CT or auxiliary contacts ofcircuit breaker and disconnectorsare connected via copperconnections to the central unit

• due to this approach centralized bus differential protection scheme is limited toapproximately 20 bays

• centralized busbar protection is mostly cheaper compared to a distributedsolution, because of less hardware and engineering effort

Page 9: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 9

Architecture of distributed bus differential protection

• bay units are installed at each bayto get all relevant data from theconnected bay

• in case of a trip command this is transferred back to the bay unitswhich give it to the connected circuit breaker

• after pre-processing these data is sent via digital communicationfrom the bay units to the central unit

• the differential algorithm is running in the central unit

I1 InI2

...

Bay

uni

t

Central unit

Bay

uni

t

Bay

uni

t

Page 10: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 10

Advantages of distributed bus differential protection

1. Distributed busbar protection is especially applied at wide area air isolated substations. The wiring of primary CTs via a long-distance lead to a high burden of the CTs. A high burden of the CTs lead to an earlier saturation of the CTs, which is an inherent problem for differential protection.

2. At distributed busbar protection a redundant feeder protection (CBFP, OCP, EFP etc.) in the bay units is possible.

3. Distributed busbar protection can typically cover a higher number of feeders.

4. Distributed busbar protection can typically easily be extended.

• today it is possible to connect merging units to a centralized bus differentialprotection

• using this approach the difference between centralized and distributed busdifferential protection will disappear

Page 11: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 11

Architecture of distributed bus differential protection using merging units

• distributed busbar differential schemecan be established using mergingunits as bay units

• a merging unit can be designed as aplain device only feeding the centraldevice of bus differential protectionwith sampled measured values

I1

In

I2

...

mer

ging

un

itCentral unit

Feed

er p

rote

ctio

n +

mer

ging

uni

t

Tran

sfor

mer

pro

tect

ion

+ m

ergi

ng u

nit

• the merging unit can also beimplemented in a feeder ortransformer protection relay

• this concept is used to save a lot ofrelays, wiring and engineering work

Page 12: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 12

Architecture of distributed bus differential protection using plain merging units only

• the same application as shown onthe last slide could be is designedin a different way

• all bays are equipped with plainmerging units

• feeder protection for bay 2 andtransformer protection for bay nare running in the central unitof bus differential protection

I1

In

I2

...

mer

ging

un

it

Central unitFeeder

protection for bay 2

Transformer protection for

bay nm

ergi

ng

unit

mer

ging

un

it

• the bay specific protection functionsare located in the central unit of busdifferential protection

Page 13: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 13

Communication architecture of classical distributed bus differential protection

• the classical proprietary solutions ofdistributed bus protection use fielddevices which are connected to thecentral device in a star architecturewithout any communication redundancy

• the use of merging units and IEC61850 enables a lot of different solutions forthe communication architecture of a bus differential scheme

...

Central unit

BayunitBay 1

BayunitBay 2

BayunitBay n

Page 14: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 14

Communication architecture of distributed bus differential protection using IEC61850

• the bay units shown on the last slide are replaced by IED’s containing themerging unit function and the capability to maintain binary signals from and tothe relevant switchgear in the connected bay

...

Central unit

IED IED IED

Switch

Bay 1 Bay 2 Bay n

• these IED’s are connected to an Ethernet switch which is connected to thecentral unit of the bus differential protection

Page 15: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 15

Redundant Communication of distributed bus differential protection using IEC61850 star structure according to PRP

• if communication redundancy is needed each IED can be connected separatelyto two different switches which are connected in parallel to the central unit

• this communication architecture is used for redundancy according to thePRP standard

...

Central unit

IED IED IED

Switch 1 Switch 2

Bay 1 Bay 2 Bay n

Page 16: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 16

Redundant Communication of distributed bus differential protection using IEC61850 ring structure according to HSR

• another solution for communication redundancy according to the Standard HSRis shown in the figure above

• the IED’s acting as bay units of bus differential protection are connected in acommunication ring with the central unit of bus differential protection

...

Central unit

IED IED IEDBay 1 Bay 2 Bay n

HSR ring

Page 17: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 17

Redundant Protection for distributed bus differential protection using IEC61850 ring structure according to HSR

• additional to the communication redundancy a protection redundancy could beimplemented

• this second central unit is able to receive the same data from the bay unitsand run redundant algorithm of bus differential protection

Central unit 1

IED IED IEDCentral unit 2 ...

HSR ring

Bay 1 Bay 2 Bay n

• a second central unit of bus differential protection is added to thecommunication ring

Page 18: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 18

Time synchronization for distributed bus differential protection using IEEE 1588

• time synchronization is utmost important for the proper function of a distributedbus differential scheme

• today the typical application for precise time synchronization is done using acommercial clock which can provide time synchronization according toIEEE 1588 with the power profile IEEE C37.238

• using sampled measured values according to IEC61869-9 the sampling of thecurrents in the different bay units has to be done at the same instances of timewith synchronization accuracy better than 1us

Central unit 1

IED IED IEDIEEE 1588 Timing master

...

HSR ring

Bay 1 Bay 2 Bay n

GPS / GNSS

• in general this master clock is an additional device like shown above

Page 19: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 19

Time synchronization for distributed bus differential protection using IEEE 1588

• this problem can be solved by a different composition of the system

• the master clock can be integrated in the central device of bus differentialprotection

...

Central unit +1588 master clock

IED IED IEDBay 1 Bay 2 Bay n

HSR ring

Switch

Switch

Switch Switch

GPS / GNSS

• the reliability of a bus differential schemebased on IEC61850 is decreaseddue to the need of additional devices likeGPS clocks and switches

• the switches to form the HSR ring could be implemented in each IED

Page 20: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 20

Bus differential protection using NCIT

• different transient behavior ofdifferent types of instrumenttransformers can produce a wrongdifferential current

• according to IEC61869-6, Annex 6Aan instrument transformer is permittedto transfer DC or is permitted to cut offthe DC with a maximum high passcutoff frequency of 1 Hz

• if different types of instrumenttransformers are applied in a busdifferential scheme, care must betaken about the stability of thealgorithm

Page 21: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 21

Output signals of two different CT for a fault current with 100% DC offset

• the blue curve represent the original fault current - this could be the output of anoptical CT which is able to measure DC

• based on this limitationa worst-case calculationcan be done consideringa fault current with 100%DC offset and a primarytime constant of 60ms

0.0 0.02 0.04 t in s-20

-10

0

10

20

30DC coupled output

highpass filtered output I in kA

• the red curve is the output of a CT with the maximum permitted high pass cutofffrequency of 1 Hz

• the black curve is the difference between the output signals of both CT’sthis difference signal would appear as a differential current!

Page 22: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 22

Difference based on samples between two CT output signals for a fault current with 100% DC offset

• using a differential protection algorithm based on samples no additionalstabilization would be necessary for the first samples

• figure left shows the differencebetween the two extreme CToutput signals in more detail

• for the first 3 samples after faultinception the deviation is muchless than 1% of the originalsignal

• using this algorithm for a longer time 10% additional stabilization should be applied

• algorithm based on pure samples should be used only for a short time after faultinceptionafter a full period algorithm based on current phasors reach a higher accuracy

0.0 0.02 0.04 t in s0

2

4

6

8

10∆I in %

Page 23: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 23

Total vector error of two CT output signals for a fault current with 100% DC offset

• for phasor based bus differential algorithm this total vector error need to becovered by additional restrained current

• for example both phasors arecalculated using full cycle sinusand cosines filter

• figure left shows the total vectorerror based on the phasordeviation of both signals

• according to the coming standard IEC61850-7-4 edition 2.1 the high pass timeconstant of the CT with digital output should be given in form of a setting

• using this setting the signals coming from CT’s with different high pass timeconstants can be transformed to signals with the same time constant

0.0 0.02 0.04 0.06 t in s0

1

2

3

4

5 TVE in %

Page 24: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 24

Conclusion

• It was shown that process bus will have a great impact to the design of bus differential protection.

• Due to the concept of merging unit as a function instead of a box, different schemes of centralized or distributed protection becomes possible.

• Process bus also enables the use of NCIT for low impedance bus differential protection.

Page 25: Process Bus for Bus Differential – Challenges, Solutions ...prorelay.tamu.edu/wp-content/uploads/sites/3/2019/... · high short circuit currents • fast fault clearing time . is

2019-03-26Page 25

Thank you for your attention!

Jörg BlumscheinPrincipal Key Expert ProtectionEM DG SA&P LM&D PPM

Wernerwerkdamm 513629 Berlin

Phone: +49 (30) 386 20135Fax: +49 (30) 386 25158

E-mail:[email protected]

siemens.com/answers