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FPGA Synthesis with the Synplify Pro Tool

®

Winter/Spring 2003

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Course OutlineCourse Outline

» Introduction

» Design Flow and Synthesis Concepts

» Synplify Pro Flow Overviewu Invoking Synplify Prou Project Optionsu Simple Synthesis RunuResults Overview

» Compiler Synthesis Optimizationu B.E.S.T. Algorithmu Supported Verilog Constructsu Supported VHDL ConstructsuRecommended Coding StylesuCompiler Options and Directivesu Synthesis Issues

» SCOPE Editor

» Mapper Synthesis OptimizationuHow the Mapper Worksu Timing Constraint EffectuMapper Attributes

» Debugging with the HDL Analyst tool» Batch ModeLab 1

Lab 2

Lab 3

Lab 4

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IntroductionIntroduction

» Introduction» Design Flow and Synthesis

Concepts

Introduction

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Synplicity’s SolutionsSynplicity’s Solutions

Introduction

Certify®

Amplify®

Physical Optimizer ™

Certify SC™

Synplify Pro®

and Synplify®

Synplify ASIC

ASIC solutions

FP

GA

solutions

brings leading-edgelogic synthesis and

verification productsto FPGA and ASIC

designers

Synplicity

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FPGA Product Line OverviewFPGA Product Line Overview

SynplifyPro Tool• Challenging Designs• Complex Projects• The Ultimate in FPGA

Synthesis

Synplify Tool• Fast• Easy to Use• Excellent Results

Amplify Physical Optimizer Physical Synthesis for FPGAs• Highest Circuit Performance• Fastest Timing Closure• Option to Synplify Pro

Introduction

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FPGA Synthesis with the Synplify Pro ToolFPGA Synthesis with the Synplify Pro Tool

» Ultra FastuB.E.S.T.TM algorithms

» Easy to UseuLanguage sensitive

Text EditoruHDL Analyst® tooluS.C.O.P.E.®

» Excellent ResultsuTiming-drivenuDirect mapping to

technology-specific primitives

Introduction

Market Leader in FPGA Synthesis

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Getting HelpGetting Help

» Online Helpu Select Help->Help, or [F1] function key from Synplify Pro Software

» Synplify Pro Tool User Guideu Pdf file found in <Synplify Pro Install Dir>/docs

» Synplify Pro Tool Reference Guideu Pdf file found in <Synplify Pro S/W Install Dir>/docs

» Synplicity Supportu Synplify Online Support [SOS] and Synplify Newsgroup» http://www.synplicity.com/support/logon_news/log_news.html» news://news.synplicity.com/Synplicity.Synplify

u Synplify First Level Support» Can be accessed from S.O.S

u Send email to [email protected] the Technical Support Hotline at (408) 215-6000

Introduction

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Design Flow and Synthesis ConceptsDesign Flow and Synthesis Concepts

Design Flow and Synthesis Concepts

» Introduction» Design Flow and Synthesis

Concepts

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constraints

HDL Design MethodologyHDL Design Methodology

Functional Spec

RTL CodingVerilog/VHDL

RTL Simulation

Synthesis

script files FPGA Technology

timinganalysis

mappednetlist

simulate mapped design

timingverification

post layoutsimulation

chip


Place & Route

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Why HDL Design Entry? Why HDL Design Entry?

» Technology independenceuNo vendor-dependent schematic/HDL entryuCommon language for synthesis and simulationuBetter suited to design re-use

» Higher level of design abstractionuDesigner can focus on chip design goalsuLeave implementation to toolsuImproves time to market for complex designs


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Synthesis in the Synplify Pro ToolSynthesis in the Synplify Pro Tool

Compile

Technology Map[Based on Device options]

Technology independent RTL View netlist[.srs]

User Constraint File[.sdc]

Mixed Verilog/VHDL

Technology view netlist[.srm]

Technology-specific netlist[.edf, .xnf, .vqm, .edn etc.]

Forward annotated timing constraints[.acf,.ncf,. lp etc.]

Post-synthesis simulation netlist [.vhm/.vm]


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Synthesis StepsSynthesis Steps

COMPILE

CREATE PROJECT

ADD HDL FILES

CREATE HDL FILES

SELECT DEVICE OPTIONS

ADD TIMING CONSTRAINTS

SYNTHESIZE

CHECK RESULTS


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Input Files to the Synplify Pro ToolInput Files to the Synplify Pro Tool

» RTL level source filesuVeriloguVHDLuBoth

» Constraint fileuDefine timing constraints such as clocks, input/output

delays, timing exceptionsuDirectives and attributes to control synthesisuTCL formatu.sdc extension


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CompilationCompilation

» Syntax checking of HDL Code

» Conversion of HDL code into technology-independent netlist

» B.E.S.T.TM

Algorithms: extraction of high level structures

» Finite State Machine(FSM) extraction and optimization

» Resource sharing of arithmetic operators

» RTL optimization

» Enables RTL View


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Behavioral Extracting Synthesis TechnologyBehavioral Extracting Synthesis Technology

Gates

Compile HDL

Logic Optimization

Technology Mapping

Synthesis

Behavior

RTL

Leve

l of A

bstra

ctio

n

Synplify

Other Synthesis Tools

High-level structure preserved throughout optimization

uUltra-fast compile time uMulti-million gate capacityuOptimization across

hierarchical boundaries


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Technology MappingTechnology Mapping

» Inputs» Technology-independent netlist generated by compiler» Constraint file

»Mapping to technology-specific structures» look-up tables [LUTs]» registers

» B.E.S.T algorithm» Behavior extraction and mapping to resources available in the

specified technology

» Timing-driven synthesis and optimization» Logic Replication» Buffering

» Enables Technology ViewDesign Flow and Synthesis Concepts

» Structuring» Critical Path re-synthesis

» RAM/ROM

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Output Files From the Synplify Pro ToolOutput Files From the Synplify Pro Tool

» Technology-specific netlist » edf for Virtex and Flex10k, edn for Orca and Actel, vqm for Apex

» Constraint file for the Place and Route toolu Forward annotated constraints and attributes specified

in the Synplify Pro tool» ncf for Virtex, acf for Flex10k, tcl for Apex, lp for Orca families

»Mapped VHDL or Verilog netlist for post-synthesis simulation

» vm for Verilog, vhm for VHDL


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Synplify Pro Flow OverviewSynplify Pro Flow Overview

Synplify Pro Flow Overview


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Invoking the Synplify Pro ToolInvoking the Synplify Pro Tool

» Invoking the Synplify Pro tool interactivelyuPC» Select Programs->Synplicity->Synplify Pro 7.0 from the Start

menuuUNIX» At the command line, type:

synplify_pro

» Invoking the Synplify Pro software in batch modeuOn PC or UNIX, type

synplify_pro -batch <file_name>


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Synplify Pro Tool Project WindowSynplify Pro Tool Project Window

HDL AnalystSCOPEText Editor

Result FilesInput Files

Modify Source Files in Project

Choose and Set Options

Tcl Commands


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Project FileProject File

» Stores data needed for a designuSource filesuDevice OptionsuConstraint filesuMultiple ImplementationsuCompiler and Mapper OptionsuResult file optionsuGlobal Frequency

» Text file with Tcl commands

» Tcl commands displayed in TCL window


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Creating a New Project Creating a New Project

Synplify Pro Project window

Helpful for new users


Creates a new project

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Adding Source FilesAdding Source Files


Filter on file type

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Creating HDL Source Files Creating HDL Source Files

» HDL Source files can be created using any editor

» Synplify Pro Text Editor uFull-Featured editor» Context-sensitive color coding» Block commenting of HDL lines of code» Selection and editing of columns» Bookmarks» Screen splitting» Other standard features:» Find, Replace, Line numbers, Auto-completion using ESC key

uIntegrated with the synthesis environment» Crossprobing between HDL code and synthesis log file» Synthesis check and syntax check on the HDL source files» Navigation through errors in all HDL source files


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Selecting a Third-Party Editor Selecting a Third-Party Editor

» Under Options -> Editor Options

» For PCuJust browse to the editor

executable

» For Solaris and HPuType: xterm –e vi

» For Linux Red HatuType: gnome-terminal –x emacs


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Text Editor Window Text Editor Window Comments are

green

Keywords are blue

Strings are red


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Creating a New Constraint FileCreating a New Constraint File


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Applying Basic Timing ConstraintsApplying Basic Timing Constraints

Clock constraint of 30 MHz specified in the “Clocks”tab

Default Input Delay of 5ns, Default Output Delay of 3ns and Output delay of 7ns on multout[11:0] specified in “Inputs/Outputs”tab


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Selecting Device OptionsSelecting Device Options


Device mapping options

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Constraint File and Output Files SelectionConstraint File and Output Files Selection

Compiler and Mapper Options

Global frequency

Result format

Simulation files and constraint files

Implementation name


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Synthesizing the Design Synthesizing the Design

The famous

Run button!


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Viewing the Log FileViewing the Log File

» Detailed text file records the steps taken during synthesis


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Log File Contents Log File Contents

» Several sectionsuCompiler reportuMapper report uTiming reportuResource usage report

»Warnings and errors can be crossprobed to the HDL codeuErrors indicated by @EuWarnings indicated by @WuNotes indicated by @N


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» System and Software InformationuCompiler version and build dateuDate and time of run

» Project Informationu Source files compiledu Top-level module

» Design InformationuHDL syntax check

and synthesis checkuWarnings on unused inputsuRemoval of redundant logic u Latch inference warningsu FSM extraction and original encodingu Inferred RAMs/ROMsu Black box instantiations

Compiler ReportCompiler Report


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» System and Software InformationuMapper version and build dateuTarget technology

» Constraint InformationuConstraint files readuAttributes assigned

» Design InformationuFlattening of the designuExtraction of countersuFSM implementationuExplicit and inferred clock netsuBuffered netsuReplication of logicuOptimization of flip flops

Mapper ReportMapper Report


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» Four individual sectionsuPerformance Summary» Required and estimated clock frequencies for each of the clocks

in the designuClock Relationships» Lists all combinations of rise and fall times

uInterface Information» Required and estimated arrival times for all the top-level ports» Bidirectional ports appear as input and output

uDetailed Timing Report for each clock domain» Critical paths information

Timing ReportTiming Report


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Performance SummaryPerformance Summary

» Table for requested and estimated period/frequency uSlack: for the most critical path for that clock domainuRising and falling edge clocks reported as one clock

domainuSystem clock: delay for combinatorial path


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Clock RelationshipsClock Relationships

» Lists the rise-to-rise, fall-to-fall, rise-to-fall, fall-to-rise times

» Paths across clock domains belonging to the same clock group have a different Starting Clock and Ending ClockuPaths across clock domains from different groups are

considered false paths


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Interface InformationInterface Information

» Timing table for all primary input/output ports»What’s reported?uReference ClockuUser ConstraintuSlack = Required Time - Arrival Time


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Timing Reported for Input Ports Timing Reported for Input Ports

» Arrival Time equal tou“define_input_delay”timing constraint value

u“0”if no timing constraint defined for this input

» Input Port Required Time derived fromureference clock period

upath delay (intrinsic + routing)

ureceiving register setup time

udefine_reg_input_delay timing constraint

udefine_multicycle_path timing constraint

Required time = “clock period”- (“path delay”+ “setup_time (receiving flop)”+ “define_reg_input_delay value”)


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Timing Reported for Output PortsTiming Reported for Output Ports

» Arrival Time derived fromupath delay from the clock input of a sequential element

to the output port

udefine_reg_output_delay timing constraint when using the “-route”option

uCombinatorial paths propagation delay calculated from the driving input port

Arrival time = “path delay”+ “define_reg_output_delay value”

»Output Port Required Time derived fromureference clock period

u“define_output_delay”timing constraint valueRequired time = “clock period”- “define_output_delay value”


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Detailed Timing Report Per Clock DomainDetailed Timing Report Per Clock Domain

» Timing table for starting point(s) and end point(s) for the worst critical path(s)uReports the 10 most critical start/end points for paths

with the worst case “slack - delta delay”uDisplays slack, arrival time or required time for each

instance

» Detailed path report the most critical pathsuOne critical path table if the clock has positive slackuTen critical paths table if the clock has negative slackuDisplays delta delay and arrival time for each instance

Arrival time = “clock delay at the source”+ “propagation delay”Delta delay = “intrinsic delay”+ “routing delay”+ “correction for

instance fanout”


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Detailed Timing Report ExampleDetailed Timing Report Example


Timing table for starting points and end points for the worst critical paths

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Detailed Timing Report Example (cont’d)Detailed Timing Report Example (cont’d)

Detailed breakdownof one of the worst paths


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Resource Usage ReportResource Usage Report

» Number of inputs/outputs

» Number of lookup tables

» Number of registers packed in I/Os or not

»Other technology-specific resources such asuRAMs and ROMsuCarry chainsuCounters

» Part and package used

» Percentage utilization


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Log Watch WindowLog Watch Window

» Displays different parameters of the log file in tabular formuRequested Clock Frequency and PerioduEstimated Clock Frequency and PerioduDevice selected

» Can show results for multiple implementations

» Select View -> Log Watch Window from Project window


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Tcl WindowTcl Window

» Displays project management commands

» Displays status of synthesis run

»Messages from a run classified under the Error, Warning, Note tabs

» Crossprobing to HDL source file allowed from all three tabs

» Select View -> Tcl Window in the Project window


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HDL Analyst toolHDL Analyst tool

»Graphical representation of the design

»Machine-generated

» Cannot be edited

uRTL view» Technology-independent schematic of the design

uTechnology view» Technology-dependent schematic of the design » View of the critical path with timing and slack information


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RTL ViewRTL View

»What is it?uGraphical representation of the HDL source codeuEverything shown before any technology specific

optimization

» BenefitsuAllows users to see exactly what was written» Novice designers can make sure that what they have written is

what they want» Expert designers can look for ways to improve their code

uRTL code is kept at a high level of abstraction to make it easier to read.


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RTL View Window RTL View Window

Hierarchy Browser Hierarchical schematic View

Bring up RTL View


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Technology ViewTechnology View

»What is it?uGraphical representation of the optimized and mapped

designuContains the exact components that make up the target

architecture (RAMs, ROMs, LUTs, LABs … .)uDisplays the function mapped inside each LUT

» BenefitsuAllows users to see exactly how their design was

implementeduCritical paths can be looked at directly and can suggest

ways of improving delay


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Technology View Window Technology View Window

Technology-specific schematic

Technology-specific components

Bring up Technology View


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Crossprobing in the HDL Analyst ToolCrossprobing in the HDL Analyst Tool

Language Sensitive EditorDescribe the design

functionality

Unique RTL ViewAnalyze a technology-independent schematic

Technology ViewView post mapped schematic

with annotated timing

Bidirectional crossprobing between all three views


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Critical Path in Technology ViewCritical Path in Technology View

Show Critical Path

Technology View


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Lab1Lab1

» Complete all the steps in Lab1


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Compiler Synthesis OptimizationCompiler Synthesis Optimization

Compiler Synthesis Optimization


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» B.E.S.T. algorithms in Synplify Pro tool have the following components:uConservation of abstractionu Integrated module generation and mapping u Automatic hierarchy optimization

» Benefits of B.E.S.T. algorithmsu Infers high level structures and keeps them

abstract for as long in the synthesis process as possible

u Allows for the use later in the mapper of technology specific resources to implement these structures

u Linear Compilation run times

B.E.S.T Algorithm In the Compiler


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Supported Verilog95 ConstructsSupported Verilog95 Constructs

» All operators (+, -, *, /, %, <, >, <=, >=, ==, !=, ===, !==, &&, ||, !, ~, &, ~&, |, ~|, ^~, ~^,

^, <<, >>, ?:, {}, {{}}) [Note: / and % supported for compile-time constants and constant powers of 2]

» Behavioral statements if-else-if, case, casex, casez, for, repeat, while, forever,

begin, end, fork, join

» Procedural assignments =, <= [Note: '<=' cannot be mixed with '=' for the same register]

» Compiler directives `define, ìfdef, èlse, èndif, ìnclude


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Supported Verilog2001 ConstructsSupported Verilog2001 Constructs

» Additional constructs on top of Verilog95 support» ANSI C style module declarationsuCombining both port and data type declarations in the port

list of modules, functions and tasks» Sensitivity listuCan combine comma and “or”to separate signalsuCan use @* or @(*) to include all signals in procedural block

» Signed arithmeticureg and net data types can be declared using the reserved

keyword signeduSigned operations can be performed for any vector length uInteger literals can also be specified using ‘sradix or

size’s<radix>Compiler Synthesis Optimization

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More Supported Verilog2001 ConstructsMore Supported Verilog2001 Constructs

» Explicit inline parameter declarationuAssign parameter value by name in instantiationuNo need to specify all parameter values uParameters in any order

» $signed and $unsigned support

» ** operator supported only for base 2

»Generate loops and conditional generate


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Verilog 2001 Support in Synplify ProVerilog 2001 Support in Synplify Pro

» Switch in Implementation OptionsuON by default for new projectsuCan be implemented in the project file as

set_option –lang_std v2001|v95


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» Parameter override using # and defparam(down one level of hierarchy only)

Parameter Override in VerilogParameter Override in Verilog

Using “#”to override parameter

Using “defparam”to override parameter

module sqrtb(z,a); parameter asize=4; output [(asize-1):0] z; input [(asize-1):0] a; … endmodule

module sqrterr(e, a); output [7:0] e; input [7:0] a; … sqrtb #(8) sq1(.z(e), .a(a));

module sqrterr(e, a); output [7:0] e; input [7:0] a; … sqrtb sq1(.z(e), .a(a)); defparam sq1.asize = 8;


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Supported VHDL StandardsSupported VHDL Standards

» Synplify Pro software supports asynthesizable subset of VHDL’93 (IEEE 1076), and the following IEEE library packages:ustd_logic_1164 unumeric_std ustd_logic_unsigned ustd_logic_signed ustd_logic_arith

Note : The VHDL compiler follows the VHDL’93 coding style, this should be remembered especially during post-synthesis simulations.


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Supported VHDL Language ConstructsSupported VHDL Language Constructs

» Inputs, outputs and inouts of the following typesustd_logic, std_logic_vector, integer, positive, signed,

unsigned, records, arrays & user-defined types» All operatorsuLogical

AND, NAND, OR, NOR, XOR, XNOR

uArithmetic +, -,*, **, /, rem, mod

uRelational >, <, =, >=, /=, <=

uShift Operators Shift_Left, Shift_right, Rotate_Left, Rotate_right,SHL, SHR, SHL, SHR

» Behavioral statementsif-else-if, case, if-generate, for-loop, for-generate, when

» Assignments<=[for signals], :=[for variables]


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GenericsGenerics

»Generics are supported

entity sqrtb is generic (asize : integer := 4); port( z : out bit_vector(asize-1 downto 0); a : in bit_vector(asize-1 downto 0)); end sqrtb;

architecture arch1 of sqrtb … end arch1;

entity sqrterr is port( e : out bit_vector(7 downto 0); a : in bit_vector(7 downto 0)); end sqrterr;

architecture arch2 of srterr is begin sq1 : sqrtb generic map (asize => 8) port map( z => e, a => a); … end arch2;


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Mixed Verilog/VHDLMixed Verilog/VHDL

» Mixed HDL design supportuCan add both Verilog and VHDL files to project

» The top module/entity name has to be specified in the Implementation optionsu If a Verilog file instantiates a VHDL design, the Verilog language

rules applyu Similarly if a VHDL file instantiates a Verilog design, the VHDL

language rules apply

» Current limitationsuGenerics or parameters cannot be passed across language

boundariesu VHDL user-defined types for ports cannot be used across

language boundaries


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Mixed HDL DesignsMixed HDL Designs


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Flip Flops with Asynchronous ResetFlip Flops with Asynchronous Reset

always @(posedge clk orposedge reset)

begin if (reset == 1’b1) q = 1’b0; else if (enable == 1’b1) q = data; end

•Always probe synchronous signals inside rising edge/falling clock edge condition check.

•Do not list the enable condition in the eventexpression of the always block, because it shouldnot trigger the always block to execute uponchanging.

RTL View


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Flip Flops with Synchronous ResetFlip Flops with Synchronous Reset

always @(posedge clk) begin if (reset == 1’b1) q = 1’b0; else if (enable == 1’b1) q = data; end

•Always probe synchronous signals inside rising edge/falling clock edge condition check.

•Do not list the enable condition in the eventexpression of the always block, because it shouldnot trigger the always block to execute uponchanging.

•Do not include the reset signal in the event expression for a synchronous reset flip-flop.

RTL View


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Single Port RAMSingle Port RAM

reg [7:0] mem[0:127];always @(posedge clk)if (we)

mem[addr] <= din;

assign dout = mem[addr];

•The write process has to be synchronous for the RAM to be inferred by the compiler.

•The read process can either be synchronous orasynchronous.

•Resets on the memory are not yet supported.•The address must be at least 2 bits wide for the compiler

to infer a RAM.

RTL View


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Dual Port RAMDual Port RAM

reg [7:0] mem[0:127];reg [6:0] raddr_reg;always @(posedge clk)beginraddr_reg <= raddr;if (we)

mem[waddr] <= din;endassign dout = mem[raddr_reg];

•The write process has to be synchronous for the RAM to be inferred by the compiler.

•The read process can either be synchronous orasynchronous.

•Resets on the memory are not yet supported.•The address must be at least 2 bits wide for the compiler

to infer a RAM.

RTL View


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ROMROM

module rom(z, a);output [3:0] z;input [4:0] a;reg [3:0] z;

always @(a) begincase (a[4:1])4'b0000: z = 4'b1000;4'b0001: z = 4'b0101;4'b0010: z = 4'b0011;4'b0011: z = 4'b1010;4'b0111: z = 4'b1000;4'b1000: z = 4'b0101;4'b1001: z = 4'b0011;4'b1011: z = 4'b1010;4'b1100: z = 4'b1000;4'b1101: z = 4'b0101;4'b1110: z = 4'b0011;4'b1111: z = 4'b1010;default: z = 4'bx;

endcaseend

endmodule

ROM Table View

•The ROM must be at least half full for it to beinferred.

•The address must be at least 2 bits wide for thecompiler to infer a ROM

RTL View


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Guidelines for Finite State MachinesGuidelines for Finite State Machines

» Separate always block / process for sequential and combinatorial portionsu Easier to read - obvious what is being registereduBetter control over type of register element used

(synchronous or asynchronous reset)

» Represent states by defined labels/enumerated typesu Easier to read - less prone to errors during coding

» Assign default values to outputs derived from the FSM before the case statementu Easier to read - less clutter from rarely assigned signalsuAvoids unwanted latches

» Assign state to ‘X’in the default clause of the case statementuAvoids mismatches between simulation of pre and

post synthesis versions


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FSM ExampleFSM Example

idle : if (enable) beginstate0 <= 1'b1;data_out <= data_in[0];next_state <= read;

endelse begin

next_state <= idle;end

read : if (enable) beginstate1 <= 1'b1;data_out <= data_in[1];next_state <= write;

endelse begin

next_state <= read;end

write : if (enable) beginstate2 <= 1'b1;data_out <= data_in[2];next_state <= idle;

endelse begin

next_state <= write;end

default : next_state <= deflt;endcase

endendmodule

module FSM1 (clk, rst, enable, data_in, data_out, state0, state1, state2);

input clk, rst, enable;input [2:0] data_in;output data_out, state0, state1, state2;

parameter deflt=2'bxx;parameter idle=2'b00;parameter read=2'b01;parameter write=2'b10;

reg data_out, state0, state1, state2;reg [1:0] state, next_state;

always @(posedge clk or negedge rst)if (!rst) state <= idle;else state <= next_state;

always @(state or enable or data_in) beginstate0 <= 1'b0;state1 <= 1'b0;state2 <= 1'b0;data_out <= 1'b0;

case (state)

Defined labels for states

Always block with sequential portion

Default values for outputs of FSM

Always block with combinatorial portion

Assign ‘X’to state in “default”case


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FSM RepresentationFSM Representation

RTL View

FSM Viewer

Transition Table


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Symbolic FSM CompilerSymbolic FSM Compiler

»Option set in the Project windowuSaved in the project

file for each implementation

» Allows compilerto recognize, extract and optimize state machines, including: uReachability analysisuTransition logic minimization

» Picks the best encoding for the state machine based on the number of states


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Syn_state_machine DirectiveSyn_state_machine Directive

» Equivalent to Symbolic FSM Compiler Project option

» Enables Symbolic FSM Compiler optimization on an individual basisuApplies to state register declarations

» Example:u Verilog

module prep3(CLK, RST, IN, OUT);input CLK, RST;input [7:0] IN;output [7:0] OUT;reg [7:0] OUT;reg [7:0] current_state /* synthesis syn_state_machine=1 */;

u VHDLsignal current_state : std_logic_vector(7 downto 0);attribute syn_state_machine : boolean;attribute syn_state_machine of current_state : signal is true;


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Syn_encoding DirectiveSyn_encoding Directive

» Encoding automatically picked by Symbolic FSM Compileru1-4 states: sequential, 5-24 states: onehot, > 24 states: gray

» Syn_encoding directiveuOver-rides default encodinguApplies to state register declarationsuLegal values: sequential, onehot, gray, safe

» Example:u Verilogreg [7:0] current_state /* synthesis syn_encoding = “sequential” */;u VHDLsignal current_state : std_logic_vector(7 downto 0);attribute syn_encoding : string;attribute syn_encoding of current_state : signal is “sequential”;


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Resource Sharing OptionResource Sharing Option

» Option set in the Project windowu Saved in the project file

for each implementation

» Allows compiler to share arithmetic operators over mutually exclusive statementsu For example, branches of a case statementuOften used for adders, subtractors, incrementors

» Reduces area of design


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Resource Sharing ExampleResource Sharing Example

module res_share (a, b, c, d, e, f, c1, c2, y);input [7:0] a, b, c, d, e, f;input [3:0] c1, c2;output [7:0] y;reg [7:0] y;

always@(a or b or c or d or e or f or c1 or c2)beginif (c1==3'b001)y = a + b;

else if (c2==3'b010)y = c + d;

elsey = e + f;

endendmodule

Resource sharing ON

Resource sharing OFF

More Adders used with Resource Sharing OFF

Adders shared with Resource Sharing ON


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Syn_sharing DirectiveSyn_sharing Directive

» Equivalent to Resource Sharing Project option» Enables Resource Sharing on a global or

individual basisuApplies to module/architecture declarations

» Example:u Verilogmodule alu(out, opcode, a, b) /* synthesis syn_sharing = "off" */;

u VHDLarchitecture rtl of top isattribute syn_sharing : string;attribute syn_sharing of rtl : architecture is “off”;


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89

Parallel_case DirectiveParallel_case Directive

» Forces a parallel multiplexed structure rather than a priority-encoded structure

» Verilog only

» Example:With parallel_casedirective

always @(select or a or b or c or d)begincasez (select) /* synthesis parallel_case */

4'b???1: out = a;4'b??1?: out = b;4'b?1??: out = c;4'b1???: out = d;default: out = 'bx;

endcaseend

Without parallel_casedirective


90

Full_case DirectiveFull_case Directive

» Used with a case, casex, or casez statement

» Indicates that all possible values have been defined, and that no additional hardware is needed to preserve signal values.

» Verilog only

» Example:

always @(select or a or b or c or d)begincasez (select) /* synthesis full_case */

2'b00: out = a;2'b01: out = b;2'b10: out = c;

endcaseend

With full_casedirective

Without full_casedirective, latch generated


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91

Without translate_on/translate_offstatements

Translate_on/off DirectiveTranslate_on/off Directive

» Portion of HDL code between translate_off and translate_on ignored by compileruUsed to skip simulation-specific or behavioral codeuEvery translate_off should be followed by a translate_on

statementuCannot be nested

» Example:

module ckt(s1, s2, a, b);

output s1, s2; input a, b;

assign s1 = a & b;

/* synthesis translate_off */

assign s2 = a | b;

/* synthesis translate_on */

endmodule Compiler ignores statements between translate_on and translate_off; s2 is unassigned.


92

Syn_black_box DirectiveSyn_black_box Directive

» Used to define a module or component as a black boxuOnly the interface is specified, the behavior is ignored

» syn_black_box used to instantiateuVendor primitives and macros (including I/Os)uUser-designed macros whose functionality was defined

in a schematic editor, or another input source

» Example:u Verilog

module OBUF(O, I) /* synthesis syn_black_box */;u VHDL

component OBUFport( O : out std_logic;

I : in std_logic);end component;attribute syn_black_box : boolean;attribute syn_black_box of OBUF : component is true;


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Syn_keep DirectiveSyn_keep Directive

»Maintains a net throughout synthesisuDuring synthesis, nets may not be maintained in order to

create an optimized circuit

» Applied to wires in Verilog and signals in VHDL

» Nets can be preserved touProbe their value during simulationuPrevent certain optimizations, such as clock enable

optimization

» Exampleu VHDLsignal q_tmp : std_logic;attribute syn_keep : boolean;attribute syn_keep of q_tmp : signal is true;


94

Syn_keep ExampleSyn_keep Example

Clock enable signal

module clken(d, en1, en2, clk, rst, q);input d;input clk, rst, en1, en2;output q;

reg q;

wire q_tmp /* synthesis syn_keep = 1 */;assign q_tmp= en2 ? d : q;always @(posedge clk or posedge rst)if (rst)q <= 0;

else if(en1)q <= q_tmp;

endmodule

Without syn_keep, compiler optimizes en1&en2 as the clock enable

Use syn_keep to specify en1 as clock enable


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95




96

Asynchronous LoadsAsynchronous Loads

Synplify Pro Warning:Register q with async load is being synthesized in compatibility mode. A synthesis/simulation mismatch is possible.

always @(posedge clk or posedge load )

beginif (load)

q = d0;else

q = d;

end


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97

Asynchronous LoadsAsynchronous Loads

wire tmp_set = load & d0; wire tmp_rst = load & ~d0;

always @(posedge clk or posedge tmp_rst or posedge tmp_set ) begin if (tmp_rst) q = 0; else if (tmp_set) q = 1; else q = d;

end


» To avoid simulation mismatches, change the RTL code as shown below

98

Latch generation Latch generation


module newmux (out1, a, b, c, sel);input a, b, c;output out1;input[1:0] sel;reg out1;

always@(a or b or c or sel)beginif (sel ==2'b10)out1 = a;

else if (sel == 2'b01)out1 = b;

else if (sel == 2'b11)out1 = c;

endendmodule

Synplify Pro Warning:Latch generated from always block for signal out1, probably caused by a missing assignment in if or case statement.

Latch generated because of missing ifcondition, select = 2’b00

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99

Latch Generation (cont’d)Latch Generation (cont’d)

» Latches can be avoided by:u Always using a default clause in a case statementuUsing a Verilog full_case directiveu Always using the else clause in an if-then-else statement

» If latches are required, then use assign statementsuNo warning issued by the Synplify Pro compiler

module latch1(q, data, clk);output q;input data, clk;

assign q = clk ? data : q;

endmodule


100

module top (q, d, s0, s1, s2, s3, clk, reset, en1);input en1, clk, reset, s0, s1, s2, s3;input [31:0] d;output q;wire[7:0] t1;assign t1 = (en1) ? d[31:24] : 8'bz;reg [7:0] q1, q1_tmp;wire q = q1;always @( d or s0 or s1 or s2 or s3 or t1)begin : proc_q1_tmpcasex({s0,s1,s2,s3})

4'b1xxx: q1_tmp <= d[7:0];4'bx1xx: q1_tmp <= d[15:8];4'bxx1x: q1_tmp <= d[23:16];4'bxxx1: q1_tmp <= t1;default: q1_tmp <= 8'b0;

endcase;endalways @( posedge clk or posedge reset)begin : proc_q1

if (reset) q1 <= 'b0;else q1 <= q1_tmp;

endendmodule

Priority Encoding versus Parallel CasePriority Encoding versus Parallel Case


» This is equivalent to the implicit priority of an if-then-elseconstructuHere b gets e only when

d=1’b1 and a != 1’b1

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101

Priority Encoding versus Parallel Case (cont’d)Priority Encoding versus Parallel Case (cont’d)

module top (q, d, s0, s1, s2, s3, clk, reset, en1);input en1, clk, reset, s0, s1, s2, s3;input [31:0] d;output q;wire[7:0] t1;assign t1 = (en1) ? d[31:24] : 8'bz;reg [7:0] q1, q1_tmp;wire q = q1;always @( d or s0 or s1 or s2 or s3 or t1)begin : proc_q1_tmpcasex({s0,s1,s2,s3}) /* synthesis parallel_case */

4'b1xxx: q1_tmp <= d[7:0];4'bx1xx: q1_tmp <= d[15:8];4'bxx1x: q1_tmp <= d[23:16];4'bxxx1: q1_tmp <= t1;default: q1_tmp <= 8'b0;

endcase;endalways @( posedge clk or posedge reset)begin : proc_q1

if (reset) q1 <= 'b0;else q1 <= q1_tmp;

endendmodule


» Same example, with inputs a and d mutually exclusive

» Use a case statement with the parallel_case directive

102

Synplify Pro Warning:Incomplete sensitivity list - assuming completenessReferenced variable B is not in sensitivity list

Incomplete sensitivity listIncomplete sensitivity list

module nand2(A,B,Y2);input A,B;output Y2;reg Y2;

always @(A or B)begin

Y2 = !(A & B);end

endmodule

module nand2(A,B,Y1);input A,B;output Y1;reg Y1;

always @(A)begin

Y1 = !(A & B);end

endmodule

Dynamic Truth Table

A B Y1 Y2

0 0 1 1 1 1 0 0 1 0 0 1 0 1 1 1

A

BY


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103

Asynchronous State MachinesAsynchronous State Machines

» They have states, and combinatorial loops

» They do not have a clearly defined clock

» Do not use synthesis tools to design asynchronous state machinesuThe synthesis tool might remove hazard-suppressing logic

» The compiler detects combinational loops in continuous assignment statements, always blocks, and built-in gate-primitive logic


Synplify Pro Warning:Found combinatorial loop

104

Asynchronous State Machine ExampleAsynchronous State Machine Example

module async1 (out, g, d);output out;input g, d;

assign out = g & d | !g & out | d & out;endmodule____________________

module async2 (out, g, d);output out;input g, d;reg out;

always @(g or d or out)begin

out = g & d | !g & out | d & out;endendmodule


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105

Unused InputsUnused Inputs

» Inputs driving logic that do not drive outputs directly or indirectly are flagged as unused

module dff(q1, data1, data2, clk);output q1;input data1, data2, clk;reg q1, q2;

always @(posedge clk)begin

q1 = data1;endalways @(posedge clk)begin

q2 = data2;endendmodule


Synplify Pro Warning:@W:”c:\design\dff.v":4:13:4:17|Input data2 is unused

uData2 does not have a path to a primary output

106

Removal of Redundant LogicRemoval of Redundant Logic

» Compiler removes redundant logic by defaultusaves area

module dff(q1, q2, q3, q4, data1, clk);output q1, q2, q3, q4;input data1, clk;reg q1, q2, q3, q4;

always @(posedge clk)begin

q1 = data1;q2 = data1;q3 = data1;q4 = data1;

end

endmodule


Synplify Pro Warning:Removing sequential element q4

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107

Lab2Lab2

» Complete all the steps in Lab2


108

SCOPE EditorSCOPE Editor

The SCOPE Editor

» SCOPE Editor» Mapper Synthesis

OptimizationuHow the Mapper Worksu Timing Constraint EffectuMapper Attributes

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SCOPE EditorSCOPE Editor

» Synthesis Constraints OPtimization EnvironmentuGraphical, spread-sheet format uConstraints and attributes classified under eight tabs

»Written out to SDC fileuTCL format

» SDC file only used by mapperuConstraints entered in SCOPE do not influence compilation

stage

»Multiple SDC files can be used in the implementationuLast one read takes precedence in case of

conflict between constraints

The SCOPE Editor

110

Main SCOPE FeaturesMain SCOPE Features

» Automatic initialization of clocks, inputs and outputs

» Auto-fill capability to help filling constraints and attributes

» Drag and drop objects from the HDL Analyst tool

» Filters out legal objects based on the constraint or attribute applied

» Filters attributes and constraints based on the object selected

» Limits attribute list to what is applicable for the selected technology

The SCOPE Editor

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111

Creating a New Constraint FileCreating a New Constraint File

The SCOPE Editor

112

Objects and Auto Fill CapabilityObjects and Auto Fill Capability

Objects filled in automatically Legal Values

Selected Tab

The SCOPE Editor

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113

Clock Frequency Clock Frequency

Clock Period

The SCOPE Editor

uIf the equation Tco + Tcomb + Tsu < clock period is valid, data transfers from register to register.

uThe Tcomb value guides the mapper to synthesize the combinational logic and reduce the levels of logic between the registers.

114

» define_clock has the following options u -disable : to disable the clock frequency definition u -freq : to specify the frequency in MHz u -period : to specify the time period in ns u -clockgroup : to specify which clocks are related to each otheru -rise/fall : to specify the length of the active portion of the clock cycleu -route : to specify an additional delay to paths in a particular clock

domainu -virtual : to constrain off chip paths by specifying the off chip clock

Clocks TabClocks Tab

The SCOPE Editor

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115

Input and Output DelayInput and Output Delay

uIf Tindelay or Toutdelay= 0, it means that a fictitious register exists at the input or output port

Input Delay Output Delay

ChipChip

The SCOPE Editor

116

Inputs/Outputs TabInputs/Outputs Tab

The SCOPE Editor

» <input default> and <output default>u define global input and output delays

» Clock Edgeu rising or falling edge that triggers the event

» Value is required if Route column isn’t used» Routeu use to increase the effective path delay without

affecting the I/O delay forward-annotated to the place and route tool

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Registers TabRegisters Tab

» Constraint reserved for advanced users

» Use to speed up paths from or to a register by including extra routing delay

The SCOPE Editor

118

Multicycle and False PathsMulticycle and False Paths

» Any combination of from, to and throughpoints is allowed

» From/To points can be registers or top-level ports

» Through points are combinatorial nets

»Multicycle paths use a number of allowed clock cycles, false paths don’t

The SCOPE Editor

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u Target technology limits list to application attributesuObject selection filters the Attributes pull-down menu to legal

attributes onlyu Attribute selection filters the Objects pull-down menu to legal

objects onlyu Value column lists legal values for an attributeu Enabled column used to select or deselect attributes uComment column

Attributes TabAttributes Tab

Attributes pull-down MenuObjects pull-down Menu

The SCOPE Editor

120

» Synplify Pro tool allows dragging and dropping of objects from the HDL Analyst tool to the SCOPE interface

» SCOPE editor also uses specific abbreviation in order to distinguish same names for different objectsuv: module or viewun: netup : portui: instanceub: bit slice

More about the SCOPE EditorMore about the SCOPE Editor

The SCOPE Editor

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121

Mapper Synthesis OptimizationMapper Synthesis Optimization

Mapper Synthesis Optimization



122

How the Mapper WorksHow the Mapper Works

» Inputs to the MapperuTechnology independent netlist [.srs] created by the

compileruTarget technology specified in the project fileuTiming constraints and attributes specified in the

constraints file [.sdc]

»GoaluTo fit the design into the smallest programmable device

AND to operate the device at the fastest frequency

» Uses the following componentsuB.E.S.T algorithmsuHierarchy optimizationuTechnology independent optimizationuDirect mapping to technology primitivesuCritical path resynthesis


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B.E.S.T AlgorithmsB.E.S.T Algorithms

» Integrated Module Generation & Mapping uMaintains inferred components at an abstract level uAutomatically combines these extracted components

with associated logic

» BenefituTakes maximum advantage of the resources available

in the target technology

Adder Module Control Logic

Synplify Pro’s IntegratedModule Generation

Logic Block

Data path & Control Integrated into one

logic block


124

Module Generation ExampleModule Generation Example

carryF

Gclb

carryF

Gclb

z[3]

z[2]

z[1]

z[0]

condb[3]a[3]

a[2]b[2]cond

condb[1]a[1]

a[0]b[0]cond

The Traditional ApproachSynplify Pro Tool’s Integrated

Module Generation

F

Gcarry

F

Gclb

F

Gcarry

F

Gclb

b[3:0]

a[3]

a[2]

a[1]

a[0]

cond

z[3]

z[2]

z[1]

z[0]

F

G

if (cond) z = a+1;else z = b;


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Hierarchy Optimization Hierarchy Optimization

» Mapper starts with the original hierarchy

» Performs global analysis and optimizes hierarchy by creating new structures, if needed

» Rebuilds hierarchy by keeping existing boundaries or creating new ones

» Provides timing budget for each hierarchical block

» Converges on the timing goal by making an area/time tradeoff


126

Hierarchy Optimization ExampleHierarchy Optimization Example

module and2_x(a, b, c);input a, b;output c;assign c = a & b;endmodule

module top(a0, a1, b, c);input a0, a1, b;output c;and2_x an1(a0, a1, an1_out);and2_x an2(an1_out, b, c);endmodule

Two levels of logic generated without hierarchical boundary optimization

Logic implemented in one lookup table with hierarchical boundary optimization


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Area MinimizationArea Minimization

» Boolean equation simplification

»Mapping the abstract RTL components to gatesuConstant propagationuBuses to bits » i.e. One 8-bit reg object to 8 individual flip-flops

Mux Decomposition Constant Propagation


uMux decompositionuFSM decomposition

128

Timing OptimizationTiming Optimization

»Gate level timing modeluIntrinsic gate delayuFanout dependent» Delay = intrinsic gate delay + T[FO]

» Timing constraintsuUser-specifieduControls levels of logic between two registers


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129

Direct Mapping to Technology PrimitivesDirect Mapping to Technology Primitives

case sel iswhen “00”=> z <= a;when “01”=> z <= b;when “10”=> z <= c;when “11”=> z <= d;when others => z <=

(others => ‘X’);end case;

o

ab

sel[0]sel[1]

LUT

cd

sel[0]sel[1]

LUT z

cascade

Altera Flex 10K

ab

sel[0]

sel[1]

cd

sel[0]

z

PFUMUX

Lattice ORCA

o

ooo

oo

o

o

z

sel[1]

sel[0]

a

b

c

d

QuickLogic

ab

sel[0]

cd

sel[0]

z

F

G

H

Xilinx XC4000

CLB

a

b

c

d

z

sel[0]

sel[1] Actel

sel[1]


130

Mapping to Special ComponentsMapping to Special Components

» XilinxuMUXF5/F6/F7/F8, Shift Register LUT, RAMs, ROMs,

Carry Chains, Block Mults

» AlterauLogic Element with Cascade, Quick-feedback counter,

MAC block, EABs and ESBs

» ActeluCM8

» Lattice ORCAuRAM, Counters, PFU Muxes


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MUX8x1 (Xilinx Virtex)MUX8x1 (Xilinx Virtex)

module mux8x1(din, sel, dout);input [7:0] din;input [2:0] sel;output dout;

assign dout = din[sel];

endmodule

Slice A

Slice B

Slice View in Virtex


132

Shift Register LUT (Xilinx Virtex)Shift Register LUT (Xilinx Virtex)

module srltest(z1, z2, a, en, clk);output z1, z2;input a;input clk, en;

reg [10:0] dataa, datab;always @(posedge clk)

dataa = {dataa[9:0], a};

always @(posedge clk)if (en) datab = {datab{9:0], a};

assign z1 = dataa[10];assign z2 = datab[10];

endmodule


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Logic Element with Cascade (Altera APEX)Logic Element with Cascade (Altera APEX)

module cascade_ex(din, dout);output dout;input [7:0] din;

reg dout;

assign dout = &din;

endmodule


134

Quick Feedback Counter (Altera APEX)Quick Feedback Counter (Altera APEX)

module cntr(clk, q, aclr);output [3:0] q;input clk, aclr;

reg [3:0] q;

always @(posedge clk or posedge aclr)

if (aclr)q <= 0;

elseq <= q + 1;

endmodule


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135

CM8 (Actel)CM8 (Actel)

module module_d(a, b, sum, clk, rst);output [7:0] sum;input clk, rst;input [7:0] a, b;

reg [7:0] sum;reg [7:0] a_int, b_int;

always @(posedge clk or posedge rst)if (rst) begin

a_int <= 0;b_int <= 0;sum <= 0;

endelse begin

a_int <= a;b_int <= b;sum <= a_int + b_int;

end

endmodule


136

RAM (Lattice ORCA)RAM (Lattice ORCA)

module ramtest(address, data_in, data_out,clk, we);

output [0:0] data_out;input clk, we;input [0:0] data_in;input [2:0] address;

reg [0:0] data[0:7];reg [7:0] a_int, b_int;

always @(posedge clk) beginif (we)

data[address] <= data_in;data_out <= data[address];

end

endmodule

RAMs are also inferred for Xilinx, Altera, Quicklogic and Cypress Technologies


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137

Critical Path ResynthesisCritical Path Resynthesis

» Reconstruct critical path logicuIncremental optimization targeting new critical path

Critical Path is from register A to register C


138





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139

Types of PathsTypes of Paths

Input to Register Register to OutputRegister to Register

Input to Output


140

Timing ConstraintsTiming Constraints

» Essential for achieving the performance goal

D Q

D Q

define_output_delay

define_multicycle_pathdefine_clock

define_input_delay

Delay Big Delay

Delay Delay


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141

Effect of Frequency ConstraintEffect of Frequency Constraint


142

Effect of Multicycle Path ConstraintEffect of Multicycle Path Constraint


More logic is used

Timing report is inaccurate

Less logic is used

Timing report is more accurate

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False PathFalse Path

» False Paths are of two typesuArchitectural false paths» Designer is aware that such paths exist

uCode-introduced false paths» Identify false paths after analyzing the schematic» Use false path attributes to make Synplify Pro ignore these paths


a

d

x

x x

+ +z

b c

Is this path from a to Z possible for x = 1 ?

0

1

0

1

1

144





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AttributesAttributes

» User-defineduGeneric» syn_hier, syn_noclockbuf, syn_maxfan, syn_useioff

uTechnology-specific» Xilinx and Altera » syn_ramstyle, syn_romstyle

» Can be applied in SCOPE editor or HDL code


146

Syn_maxfan AttributeSyn_maxfan Attribute

module test(a, clk, rst, din, q);input [3:0] a;input [31:0] din;input clk, rst;output [31:0] q;

reg [31:0] q;reg en /* synthesis syn_maxfan = 10 */;

always @(posedge clk or posedge rst)begin

if (rst) beginen <= 0;q <= 0;

endelse beginen <= &a;if (en)q <= din;

endend

endmoduleWithout syn_maxfan

With syn_maxfan


uApplied on an input or registeruTakes an integer value uSpecifies maximum fanoutuResults in replication

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147

module inc(a_in, a_out) /* synthesis syn_hier = "hard" */;input [3:0] a_in;output [3:0] a_out;assign a_out = a_in + 1;endmodule

module reg4(clk, rst, d, q) /* synthesis syn_hier = "hard" */;input [3:0] d;input clk, rst;output [3:0] q;reg [3:0] q;always @(posedge clk or posedge rst)

if(rst)q <= 0;

elseq <= d;

endmodule

module top(clk, rst, q);input clk, rst;output [3:0] q;wire [3:0] a_in;inc i1(q, a_in);reg4 r1(clk, rst, a_in, q);endmodule

Syn_hier AttributeSyn_hier Attribute

With syn_hier = “hard”

Automatic flattening, counter inferred


uApplied on modules/architecturesuTakes a string value uMaintain boundary of a module by using syn_hier = “hard”

148

Syn_noclockbuf AttributeSyn_noclockbuf Attribute

uUsed on ports or entire modulesuTakes a boolean valueuTurns off clock resource usage

module simpledff(clk, d, q);input [3:0] d;input clk /* synthesis syn_noclockbuf = 1 */;output [3:0] q;

reg [3:0] q;

always @(posedge clk) q <= d;

endmodule

With syn_noclockbuf Without syn_noclockbuf


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149

Syn_useioff AttributeSyn_useioff Attribute

module dff(q, d, clock, reset);input d;input clock, reset;output q /* synthesis syn_useioff = 1*/;

reg temp, q;

always @(posedge clock or posedge reset)begin

if (reset) begintmp <= 0;q <= 0;end

else begintmp <= d;q <= tmp;

endend

endmodule

uCan be applied on ports or entire modulesuTakes a boolean valueuUsed to control I/O register packing


Without syn_useioff

With syn_useioff

150

Syn_ramstyle AttributeSyn_ramstyle Attribute

module ram_test(q, addr, data, we, clk);input [1:0] d;input clk, we;Input [2:0] addr;output [1:0] q;

reg [1:0] mem[7:0] /* synthesis syn_ramstyle = “registers”*/;

always @(posedge clk)if (we)mem[addr] <= data;

assign q = mem[addr];

endmodule

With syn_ramstyle=“registers”

Without syn_ramstyle

uApplied on the RAM primitiveuTakes a string valueuDetermines the RAM implementation


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151

module romz(z,a);output [3:0] z;;input [4:0] a;reg [3:0] z /* synthesis syn_romstyle = “logic”*/;

always @(a)case (a)

5’b00000 : z = 4’b1011;5’b00001 : z = 4’b0001;5’b00100 : z = 4’b0011;5’b00110 : z = 4’b0010;5’b00111 : z = 4’b1110;5’b01001 : z = 4’b0111;5’b01010 : z = 4’b0101;5’b01101 : z = 4’b0100;5’b10000 : z = 4’b1100;5’b10001 : z = 4’b1101;5’b10010 : z = 4’b1111;5’b10011 : z = 4’b1110;5’b11000 : z = 4’b1010;5’b11010 : z = 4’b1011;5’b11110 : z = 4’b1001;5’b11111 : z = 4’b1000;default : z = 4’b0000;endcaseendendmodule

Syn_romstyle AttributeSyn_romstyle Attribute

With syn_romstyle = “block_rom”

With syn_romstyle = “logic”


152

Guidelines for Attribute UsageGuidelines for Attribute Usage

» Attributes can guide the mapper to the optimal synthesis result

» Attributes are application-specificui.e. syn_ramstyle/romstyle can be tailored to meet

design needs

»GuidelinesuLet the mapper decide how to synthesize the designuAnalyze the synthesis result in the technology

schematicuUse the appropriate attribute to guide and control the

mapper


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153

Debugging with HDL Analyst toolDebugging with HDL Analyst tool

Debugging with the HDL Analyst tool

» Debugging with the HDL Analyst tool

» Batch Mode

154

HDL Analyst Advanced FeaturesHDL Analyst Advanced Features

» Hierarchical and Flattened Views » Advanced Filtering

» Crossprobing from Place and Route timing files

» FSM Viewer


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155

Hierarchical and Flattened ViewsHierarchical and Flattened Views

» Views are hierarchical by default

» RTL View can be flattened to generic logic cells

» Technology View can be flattened to technology primitive or boolean logic level

» Selective flattening achieved using Dissolve Instances or Flatten Current Schematic

» Instances can be hidden to prevent flattening their contents


156

FilteringFiltering

» Select and filter on one specific component or a group of components as a first stepuDoes not load the entire design when subsequent

commands are executed

» Combine filtering with push/pop mode to navigate between hierarchical levelsuBetter memory usage than working on a flat schematic


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Displaying Specific PathsDisplaying Specific Paths

» Trace any cone of logicuExpand logic fanning out from pins or nets

» Trace any pathuselect one or more objects and show everything

connecting themuUseful to locate critical paths reported after Place and

RouteuTypically the start and end points are known and

components between them can be viewed in the HDL Analyst tool

» Critical pathuInstances on critical path automatically filtered in

Technology ViewuHierarchical or flattened view


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Tracing a Cone of Logic From a NetTracing a Cone of Logic From a Net

ORSelect Net Driver

User can inspect the driver of a specific net

Select Net InstancesShow everything that is

connected to the net


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Tracing a Cone of Logic From a PinTracing a Cone of Logic From a Pin


Expand Shows everything that is

connected to that pin

Select Pin

Filter the selected component THEN

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Tracing a PathTracing a Path

Expand PathsShows everything that is

between the two components

Select Two Components

Filter the selected components THEN


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Crossprobing with Place and RouteCrossprobing with Place and Route

» After place and route, fitting tools generate timing reports with critical path informationuInformation can be imported into the Synplify Pro tool to

show the post-place and route critical paths uAny text file that lists the components in a path can be

crossprobed into a HDL Analyst view

» Steps to crossprobeuOpen the RTL View uOpen the Technology ViewuOpen the Place and Route timing report file in the

Synplify Pro tooluSelect the critical pathuCrossprobe to HDL Analyst views


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Crossprobing ExampleCrossprobing Example

Place and Route timing report File with Critical

Path selected

Technology View showing the selected

critical path


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FSM ViewerFSM Viewer

» State machines shown as onehot encoding in RTL ViewuNo decoding needed, onehot is easier to interpret

» FSM Viewer invoked by pushing into State Machine primitive in RTL ViewuHas three tabs» State transition diagram» RTL encoding» Shows state machine as onehot encoding

» Mapped encoding» Shows exactly how the mapper implemented state machine» Direct link between state registers and HDL code


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FSM Viewer WindowFSM Viewer Window

RTL View with state machine primitive [onehot representation]

FSM Viewer –State Transition Diagram and Transition Table


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FSM Viewer RTL Encodings TabFSM Viewer RTL Encodings Tab

» Shows the onehot table corresponding to the RTL view


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FSM Viewer Mapped Encodings TabFSM Viewer Mapped Encodings Tab

» Shows how the state machine was finally implemented


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Putting it all togetherPutting it all together

» Test caseuHierarchical design, with two lower level modules

» Design has gone through Place and RouteuRequested frequency was 80 MHz, actual is 69 MHz

» Try crossprobing between timing report file and Technology Viewu Technology view shows many levels of logic between start and end

point of critical path

» Try crossprobing between Technology View and RTL Viewu Select the start and end point of critical path in Technology ViewuCrossprobe to RTL Viewu Expand paths between the start and end point

in the RTL View


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Tracing Place and Route Critical PathTracing Place and Route Critical Path

Tech viewStart and end points

RTL viewFilter RTL and choose

Expand Path


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Tracing a Cone of LogicTracing a Cone of Logic

RTL viewExpand the output to

see what is there


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Putting it all togetherPutting it all together

RESULTS

82 MHz!!!!


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Batch ModeBatch Mode

» Debugging with the HDL Analyst tool

» Batch Mode

Batch Mode

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Synplify Pro Batch ModeSynplify Pro Batch Mode

» Available on all platforms

» Requires a floating license

» Use project file or TCL file as input

» Design synthesized using the options set in the input file

» If there are errors, see the stdout or stdout.log.uCompilation and mapping status and errors are written to the

<design>.srr fileu return code:0 for successful process completion (including

warnings)u return code:1 for failure or error conditions

Batch Mode

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Batch Mode with a Project FileBatch Mode with a Project File

» At the command prompt:synplify_pro -batch <project_name>.prj

» A complete synthesis process including both compilation and mapping is executed

Batch Mode

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Batch Mode with a TCL ScriptBatch Mode with a TCL Script

» Run from the command prompt or from the Synplify Pro TCL window:synplify_pro -batch <TCL_script_name>.tcl

» The TCL should contain the following lines:uat the top: project -newuat the bottom:» for a complete synthesis process: project -run

exit» for compilation only: project -compile

exit

Batch Mode

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Shell Scripts Shell Scripts

» Shell scripts can be used to perform synthesis and automatically follow it with simulation or place and route

» Example running the Synplify Pro, MTI and Quartus software:

synplify_pro -batch proj2001.prjvlib synplify.vhdvcom -93 -work synplify synplify.vhdvlib workvcom -93 U1.vhmvlog tb.vvsim -c -t 100ps -do wave.do testquartus_cmd -f U1_cons.tcl

Batch Mode

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Lab3 and Lab4Lab3 and Lab4

» Complete all the steps in Lab3 and Lab4

Pro intro 72 - pudn.comread.pudn.com/downloads38/ebook/131545/FPGA Synthesis with the Synplify Pro...

Documents

Transcript of Pro intro 72 - pudn.comread.pudn.com/downloads38/ebook/131545/FPGA Synthesis with the Synplify Pro...