Principles of Adiabatic ProcessesPrinciples of Adiabatic Processes

Adiabatic Processes - overviewAdiabatic Processes - overview• Adiabatic steps in the reversible Carnot cycleAdiabatic steps in the reversible Carnot cycle• Evolution of the meaning of “adiabatic”Evolution of the meaning of “adiabatic”• Time-proportional reversibility (TPR) of quasi-Time-proportional reversibility (TPR) of quasi-

adiabatic processesadiabatic processes• Adiabatic theorem of quantum mechanicsAdiabatic theorem of quantum mechanics• Adiabatic transitions of a two-state systemAdiabatic transitions of a two-state system• Logic & memory in irreversible and adiabatic Logic & memory in irreversible and adiabatic

processes.processes.

The Carnot CycleThe Carnot Cycle

• In 1822-24, Sadi Carnot analyzed the efficiency In 1822-24, Sadi Carnot analyzed the efficiency of an ideal heat engine all of whose steps were of an ideal heat engine all of whose steps were reversiblereversible, and furthermore proved that:, and furthermore proved that:– AnyAny reversible engine (regardless of details) would reversible engine (regardless of details) would

have the have the samesame efficiency efficiency ((TTHHTTLL)/)/TTHH..– NoNo engine could have greater efficiency than a engine could have greater efficiency than a

reversible engine w/o producing work from nothingreversible engine w/o producing work from nothing – TemperatureTemperature itself could be defined on a itself could be defined on a

thermodynamic scale based on heat recoverable by a thermodynamic scale based on heat recoverable by a reversible engine operating between reversible engine operating between TTHH and and TTLL

Steps of Carnot CycleSteps of Carnot Cycle• IsothermalIsothermal expansion at expansion at TTHH

• AdiabaticAdiabatic (without flow of (without flow ofheat) expansion heat) expansion TTHHTTLL

• Isothermal compression at Isothermal compression at TTLL

• Adiabatic compression Adiabatic compression TTLLTTHH V

P

TL

TH

Reser-voir

Reser-voir

Reser-voir

Reser-voir

Iso-thermal

Adia-batic

Adia-batic

Iso-thermal

Carnot Cycle TerminologyCarnot Cycle Terminology• AdiabaticAdiabatic (Latin): literally “Without flow of heat” (Latin): literally “Without flow of heat”

– I.e.I.e., no entropy , no entropy enters or leavesenters or leaves the system the system

• IsothermalIsothermal: “At the same temperature”: “At the same temperature”– Temperature of system Temperature of system remains constantremains constant as entropy enters or leaves. as entropy enters or leaves.

• Both kinds of steps, Both kinds of steps, in the case of the Carnot cyclein the case of the Carnot cycle, are , are examples of examples of isentropicisentropic processes processes – ““at the same entropy”at the same entropy”– I.e.I.e., no (known) information is transformed into entropy in either , no (known) information is transformed into entropy in either

processprocess

• But, the usage of the word “adiabatic” in applied physics has But, the usage of the word “adiabatic” in applied physics has mutatedmutated to essentially to essentially meanmean isentropic. isentropic.

OldOld and and NewNew “Adiabatic” “Adiabatic”

• Consider a closed system where you just Consider a closed system where you just lose track of its detailed evolution:lose track of its detailed evolution:– It’s It’s adiabaticadiabatic (no (no netnet heat flow), heat flow),– But it’s not “But it’s not “adiabaticadiabatic” (not isentropic)” (not isentropic)

• Consider a box containing some heat,Consider a box containing some heat,flying ballistically out of the system:flying ballistically out of the system:– It’s not It’s not adiabaticadiabatic, (no heat flow), (no heat flow)

• because heat is “flowing” out of the systembecause heat is “flowing” out of the system– But it’s “But it’s “adiabaticadiabatic” (no entropy is generated)” (no entropy is generated)

Box o’ Heat

“The System”

Justifying the Modern UsageJustifying the Modern Usage• In an In an adiabaticadiabatic process following a desired process following a desired

trajectory through configuration space,trajectory through configuration space,– No heat flowsNo heat flows in or out of in or out of the subsystem consisting of the subsystem consisting of

those particular degrees of freedomthose particular degrees of freedom whose variation whose variation carries out the motion along the desired trajectory.carries out the motion along the desired trajectory.

• E.g.E.g., the computational degrees of freedom in a , the computational degrees of freedom in a computational process.computational process.

– No heat flow No heat flow no entropy flow no entropy flow• Heat is just energy whose configuration info. is entropyHeat is just energy whose configuration info. is entropy

– No entropy flow No entropy flow no sustained entropy generation no sustained entropy generation• Since bounded systems have a maximum entropySince bounded systems have a maximum entropy

Quasi-Adiabatic ProcessesQuasi-Adiabatic Processes• CompleteComplete adiabaticity means absolutely adiabaticity means absolutely zerozero

rate of entropy generationrate of entropy generation– Requires infinite degree of isolation of system from Requires infinite degree of isolation of system from

uncontrolled external environment!uncontrolled external environment! Impossible to Impossible to completely completely achieve in practice.achieve in practice.

• Real processes are only adiabatic to the extent Real processes are only adiabatic to the extent that their entropy generation that their entropy generation approaches approaches zero.zero.– Term “quasi-adiabatic” emphasizes imperfectionTerm “quasi-adiabatic” emphasizes imperfection

• AsymptoticallyAsymptotically adiabatic designs conceptually adiabatic designs conceptually approach 0 in the limit of variation of specified approach 0 in the limit of variation of specified technology design parameter(s)technology design parameter(s)– E.g.E.g., low device frequency, large device size, low device frequency, large device size

Quasi-Adiabatic ProcessesQuasi-Adiabatic Processes• No real process is No real process is completelycompletely adiabatic adiabatic

– Because some outside system may always have enough Because some outside system may always have enough energy to interact with & disturb your system’s energy to interact with & disturb your system’s evolution - evolution - e.g.e.g., cosmic ray, asteroid, cosmic ray, asteroid Evolution of system state is never perfectly knownEvolution of system state is never perfectly known

– Unless you know the exact quantum state of the whole universeUnless you know the exact quantum state of the whole universe– Entropy of your system always increases.Entropy of your system always increases.

• Unless it is Unless it is alreadyalready at a maximum (at equilibrium) at a maximum (at equilibrium)– Can’t really be at Can’t really be at completecomplete equilibrium with its surroundings equilibrium with its surroundings

» unless whole universe is at utterly stable “heat death” state.unless whole universe is at utterly stable “heat death” state.• Systems at equilibrium are sometimes called “Systems at equilibrium are sometimes called “staticstatic.”.”

• Non-equilibrium, quasi-adiabatic processes are Non-equilibrium, quasi-adiabatic processes are sometimes also called sometimes also called quasi-staticquasi-static– Changing, but near a local equilibrium otherwiseChanging, but near a local equilibrium otherwise

Quantifying AdiabaticityQuantifying Adiabaticity• An appropriate metric for quantifying the An appropriate metric for quantifying the degree degree

of adiabaticityof adiabaticity of any process is just to use the of any process is just to use the quality factor Qquality factor Q of that process. of that process.– QQ isn’t just for oscillatory processes any more isn’t just for oscillatory processes any more

• QQ is generally the ratio is generally the ratio EEtranstrans / / EEdissdiss between the: between the:– Energy Energy EEtranstrans involved in carrying out a process involved in carrying out a process

• transitioning between states along a trajectorytransitioning between states along a trajectory– Amount Amount EEdissdiss of energy dissipated during the process. of energy dissipated during the process.

• Normally also matches the following ratios:Normally also matches the following ratios:– Physical information content / entropy generatedPhysical information content / entropy generated– Quantum computation rate / decoherence rateQuantum computation rate / decoherence rate– Decoherence time / quantum-transition timeDecoherence time / quantum-transition time

Degree of ReversibilityDegree of Reversibility• The The degree of reversibilitydegree of reversibility (a.k.a. (a.k.a. reversibilityreversibility, ,

a.k.a. a.k.a. thermodynamic efficiencythermodynamic efficiency) of any quasi-) of any quasi-adiabatic process is defined as the ratio of:adiabatic process is defined as the ratio of:– the total free energy at the start of the processthe total free energy at the start of the process by the total energy spent in the processby the total energy spent in the process

• Or, equivalently:Or, equivalently:– the known, accessible information at the startthe known, accessible information at the start by the amount that is converted to entropyby the amount that is converted to entropy

• This same quantity is referred to as the (per-This same quantity is referred to as the (per-cycle) “quality factor” cycle) “quality factor” QQ for any resonant for any resonant element (element (e.g.e.g., , LCLC oscillator) in EE. oscillator) in EE.

)(

)0(

tE

E

spent

free

tS

K

0

The “Adiabatic Principle”The “Adiabatic Principle”• Claim: Claim: Any Any idealideal quasi-adiabatic process quasi-adiabatic process

performed over time performed over time tt has a thermodynamic has a thermodynamic efficiency that is proportional to efficiency that is proportional to tt, , – in the limit as in the limit as tt0.0.

• We call processes that realize this idealization We call processes that realize this idealization time-proportionally reversibletime-proportionally reversible (TPR) processes. (TPR) processes.

• Note that the total energy spent (Note that the total energy spent (EEspentspent), and the ), and the

total entropy generated (total entropy generated (SS), are both ), are both inverselyinversely proportional to proportional to tt in any TPR process. in any TPR process.– The slower the process, the more energy-efficient.The slower the process, the more energy-efficient.

Proving the Adiabatic PrincipleProving the Adiabatic Principle(See RevComp memo #M14)(See RevComp memo #M14)• Assume free energy is in generalized Assume free energy is in generalized kinetickinetic

energy of motion energy of motion EEkk of system through its of system through its configuration space.configuration space.

EEkk = ½ = ½mvmv22 vv22 = ( = (//tt))22 tt22 for for mm, , const. const.• Assume that every Assume that every ttff time, on average ( time, on average (mean free mean free

timetime), a constant fraction ), a constant fraction ff of of EEkk is is thermalizedthermalized (turned into heat)(turned into heat)

• Whole process thermalizes energy Whole process thermalizes energy ff((t/tt/tff))EEk k tttt22 = = tt11. Constant in front is . Constant in front is ½ ½ fmfm22/t/tff : : 22, where , where =½=½fm/tfm/tff is the is the effective viscosityeffective viscosity..

Example: Electrical ResistanceExample: Electrical Resistance• We know We know PPspentspent==II22R=R=((QQ//tt))22RR, ,

or or EEspentspent ==PtPt = = QQ22R/tR/t. . Note scaling with 1/ Note scaling with 1/tt– Charge transfer through a resistor obeys the Charge transfer through a resistor obeys the

adiabatic principle!adiabatic principle!• Why is this so, microscopically?Why is this so, microscopically?

– In most situations, conduction electrons have a In most situations, conduction electrons have a large Fermi velocity or thermal velocity relative to large Fermi velocity or thermal velocity relative to drift velocity.drift velocity. Scatter off of lattice-atom cross-sections with a mean Scatter off of lattice-atom cross-sections with a mean

free time free time ttff that is fairly independent of drift velocity that is fairly independent of drift velocity– Each scattering event thermalizes the electron’s Each scattering event thermalizes the electron’s

drift kinetic energy - a frac. drift kinetic energy - a frac. ff of current’s total of current’s total EEkk

• Therefore assumptions in prev. proof apply!Therefore assumptions in prev. proof apply!

The Adiabatic TheoremThe Adiabatic Theorem• A result in basic quantum theoryA result in basic quantum theory

– Proved in many quantum mechanics textbooksProved in many quantum mechanics textbooks• Paraphrased:Paraphrased: A system initially in its ground state (or A system initially in its ground state (or

more generally, its more generally, its nnth energy eigenstate) will, after th energy eigenstate) will, after subjecting it to a sufficiently slow change of applied subjecting it to a sufficiently slow change of applied forces, remain in the corresponding state, with high forces, remain in the corresponding state, with high probability.probability.– Result has been recently shown to be very general.Result has been recently shown to be very general.

• Amount of leakage out of desired state is Amount of leakage out of desired state is proportional to speed of transition, at low speeds.proportional to speed of transition, at low speeds. Quantum systems obey the adiabatic principle!Quantum systems obey the adiabatic principle!

Focus of most of the work on adiabatics to date

Some Loss-Inducing InteractionsSome Loss-Inducing InteractionsFor ordinary voltage-coded electronics:For ordinary voltage-coded electronics:• Interactions whose dissipation scales with speed:Interactions whose dissipation scales with speed:

– Parasitic EM emission from dynamic (Parasitic EM emission from dynamic (CC,,LL) reactances) reactances– Scattering of ballistic electrons from lattice Scattering of ballistic electrons from lattice

imperfections, causing Ohmic resistanceimperfections, causing Ohmic resistance• Interactions having different scaling laws:Interactions having different scaling laws:

– Interference from outside EM sourcesInterference from outside EM sources– Thermally-activated leakage of electrons over potential Thermally-activated leakage of electrons over potential

energy barriersenergy barriers– Quantum tunneling of electrons through narrow barriers Quantum tunneling of electrons through narrow barriers

(sub-Fermi wavelength)(sub-Fermi wavelength)– Losses due to intentional treatment of known Losses due to intentional treatment of known

physical information as entropy (bit erasure)physical information as entropy (bit erasure)

Some Ways to Reduce LossesSome Ways to Reduce Losses

• EM interference / emission:EM interference / emission: Add shielding, use high-Add shielding, use high-QQ MEMS/NEMS oscillatorsMEMS/NEMS oscillators

• Scattering/resistance:Scattering/resistance: Ballistic FETs, superconductorsBallistic FETs, superconductors• Thermal leakage:Thermal leakage: avoid low avoid low VVTT and/or high temps and/or high temps

• Tunneling:Tunneling: thick tunnel barriers, high-thick tunnel barriers, high-κκ dielectrics, dielectrics, conductors w. low Fermi-level/high electron affinity, conductors w. low Fermi-level/high electron affinity, vacuum-gap barriers?vacuum-gap barriers?

• Intentional bit erasure:Intentional bit erasure: reduce voltages, use mostly-reduce voltages, use mostly-reversible adiabatic logic designsreversible adiabatic logic designs

Adiabatic Circuits & Adiabatic Circuits & Reversible ComputingReversible Computing

Myths, Controversies & Myths, Controversies & MisconceptionsMisconceptions

Some Claims Against Reversible ComputingSome Claims Against Reversible Computing Eventual Resolution of ClaimEventual Resolution of Claim

John von Neumann, 1949 – Offhandedly remarks during a lecture that computing John von Neumann, 1949 – Offhandedly remarks during a lecture that computing requires requires kTkT ln 2 dissipation per “elementary act of decision” (bit-operation). ln 2 dissipation per “elementary act of decision” (bit-operation).

No proof provided. Twelve years later, Rolf Landauer of IBM tries valiantly to No proof provided. Twelve years later, Rolf Landauer of IBM tries valiantly to prove it, but succeeds only for logically irreversible operations.prove it, but succeeds only for logically irreversible operations.

Rolf Landauer, 1961 – Proposes that the logically irreversible operations that can be Rolf Landauer, 1961 – Proposes that the logically irreversible operations that can be seen to necessarily cause dissipation are irreducible.seen to necessarily cause dissipation are irreducible.

Landauer’s argument for irreducibility of logically irreversible operations was Landauer’s argument for irreducibility of logically irreversible operations was conclusively refuted by Bennett’s 1973 paper (partially presaged by Lecerf).conclusively refuted by Bennett’s 1973 paper (partially presaged by Lecerf).

Bennett’s 1973 construction is criticized for using too much memory.Bennett’s 1973 construction is criticized for using too much memory. Bennett devises a more space-efficient version of the algorithm in 1989.Bennett devises a more space-efficient version of the algorithm in 1989.

Bennett’s models criticized by various parties for depending on random Brownian Bennett’s models criticized by various parties for depending on random Brownian motion, and not making steady forward progress.motion, and not making steady forward progress.

Fredkin and Toffoli at MIT, 1980, provide ballistic “billiard ball” model of Fredkin and Toffoli at MIT, 1980, provide ballistic “billiard ball” model of reversible computing that makes steady progress.reversible computing that makes steady progress.

Various parties including Zurek note that Fredkin’s original classical-mechanical Various parties including Zurek note that Fredkin’s original classical-mechanical billiard-ball model is chaotically unstable.billiard-ball model is chaotically unstable.

Zurek, 1984, shows that quantum models can avoid the chaotic instabilities. Zurek, 1984, shows that quantum models can avoid the chaotic instabilities. (Though there are workable classical ways to fix the problem also.)(Though there are workable classical ways to fix the problem also.)

Various parties propose that classical reversible logic principles won’t work at the Various parties propose that classical reversible logic principles won’t work at the nanoscale, for unspecified or vaguely-stated reasons.nanoscale, for unspecified or vaguely-stated reasons.

Drexler, 1980’s, designs various mechanical nanoscale reversible logics and Drexler, 1980’s, designs various mechanical nanoscale reversible logics and carefully analyzes their energy dissipation.carefully analyzes their energy dissipation.

Carver Mead, CalTech, 1980 – Attempts to show that the Carver Mead, CalTech, 1980 – Attempts to show that the kTkT bound is unavoidable bound is unavoidable in electronic devices, via a collection of counter-examples.in electronic devices, via a collection of counter-examples.

No general proof provided. Later he asked Feynman about the issue; in 1985 No general proof provided. Later he asked Feynman about the issue; in 1985 Feynman provided a quantum-mechanical model of reversible computing.Feynman provided a quantum-mechanical model of reversible computing.

Various parties point out that Feynman’s model of reversible computing only Various parties point out that Feynman’s model of reversible computing only supports serial computation.supports serial computation.

Margolus at MIT, 1990, demonstrates a parallel quantum model of reversible Margolus at MIT, 1990, demonstrates a parallel quantum model of reversible computing—but only with 1 dimension of parallelism. computing—but only with 1 dimension of parallelism.

People question whether the various theoretical models can be validated with a People question whether the various theoretical models can be validated with a working electronic implementation.working electronic implementation.

Seitz and colleagues at CalTech, 1985, demonstrate working energy recovery Seitz and colleagues at CalTech, 1985, demonstrate working energy recovery circuits using adiabatic switching principles.circuits using adiabatic switching principles.

Seitz, 1985—Has some working circuits, but unsure if arbitrary logic is possible.Seitz, 1985—Has some working circuits, but unsure if arbitrary logic is possible. Koller & Athas, Hall, and Merkle (1992) separately devise general reversible Koller & Athas, Hall, and Merkle (1992) separately devise general reversible combinational logics.combinational logics.

Koller & Athas, 1992 – Conjecture reversible Koller & Athas, 1992 – Conjecture reversible sequential sequential feedback logic impossible.feedback logic impossible. Younis & Knight @MIT do reversible sequential, pipelineable circuits in 1993-94.Younis & Knight @MIT do reversible sequential, pipelineable circuits in 1993-94.

Some computer architects (including anonymous ISCA reviewers) wonder whether Some computer architects (including anonymous ISCA reviewers) wonder whether the constraint of reversible logic leads to unreasonable design convolutions.the constraint of reversible logic leads to unreasonable design convolutions.

Vieri, Frank and coworkers at MIT, 1995-99, refute these qualms by demonstrating Vieri, Frank and coworkers at MIT, 1995-99, refute these qualms by demonstrating straightforward designs for fully-reversible and scalable gate arrays, straightforward designs for fully-reversible and scalable gate arrays, microprocessors, and instruction sets.microprocessors, and instruction sets.

Some computer science theorists suggest that the algorithmic overheads of Some computer science theorists suggest that the algorithmic overheads of reversible computing might outweigh their practical benefits.reversible computing might outweigh their practical benefits.

Frank, 1997-2003, publishes a variety of rigorous theoretical analysis refuting these Frank, 1997-2003, publishes a variety of rigorous theoretical analysis refuting these claims for the most general classes of applications.claims for the most general classes of applications.

Various parties point out that high-quality power supplies for adiabatic circuits seem Various parties point out that high-quality power supplies for adiabatic circuits seem difficult to build electronically.difficult to build electronically.

Frank, 2000, suggests microscale/nanoscale electro mechanical resonators for high-Frank, 2000, suggests microscale/nanoscale electro mechanical resonators for high-quality energy recovery with desired waveform shape and frequency.quality energy recovery with desired waveform shape and frequency.

Frank, 2002—Briefly wonders if synchronization of parallel reversible computation Frank, 2002—Briefly wonders if synchronization of parallel reversible computation in 3 dimensions (not covered by Margolus) might not be possible.in 3 dimensions (not covered by Margolus) might not be possible.

Later that year, Frank devises a simple mechanical model showing that parallel Later that year, Frank devises a simple mechanical model showing that parallel reversible systems can indeed be synchronized locally in 3 dimensions.reversible systems can indeed be synchronized locally in 3 dimensions.

Adiabatic Circuits and Adiabatic Circuits and Reversible ComputingReversible Computing

Commonly Encountered Myths, Commonly Encountered Myths, Fallacies, and PitfallsFallacies, and Pitfalls

(in the Hennessy-Patterson tradition)(in the Hennessy-Patterson tradition)

Myths about Adiabatic Circuits Myths about Adiabatic Circuits & Reversible Computing& Reversible Computing

• ““Someone proved that Someone proved that computing with <<computing with <<kTkT free-energy loss per bit-free-energy loss per bit-operation is impossible.”operation is impossible.”

• ““Physics isn’t reversible.”Physics isn’t reversible.”• ““An energy-efficient An energy-efficient

adiabatic clock/power adiabatic clock/power supply is impossible to supply is impossible to build.”build.”

• ““True adiabaticity doesn’t True adiabaticity doesn’t require reversible logic.”require reversible logic.”

• ““Sequential logic can’t be Sequential logic can’t be done adiabatically.”done adiabatically.”

• ““Adiabatic circuits require Adiabatic circuits require many clock/power rails many clock/power rails and/or voltage levels.”and/or voltage levels.”

• ““Adiabatic design is Adiabatic design is necessarily difficult.”necessarily difficult.”

Fallacies about Adiabatic Circuits Fallacies about Adiabatic Circuits and Reversible Computingand Reversible Computing

• ““Since speed scales with Since speed scales with energy dissipation in energy dissipation in adiabatic circuits, they adiabatic circuits, they aren’t good for high-aren’t good for high-performance performance computing.”computing.”

• ““If I tried and failed to If I tried and failed to invent an efficient invent an efficient adiabatic logic, it must adiabatic logic, it must be impossible.”be impossible.”

• ““The algorithmic The algorithmic overheads of reversible overheads of reversible computing mean it can computing mean it can never be cost-effective.”never be cost-effective.”

• ““Since leakage gets Since leakage gets worse in nanoscale worse in nanoscale devices, adiabatics is devices, adiabatics is doomed.”doomed.”

Pitfalls in Adiabatic Circuits and Pitfalls in Adiabatic Circuits and Reversible ComputingReversible Computing

• Using diodes in the Using diodes in the charge-return path.charge-return path.

• Forgetting to obey one of Forgetting to obey one of the transistor rules.the transistor rules.

• Using traditional models Using traditional models of computational of computational complexity.complexity.

• Restricting oneself to an Restricting oneself to an asymptotically inefficient asymptotically inefficient design style.design style.

• Assuming that the best Assuming that the best reversible and reversible and irreversible algorithms irreversible algorithms are similar.are similar.

• Failing to optimize the Failing to optimize the degree of reversibility of degree of reversibility of a design.a design.

• Ignoring charge leakage Ignoring charge leakage in low-power/adiabatic in low-power/adiabatic design.design.

Adiabatic/Reversible ComputingAdiabatic/Reversible Computing

Basic Models and ConceptsBasic Models and Concepts

Bistable Potential-Energy WellsBistable Potential-Energy Wells• Consider any system having an adjustable, bistable Consider any system having an adjustable, bistable

potential energy surface (PES) in its configuration space.potential energy surface (PES) in its configuration space.• The two stable states form a natural The two stable states form a natural bitbit..

– One state represents 0, the other 1.One state represents 0, the other 1.

• Consider now the P.E. well havingConsider now the P.E. well havingtwo adjustable parameters:two adjustable parameters:– (1) Height of the potential energy barrier(1) Height of the potential energy barrier

relative to the well bottomrelative to the well bottom– (2) Relative height of the left and right(2) Relative height of the left and right

states in the well (bias)states in the well (bias)

0 1

(Landauer ’61)

Possible Parameter SettingsPossible Parameter Settings• We will distinguish six qualitatively We will distinguish six qualitatively

different settings of the well parameters, as different settings of the well parameters, as follows… follows…

Direction of Bias Force

BarrierHeight

One Mechanical ImplementationOne Mechanical Implementation

spring spring

Rightwardbias

Leftwardbias

Barrier up

Barrier down

Barrierwedge

Stateknob

Possible Adiabatic TransitionsPossible Adiabatic Transitions• Catalog of all the possible transitions in Catalog of all the possible transitions in

these wells, these wells, adiabaticadiabatic & & notnot......

Direction of Bias Force

BarrierHeight

0 0 0

111

10 N

(Ignoring superposition states.)

leak

leak

“1”states

“0”states

Ordinary Ordinary IrreversibleIrreversible Logics Logics• Principle of operation:Principle of operation: Lower a barrier, or not, Lower a barrier, or not,

based on input. Series/parallel combinations ofbased on input. Series/parallel combinations of barriers do logic. Major barriers do logic. Major dissipation in at least one of dissipation in at least one of

the possible transitions.the possible transitions.0

1

0

Example: Ordinary CMOS logics

Input changes,barrier

lowered

Outputirreversiblychanged to 0

• Amplifies input signals.

Ordinary Ordinary IrreversibleIrreversible Memory Memory

• Lower a barrier, dissipating stored information.Lower a barrier, dissipating stored information. Apply an input bias.Apply an input bias. Raise the barrier to latch Raise the barrier to latch the new informationthe new informationinto place.into place. Remove inputRemove inputbias.bias.

0 0

11

10 N

Example:ordinaryDRAM

Dissipationhere can be

made as low as kT ln 2

Input“0”

Input“1”

Barrier up

Barrierup

Retractinput

Retractinput

(1)

(2) (2)

(3)

Input-Bias Clocked-Barrier LogicInput-Bias Clocked-Barrier Logic• Cycle of operation:Cycle of operation:

– (1) (1) Data input applies biasData input applies bias• Add forces to do logicAdd forces to do logic

– (2) (2) Clock signal raises barrierClock signal raises barrier– (3) (3) Data input bias removedData input bias removed

0 0

11

10 N

Can amplify/restore input signalin the barrier-raising step.

Can reset latch reversibly (4) given copy ofcontents.

Examples: AdiabaticQDCA, SCRL latch, Rod logic latch, PQ logic,Buckled logic

(1) (1)

(2)

(2)(3)

(3)

(4)(4)

(4) (4)

(4)

(4)

Input-Barrier, Clocked-Bias RetractileInput-Barrier, Clocked-Bias Retractile

• Cycle of operation:Cycle of operation:– (1) Inputs raise or lower barriers(1) Inputs raise or lower barriers

• Do logic w. series/parallel barriersDo logic w. series/parallel barriers– Clock applies bias force, which changes state, or notClock applies bias force, which changes state, or not

0 0 0

10 N

• Barrier signal amplified.• Must reset output prior to changing input.• Combinational logic only!

(1) Input barrier height

(2) Clocked force applied

Examples:Hall’s logic,SCRL gates,Rod logic interlocks

Input-Barrier, Clocked-Bias LatchingInput-Barrier, Clocked-Bias Latching

0 0 0

1

10 N

●● Cycle of operation:Cycle of operation:1.1. Input Input conditionally lowersconditionally lowers barrier barrier

• Do logic w. series/parallel barriersDo logic w. series/parallel barriers

2.2. Clock applies bias force; conditional bit flipClock applies bias force; conditional bit flip3.3. Input removed, Input removed, raisingraising the barrier & the barrier &

locking in the state-changelocking in the state-change4.4. ClockClock

bias canbias canretractretract

Examples: Mike’s4-cycle 2-level adiabaticCMOS logic (2LAL)

(1)

(2) (2)

(2) (2)

(3)

(4)(4)

Sleeve

(a)

(b)

(c)

(d)

(e)

(f)

Full Classical-Mechanical ModelFull Classical-Mechanical ModelClaim: The following components Claim: The following components are sufficient for a complete, are sufficient for a complete, scalable, parallel, pipelinable, scalable, parallel, pipelinable, linear-time, stable, classical linear-time, stable, classical reversible computing system:reversible computing system:(a) Ballistically rotating flywheel (a) Ballistically rotating flywheel driving linear motion.driving linear motion.(b) Scalable mesh to synchronize (b) Scalable mesh to synchronize local flywheel phases in 3-D.local flywheel phases in 3-D.(c) Sinusoidal to flat-topped (c) Sinusoidal to flat-topped waveform shape converter. waveform shape converter. (d) Non-amplifying signal inverter (d) Non-amplifying signal inverter (NOT gate).(NOT gate).(e) Non-amplifying OR/AND gate.(e) Non-amplifying OR/AND gate.(f) Signal amplifier/latch.(f) Signal amplifier/latch.

Primary drawback: Slow propagationspeed of mechanical (phonon) signals. cf. Drexler ‘92

Adiabatic electronics & Adiabatic electronics & CMOS implementationsCMOS implementations

Conventional Gates are IrreversibleConventional Gates are Irreversible• Logic gate behavior (on receiving new input):Logic gate behavior (on receiving new input):

– Many-to-one transformation of local state!Many-to-one transformation of local state!– Required to dissipate bRequired to dissipate bTT, by Landauer principle, by Landauer principle– Incurs ½Incurs ½CVCV22 dissipation in 2 out of 4 cases. dissipation in 2 out of 4 cases.

Just beforetransition:

Aftertransition:

in out in out0 00 1 0 11 0 1 01 1

in out

Example:

Static CMOS Inverter:

Transformation of local state:

Exact formula:

for frequency reduction f : RC/t

2/1diss 11 CVeffE f

Common Mistakes to AvoidCommon Mistakes to Avoid

In Adiabatic DesignIn Adiabatic Design

Common Mistakes to Avoid:Common Mistakes to Avoid:

• Don’t use diodes in charge-return path!Don’t use diodes in charge-return path!– The built-in voltage drop kills adiabaticity.The built-in voltage drop kills adiabaticity.

• Don’t disobey adiabatic transistor rules by Don’t disobey adiabatic transistor rules by either:either:– Turning on transistor with voltage across itTurning on transistor with voltage across it– Turning off transistor with current thru it!Turning off transistor with current thru it!

• This one is often neglected!This one is often neglected!

• Use mostly-reversible logic!Use mostly-reversible logic!– Optimize degree of reversibility for applicationOptimize degree of reversibility for application

• Don’t over-constrain the design family!Don’t over-constrain the design family!– Asymptotically efficient circuits should be possibleAsymptotically efficient circuits should be possible

Adiabatic Rules for TransistorsAdiabatic Rules for Transistors• Rule 1: Rule 1: Never turn Never turn onon a transistor if it has a nonzero voltage a transistor if it has a nonzero voltage

across it!across it!– I.e.I.e., between its source & drain terminals., between its source & drain terminals.– Why:Why: This erases info. & causes ½ This erases info. & causes ½CVCV22 disspation. disspation.

• Rule 2:Rule 2: Never apply a nonzero voltage across a transistor even Never apply a nonzero voltage across a transistor even duringduring any on any onoff transition!off transition!– Why: Why: When partially turned on, the transistor has relatively When partially turned on, the transistor has relatively

low low RR, gets high , gets high PP==VV22//RR dissipation. dissipation.– Corollary:Corollary: Never turn Never turn offoff a transistor if it has a nonzero a transistor if it has a nonzero

current going through it!current going through it!• Why: Why: As As RR gradually increases, the gradually increases, the VV==IRIR voltage drop voltage drop

will build, and then rule 2 will be violated.will build, and then rule 2 will be violated.

Adiabatic Rules, continued…Adiabatic Rules, continued…• Transistor Rule 3:Transistor Rule 3: Never Never suddenlysuddenly change the voltage change the voltage

applied across any applied across any onon transistor. transistor.– Why:Why: So transition will be more reversible; dissipation So transition will be more reversible; dissipation

will approach will approach CVCV22((RCRC//tt), not ½), not ½CVCV22..Adiabatic rules for other components:Adiabatic rules for other components:• DiodesDiodes: Don’t use them at all!: Don’t use them at all!

– There is always a built-in voltage drop across them!There is always a built-in voltage drop across them!• ResistorsResistors: Avoid : Avoid moderatemoderate network resistances, if poss. network resistances, if poss.

– e.g.e.g. stay away from range >10 k stay away from range >10 k and <1 M and <1 M• CapacitorsCapacitors: Minimize, reliability permitting.: Minimize, reliability permitting.

– Note: Dissipation scales with Note: Dissipation scales with CC22!!

Transistor Rules SummarizedTransistor Rules Summarized

offhigh high

onhigh low

offhigh

offlow low

low

onhigh high

onlow low

Legal adiabatic transitions in green. (For n- or p-FETs.)Dissipative states and transitions in red.

offhigh low

onhighlow

SCRL: Split-level Charge SCRL: Split-level Charge Recovery LogicRecovery Logic

The First Pipelined Fully-Adiabatic The First Pipelined Fully-Adiabatic CMOS LogicCMOS Logic

(Younis & Knight, MIT, ’94)(Younis & Knight, MIT, ’94)

Just beforetransition:

Aftertransition:

in out in out0 ½ 0 11 ½ 1 0

Transformation of local state:

Input-Barrier, Clocked-Bias RetractileInput-Barrier, Clocked-Bias Retractile

• Cycle of operation:Cycle of operation:– Inputs raise or lower barriersInputs raise or lower barriers

• Do logic w. series/parallel barriersDo logic w. series/parallel barriers– Clock applies bias force which changes state, or notClock applies bias force which changes state, or not

0 0 0

10 N

* Must reset outputprior to input.* Combinational logiconly!

Input barrier height

Clocked force applied

Examples:Hall’s logic,SCRL gates,Rod logic interlocks

Retractile Logic w. SCRL gatesRetractile Logic w. SCRL gates• Simple combinational logic of any depth Simple combinational logic of any depth NN::

– Requires Requires NN timing phases timing phases– Non-pipelinedNon-pipelined– No sequential reuse ofNo sequential reuse of

HW (even worse)HW (even worse)

• We needWe needsequentialsequentiallogic!logic!

Time

Sequential Retractile LogicSequential Retractile Logic• Approach #1 (Hall ‘92):Approach #1 (Hall ‘92):

– After every After every NN stages, invoke an irreversible latch stages, invoke an irreversible latch• stores the output of the last stagestores the output of the last stage

– Then, Then, retractretract all the stages, all the stages,– and begin a new cycleand begin a new cycle

• Problems:Problems:– Reduces dissipation by at most a factor of Reduces dissipation by at most a factor of NN– Also reduces HW efficiency by order Also reduces HW efficiency by order NN! !

• In worst case, compared to a pipelined, sequential circuitIn worst case, compared to a pipelined, sequential circuit

• Approach #2 (Knight & Younis, ‘93):Approach #2 (Knight & Younis, ‘93):– The “store output” stage can The “store output” stage can alsoalso be reversible! be reversible!– Gives fully-adiabatic, sequential, pipelined circuits!Gives fully-adiabatic, sequential, pipelined circuits!

• NN can be as small 1 or 2 & still have arbitrarily high can be as small 1 or 2 & still have arbitrarily high QQ

Simple Reversible CMOS LatchSimple Reversible CMOS Latch• Uses a standard CMOS Uses a standard CMOS transmission gatetransmission gate• Sequence of operation:Sequence of operation:

(1) input initially matches latch contents (output)(1) input initially matches latch contents (output)(2) input changes(2) input changesoutput changes (3) latch closesoutput changes (3) latch closes

(4) input (4) input removedremoved

P

P

in out

Before Input Inputinput: arrived: removed:in out in out in outa a a a a a

b b a b

Resetting a Reversible LatchResetting a Reversible Latch• Can reversibly Can reversibly unlatchunlatch data as follows: data as follows:

(exactly the reverse of the latching process)(exactly the reverse of the latching process)– (1) Data value (1) Data value dd stored on memory node M. stored on memory node M.– (2) Present an exact copy of (2) Present an exact copy of dd on input. on input.– (3) Open the latch (connecting input to M).(3) Open the latch (connecting input to M).

• No dissipation since voltage levels matchNo dissipation since voltage levels match– (4) Retract the copy of (4) Retract the copy of dd from the input. from the input.

• Retracts copy stored in latch also.Retracts copy stored in latch also.

Input-Bias Clocked-Barrier LogicInput-Bias Clocked-Barrier Logic• Cycle of operation:Cycle of operation:

– Data input applies biasData input applies bias• Add forces to do logicAdd forces to do logic

– Clock signal raises barrierClock signal raises barrier– Data input bias removedData input bias removed

0 0

11

10 N

Input“0”

Input“1”

Retractinput

Retractinput

Clockbarrier

upClock up

Can amplify/restore input signalin clocking step.

Can reset latch reversibly givencopy of contents.

Examples: AdiabaticQDCA, SCRL latch, Rod logic latch, PQ logic,Buckled logic

SCRL 6-tick clock cycleSCRL 6-tick clock cycle

inout

Initial state: All gates off, all nodes neutral.

SCRL 6-tick clock cycleSCRL 6-tick clock cycle

inout

Tick #1: Input goes valid, forward T-gate opens.

SCRL 6-tick clock cycleSCRL 6-tick clock cycle

inout

Tick #2: Forward gate charges, output goes valid.(Tick #1 of subsequent gate.)

SCRL 6-tick clock cycleSCRL 6-tick clock cycle

inout

Tick #3: Forward T-gate closes, reverse gate charges.

SCRL 6-tick clock cycleSCRL 6-tick clock cycle

inout

Tick #4: Reverse T-gate opens, forward gate discharges.

SCRL 6-tick clock cycleSCRL 6-tick clock cycle

inout

Tick #5: Reverse gate discharges, input goes neutral.

SCRL 6-tick clock cycleSCRL 6-tick clock cycle

inout

Tick #6: Reverse T-gate closes, output goes neutral.Ready for next input!

24 ticks/cyclein this version-includes 2-levelretractile stages

Some Timing TerminologySome Timing TerminologyFor sequential adiabatic circuits:For sequential adiabatic circuits:• 1 Tick1 Tick: Time for a single ramp transition: Time for a single ramp transition

– adiabatic speed fraction adiabatic speed fraction ff times the RC gate delay. times the RC gate delay.• 1 Phase1 Phase: Latency for a data value to propagate : Latency for a data value to propagate

forward by 1 pipeline stage.forward by 1 pipeline stage.• 1 Cycle1 Cycle: Minimum period for all timing : Minimum period for all timing

information to return back to its initial state.information to return back to its initial state.• Diadic:Diadic: Two retractile levels per gate Two retractile levels per gate

– permits inverting or non-inverting logic.permits inverting or non-inverting logic.• Dual rail:Dual rail: Two wires per logic value Two wires per logic value

– permits universal logic with monodic gatespermits universal logic with monodic gates

Monadic:only 1 level

Some Figures of DemeritSome Figures of Demerit• Some quantities we may wish to minimize:Some quantities we may wish to minimize:

– Ticks/phase:Ticks/phase:• proportional to logic propagation latencyproportional to logic propagation latency

– Ticks/cycle:Ticks/cycle:• reciprocal to rate of data throughputreciprocal to rate of data throughput

– Transistor-ticks/cycle:Transistor-ticks/cycle:• reciprocal to HW cost-efficiencyreciprocal to HW cost-efficiency

– Number of required clock/power input signals:Number of required clock/power input signals:• supplying these may be a significant component of supplying these may be a significant component of

system costsystem cost– Number of distinct voltage levels required:Number of distinct voltage levels required:

• may affect reliability/power tradeoffmay affect reliability/power tradeoff

Some Interesting QuestionsSome Interesting Questions• About pipelined, sequential, fully-adiabatic About pipelined, sequential, fully-adiabatic

CMOS logic:CMOS logic:– Q: Does it require an intermediate voltage level?Q: Does it require an intermediate voltage level?

• A: No, you can get by with only 2 different levels.A: No, you can get by with only 2 different levels.– Q: What is the minimum number of externally Q: What is the minimum number of externally

provided timing signals you can get away with?provided timing signals you can get away with?• A: A: 4 (4 (12 if split levels are used)12 if split levels are used)

– Q: Can the order-Q: Can the order-NN different timing signals needed different timing signals needed for long retractile cascades be internally generated for long retractile cascades be internally generated within an adiabatic circuit?within an adiabatic circuit?

• A: Yes, but not statically, unless A: Yes, but not statically, unless NN22 hardware is used hardware is used– where where NN is the number of stages per full sequential cycle is the number of stages per full sequential cycle

• We now demonstrate these answers.We now demonstrate these answers.

Some Timing ExamplesSome Timing ExamplesSee next slide for some detailed timing diagrams.See next slide for some detailed timing diagrams.• N-N-level retractile cascades:level retractile cascades:

– 22NN ticks/phase × 1 phase/cycle = 2 ticks/phase × 1 phase/cycle = 2NN ticks/cycle ticks/cycle • 3-phase fully-static diadic SCRL3-phase fully-static diadic SCRL

– 8 ticks/phase × 3 phases/cycle = 24 ticks/cycle8 ticks/phase × 3 phases/cycle = 24 ticks/cycle• 2-phase fully-static monadic SCRL2-phase fully-static monadic SCRL

– 5 ticks/phase × 2 phases/cycle = 10 ticks/cycle5 ticks/phase × 2 phases/cycle = 10 ticks/cycle• 2-phase fully-static diadic SCRL2-phase fully-static diadic SCRL

– 6 ticks/phase × 2 phases/cycle = 12 ticks/cycle6 ticks/phase × 2 phases/cycle = 12 ticks/cycle• 6 tick/cycle dynamic SCRL detailed previously:6 tick/cycle dynamic SCRL detailed previously:

– 1 tick/phase × 6 phases/cycle = 6 ticks/cycle1 tick/phase × 6 phases/cycle = 6 ticks/cycle

Some SCRL timing diagramsSome SCRL timing diagrams

Reversible / Adiabatic Chips Reversible / Adiabatic Chips Designed @ MIT, 1996-1999Designed @ MIT, 1996-1999

By the author and other then-students in the MIT Reversible Computing group,under AI/LCS lab members Tom Knight and Norm Margolus.

2LAL: 2-Level Adiabatic Logic2LAL: 2-Level Adiabatic Logic

A Novel Alternative to SCRLA Novel Alternative to SCRL

2LAL: 2-level Adiabatic Logic2LAL: 2-level Adiabatic Logic

• Use simplified T-gate symbol:Use simplified T-gate symbol:• Basic buffer element:Basic buffer element:

– cross-coupled T-gatescross-coupled T-gates

• Only 4 timing signals,Only 4 timing signals,4 ticks per cycle:4 ticks per cycle: ii rises during tick rises during tick i i ii falls during tick ( falls during tick (ii+2) mod 4+2) mod 4

P

P

P

:

in

out

1

0

0 1 2 3Tick #

0

1

2

3

(Implementable using ordinary CMOS transistors)

2LAL Cycle of Operation2LAL Cycle of Operation

in

in1

in=0

01

01

10

11

out1

out=0

00

00

in011

out0

Tick #0 Tick #1 Tick #2 Tick #3

2LAL Shift Register Structure2LAL Shift Register Structure• 1-tick delay per logic stage:1-tick delay per logic stage:

• Logic pulse timing & propagation:Logic pulse timing & propagation:

in1

0

2

1

3

2

out

0

3

in

in

0 1 2 3 ... 0 1 2 3 ...

More complex logic functionsMore complex logic functions• Non-inverting Boolean functions:Non-inverting Boolean functions:

• For inverting functions, must use quad-rail logic For inverting functions, must use quad-rail logic encoding:encoding:– To invert, justTo invert, just

swap the rails!swap the rails!• Zero-transistorZero-transistor

“inverters.”“inverters.”

A

B

A

AB

A B

AB

A0

A0

A1

A1

A = 0 A = 1

Hardware Efficiency issuesHardware Efficiency issues• Hardware efficiencyHardware efficiency: How many logic operations : How many logic operations

per unit hardware per unit time?per unit hardware per unit time?• Hardware spacetime complexity:Hardware spacetime complexity: How much How much

hardware for how much time per logic op?hardware for how much time per logic op?• We’re interested in minimizing:We’re interested in minimizing:

(# of transistors) × (# of ticks) / (gate cycle)(# of transistors) × (# of ticks) / (gate cycle)• SCRL inverter, w. return path:SCRL inverter, w. return path:

– (8 transistors) (8 transistors) (6 ticks) = 48 transistor-ticks (6 ticks) = 48 transistor-ticks

• Quad-rail 2LAL buffer stage:Quad-rail 2LAL buffer stage:– (16 transistors) (16 transistors) (4 ticks) = 64 transistor-ticks (4 ticks) = 64 transistor-ticks

More SCRL vs. 2LALMore SCRL vs. 2LAL• SCRL reversible NAND, w. all inverters:SCRL reversible NAND, w. all inverters:

– (23 transistors) (23 transistors) (6 ticks) = 138 T-ticks (6 ticks) = 138 T-ticks

• Quad-rail 2LAL AND:Quad-rail 2LAL AND:– (48 transistors) (48 transistors) (4 ticks) = 192 T-ticks (4 ticks) = 192 T-ticks

• Result of comparison:Result of comparison: Although 2LAL Although 2LAL minimizes # of rails, and # ticks/cycle, it does minimizes # of rails, and # ticks/cycle, it does notnot minimize overall spacetime complexity.minimize overall spacetime complexity.

• The question of whether 6-tick SCRL minimizes The question of whether 6-tick SCRL minimizes per-op spacetime complexity among pipelined per-op spacetime complexity among pipelined adiabatic CMOS logics is still open.adiabatic CMOS logics is still open.

Minimizing Power-Clock SignalsMinimizing Power-Clock Signals• How many external clock signals required?How many external clock signals required?

– NN-level-deep retractile cascade logic:-level-deep retractile cascade logic:• 22NN waveforms × 1 phase = 2 waveforms × 1 phase = 2NN signals signals

– 6 tick/cycle, 6-phase dynamic SCRL:6 tick/cycle, 6-phase dynamic SCRL:• 6 waveforms × 6 phases = 36 signals6 waveforms × 6 phases = 36 signals

– 24 tick/cycle, 3-phase static SCRL:24 tick/cycle, 3-phase static SCRL:• 12 waveforms × 3 phases = 36 signals12 waveforms × 3 phases = 36 signals

– 4 tick/cycle, 2LAL:4 tick/cycle, 2LAL:• 1 waveform × 4 phases = 4 signals!1 waveform × 4 phases = 4 signals!

• It turns out that 12 signals are sufficient to It turns out that 12 signals are sufficient to implement implement anyany combination of 2-level or 3- combination of 2-level or 3-level logics (including retractile) on-chip!level logics (including retractile) on-chip!

How to Do ItHow to Do It• Circular 2LAL shifter; pulse-gated clocksCircular 2LAL shifter; pulse-gated clocks 0 1 2 3

Tick #

P0

P1

P2

P3

0

1

2

3

inP1

P0

P2

P1

P3

P2

out

P0

P3

22

0

2

12-rail system: pros & cons12-rail system: pros & cons• Pros:Pros:

– Completely solves adiabatic timing design problemCompletely solves adiabatic timing design problem– Enables mixtures of retractile, SCRL, and other logic Enables mixtures of retractile, SCRL, and other logic

styles on 1 chipstyles on 1 chip– Enables simple fully-adiabatic SRAM & DRAMEnables simple fully-adiabatic SRAM & DRAM

• Cons:Cons:– Timing signals are dynamicTiming signals are dynamic– Known fully-static alternatives use order Known fully-static alternatives use order NN22 gates and gates and

signals for signals for NN-tick-long cycles-tick-long cycles• NN can be large in a chip that includes deep retractile can be large in a chip that includes deep retractile

networksnetworks– Energy waste in driving the source/drain junction Energy waste in driving the source/drain junction

capacitances of all the T-gates even when timing pulse capacitances of all the T-gates even when timing pulse isn’t present isn’t present

• SOI reduces these parasiticsSOI reduces these parasitics

GCALGCAL: General CMOS Adiabatic Logic: General CMOS Adiabatic Logic• A general CMOS adiabatic design methodology A general CMOS adiabatic design methodology

– Currently under development at UFCurrently under development at UF• Combines best features of SCRL, 2LAL, and retractile logics:Combines best features of SCRL, 2LAL, and retractile logics:

– Permits designs attaining asymptotically optimal cost-efficiencyPermits designs attaining asymptotically optimal cost-efficiency• For any combination of time, space, spacetime, energy costsFor any combination of time, space, spacetime, energy costs

– Arbitrarily high degree of reversibilityArbitrarily high degree of reversibility– Permits using minimal 2-level and 3-level adiabatic gatesPermits using minimal 2-level and 3-level adiabatic gates– Requires only 4 externally supplied clock/power signals for 2-level logicRequires only 4 externally supplied clock/power signals for 2-level logic

• And only 12 total for mixed 2-level + 3-level logicAnd only 12 total for mixed 2-level + 3-level logic– Supports mixtures of fully-pipelined and retractile logic.Supports mixtures of fully-pipelined and retractile logic.– Supports quiescent dynamic/static latches & RAM cellsSupports quiescent dynamic/static latches & RAM cells

• Tools currently under development:Tools currently under development:– A new HDL specialized for describing adiabatic designsA new HDL specialized for describing adiabatic designs– Digital circuit simulator with adiabaticity checkerDigital circuit simulator with adiabaticity checker– Adiabatic logic synthesis tool, with automatic legacy design converterAdiabatic logic synthesis tool, with automatic legacy design converter

GCAL DRAM/SRAM cellsGCAL DRAM/SRAM cells

• GCAL DRAM cellGCAL DRAM cell– 4 transistors4 transistors– 4 word lines/row4 word lines/row– 2 bit lines/col (or 1)2 bit lines/col (or 1)

• GCAL SRAM cellGCAL SRAM cell– 8 transistors8 transistors– 6 word lines/row6 word lines/row– 2 bit lines/col (or 1)2 bit lines/col (or 1)

DRAM Cell Write CycleDRAM Cell Write Cycle1.1. All nodes initially ½.All nodes initially ½.

• T-gate initially closed (off).T-gate initially closed (off).

2.2. Transmission gate opens.Transmission gate opens.• Internal node is connected to Internal node is connected to

bit-line (at matching voltage).bit-line (at matching voltage).

3.3. Bit line transitions to 0 or 1.Bit line transitions to 0 or 1.• Pulls internal node to matching level.Pulls internal node to matching level.

4.4. Transmission gate closes.Transmission gate closes.• Internal node latched to new level.Internal node latched to new level.

5.5. Bit line transitions back to ½.Bit line transitions back to ½.• Prepares for a new cycle.Prepares for a new cycle.

Use the reverse sequence of operations to unwrite.Use the reverse sequence of operations to unwrite.

DRAM Cell Read CycleDRAM Cell Read Cycle1.1. All external nodes initially ½.All external nodes initially ½.

• T-gate initially off.T-gate initially off.• Internal node contains data.Internal node contains data.

2.2. Inverter rails split.Inverter rails split.• Bit line set to (inverted) data.Bit line set to (inverted) data.

3.3. T-gate at end of column latches bit-line data.T-gate at end of column latches bit-line data.4.4. Inverter rails merge.Inverter rails merge.

• Bit line restored to ½ level.Bit line restored to ½ level.

Can use the reverse sequence of operations to Can use the reverse sequence of operations to unread copy of data available at end of unread copy of data available at end of column.column.

Fully-Adiabatic DRAM cellFully-Adiabatic DRAM cell• 6T, 6 lines/row, 1 line/column (in/out together)6T, 6 lines/row, 1 line/column (in/out together)• Read cycle:Read cycle:

– Initially: Initially: lines neutral, out neutral, lines neutral, out neutral, RR off off– RR for desired row turns on for desired row turns on for desired row splits, driving for desired row splits, driving outout column column– RR turns off, turns off, outout is read is read merges, merges, outout is reset is reset

• Write cycle:Write cycle:– First, do read cycle.First, do read cycle.– inin is set to is set to outout– WW turns on turns on– inin changed to new value... changed to new value...

Fully-Adiabatic SRAMFully-Adiabatic SRAM• 10-T, 10 lines/row, 1 line/column10-T, 10 lines/row, 1 line/column• Operation similar to DRAM, except:Operation similar to DRAM, except:• Read-out:Read-out:

T2 off; N2 retracts; T3 on; N2 asserts; T2 on, T3 offT2 off; N2 retracts; T3 on; N2 asserts; T2 on, T3 off

• Write:Write:T2 off; N2 retracts; N1 retracts, copy of M presented T2 off; N2 retracts; N1 retracts, copy of M presented

on input; T1 on; inon input; T1 on; inchanges; T1 off, N1changes; T1 off, N1asserts; N2 asserts; T2 onasserts; N2 asserts; T2 on

M

N1 N2

T1 T2 T3in out

Limits of AdiabaticsLimits of Adiabatics

Structured SystemsStructured Systems• A A structuredstructured system is defined as a system system is defined as a system

about whose state we have some knowledge.about whose state we have some knowledge.– Some of its physical information is known.Some of its physical information is known. Its entropy is not at a maximum (by defn.).Its entropy is not at a maximum (by defn.). It is not at equilibrium (by defn.).It is not at equilibrium (by defn.).

• For states with a given energy For states with a given energy EE,,– we say the system’s energy is we say the system’s energy is distributed amongdistributed among

those states, in proportion to their probability.those states, in proportion to their probability.All statesof the abstractsystem havingenergy E

States w.prob. > 0

The system’senergy is“in here”

Desired TrajectoriesDesired Trajectories• Any structured systemAny structured system

we build to servewe build to servesome purposesome purposehas somehas somedesireddesiredtrajectory, or set oftrajectory, or set oftrajectories, through its configuration space that trajectories, through its configuration space that we would ideally like it to follow at all times.we would ideally like it to follow at all times.– Think of any given state as having a specific Think of any given state as having a specific

“desirability” at any given time.“desirability” at any given time.

Config-uration

Time

Desired trajectories

Energy LossesEnergy Losses• Energy dissipation can be viewed as a departure Energy dissipation can be viewed as a departure

of part of the system’s energy away from the of part of the system’s energy away from the system’s desired trajectory.system’s desired trajectory.

• E.g.E.g., 1 of 10, 1 of 1066 electrons electronsleaks out of aleaks out of aDRAM cell =DRAM cell =system’s energy hassystem’s energy hasdeparted from desireddeparted from desiredtrajectory (all 10trajectory (all 1066 stay) stay)by a small amount by a small amount

Config-uration

Energy that hasdeparted from desired

trajectories

Time

Limits of Adiabatics I:Limits of Adiabatics I:FrictionFriction

Generalized FrictionGeneralized Friction• Any force leading to departure from desired Any force leading to departure from desired

trajectory that obeys the adiabatic principle:trajectory that obeys the adiabatic principle:– I.e.I.e., force strength (& total energy loss) is proportional , force strength (& total energy loss) is proportional

to velocity along trajectory at low velocitiesto velocity along trajectory at low velocities

• Examples:Examples:– Ordinary sliding frictionOrdinary sliding friction– Fluid viscosityFluid viscosity– Electrical resistanceElectrical resistance– Forces causing electromagnetic radiative lossesForces causing electromagnetic radiative losses– Forces causing losses in inelastic collisionsForces causing losses in inelastic collisions

Ways to Quantify FrictionWays to Quantify FrictionNormal friction measures referring to length, mass, Normal friction measures referring to length, mass, etc.etc.

may not apply to may not apply to allall processes. processes.For a given mechanism executing a specified process (For a given mechanism executing a specified process (i.e.i.e., ,

following a specified desired trajectory or -ies) over a following a specified desired trajectory or -ies) over a time time tt::

• Energy coefficient:Energy coefficient: ccEE = = EElostlost··tt = = EElostlost//qq– Energy dissipated from traj. per unit of “quicknessEnergy dissipated from traj. per unit of “quickness””

• Note Note quicknessquickness qq = 1/ = 1/tt has units like Hz has units like Hz

• Entropy coefficient:Entropy coefficient: ccSS = = SSmademade··tt = = SSmademade//qq– New entropy generated per unit of quicknessNew entropy generated per unit of quickness

• Note that Note that ccE E = = ccSS··TT at temperature at temperature T.T.

What matters!

Energy Coefficient in ElectronicsEnergy Coefficient in Electronics• For charging capacitive load For charging capacitive load CC by voltage by voltage VV through through

effective resistance effective resistance RR::ccEE = = EElostlostt = t = ((CVCV22RC/tRC/t))t = Ct = C22VV22RR

• If the resistances are voltage-controlled switches with gain If the resistances are voltage-controlled switches with gain factor factor kk controlled by the same voltage controlled by the same voltage VV, then effective , then effective R R 1/ 1/kVkV

ccEE = C = C22V/kV/k

• In constant-field-scaled CMOS, In constant-field-scaled CMOS, kk 1/ 1/ddox ox , , C C , and , and

VV , so, soccEE 33// = = 44; ; EElostlost = = ccEE//t t 44// = = 33

(like (like CVCV22 energy) energy)

Degree of Reversibility of CMOSDegree of Reversibility of CMOS• What is the What is the QQ of a min-size CMOS transistor? of a min-size CMOS transistor?

QQ = = EEfreefree//EEdissdiss

= = EEfreefree/(/(ccEE//tt) )

= ½ = ½CVCV22/(/(CC22VV22R/tR/t)) = ½( = ½(tt//RCRC)) = ½ = ½ ss ((ss = slowdown factor) = slowdown factor)

• Note:Note: Using transistors wider than minimum-size Using transistors wider than minimum-size (larger (larger CC, smaller , smaller RR) wouldn’t change ) wouldn’t change RCRC or or QQ, and , and would increase overall dissipation by increasing would increase overall dissipation by increasing ccEE..

Lower Bounds on Friction?Lower Bounds on Friction?• No general (technology-independent) lower bounds No general (technology-independent) lower bounds

on friction coefficients for interesting types of on friction coefficients for interesting types of processes (processes (e.g.e.g. computation) are currently known. computation) are currently known.

• Clever engineering may eventually reduce the Clever engineering may eventually reduce the friction in desired processes to values as small as is friction in desired processes to values as small as is desired.desired.

• Some ways:Some ways:– Reduce number of moving parts (or particles)Reduce number of moving parts (or particles)– Isolate “moving parts” of system from unwanted Isolate “moving parts” of system from unwanted

interactions w. environmentinteractions w. environment

Entropy coefficients of some Entropy coefficients of some reversible logic gate operationsreversible logic gate operations

From Frank, “Ultimate theoretical models of From Frank, “Ultimate theoretical models of nanocomputers” (nanocomputers” (NanotechnologyNanotechnology, 1998):, 1998):

• SCRL, circa 1997:SCRL, circa 1997: ~1~1 b/Hzb/Hz• Optimistic reversible CMOS:Optimistic reversible CMOS: ~10~10 b/kHzb/kHz• Merkle’s “quantum FET:”Merkle’s “quantum FET:” ~1.2 ~1.2 b/GHzb/GHz• Nanomechanical rod logic:Nanomechanical rod logic: ~.07~.07 b/GHzb/GHz• Superconducting PQ gate:Superconducting PQ gate: ~25~25 b/THzb/THz• Helical logic:Helical logic: ~.01~.01 b/THzb/THz

How low can you go? We don’t really know!

Is Adiabatic Limit Achievable?Is Adiabatic Limit Achievable?• Even if there is some lower bound on Even if there is some lower bound on ccSS, it seems we , it seems we

can have can have SSmademade 0 as 0 as t t ..

• What factors may prevent this?What factors may prevent this?– Any lower bound >0 on the number of irreversible bit-Any lower bound >0 on the number of irreversible bit-

operations performed. (Each has operations performed. (Each has SSmade made 1.) 1.)• Fortunately, the lower bound can always be made 0.Fortunately, the lower bound can always be made 0.

– Any lower bound on the rate of energy Any lower bound on the rate of energy leakageleakage, even when , even when system is completely stopped.system is completely stopped.

– Any upper bound on the Any upper bound on the QQ of the clocking & synchronization of the clocking & synchronization system.system.

• The system dissipates The system dissipates EEfreefree//QQ on every cycle. on every cycle.• No technology-independent upper bounds on No technology-independent upper bounds on QQ known known

Some SynonymsSome Synonyms• LeakageLeakage of energy or (equivalently) probability of energy or (equivalently) probability

mass out of a desired configuration or mass out of a desired configuration or trajectory.trajectory.

• Occurrence of errorsOccurrence of errors in the desired analog or in the desired analog or digital state of a system. (Motion away from digital state of a system. (Motion away from desired states.)desired states.)

• DecayDecay of structureof structure of a structured system. (The of a structured system. (The state departs from desired state.)state departs from desired state.)

Leakage = Error = Decay

Perfect Mechanisms?Perfect Mechanisms?• If a structured system is If a structured system is perfectlyperfectly closed closed,,

– I.e.I.e. non-interacting with other systems, at all! non-interacting with other systems, at all!– AndAnd if its internal interactions are if its internal interactions are perfectlyperfectly known, known,

• Then,Then, and only then, is its (von Neumann) entropy going and only then, is its (von Neumann) entropy going to be a constant.to be a constant.

• Otherwise,Otherwise, its entropy will continuously increase as we its entropy will continuously increase as we lose track of its state.lose track of its state.– In this case, In this case, no mechanism is perfect,no mechanism is perfect, in that some of its in that some of its

energy (energy (i.e.i.e. some probability mass) is always leaking away some probability mass) is always leaking away from the desired trajector(y/ies) at some nonzero base rate, from the desired trajector(y/ies) at some nonzero base rate, even when the rate of system’s progress along its even when the rate of system’s progress along its trajectory is zero.trajectory is zero.

Leakage LimitsLeakage Limits• Claim: Claim: NoNo real, structured system can have absolutely real, structured system can have absolutely

zerozero rate of energy leakage out of its desired trajectories, rate of energy leakage out of its desired trajectories, even if not moving.even if not moving.

• However:However: No general, No general,technology-independenttechnology-independentlower bound onlower bound onleakage ratesleakage ratesis known (otheris known (otherthan zero.)than zero.)

• Engineering advances Engineering advances mightmightmake leakage as small as desired.make leakage as small as desired.

Config-uration

Energy that hasleaked from desired

configuration

Time

Quantifying LeakageQuantifying Leakage• For a given structured system:For a given structured system:• Leakage power:Leakage power: PPleakleak = = dEdEleakleak / / dtdt

• Spontaneous entropy generation rate:Spontaneous entropy generation rate:SSleakleak = = dSdSleakleak / / dtdt

• Again, note Again, note PPleakleak = = SSleakleak · · TT at temperature at temperature TT..

•

•

Ways to Decrease LeakageWays to Decrease Leakage• Have high potential-energy barriersHave high potential-energy barriers

– slows down thermally excited leakage exponentiallyslows down thermally excited leakage exponentially• Have Have thickthick potential-energy barriers potential-energy barriers

– slows down quantum tunneling exponentiallyslows down quantum tunneling exponentially• Example: Older generations of CMOS!Example: Older generations of CMOS!• Mechanical (clockwork) systems have high Mechanical (clockwork) systems have high

potential energy barriers, for their size:potential energy barriers, for their size:– Decay may require atoms to diffuse out of tightly-Decay may require atoms to diffuse out of tightly-

bonded spots.bonded spots.– Mechanisms that avoid making/breaking contacts Mechanisms that avoid making/breaking contacts

((e.g.e.g. buckled logic) avoid losses due to buckled logic) avoid losses due to stictionstiction..

Limits of Adiabatics II:Limits of Adiabatics II:LeakageLeakage

Minimum Losses w. LeakageMinimum Losses w. Leakage

S

leak

E

leakopt c

S

c

Pt

Sleak

Eleak

2

2

cST

cP

Eleak = Pleak·tr

Eadia = cE / tr

Etot = Eadia + Eleak

Minimum Loss DerivationMinimum Loss Derivation

leakEr

leakE2r

2rleakE

tot

leak2rE

r

rleak

r

rE

r

leakadia

r

tot

/

/

minimum) is (when 0

/

d

)d(

d

)/d(

d

)d(

d

d

Pct

Pct

tPc

E

Ptc

t

tP

t

tc

t

EE

t

E

Eleak

EleakEleak

leakEleakEleakE

rleakrEmin

2

//

/

cP

cPcP

PcPcPc

tPtcE

Leakage in CMOSLeakage in CMOS• In a given technology with constant-field scaling, In a given technology with constant-field scaling,

leakage becomes worse at smaller scales leakage becomes worse at smaller scales because:because:– Energy barriers between states are lowerEnergy barriers between states are lower

• Higher rates of thermally-induced leakage, at given Higher rates of thermally-induced leakage, at given TT• Higher rates of quantum tunneling (temp.-independent)Higher rates of quantum tunneling (temp.-independent)

– Energy barriers between states are narrowerEnergy barriers between states are narrower• Higher rates of quantum tunnelingHigher rates of quantum tunneling

– These effects get worse exponentially with 1/length These effects get worse exponentially with 1/length (doubly-exponentially with time)(doubly-exponentially with time)

• Need alt. technologies w. high energy barriers!Need alt. technologies w. high energy barriers!

Future Techs. w. Low Leakage?Future Techs. w. Low Leakage?• How can we achieve low entropy coefficients in How can we achieve low entropy coefficients in

minimum-scale (atomic-scale) devices?minimum-scale (atomic-scale) devices?– Need high energy barriers:Need high energy barriers:

• Can achieve using atomic (not just electronic) interactions:Can achieve using atomic (not just electronic) interactions:– E.g.E.g. mechanical logics (rod logic, buckling logic) mechanical logics (rod logic, buckling logic)– If strong bonds (If strong bonds (e.g.e.g. C-C) are used in structure, rates of unwanted C-C) are used in structure, rates of unwanted

bond breakage can made be very low.bond breakage can made be very low.– Rate for an atom passing Rate for an atom passing throughthrough another one ( another one (e.g.e.g. knobs in rod knobs in rod

logic) is logic) is extremelyextremely low due to low due to » height of barrier: strength of Coulombic & fermionic height of barrier: strength of Coulombic & fermionic

repulsion between electrons, &repulsion between electrons, &» width of barrier: large number of particles involvedwidth of barrier: large number of particles involved

• Other possibilities?Other possibilities?

Minimum Dissipation with Variable Minimum Dissipation with Variable VV

• Notice that this function of V approaches 0 exponentially as V→∞, – This is even true if we scale CV!

• Thus, there is Thus, there is nono lower limit to the energy lower limit to the energy dissipation of adiabatic field-effect circuits!dissipation of adiabatic field-effect circuits!– The key is to make devices The key is to make devices largerlarger, not smaller!, not smaller!

• Device sizes need grow only logarithmically.Device sizes need grow only logarithmically.

T

T

T

V

V

V

Elk

CV

VC

kVCkV

cPE

2/2

/42

2/321

min

e2

e2

/2e2

2

TV

lklk

kV

VIP/3

21 e

T

T

V

Vlk

kV

II

/221

/max

e

e

kVC

RVCcE

/2 2

22

kV

IVR

/2

/ max

221

max kVI

Maximum Maximum QQ factor in terms of factor in terms of VV• The maximum logic The maximum logic QQ factor is the maximum factor is the maximum

ratio between the energy involved in carrying ratio between the energy involved in carrying out a logical transition, and the energy out a logical transition, and the energy dissipated by the circuit during the transition.dissipated by the circuit during the transition.– We just calculated the minimum energy dissipated.We just calculated the minimum energy dissipated.

• Thus, Thus, QQmaxmax = = EEinvolvedinvolved//EEdiss,mindiss,min

= ½ = ½CVCV22/(2/(2CVCV22exp(exp(−−VV/2/2φφTT))))

= (1/4)exp( = (1/4)exp(VV/2/2φφTT))– Note that the maximum logic Note that the maximum logic QQ-factor goes up -factor goes up

exponentially with the logic-swing voltage exponentially with the logic-swing voltage VV..

Minimum energy & Minimum energy & RRoffoff//RRonon ratio ratio• (A simpler version of earlier derivation.) Note that:(A simpler version of earlier derivation.) Note that:

ccEE = = CC22VV22RRonon

and if the dominant leakage mode is source/drain, then:and if the dominant leakage mode is source/drain, then:PPleakleak = = VV22//RRoffoff

• So putting the two together:So putting the two together:ccEEPPleakleak = = CC22VV44((RRonon//RRoffoff))

EEminmin = 2( = 2(ccEEPPleakleak))1/21/2 = 2 = 2CVCV22((RRonon//RRoffoff))1/21/2

• So we can rederive the maximum logic So we can rederive the maximum logic QQ as follows: as follows:QQmaxmax = ½ = ½CVCV22 / (2 / (2CVCV22((RRonon//RRoffoff))1/21/2))

= ¼(= ¼(RRoffoff//RRonon))1/21/2

= ¼(= ¼(IImaxmax//IIleakleak))1/21/2

= ¼(= ¼(rron/offon/off))1/21/2

Limits of Adiabatics III:Limits of Adiabatics III:Clock/Power SuppliesClock/Power Supplies

See transparencies.See transparencies.

Timing in Adiabatic SystemsTiming in Adiabatic SystemsWhen multiple adiabatic devices interact, the relative When multiple adiabatic devices interact, the relative timingtiming must be must be

precise, in order to ensure that adiabatic rules are met.precise, in order to ensure that adiabatic rules are met.

• There are two basic approaches to timing:There are two basic approaches to timing:– GlobalGlobal (a.k.a. (a.k.a. clockedclocked, a.k.a. , a.k.a. synchronoussynchronous) timing:) timing:

• This is the approach in nearly all conventional irreversible CPUs.This is the approach in nearly all conventional irreversible CPUs.• Also is the basis for all practical adiabatic and quantum computing Also is the basis for all practical adiabatic and quantum computing

mechanisms that have been proposed to date.mechanisms that have been proposed to date.– LocalLocal (a.k.a. (a.k.a. self-timedself-timed, a.k.a. , a.k.a. asynchronousasynchronous) timing:) timing:

• Implemented in a few commercial irreversible chips.Implemented in a few commercial irreversible chips.• Feynman ‘86 showed that a self-timed Feynman ‘86 showed that a self-timed serialserial reversible computation reversible computation

was implementable in QM, in principle.was implementable in QM, in principle.• Margolus ‘90 extended this to a 2-D model with 1-D of parallelism. - Margolus ‘90 extended this to a 2-D model with 1-D of parallelism. -

Can it still work in a full 3-D, fully-quantum-mechanical?Can it still work in a full 3-D, fully-quantum-mechanical?– Indications from considering classical-mechanical 3D meshes of coupled Indications from considering classical-mechanical 3D meshes of coupled

oscillators is “yes.”oscillators is “yes.”

Global TimingGlobal Timing• Examples of adiabatic systems designed on the Examples of adiabatic systems designed on the

basis of global, synchronous timing:basis of global, synchronous timing:– Adiabatic CMOS with external power/clock railsAdiabatic CMOS with external power/clock rails– Superconducting parametric quantron (Likharev)Superconducting parametric quantron (Likharev)– Adiabatic Quantum-Dot Cellular Automaton (Lent)Adiabatic Quantum-Dot Cellular Automaton (Lent)– Adiabatic mechanical logics (Merkle, Drexler)Adiabatic mechanical logics (Merkle, Drexler)– All proposed quantum computersAll proposed quantum computers

• A potential problem: Synchronous timing may A potential problem: Synchronous timing may not scale well to large machine sizes.not scale well to large machine sizes.– Work by Janzig & others raises issues of possible Work by Janzig & others raises issues of possible

limits on timing systems due to quantum uncertainty.limits on timing systems due to quantum uncertainty.• Issue is still unresolved.Issue is still unresolved.

Clock/Power Supply DesiderataClock/Power Supply Desiderata• Here are some requirements for a good adiabatic timing Here are some requirements for a good adiabatic timing

signal / power supply for driving voltage-coded logic:signal / power supply for driving voltage-coded logic:– Generate a trapezoidal voltage waveform with Generate a trapezoidal voltage waveform with very flatvery flat

high/low regions.high/low regions.• Needed to avoid current through transistors when turning them offNeeded to avoid current through transistors when turning them off• The flatness of the signal limits the maximum The flatness of the signal limits the maximum QQ factor of the logic. factor of the logic.• Waveform during the highWaveform during the high↔↔low transitions should low transitions should ideallyideally be linear, be linear,

– But this does But this does not not affect the maximum logic affect the maximum logic QQ, , onlyonly the energy coefficient. the energy coefficient.» So long as ramp slope scales down everywhere with transition time.So long as ramp slope scales down everywhere with transition time.

– Operate resonantly with the logic circuit, with a high Operate resonantly with the logic circuit, with a high Q Q factor.factor.• The power supply’s The power supply’s QQ will limit the overall system will limit the overall system QQ

– If possible, scale If possible, scale QQ tt (cycle time) (cycle time)• Required to be considered an Required to be considered an adiabaticadiabatic mechanism. mechanism.• May conflict w. inductor scaling laws!May conflict w. inductor scaling laws!• At the least, At the least, QQ should still be high at leakage-limited speed should still be high at leakage-limited speed

– Have a reasonable cost, compared to the logic it powers.Have a reasonable cost, compared to the logic it powers.– Be scalable to large meshes of mutually synchronized devices.Be scalable to large meshes of mutually synchronized devices.

Supply concepts in my researchSupply concepts in my research• Superpose several sinusoidal signals from Superpose several sinusoidal signals from

phase-synchronized oscillators at harmonics of phase-synchronized oscillators at harmonics of fundamental frequencyfundamental frequency– Weight these frequency components as per Fourier Weight these frequency components as per Fourier

transform of desired waveformtransform of desired waveform

• Create relatively high-Create relatively high-LL integrated inductors via integrated inductors via vertical, helical metal coilsvertical, helical metal coils– Only thin oxide layers between turnsOnly thin oxide layers between turns

• Use mechanically oscillating, capacitive MEMS Use mechanically oscillating, capacitive MEMS structures structures in vacuoin vacuo as high- as high-QQ (~10k) oscillator (~10k) oscillator– Use geometry to get desired wave shape directlyUse geometry to get desired wave shape directly

Early supply conceptsEarly supply concepts• Inductors & switches.Inductors & switches.

– See transparency.See transparency.

• Stepwise charging.Stepwise charging.– See transparency.See transparency.

Newer Supply ConceptsNewer Supply Concepts• Transmission-line-based adiabatic resonators.Transmission-line-based adiabatic resonators.

– See transparency.See transparency.

• MEMS-based resonant power supplyMEMS-based resonant power supply– See next couple of slidesSee next couple of slides

• Ideal adiabatic supplies - Can they exist?Ideal adiabatic supplies - Can they exist?– Idealized mechanical model: See transparency.Idealized mechanical model: See transparency.– But, there may be quantum limits to But, there may be quantum limits to

reusability/scalability of global timing signals.reusability/scalability of global timing signals.• This is a very fundamental issue!This is a very fundamental issue!

MEMS/NEMS ResonatorsMEMS/NEMS Resonators

A Novel Clock/Power Supply A Novel Clock/Power Supply Technology for Adiabatic CircuitsTechnology for Adiabatic Circuits

MEMS/NEMS ResonatorsMEMS/NEMS Resonators• State of the art of technology demonstrated in State of the art of technology demonstrated in

lab:lab:– Frequencies up to the 100s of MHz, even GHzFrequencies up to the 100s of MHz, even GHz– QQ’s >10,000 in vacuum, several thousand even in air!’s >10,000 in vacuum, several thousand even in air!

• Rapidly becoming Rapidly becoming technology of choicetechnology of choicefor commercial RF for commercial RF filters, filters, etc.etc., in , in communicationscommunicationsSoC (Systems-on-SoC (Systems-on-a-Chip) a-Chip) e.g.e.g. for for cellphones.cellphones.

U. Mich., poly, U. Mich., poly, ff=156 MHz, =156 MHz, QQ=9,400=9,400

34 µm

• Energy storedEnergy storedmechanically.mechanically.

• Variable couplingVariable couplingstrength strength →→ custom customwave shape.wave shape.

• Can reduce lossesCan reduce lossesthrough balancing,through balancing,filtering.filtering.

A MEMS Supply ConceptA MEMS Supply Concept

Limits of Adiabatics:Limits of Adiabatics:SummarySummary

Some final remarks.Some final remarks.

Summary of Limiting FactorsSummary of Limiting FactorsWhen considering adiabaticizing a system, ask:When considering adiabaticizing a system, ask:• What fraction of system power is in logic?What fraction of system power is in logic? ffLL

– Vs. Displays, transmitters, propulsion.Vs. Displays, transmitters, propulsion.

• What fraction of logic is done adiabatically?What fraction of logic is done adiabatically? ffaa

– Can be all, but w. cost-efficiency overheads.Can be all, but w. cost-efficiency overheads.

• How large is the How large is the IIonon//IIoffoff ratio of switches? ratio of switches?– Affects leakage & minimum adiabatic energy.Affects leakage & minimum adiabatic energy.

• What is the What is the QQsupsup of the resonant power supply? of the resonant power supply?

• What is the relative cost of energy / logic?What is the relative cost of energy / logic? rr$$

– E.g.E.g. decreasing power cost by decreasing power cost by rr$$ by increasing by increasing

HW cost by HW cost by rr$$ will not help. will not help. “Power premium”“Power premium”

Minimizing cost/performanceMinimizing cost/performance• $$PP = Cost of power in original system = Cost of power in original system

• $$HH = Cost of logic HW in original system = Cost of logic HW in original system

• $$PP = = rr$$$$HH; ; $$HH = = $$PP//rr$$

• For cost-efficiency inverse to energy savings:For cost-efficiency inverse to energy savings:• $$tot,mintot,min = = $$PPrr$$

−−1/21/2 + + $$HHrr$$1/21/2

= 2 = 2 $$PPrr$$−−1/21/2

• $$tot,origtot,orig = = $$PP + + $$HH = (1+ = (1+rr$$))$$HH = ((1+ = ((1+rr$$)/)/rr$$) ) $$PP

• $$tot,origtot,orig//$$tot,mintot,min = ½(1+ = ½(1+rr$$))rr$$−−1/21/2

½ ½rr$$1/21/2 for large for large rr$$

Summary of adiabatic limitsSummary of adiabatic limits• Cost-effective adiabatic energy savings factorCost-effective adiabatic energy savings factor::

SSaa = = EEconvconv / / EEadiaadia in cost-effective adiabatic systemin cost-effective adiabatic system

• Some rough upper bounds on Some rough upper bounds on SSaa::

SSaa ~ 1/(1 ~ 1/(1ffLL))

SSaa ~ 1/(1 ~ 1/(1ffaa))

SSaa ~ ¼( ~ ¼(rron/offon/off))1/21/2

SSaa QQsupsup

SSaa ~ ~ rr$$1/21/2 (worse for non-ideal apps)(worse for non-ideal apps)

• ButBut, this ignores benefits from adiabatics of , this ignores benefits from adiabatics of denser packing & smaller communications delays denser packing & smaller communications delays in parallel algorithms. in parallel algorithms. (More later.) (More later.)