Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y...
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Course Notes
E&CE 730
Physics and Modeling of Semiconductor Devices
Table of Contents
1 Semiconductor Physics Review 1
2 PN-Junction Diodes 39
3 Bipolar Transistors 94
3 MOS Transistors 198
Prepared by:
Professor John S. HamelDepartment of Electrical & Computer Engineering
University of WaterlooWaterloo, Ontario, Canada
January, 2002
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ii
Principle Textbook References:
References
[Bipolar Diode and Transistor Physics] D. Roulston, Bipolar Semiconductor
Devices. McGraw Hill, 1990, TK7871.86.R68
[MOS Transistor Physics] Y. P. Tsividis, Operation and Modeling of the MOS
Transistor. McGraw-Hill, international edition ed., 1988, TK7871.99.M44T77
[Bipolar Transistor Modeling] I. Getreu, Modeling the bipolar transistor. NewYork, NY: Elselvier, 1978, TK7871.96.B55G47
[MOS Transistor Modeling] N. Arora,MOSFET Models for VLSI Circuit Sim-
ulation, Theory and Pratice. Springer-Verlag, 1993, TK7871.95.A76
[SPICE Models for Diodes, Bipolar, and MOS Transistors] P. Antognettiand G. Massobrio, Semiconductor Device Modeling with SPICE. McGraw Hill,1987, TK7867.S46
[Thin Film Transistors] David W. Greve, Field E�ect Devices and Applications
Prentice Hall, 1998, TK7871.95.G74 (pp. 276-288)
Additional References:
References
[1] P. Ashburn, Design and Realization of Bipolar Transistors. John Wiley & Sons,1988.
[2] J.Lindmayer and C. Wrigley, Fundamentals of Semiconductor Devices. VanNostrand, 1965.
[3] T. Ning and D. Tang, \Method of determining the emitter and base series resis-tances of bipolar transistors," IEEE Transactions on Electron Devices, vol. 31,pp. 409{412, apr 1984.
[4] J.-S. Park, A. Neugroschel, V. de la Torre, and P. Zdebel, \Measurement ofcollector and emitter resistances in bipolar transistors," IEEE Transactions on
Electron Devices, vol. 38, pp. 365{372, February 1991.
[5] Y. P. Tsividis, The MOS Transistor. McGraw-Hill, international edition ed.,1988.
[6] S. Sze, Physics of Semiconductor Devices. John Wiley & Sons, 2 ed., 1981.
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[7] B. Johnson, T. Quarles, A. Newton, D. Pederson, and A. Sangiovanni-Vincentelli, SPICE3 Version 3e User's Manual. Department of Electrical Engi-neering and Computer Sciences, University of California, Berkeley, USA, 1991.
[8] B. Sheu, D. Scharfetter, P.-K. Ko, and M.-C. Jeng, \BSIM: Berkeley short-channel IGFET model for MOS transistors," IEEE Transactions of Solid-State
Circuits, vol. sc-22, pp. 558{565, August 1987.
[9] W. Liu, X. Jin, J. Chen, M.-C. Jeng, Z. Liu, Y.Cheng, K. Chen, M. Chan,K. Hui, J. Huang, R. Tu, P. K. Ko, and C. Hu, BSIM3v3.2 MOSFET Model
User's Manual. Department of Electrical Engineering and Computer Sciences,University of California, Berkeley, USA, 1998.
[10] BSIM3 Website: http://www-device.eecs.berkeley.edu/~bsim3/
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Physical Constants
Electronic charge q = 1:6� 10�19CPlanck's constant h = 6:63� 10�34JsThermal voltage (300oK) VT = kT=q = = 0:026VElectron volt 1eV = 1:6� 10�19JAvogadro's number N = 6:02� 1026kg�1
Velocity of light c = 2:998� 108ms�1
Electronic rest mass mo = 9:11� 10�31kgPermittivity of free space �o = 8:85� 10�12Fm�1
= 8:85� 10�14Fcm�1
Permeability of free space �o = 4� � 10�7Hm�1
Boltzmann's constant k = 1:38� 10�23JoK�1
= 8:617� 10�5eV oK�1
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Properties of Some Common Semiconductors and SiO2 at 300o K
Property Si Ge GaAs InSb GaP SiO2
Atomic 28:09 72:60 144:6 236:6 100:7(molecular)weightAtomic density 5� 1022 4:4� 1022 2:21� 1022 2:9� 1022 4:94� 1022
(cm�3)Lattice 0:543 0:566 0:565 0:648 0:545constant (nm)Density 2:33 5:32 5:32 5:79 4:13 � 2:2 (depends upon(g cm�2) processing conditions)Melting 1415 937 1238 525 1470 � 1600point (oC)Energy gap (eV ) 1:12 0:67 1:424 0:18 2:26 8Gap type Indirect Indirect Direct Direct IndirectE�ectivedensity of states:� Nc (cm
�3) 2:8� 1019 1:04� 1019 4:7� 1017 | 1:7� 1019
� Nv (cm�3) 1:04� 1019 6:0� 1018 7:0� 1018 | 2:25� 1019
Intrinsic carrierconcentrationni (cm
�3) 1:5� 1010 2:4� 1013 2� 106 � 1016 8Relative 11:8 16 13:1 15:9 10:2 � 3:85 (depends upondielectric process conditions)constant (�r) (dielectric constant �s = �r�o)Mobility (cm2V �1s�1)(intrinsicsemiconductor)� electron (�n) 1350 3900 8500 8� 104 300� hole (�p) 480 1900 450 1250 150E�ective mass (kg):� electrons (me) 0:33mo 0:22mo 0:063mo
� holes (mh) 0:5mo 0:31mo 0:5mo
Breakdown � 3� 105 � 1� 105 � 4� 105 � 1� 107
electric�eld (V cm�1)
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SPICE 2G Bipolar Transistor Model Parameters
Basic D.C. Parameters
IS Saturation CurrentBF Maximum ideal d.c. forward common-emitter current
gainBR Maximum ideal d.c. reverse common-emitter current
gainNF Forward collector current ideality factorNR reverse collector current ideality factor
Basic A.C. Parameters
RC Collector resistanceRE Emitter resistanceRB Base resistanceIRB Current where base resistance falls halfway
between its maximum and minimum valueRBM Minimum high current value of base resistanceCJE Zero bias emitter-base junction capacitanceVJE Emitter-base built-in junction voltageMJE Emitter-base capacitance voltage exponentCJC Zero bias collector-base junction capacitanceVJC Collector-base built-in junction voltageMJC Collector-base capacitance voltage exponentCJS Zero bias collector-substrate junction capacitanceVJS Collector-substrate built-in junction voltageMJS Collector-substrate capacitance voltage exponentFC CoeÆcient for depletion capacitance in forward biasTF Forward transit timeTR Reverse transit time
Gummel-Poon Model Parameters
IKF Knee current for forward current gain roll-o� athigh currents
IKR Knee current for reverse current gain roll-o� athigh currents
VAF Forward Early voltageVAR Reverse Early voltageXTF CoeÆcient to model impact of lateral base
widening on forward transit time at high currentsVTF Voltage describing dependence of forward transit time
on VBC under saturation conditionsISE Saturation current for emitter-base junction leakageNE Low forward base current ideality factorISC Saturation current for collector-base junction leakageNC Low reverse base current ideality factor
Additional Parameters
EG Semiconductor bandgap to model temperaturedependence of IS
XTI Temperature exponent for e�ect on ISXTB forward and reverse gain temperature coeÆcient
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vii
PTF excess phase shift in a.c. current gain at thetransition frequency
KF Flicker noise coeÆcientAF Flicker noise exponent
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viii
Parameters for SPICE MOSFET Models Levels 1,2 and 3
SPICE Default TypicalSymbol Keyword LEVEL Parameter Description Value Value UnitsVTO VTO 1-3 Zero-bias threshold voltage 1.0 1.0 VKP KP 1-3 Transconductance parameter 2� 10�5 3� 10�5 A=V 2
GAMMA 1-3 Body-e�ect parameter 0.0 0.35 V 1=2
2�F PHI 1-3 Surface inversion potential 0.6 0.65 V� LAMBDA 1,2 Channel length modulation 0.0 0.02 V �1
tox TOX 1-3 Gate oxide thickness 1� 10�7 1� 10�7 mNA NSUB 1-3 Substrate doping 0.0 1� 1015 cm�3
NSS NSS 2,3 Surface state density 0.0 1� 1010 cm�2
NFS NFS 2,3 Surface fast state density 0.0 1� 1010 cm�2
Neff NEFF 2 Total channel charge coeÆcient 1 5 |Xj XJ 2,3 Source/drain vertical junction depth 0.0 1� 10�6 mLD LD 1-3 Source/drain lateral di�usion length 0.0 0:8� 10�6 mTPG TPG 2,3 Type of gate material 1 1 |�o UO 1-3 Surface mobility 600 700 cm2=(V:s)Uc UCRIT 2 Critical electric �eld for mobility 1� 104 1� 104 V=cmUe UEXP 2 Exponential coeÆcient for mobility 0.0 0.1 |Ut UTRA 2 Transverse �eld coeÆcient 0.0 0.5 |
XQC 2,3 CoeÆcient of channel charge share 0.0 0.4 |vmax VMAX 2,3 Maximum carrier drift velocity 0.0 5� 104 m=secÆ DELTA 2,3 Width e�ect on threshold voltage 0.0 1.0 |� ETA 3 Static feedback on threshold voltage 0.0 1.0 |� THETA 3 Mobility modulation 0.0 0.5 V �1
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Parameters for SPICE MOSFET Models Levels 1,2 and 3 (continued)AF AF 1-3 Flicker noise exponent 1.0 1.2 |KF KF 1-3 Flicker noise coeÆcient 0.0 1� 10�26 |IS IS 1-3 Bulk junction saturation current 1� 10�14 1� 10�15 AJS JS 1-3 Bulk junction saturation current 0.0 1� 10�8 A
per unit area�j PB 1-3 Bulk junction potential 0.8 0.75 VCj CJ 1-3 Zero-bias bulk capacitance 0.0 2� 10�4 F=m2
per unit areaMj MJ 1-3 Bulk-junction grading coeÆcient 0.5 0.5 |Cjsw CJSW 1-3 Zero-bias junction perimeter 0.0 1� 10�9 F/m
capacitance per unit lengthFC 1-3 Bulk junction forward bias 0.5 0.5 |
coeÆcientCGBO CGBO 1-3 Gate-bulk overlap capacitance 0.0 2� 10�10 F=m
per unit lengthCGDO CGDO 1-3 Gate-drain overlap capacitance 0.0 4� 10�11 F=m
per unit lengthCGSO CGSO 1-3 Gate-source overlap capacitance 0.0 4� 10�11 F=m
per unit lengthRD RD 1-3 Drain series resistance 0.0 10.0 RS RS 1-3 Source series resistance 0.0 10.0 Rsh RSH 1-3 Source/drain sheet resistance 0.0 30.0 per square
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x
Parameters for SPICE MOSFET Models Levels 4 (BSIM)
SPICE Length/WidthSymbol Keyword Parameter Description Units DependencyVfb VFB Flat-band voltage V yes2�F PHI Surface inversion potential V yes
K1 K1 Body e�ect coeÆcient V 1=2 yesK2 K2 Drain/source depletion charge-sharing coeÆcient | yes� ETA Zero-bias drain-induced barrier-lowering coeÆcient | yes
MUZ Zero-bias mobility cm2=V � s�L DL Shortening of channel length �m�W DW Narrowing of channel width �mUo UO Zero-bias transverse-�eld mobility degradation coeÆcient V �1 yesU1 U1 Zero-bias velocity saturation coeÆcient �m=V yes
X2MZ Sensitivity of mobility to substrate biasat VDS = 0 cm2=V 2
� s yesX2E Sensitivity of drain-induced barrier lowering e�ect to
substrate bias V �1 yesX3E Sensitivity of drain-induced barrier lowering e�ect
to drain bias at VDS = VDD V �1 yesX2U0 Sensitivity of transverse �eld mobility degradation e�ect
to substrate bias V �2 yesX2U1 Sensitivity of velocity saturation e�ect
to substrate bias �mV �2 yesMUS Mobility at zero substrate bias and at VDS = VDD cm2=V 2
� sX2MS Sensitivity of mobility to substrate bias
at VDS = VDD cm2=V 2� s yes
X3MS Sensitivity of mobility to drain bias at VDS = VDD cm2=V 2� s yes
X3U1 Sensitivity of velocity saturation e�ectto drain bias at VDS = VDD �m=V 2
tox TOX Gate oxide thickness �mT TEMP Temperature at which parameters were measured oC
VDD VDD Measurement bias range VCGDO CGDO Gate-drain overlap capacitance per channel width F=mCGSO CGSO Gate-source overlap capacitance per channel width F=mCGBO CGBO Gate-bulk overlap capacitance per channel length F=m
XPART gate-oxide capacitance-charge model ag |no NO Zero-bias subthreshold slope coeÆcient | yesnb NB Sensitivity of subthreshold slope to substrate bias | yesnd NB Sensitivity of subthreshold slope to drain bias | yesRsh RSH Drain and source di�usion sheet resistance per squareJs JS Source/drain junction current density A=m2
PB Built-in potential of source/drain junction VMJ Grading coeÆcient of source/drain junction |
PBSW Built-in potential of source/drain junction sidewall VMJSW Grading coeÆcient of source/drain junction sidewall |
Cj CJ Source/drain junction capacitance per unit area F=m2
Cjsw CJSW Source/drain junction sidewall capacitance per unit length F=mWDF Source/drain junction default width mDELL Source/drain junction length reduction m
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Semiconductor Physics Review, E&CE 730, January, 2002 1
1 Semiconductor Physics Review
E&CE 730Physics & Modeling of Semiconductor Devices
Prepared by:
Professor John S. HamelDepartment of Elecrtrical & Computer Engineering
University of WaterlooWaterloo, Ontario, Canada, N2L 3G1
January, 2002
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Semiconductor Physics Review, E&CE 730, January, 2002 2
Semiconductor Physics Review
Metals, Insulators, and Semiconductors
� When atoms combine to form solids, the outer most electrons (valence
electrons) of each atom interact between atoms to form bonds.
� Since quantum mechanics forbids electrons from occupying the same
precise quantum state, the allowed energies of the valence electrons
from all atoms comprising the crystal spread out into an energy band
called the valence band.
� The next allowed energy state of each individual atom in the solid also
spreads out due to the interaction between atoms forming another
higher energy band called the conduction band.
� If the temperature is above zero degrees Kelvin, electrons can be ex-
cited from the valence band to the conduction band leaving a vacant
position or hole in the valence band that appears to be a positively
charged particle.
� The di�erence in energy between the valence and conduction band
edges is known as the bandgap Eg.
� An insulator has a much larger bandgap than a semiconductor or metal
and is therefore much less conductive.
� A metal has a negative bandgap since the bottom of the conduction
band is lower in energy than the highest energy level in the valence
band resulting in a considerable number of electrons in the conduction
band giving rise to a high electrical conductivity.
� A semiconductor has a positive bandgap somewhere between that of
a metal and an insulator.
� A full or empty energy band cannot conduct electricity since there are
no vacant positions in the full band for electrons to move to and there
are no electrons available in an empty band for conduction.
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Semiconductor Physics Review, E&CE 730, January, 2002 3
� A partially �lled energy band therefore is required to conduct electric-
ity, such as when some electrons transition from the valence band to
the conduction band.
ValenceBand
ConductionBand
ValenceBand
ConductionBand
Conduction
Band
Valence
Band
Eg
Eg (e.g. 8 eV)
Metal
Insulator
Semiconductor
(e.g. 1.12 eV for Silicon)
a)
c)
b)
o0 K
Valence and Conduction Bands for a) metal, b) insulator, and c)
semiconductor
Intrinsic and Extrinsic Semiconductors
� A semiconductor in which there are only the atoms which comprise
the semiconductor crystal (e.g. silicon atoms) is considered to be in-
trinsic.
� An intrinsic semiconductor has the same number for free electrons and
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Semiconductor Physics Review, E&CE 730, January, 2002 4
holes since to create a free electron in the conduction band, an electron
must leave a hole behind in the valance band.
n = p = ni
� Since intrinsic semiconductors have very low conductivity at room tem-
perature, small quantities of impurity dopants (e.g. Phosphorus, (P),
Arsenic (As), and Boron (B) used in silicon and germanium) are in-
troduced to increase the number of free electrons or holes.
� An n-type dopant atom contains one more valence electron than the
semiconductor atoms (e.g. P, As in silicon) and therefore donates an
extra electron to the conduction band if it replaces a silicon atom in
the crystal lattice.
� A p-type dopant atom contains one less valence electron than the semi-
conductor atoms (e.g. B in silicon) and therefore leaves a vacancy or
hole in the valance band if it replaces a silicon atom in the crystal
lattice.
� Doped semiconductors are called extrinsic.
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Semiconductor Physics Review, E&CE 730, January, 2002 5
+4 . . +4 . . +4
..
..
+4
..
. . . .
..
+4
..
..
+4 . . +4 . . +4
+5
. . . .
..
..
..
. . . .
..
..
. . . .
.
+3
+4 +4+4
+4
+4+4+4
+4
extra hole
.
extra electron
Donor Impurity
a)bond
silicon atom
b)
Acceptor Impurity
Crystal structure of silicon with a silicon atom displaced by a) a donor
impurity, and b) an acceptor impurity.
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Semiconductor Physics Review, E&CE 730, January, 2002 6
E cEd
E v
E c
E v
|E = 1.12 eVg
|E = 1.12 eVg
Conduction Band Conduction Band
Valence BandValence Band
aE
0.05 eV 0.05 eV
Energy
Donor Level
AceeptorLevel
a) b)
n-type silicon p-type silicon
Energy band diagram of a) an n-type semiconductor and b) a p-type
semiconductor
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Semiconductor Physics Review, E&CE 730, January, 2002 7
Direct and Indirect Bandgap Semiconductors
� Free electrons and holes in a semiconductor can be thought of as wave
packets in quantum mechanical terms.
� A wavenumber k can be associated with the free electrons and holes
that is proportional to the carrier momentum p such that,
p =h
�=hk
2�
� The crystalline structure and the type of atoms in the semiconductor
determine the relationship between what combinations of energy and
momentum an electron or hole can travel through the crystal in a
particular direction without being interfered with.
� These relationships between energy and momentum are referred to as
dispersion curves, E versus k diagrams, or energy band
diagrams.
� If the bottom of the conduction band in the E versus k diagram cor-
responds to the top of valence band at the same momentum, then the
semiconductor is referred to as an direct bandgap semiconduc-
tor.
� If the bottom of the conduction band in the E versus k diagram does
not correspond to the top of valence band at the same momentum, then
the semiconductor is referred to as an indirect bandgap semicon-
ductor.
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Semiconductor Physics Review, E&CE 730, January, 2002 8
Eg
Conduction
Band
Valence
Semiconductor
E
kEg
Conduction
Band
Valence
Direct Bandgap
Semiconductor
E
k
Indirect Bandgap
a) b)
(1.42 eV for GaAs) (1.12 eV for Si)
Energy Band Diagram with E versus k for a) GaAs and b) Silicon
� The simplest approximation assumes that E depends upon the square
of the momentum resulting in parabolic shaped conduction and valence
bands.
E =1
2mv2 classical kinetic energy of a particle
/ (mv)2 = p2 classical momentum squared
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Semiconductor Physics Review, E&CE 730, January, 2002 9
E = quantum kinetic energy of a particle
/ p2 / k2 quantum momentum squared
� The periodic electric potentials presented to free electrons and holes
by the charged nuclei of semiconductor crystal atoms in uence their
motions making them appear to have less mass than the actual rest
mass of a free electron in a vacuum.
� Electrons and holes are therefore assigned e�ective mass me and
mh that are expressed as fractions of the rest electron mass mo.
me(Si) = 0:33mo; mh(Si) = 0:5mo
Free Carrier Densities:
Fermi Distribution, Density of States
� To determine how many free electrons there are in the conduction
band and how many free holes there are in the valence band at a given
temperature it is necessary to know two things:
1. How many states are available for electrons and holes at a particular
energy level (density of states function Ne(E), Nh(E)).
2. The probability that an electron will exist at a particular energy
level (Fermi Probability Distribution f(E)).
� The probability that a hole will exist at an energy level in the valence
band is given by (1� f(E)) since a hole is the absence of an electron.
� Actual electron and hole concentrations are given by the product of
the density of states and the probability functions for the particular
carrier type.
� Assuming that energy in the conduction and valence bands is propor-
tional to the square of the momentum (parabolic band approximation):
Ne(E) =4�
h3(2me)
3=2(E �Ec)1=2
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Semiconductor Physics Review, E&CE 730, January, 2002 10
Nh(E) =4�
h3(2mh)
3=2(Ev �E)1=2
� h = Planck's constant, me and mh = e�ective masses of electrons and
holes, Ec and Ev = bottom and top of conduction and valence energy
band.
� Fermi Distribution f(E) is given by:
f(E) =1
exp ((E �Ef)=kT ) + 1
� Ef is called the Fermi Energy Level and is de�ned as the energy
where there is a 1/2 probability that an electron will exist at that
energy level.
� If Ef � E, one obtains Boltzmann Statistics where f(E) is
approximated by:
f(E) � exp ((Ef �E)=kT )
oKoK
oK
f(E)1.00.50.0
Ef
E
T = 0 degrees Kelvin
100
300
400
Behaviour of Fermi-Dirac Distribution f(E) at di�erent
temperatures
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Semiconductor Physics Review, E&CE 730, January, 2002 11
� Electron Density per unit volume is obtain by integrating the product
of the density of states function for electrons Ne(E) and the probabil-
ity of occupation function for electrons f(E) over all energies in the
conduction band:
no =Z1
Ecf(E)Ne(E)dE
= Nc exp
0B@(Ef �Ec)
kT
1CA if Ef < (Ec � 3kT )
� Likewise, integrating the product of the density of states function for
holes Nh(E) and the probability of occupation function for holes (1�f(E)) over all available energies in the valence band, gives the hole
concentration in the valence band:
po =Z Ev1
(1� f(E))Nh(E)dE
= Nv exp
0B@(Ev �Ef)
kT
1CA if Ef > (Ev + 3kT )
� po is the equilibrium free hole concentration that is determined by
thermally generated holes and doping.
� no is the equilibrium free electron concentration that is determined by
thermally generated electrons and doping.
![Page 22: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/22.jpg)
Semiconductor Physics Review, E&CE 730, January, 2002 12
area = n i
area = n i
N (E)e
N (E)h
N (E)e
N (E)h
Ec
Ei
Ev
f(E)
E EE
kT
kT
a) b) c)
0.5 1.00.0 (1-f(E))
f(E)
a) Density of States Function N(E), b) Fermi-Dirac Function f(E), c)
Product of N(E)f(E) with shaded areas representing intrinsic carrier
concentration ni
![Page 23: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/23.jpg)
Semiconductor Physics Review, E&CE 730, January, 2002 13
area = p n
N (E)h
N (E)h(1-f(E))
N (E)e N (E)
ef(E)E
c
Ev
f(E)
E EE
a) b) c)
0.0
Ef E d
area = n n
0.5 1.0
Extrinsic carrier dependence on position of Fermi level in conduction and
valence bands.
� Nc and Nv are called the e�ective densities of energy states per
unit volume for electrons and holes, respectively.
Nc = 2
0@2�mekT
h2
1A3=2
Nv = 2
0@2�mhkT
h2
1A3=2
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Semiconductor Physics Review, E&CE 730, January, 2002 14
� The Mass Action Law is obtain by multiplying n and p to obtain:
nopo = NcNv exp
0@�Eg
kT
1A = n2i
� Eg = Ec �Ev is the bandgap
� For an intrinsic semiconductor n = p = ni.
� Therefore, for an intrinsic semiconductor one can write,
no = ni = Nc exp
0B@(Ei � Ec)
kT
1CA
po = ni = Nv exp
0B@(Ev � Ei)
kT
1CA
� For an intrinsic semiconductor Ef � Ei, where Ei is approximately
halfway between Ev and Ec or in the mid-gap energy position.
� For an extrinsic semiconductor one can then write,
no = ni exp
0B@(Ef �Ei)
kT
1CA
po = ni exp
0B@(Ei �Ef)
kT
1CA
� The Mass Action Law also holds for extrinsic semiconductors since
nopo is independent of the Fermi Level.
� The Mass Action Law is valid for thermal equilibrium conditions
which implies no current ow or optical generation of excess free elec-
trons or holes.
� The Fermi Level Ef can be used to indicate the number of electrons
and holes.
� As Ef approaches Ec the number of free excess electrons increases,
but the number of free excess holes decreases.
� As Ef approaches Ev the number of free excess holes increases, but
the number of free excess electrons decreases.
![Page 25: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/25.jpg)
Semiconductor Physics Review, E&CE 730, January, 2002 15
� Doping the semiconductor n-type therefore increases the number of
excess free electrons while simultaneously decreasing the number of
excess free holes in accordance with the Mass Action Law.
� The reverse is true for p-type doping.� If a semiconductor contains both n-type and p-type impurities that are
uniformly distributed throughout the semiconductor, then the number
of free electrons and holes per unit volume can be determined by re-
alising that the total net charge anywhere in the semiconductor must
sum to zero (Charge Neutrality Condition) such that,
no +N�
a = po +N+d
� Solving the Mass Action Law and Charge Neutrality Equations gives,
no =1
2
"(Nd �Na) +
r(Nd �Na)2 + 4n2i
#
po =1
2
"(Na �Nd) +
r(Na �Nd)2 + 4n2i
#
� If Nd � Na and Nd � ni, then no � Nd, po � n2i=Nd
� If Na � Nd and Na � ni, then po � Na, no � n2i=Na
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Semiconductor Physics Review, E&CE 730, January, 2002 16
T( K)o
n
N
n
d
100 200 300 400 500 600 7000
ni
Intrinsic
(Si)-3
N = 1x10 cm16
d
Ionization Freezeout
n
N
n
d
Extrinsic
Range
1.0
Electron density to donor concentration ratio as a function of
temperature for silicon
� Excess free electrons and holes can be introduced into the semiconduc-
tor above the equilibrium concentrations by either electrical injection
or optical generation.
� The electrical injection and/or optical generation of excess electrons
and holes places the semiconductor out of thermal equilibrium.
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Semiconductor Physics Review, E&CE 730, January, 2002 17
� p̂ is the concentration of excess holes per unit volume above the equi-
librium value.
� n̂ is the concentration of excess electrons per unit volume above the
equilibrium value.
� The total number of free holes is equal to the excess plus the equilib-
rium value such that,
p = p̂ + po
� The total number of free electrons is equal to the excess plus the equi-librium value such that,
n = n̂ + no
� If excess electrons and holes are either injected or optically generated
than the pn product will be greater than nopo = n2i given by the Mass
Action Law.
Current Flow Mechanisms
� There are two mechanisms responsible for current ow within a semi-
conductor:
1. Drift Current - caused by applied electric �eld.
2. Di�usion Current - caused by free carrier concentration gradi-
ents.
Drift Current
� For zero applied electric �eld E = 0, thermal energy causes free carriers
to accelerate thereby resulting in the carriers gaining kinetic energy.
The accelerated carriers then lose the energy by being forced to change
direction (i.e. scattered) by the presence of charged and neutral atoms
in the semiconductor. This process of acceleration and de-acceleration
is repeated continuously.
� The net movement of thermally excited carriers results in zero cur-
rent ow in any particular direction since the direction of accelerated
motion is random.
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Semiconductor Physics Review, E&CE 730, January, 2002 18
� If an electric �eld is applied, then this random thermal motion tends
to drift in the direction dictated by E .� The average thermal velocity vth imparted to free carriers thermally
is limited by the frequency with which carriers collide with atoms and
the temperature.
� vth � 107cm=sec for silicon.
Zero Electric Field
a)
Non-Zero Electric Field
b)
Typical path of electrons in a semiconductor crystal a) for no electric
�eld, and b) with electric �eld.
� On average, a free carrier cannot be accelerated in a semiconductor
by an externally applied electric �eld to a velocity faster than vthwhich sets a fundamental limit on the switching speed of conventional
semiconductor devices such as bipolar and MOS transistors.
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Semiconductor Physics Review, E&CE 730, January, 2002 19
� For low electric �elds, where the drift velocity vd is much less than
vth, it can be assumed that vd depends linearly upon E such that,
vd = �E� � is referred to as the carrier mobility.
Drift Velocity 10 cm/sec6
10
20
1.0 2.0
Electric Field 10 V/cm4
Electron (Si)
Hole (Si)
Electron (GaAs)
Drift velocity as a function of the electric �eld.
![Page 30: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/30.jpg)
Semiconductor Physics Review, E&CE 730, January, 2002 20
� The mobility depends upon many factors including:
1. the e�ective mass of the free carrier
2. the type of semiconductor
3. the concentration of impurity dopant atoms
4. the temperature
� Since the e�ective masses of electrons and holes are di�erent, a mobility
for electrons �n and for holes �p must be de�ned.
� The e�ective masses for electrons and holes take into account the in u-
ence of the periodic potential of the semiconductor lattice atom nuclei
on the movement of free carriers.
� Temperature causes the lattice atoms in the semiconductor to vibrate
about their central lattice sites which further reduces the mobility of
carriers | Lattice or Phonon Scattering.
� Ionised and therefore charged �xed impurity dopant atoms further
reduce mobility | Impurity Scattering.
� As temperature increases, the impact of lattice scattering becomes
greater.
� As temperature decreases, the impact of impurity scattering becomes
greater.
� In highly doped semiconductors at lower temperatures, the mobility is
limited by impurity scattering mechanisms.
� In lightly doped semiconductors at higher temperatures, the mobility
is limited by lattice scattering mechanisms.
� The total mobility for a particular carrier is determined empirically by,
1
�=
1
�I+
1
�L
� �I is the mobility if carrier scattering were only in uenced by impurity
scattering.
![Page 31: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/31.jpg)
Semiconductor Physics Review, E&CE 730, January, 2002 21
� �L is the mobility if carrier scattering were only in uenced by lattice
atom scattering.
T
Mobility Limited by
Impurity Scattering OnlyMobility
Scattering Only
Mobility Limited by Lattice
Mobility as a function of temperature in silicon.
![Page 32: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/32.jpg)
Semiconductor Physics Review, E&CE 730, January, 2002 22
N = 10 cm-313
d
Temperature, K
100 200 300 400 50010
10
2
104
3
Electron
Mobilty
cm /V.sec2
5 x 10
10
10
10
18
18
17
16
Mobility variation with temperature showing the e�ect of lattice and
impurity scattering.
![Page 33: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/33.jpg)
Semiconductor Physics Review, E&CE 730, January, 2002 23
102
103
104
102
103
104
102
103
104
Impurity Concentration, cm-3
Mobility, cm /V-sec
1014
1015
1016
1017
1018
1019
2
Ge
Si
GaAs
T = 300 K
electron
hole
electron
electron
hole
hole
Electron and hole mobilities versus impurity concentration for Ge, Si,
and GaAs at 300 K.
� Electron drift current is given by,
In = �qAnvd = qAn�nE� Hole drift current is given by,
Ip = qApvd = qAp�pE� A is the cross-sectional area perpendicular to current ow.
� Electron current moves opposite to the positive electric �eld and posi-
tive current is de�ned as the direction of positive charge ow which is
![Page 34: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/34.jpg)
Semiconductor Physics Review, E&CE 730, January, 2002 24
opposite to negative electron ow.
� Hole and electron currents add together to form the total current I =
In + Ip.
In
In
A
L
-3n, cm
Current conduction in a semiconductor bar.
� The resistance of a bar of semiconductor of cross-sectional area A and
length L, and that is uniformly doped with Nd and Na impurities per
unit volume is given by,
R =V
I=
V
qA(p�p + n�n)E=
V
qA(p�p + n�n)V=L
=L
qA(p�p + n�n)
= �L
A
![Page 35: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/35.jpg)
Semiconductor Physics Review, E&CE 730, January, 2002 25
� � is the resistivity in ohm� cm and is given by,
� =1
q(p�p + n�n)� cm
� � is the conductivity and is given by,
� =1
��1cm�1
10 1010
1
10
10
10
1016 18 2014
-4
-2
2
Impurity Concentration, cm-3
p GaAs
p Si
n Sin GaAs
T = 300 K
Resistivity, ohm-cm
Resistivity versus impurity concentration in Si and GaAs at 300 K.
� Sheet ResistanceRs is the resistance of a square of a semiconductor
layer of thickness t such that,
Rs = �L
A= �
L
t� L=�
t per square
� Sheet resistance is a convenient parameter with which to calculate
the total resistance of layers of semiconducting material that have a
complicated shape.
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Semiconductor Physics Review, E&CE 730, January, 2002 26
I
t
LL
Area = L t
Resistivity
A single square of semiconductor layer for sheet resistance calculation
Di�usion Current
� Di�usion is a phenomenon whereby particles in regions of high con-
centration tend to move to regions of lower concentration thereby con-
stituting a di�usion current.
� Free excess electrons and holes will di�use from regions of higher con-
centration to regions of lower concentration, the rate of ow depending
upon the slope of the concentration as a function of position.
� Electron di�usion current In is given by,
In = qADndn
dx
� Hole di�usion current Ip is given by,
Ip = �qADpdp
dx
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Semiconductor Physics Review, E&CE 730, January, 2002 27
� Dn and Dp are the electron and hole di�usivities, respectively.
� Di�usivity is related to mobility by Einstein's Relation:
Dn =kT
q�n; Dp =
kT
q�p;
kT
q� VT
� VT is called theThermal Voltage, and is the equivalent voltage that
would have to be applied externally to obtain a drift current equal to
that which is caused by thermally driven di�usion current.
� VT � 26mV at room temperature of 300o K.
Total Current
� Total electron and hole current is the sum of the drift and di�usion
components such that,
In = qA
0@�nnE +Dn
dn
dx
1A
Ip = qA
0@�ppE �Dp
dp
dx
1A
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Semiconductor Physics Review, E&CE 730, January, 2002 28
Generation and Recombination of Excess Carriers
� Generation is the process of creating electron-hole pairs by exciting
an electron from the valence band into the conduction band thereby
simultaneously creating a free electron and hole.
� Generation can by caused both thermally and optically.
� Recombination is the process whereby a free electron in the conduc-
tion band moves back into a vacant position (hole) in the valence band,
whereby a free excess electron and hole are annihilated simultaneously.
> E gh
E
E
c
v
GL
Gth
Rth
U
Band-to-band generation and recombination of electron-hole pairs in a
semiconductor
� Under thermal equilibrium conditions, the rate of thermal generation
of free electron-hole pairs Gth exactly equals the rate of recombination
Rth.
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Semiconductor Physics Review, E&CE 730, January, 2002 29
� If excess electrons and/or holes, in excess of the background thermal
equilibrium values, are introduced to the semiconductor by either op-
tical generation at a rate of G or electrical injection, then there will be
additional recombination of carriers at a rate of U as the semiconductor
will attempt to regain thermal equilibrium conditions.
� To optically generate excess carriers, a photon with at least enough
energy to equal the bandgap energy Eg must excite an electron from
the valence band into the conduction band such that,
Ephoton = h� =hc
�� Eg
� � is the frequency of light, c is the speed of light, and � is the wave-
length of light.
� Excess electrons and holes can recombine by either direct or indirect
recombination mechanisms.
� Before recombination can occur, the electron and hole must have the
same momentum since momentum must always be conserved in any
physical process.
� If an electron and hole can recombine without any change in momen-
tum, then the recombination is considered to be direct.
� If an electron can recombine directly, then the energy loss by the elec-
tron will be equal to the bandgap energy Eg which is radiated as visible
light in the form of a photon.
� Indirect recombination occurs if either the electron or hole need to
experience a loss in momentum before recombination is possible.
� The change in momentum is usually accompanied by a loss of energy
as well to a third entity preventing the emission of a photon during
the recombination process.
� One entity that can carry away excess momentum are lattice atom
vibrations which can be thought of as particles called phonons.
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Semiconductor Physics Review, E&CE 730, January, 2002 30
� Recombination which involves phonons results in the excess electron
energy being converted into increased lattice vibration which is dissi-
pated as heat.
Eg
Conduction
Band
Valence
Semiconductor
E
kEg
Conduction
Band
Valence
Direct Bandgap
Semiconductor
E
k
Indirect Bandgap
a) b)
(1.42 eV for GaAs) (1.12 eV for Si)
Energy Band Diagram with E versus k for a) GaAs and b) Silicon
� Direct recombination is only possible in semiconductors in which the
lowest energy in the conduction band coincides with the same momen-
tum k as the highest energy level in the valence band.
� These types of semiconductors are called direct bandgap semicon-
ductors (e.g. GaAs).
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Semiconductor Physics Review, E&CE 730, January, 2002 31
� Semiconductors in which the lowest energy level in the conduction
band does not coincide with the same momentum as the highest en-
ergy level in the valence band are known as indirect bandgap semi-
conductors e.g. (Si, Ge).
� Indirect recombination mechanisms dominate in indirect bandgap semi-
conductors making these semiconductors ineÆcient generators of visi-
ble light.
� Phonon-assisted recombination in indirect bandgap semiconductors
does not occur with a very high probability.
� Another entity, referred to as traps, is principally responsible for car-
rier recombination in indirect semiconductors.
� A trap is caused by defects in crystalline structure or certain foreign
impurities (such as metals) that enable an electron or hole to exist at
an energy level in the forbidden gap.
� A trap can therefore capture or trap an electron and a hole to facilitate
recombination.
� A trap assisted recombination will not in general produce visible light
since the energy given o� by the electrons and holes is less than the
bandgap and is usually too small for a visible photon to emerge.
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Semiconductor Physics Review, E&CE 730, January, 2002 32
Valence Band
Conduction Band
Ev
Ef
Ei
E c
E t
1 2
3 4
Generation and recombination via intermediate states or traps
� Trap assisted indirect recombination is the most common form of re-
combination in indirect semiconductors and can be calculated using
the Shockley-Read-Hall (SRH) formula:
U =cmNt(pn� n2i )
n + p + 2ni cosh[(Et �Ei)=kT ]
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Semiconductor Physics Review, E&CE 730, January, 2002 33
� cm is a capture cross-section area, Nt is the concentration of trapping
centres per unit volume, and Et is the allowed energy level of the trap
in the forbidden gap.
� Maximum recombination rate per unit volume of excess carriers U
occurs if the trap energy Et is halfway between the conduction and
valance band edges (i.e. Et = Ei).
� It can be shown that if there are many more excess electrons than
excess holes n � p and n � ni, then recombination is controlled by
the number of excess holes (which are minority carriers) such that,
Up =p̂n�p
� For the opposite case where p � n the recombination rate per unit
volume of excess electrons (which are minority carriers) is,
Un =n̂p�n
� �p and �n are called the hole and electron lifetimes and represent the
average length of time that a free excess hole or electron is expected
to exist before recombining.
� Indirect recombination can also occur at the surface of a semiconduc-
tor.
� In addition to the types of unwanted impurities (e.g. metal ions) that
are found in the bulk of a semiconductor, traps at the surface can
result from unsatis�ed semiconductor atom bonds (dangling bonds)
which gives rise to surface states.
� Most of these dangling bonds can be passivated by the growth of oxide
(e.g. SiO2) at the surface greatly reducing the amount of indirect
carrier recombination at the semiconductor surface.
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Semiconductor Physics Review, E&CE 730, January, 2002 34
a)
b)
x
p
x=0
Surface States
p
pn
E v
Ec
no
Surface
A semiconductor surface depicting the minority carrier distribution
in the vicinity of a surface with surface states.
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Semiconductor Physics Review, E&CE 730, January, 2002 35
Electro-Static Fields and Potentials in Semiconductors
� The electro-static �eld E is given by the negative of the gradient of the
electro-static potential or voltage .
E = �d dx
� Recognising that force F = qE and that work or energy E is de�ned
as force time distance one can write,
E =ZFdx = q
ZEdx = �q
Z d dxdx = �q
� A free electron at energy equal to the lowest available energy level in
the conduction band Ec has only potential energy.
� If an electric �eld is applied, then the free electron gains kinetic energy
which moves it upwards in energy in the conduction band.
� A free hole at energy equal to the highest available energy level in the
valence band Ev has only potential energy.
� If an electric �eld is applied, then the free hole gains kinetic energy
which moves it downwards in energy in the valence band.
� An electric �eld therefore has the e�ect of titling the energy bands as
a function of distance so that the lower energies correspond to higher
positive voltage.
� It is normal to de�ne the zero potential level in a semiconductor to
correspond in energy to the intrinsic energy level Ei midway between
the valence and conduction band edges such that,
= �Ei
q
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Semiconductor Physics Review, E&CE 730, January, 2002 36
potential energy
potential energy
kinetic energy
kinetic energy electric field
a) b)
E v
Ei
E c
Ev
Ei
Ec
of holes
of holes
of electrons
of electrons
Energy band diagram of a semiconductor with a) zero electric �eld, and
b) an electric �eld.
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Semiconductor Physics Review, E&CE 730, January, 2002 37
Poisson's Equation
� The potential or voltage within a semiconductor can be related to the
net charge at any location by Poisson's Equation,
@E@x
= �@2
@x2=q(p +N+
d � n�N�
a )
�s
� �s is the semiconductor permittivity and is given by the product of the
semiconductor relative permittivity �r and the permittivity of free
space �o such that,
�s = �o�r
� For silicon,�s = �o�r = (8:85� 10�14)(11:8) = 1:04� 10�12 Farads per cm
Continuity Equation
� Continuity equations can be written for holes and electrons in order to
keep track of how many holes and electrons are generated, recombine,
and pass through a particular region of a semiconductor from current
ow.
� The continuity equations can be derived by recognising that charge
must be conserved.
� The electron continuity equation is given by,
�1
q
@Jn@x
= G� Un � @n
@t
� The hole continuity equation is given by,
1
q
@Jp@x
= G� Up � @p
@t
� Jn and Jp are electron and hole current densities normalised with
respect to the cross-sectional area perpendicular to current ow.
![Page 48: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/48.jpg)
Semiconductor Physics Review, E&CE 730, January, 2002 38
J p(x)
q
x
x + x
q
J p
(x + x)
x
lim= 0 x
J p(x)
q q
J p
(x + x)1 1q
x
J p=
Up
x
p (x)
G
Current continuity in a semiconductor.
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PN -Junction Diodes, E&CE 730, January, 2002 39
2 PN-Junction Diodes
E&CE 730Physics & Modeling of Semiconductor Devices
Prepared by:
Professor John S. HamelDepartment of Elecrtrical & Computer Engineering
University of WaterlooWaterloo, Ontario, Canada, N2L 3G1
January, 2002
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PN -Junction Diodes, E&CE 730, January, 2002 40
The PN-Junction in Thermal Equilibrium
DonorAcceptorIon
Hole
IonElectron
Junction
Space Charge Layerp-neutral region n-neutral region
metalcontact
metal
n-sidep-side
contact
Formation of Space Charge Layers and Neutral Regions in a
PN -Junction Diode
� A pn-junction is formed when p-type and n-type semiconductors are
joined together.
� The mechanical boundary between the p and n sides is referred to as
the metallurgical junction or simply the junction.
� The concentration di�erence between holes on the p and n sides results
in holes on the p side near the junction di�using across the junction
to the n side.
� The concentration di�erence between electrons on the n and p sides
results in electrons on the n side near the junction di�using across the
junction to the p side.
� When the holes leave the p side they leave behind un-compensated
ionised acceptor dopant atoms which have a net negative charge.
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PN -Junction Diodes, E&CE 730, January, 2002 41
� When the electrons leave the n side they leave behind un-compensated
ionised donor dopant atoms which have a net positive charge.
� These charged ions (called space charge) give rise to an electric �eld
which eventually becomes large enough to oppose any further di�usion
of holes and electrons across the junction.
� The charged layer in the vicinity of the junction is referred to as the
space charge layer or depletion region since it is nearly depleted of
free electrons and holes.
� Actually, holes and electrons continue to di�use across the junction,
but the electric �eld in the space charge layer results in an opposing
drift current of holes and electrons in the opposite direction resulting in
zero net current in the pn-junction when no externally applied voltage
is present.
� Previously derived expressions for free equilibrium electron and hole
concentrations are given by,
no = ni exp
0@Ef �Ei
kT
1A ; po = ni exp
0@Ei � Ef
kT
1A
� Using V = �Ei=q and de�ning the fermi potential �f = Ef=q � 0
one can write,
no = ni exp
0@ VVT
1A ; po = ni exp
0@�VVT
1A
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PN -Junction Diodes, E&CE 730, January, 2002 42
x
0
-W p Wn
npo
pno
Metal
Contact
Metal
Contact
W
np
( x )p
n( x )
ppo
= N An
no= N
D
-W pnp
( ) Wnp
n( )
p-neutral region space charge layer n-neutral region
x
x
0
0 W
Co-ordinate Systems and Conventions Used for Space Charge Layer
and Neutral Regions in a PN -Junction Diode
� For a pn-junction with a space charge layer that is Wp wide on the p
side and Wn wide on the n side where x = 0 in the centre allows one
to write,
V (Wn) = VT ln
0B@no(Wn)
ni
1CA ; V (�Wp) = �VT ln
0B@po(�Wp)
ni
1CA
� The total potential drop across the junction or built-in voltage Vbi is,
Vbi = V (Wn)� V (�Wp) = VT ln
0B@no(Wn)po(�Wp)
n2i
1CA
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PN -Junction Diodes, E&CE 730, January, 2002 43
� For a uniformly doped p and n sides where p � n on the p side and
n� p on the n side, no(Wn) = ND and po(�Wp) = NA giving,
Vbi = V (Wn)� V (�Wp) = VT ln
0@NDNA
n2i
1A
Energy Band Diagrams for a PN-Junction
� If the Fermi energy level Ef is de�ned as the zero voltage level, then
the electric �eld E becomes the slope of the intrinsic energy level Ei
such that,
E =1
q
dEi
dx= �dV
dx
� where V is de�ned as,
V � �Ei
q
� Hole current density Jp is given by,
Jp = q�ppE � qDpdp
dx
� The di�usion component of hole current can be expressed in terms of
the Fermi and intrinsic levels such that,
qADpdp
dx= ADp
q
kT
0@dEi
dx� dEf
dx
1Ani exp
0@Ei �Ef
kT
1A
= ADppq
kT
0@dEi
dx� dEf
dx
1A
� Likewise, the drift component of hole current can be expressed as,
qA�ppE = Aq
kTDpp
dEi
dx
![Page 54: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/54.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 44
� Combining the drift and di�usion components of hole current one ob-
tains,
Jp = �ppdEf
dx
� Likewise, one can write for electron current,
Jn = �nndEf
dx
� Therefore, under thermal equilibrium conditions (zero current), the
Fermi level is constant with respect to position, or,
dEf
dx= 0
� It should be noted that, strictly, the concept of a Fermi level Ef is
only valid under thermal equilibrium conditions.
� The concept of a Fermi level can be extended to the case where current
is owing or when light is used to generate excess holes and electrons
such that carrier concentrations are above thermal equilibrium condi-
tion values.
� This is done using separate Quasi Fermi Levels for electrons and
holes.
� For a zero biased pn-junction diode, since no current ows, the Fermi
level must be constant everywhere in the diode.
� Since the Fermi level is constant, the conduction and valence bands
must vary with position across the space charge layer in order to align
with one another across the pn-junction.
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PN -Junction Diodes, E&CE 730, January, 2002 45
Ec
Ev
Ef
iE ( q n
)
qo
( q )p
c)
Ef
Ef
Ec
Ec
Ev
Ev
Ec
Ev
Ef
p-type
Ef
n-type
q(Nd
N a )
p-region
neutral
neutral
n-region
b)
neutral
p-region
neutral
n-region
Depletion Region
xBoundary
Layer
BoundaryLayer
d)
a)
a) Energy bands for isolated p- and n-type regions before contact, b)
Fermi-level alignment, c) energy band diagram after contact, and d)
depletion and neutral regions
![Page 56: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/56.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 46
Calculating Electric Field and Potential Distribution in an
Abrupt Uniformly Doped PN Junction Space Charge
Layer:
x
0
-W p Wn
npo
pno
Metal
Contact
Metal
Contact
W
np
( x )p
n( x )
ppo
= N An
no= N
D
-W pnp
( ) Wnp
n( )
p-neutral region space charge layer n-neutral region
x
x
0
0 W
Co-ordinate Systems and Conventions Used for Space Charge Layer and
Neutral Regions in a PN -Junction Diode
� Poisson's equation can be used to determine the nature of the internal
electric �eld, internal potential distribution, and width of the space
charge layer.
� To calculate the space charge layer width, the following approximations
will be made:
1. the space charge layer is completely depleted of free carriers | the
depletion approximation.
2. uniform doping on both sides.
3. an abrupt junction.
4. all the applied voltage is dropped across the space charge layer
which implies that the electric �eld outside the depletion region
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PN -Junction Diodes, E&CE 730, January, 2002 47
is zero and the regions outside the space charge layer are charge
neutral.
� Poisson's Equation:
dEdx
=q(p +N+
D � n�N�
A )
�s= �qd
2V
dx2
� for 0 < x < Wn:
dEdx
=qND
�s; En(x) = qNDx
�s+ C1; En(Wn) = 0 =) C1 =
�qNDWn
�s
� therefore,
En(x) = �qND
�s(Wn � x)
Vn(x) = �Z Wn
0En(x)dx =
qND
�s(Wnx� x2
2) + C2
=qND
2�s(2Wnx� x2) + C2
C2 =�qND
2�s(2W 2
n �W 2n) + Vn(Wn) =
�qND
2�sW 2
n + Vn(Wn)
Vn(x)� Vn(Wn) =�qND
2�s(W 2
n � 2Wnx + x2)
=�qND
2�s(Wn � x)2
� similarly, for �Wp < x < 0:
Ep(x) = �qNA
�s(Wp + x)
Vp(x)� V (�Wp) =qNA
2�s(Wp + x)2
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PN -Junction Diodes, E&CE 730, January, 2002 48
� at x = 0 (at the metallurgical junction) Vp(0) = Vn(0):
� therefore,
Vp(0)� Vp(�Wp)� Vn(0) + Vn(Wn) =qNA
2�sW 2
p +qND
2�sW 2
n
= Vbi (built{in voltage)
� at x = 0:
Ep(0) = En(0) =) NAWp = NDWn
� �nding Wn and Wp:
Vbi =qNAW
2p
2�s+qNDW
2n
2�s; Wn =
NA
NDWp
=
0B@qNA
2�s+qND
2�s
N 2A
N 2D
1CAW 2
p =q
2�s
0B@NA +
N 2A
ND
1CAW 2
p
=q
2�s
0B@NAND +N 2
A
ND
1CAW 2
p =q
2�s
0B@NA(ND +NA)
ND
1CAW 2
p
� therefore,
Wp =
vuuuut 2�sNDVbiqNA(ND +NA)
; Wn =
vuuuut 2�sNAVbiqND(ND +NA)
Wscl = Wp +Wn
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PN -Junction Diodes, E&CE 730, January, 2002 49
N d
W p
W nN a
dN N a
x
x
x
np
c)
b)
a)
m
p
nV
VVbi
0
0
0
The step pn junction showing a) space charge distribution, b) electric
�eld, and c) potential diagrams.
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PN -Junction Diodes, E&CE 730, January, 2002 50
Reverse Biased PN-Junction Diode
� if a voltage is applied to reverse bias the pn-junction (negative voltage
applied to the p-side and positive voltage applied to the n-side of the
diode), then the barrier voltage is e�ectively increased by the amount
of the applied reverse bias (VR) above the built-in voltage.
VR = applied reverse bias
Therefore, VR + Vbi =qNAW
2p
2�s+qNDW
2n
2�s
=) Wp =
vuuuut2�sND(Vbi + VR)
qNA(ND +NA)and Wn =
vuuuut2�sNA(Vbi + VR)
qND(ND +NA)
Junction Capacitance
� the space charge on either side of the junction in the depleted space
charge layer behaves electrically like a parallel plate capacitor.
� the following formula for junction capacitance is strictly valid only for
a fully depleted space charge layer. In reality, there are free carriers in
the space charge layer, particularly for forward bias, since electrons and
holes are being injected across the space charge layer under forward
bias conditions.
� the following formula for junction capacitance is most accurate for
reverse bias and can generally be used for low forward biases up to
approximately one half the built-in voltage.
Cj =dQp
dVR=dQn
dVR; Qp = qANAWp; Qn = qANDWp
� A = diode area, Qp = net positive charge on n-side of space charge
layer, and Qn = net negative charge on p-side of space charge layer.
Cj =dQp
dVR= qANA
dWp
dVR= qANA
d
dVR
8>>><>>>:
0B@ 2�sND
qNA(ND +NA)
1CA12
(Vbi + VR)12
9>>>=>>>;
![Page 61: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/61.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 51
= qANA
0@12
1A0B@ 2�sND
qNA(ND +NA)
1CA12
(Vbi + VR)�12
= A
0B@ q�sNAND
2(ND +NA)
1CA120@ 1
Vbi + VR
1A12
= A
0B@ q�sNAND
2(ND +NA)Vbi
1CA120B@ 1
1 + VR=Vbi
1CA12
=Cjo
(1 + VR=Vbi)12=
Cjo
(1� VF=Vbi)12
� VF = forward bias = �VR
Cjo
Cj
V biV bi /
Simple
More Accurate
Reverse Bias Forward Bias
Theory
Calculation
2 V A
Behaviour of pn junction depletion-layer capacitance Cj as a function of
bias voltage VR.
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PN -Junction Diodes, E&CE 730, January, 2002 52
Forward Biased PN-Junction Diode
----
------
+++++++
+++
F (drift)p
F (diff)p
F (diff)n
F (drift)n
o
o
+++++++
+++
----
------
F (diff)n
F (drift)n
F (diff)p
F (drift)p
oq( V)
qV
++
--
Hole
Electron
Energy
Energy
Depletion
Layer
p n
a)
---
+++
--
++
b)
Energy band diagram of the pn junction under a) thermal equilibrium,
and b) forward bias.
� the e�ect of applying a forward voltage bias (VF ) on the pn-junction
(positive voltage on the p-side and negative voltage on the n-side of
the diode) is to cause the built-in potential barrier to be lowered to an
amount Vbi � VF .
Principle of Detailed Balance
� concentration gradients of holes and electrons between n- and p-sides
result in holes di�using from p- to n-side and electrons di�using from
n- to p-side.
� the electric �eld in the space charge layer results in electrons drifting
from p- to n-side and holes drifting from n- to p-side.
� in thermal equilibrium (no bias), di�usion and drift currents are exactly
balanced and oppose one another to yield zero net ow of current in
the diode.
![Page 63: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/63.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 53
� if a forward bias voltage is applied, then the balance is upset in favour
of the di�usion currents.
� the e�ect of forward bias is to increase the concentrations of holes and
electrons at the space charge layer edges of the n-neutral and p-neutral
regions, respectively, above their thermal equilibrium values.
Carrier Concentrations in a Forward Biased PN Junction
Diode
x
0
-W p Wn
npo
pno
Metal
Contact
Metal
Contact
W
np
( x )p
n( x )
ppo
= N An
no= N
D
-W pnp
( ) Wnp
n( )
p-neutral region space charge layer n-neutral region
x
x
0
0 W
Carrier Concentrations at Edges of Space Charge Layer in Neutral
Regions in a PN -Junction Diode under Forward Bias Conditions
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PN -Junction Diodes, E&CE 730, January, 2002 54
nno = equilibrium electron concentration on n{side
ppo = equilibrium hole concentration on p{side
npo = equilibrium electron concentration on p{side
pno = equilibrium hole concentration on n{side
� Using the Mass Action Law (for zero bias):
nno(Wn)pno(Wn) = n2i ; ppo(�Wp)npo(�Wp) = n2i
Vbi = VT ln
0B@nno(Wn)ppo(�Wp)
n2i
1CA
= VT ln
0B@ nno(Wn)
npo(�Wp)
1CA
= VT ln
0B@ppo(�Wp)
pno(Wn)
1CA
� therefore for zero bias:
nno(Wn) = npo(�Wp) exp
0@VbiVT
1A
ppo(�Wp) = pno(Wn) exp
0@VbiVT
1A
� for forward bias VF :
nn(Wn) = np(�Wp) exp
0@Vbi � VF
VT
1A
pp(�Wp) = pn(Wn) exp
0@Vbi � VF
VT
1A
![Page 65: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/65.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 55
� for low to moderate forward bias:
nn(Wn) � nno(Wn) and pp(�Wp) � ppo(�Wp)
np(�Wp) = nno(Wn) exp
0@�VbiVT
1A exp
0@VFVT
1A = npo(�Wp) exp
0@VFVT
1A
� excess minority carrier electron concentration n̂p at the edge of the
p-neutral region near the space charge layer under forward bias condi-
tions is,
n̂p(�Wp) = np(�Wp)� npo(�Wp) = npo(�Wp)
24exp
0@VFVT
1A� 1
35
� also, for holes,
pn(Wn) = pno(Wn) exp
0@VFVT
1A
� therefore, the excessminority carrier hole concentration p̂n at the edge
of the n-neutral region near the space charge layer under forward bias
conditions is,
p̂n(Wn) = pn(Wn)� pno(Wn) = pno(Wn)
24exp
0@VFVT
1A� 1
35
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PN -Junction Diodes, E&CE 730, January, 2002 56
Di�usion Approximation
Metal
Contact
Metal
Contact
ppo
= N An
no= N
D
minority carriers minority carriers
p-neutral region space charge layer n-neutral region
majority carriers majority carriers
Majority Carrier Cancelation of Electric Fields in Neutral Regions | the
Di�usion Approximation
� to calculate the diode current that will result for a given forward bias
voltage VF , the diode can be split into a space charge layer (depleted
of free carriers) and neutral regions.
� the neutral regions are charge neutral in that there are an equal num-
ber of positive and negative charges per unit volume at all positions
within the neutral regions.
� when minority carriers are injected into a neutral region (e.g. holes
into the n-neutral region), charges of opposite sign must be added from
the metal contact to compensate the extra injected charge to maintain
charge neutrality.
� this compensation of injected minority carrier charge eliminates electric
�elds which would otherwise arise within the neutral region.
� if the impurity concentration in a neutral region is constant with posi-
tion (i.e. uniform), then to a good approximation only di�usion current
need be considered as drift current arising from electric �elds will be
negligible.
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PN -Junction Diodes, E&CE 730, January, 2002 57
D.C. Forward Current for a PN-Junction
Wide Diode Case
x
0
-W p Wn
npo
pno
Metal
Contact
Metal
Contact
W
ppo
= N An
no= N
D
pn
( 0 )
pn
( x )n
p( x )
np
( 0 )
p-neutral region space charge layer n-neutral region
x
x
0
0 W
Minority Carrier Distributions in Neutral Regions Under Forward Bias
Conditions
� in n{neutral region, neglecting hole drift current:
Ip(x) = qA(�ppnE �Dpdpndx
) � �qADpdpndx
� also,
� 1
qA
dIpdx
=pn � pno�p(x)
=p̂n(x)
�p(x)
� pn(x) =total minority carrier hole concentration in n{neutral region.
� p̂n(x) = excess minority carrier hole concentration in n{neutral region
� pn(x) = p̂n(x) + pno(x)
� �p(x) = position-dependent hole lifetime in n{neutral region
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PN -Junction Diodes, E&CE 730, January, 2002 58
� A = diode area
� for a uniformly doped pn junction (n-side doped ND),
pno(x) =n2iND
= constant
� therefore,dpndx
=dp̂ndx
; Ip(x) = �qADpp̂ndx
;�1qA
dIpdx
=p̂n(x)
�p(x)
� combining equations yields a second order linear di�erential equation:
Dpd2p̂ndx2
� p̂n�p
= 0
� re-arranging gives,d2p̂ndx2
� p̂nDp�p
= 0
� de�ne Lp �qDp�p which is called \Di�usion Length."
� the di�erential equation can then be written,
d2p̂ndx2
� p̂nL2p
= 0
� assume a form of the solution for p̂n(x) that is exponential:
p̂n(x) = C exp(mx); C = a constant
� therefore,dp̂ndx
= mC exp(mx);d2p̂ndx2
= m2C exp(mx)
� substituting the above into the di�erential equation yields:
m2C exp(mx)� C exp(mx)=L2p = 0
� solving for m yields:
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PN -Junction Diodes, E&CE 730, January, 2002 59
m2 =1
L2p
; m = � 1
Lp
� there are two possible values for m which implies that one needs two
constants of integration C such that the solution for p̂n(x) becomes,
p̂n(x) = C1 exp
0B@�xLp
1CA + C2 exp
0B@ xLp
1CA
� to �nd C1 and C2, one needs \boundary conditions":
� a \Wide" diode by de�nition means that all minority carriers will
recombine with majority carriers before reaching metal contact.
� therefore, the second part of solution involving C2 must always be zero
or,
p̂n(x = W ) = 0 =) C2 = 0
� the constant C1 can be determined from a knowledge of p̂n(0) which is
simply the value of the hole concentration injected into the n-neutral
region at the space charge layer edge.
� therefore,
C1 = p̂n(x = 0) = pno
24exp
0@VFVT
1A� 1
35
� therefore, for a wide diode:
p̂n(x) = pno
24exp
0@VFVT
1A� 1
35 exp
0B@�xLp
1CA
= p̂n(0) exp
0B@�xLp
1CA
� similarly in p{neutral region, for a wide diode:
n̂p(x0) = npo
24exp
0@VFVT
1A� 1
35 exp
0B@�x
0
Ln
1CA
= n̂p(00) exp
0B@�x
0
Ln
1CA
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PN -Junction Diodes, E&CE 730, January, 2002 60
� Ln �pDn�n
� a wide neutral region implies that the width of the neutral region is
much larger than the minority carrier di�usion length (i.e. W >> Lp
or W 0 >> Ln).
� the minority carrier currents then become:
� in the n-neutral region:
Ip(x) = �qADpdpndx
=qADpp̂n(0)
Lpexp
0B@�xLp
1CA
� in the p-neutral region:
In(x0) = qADn
dnpdx
=qADnn̂p(0
0)
Lnexp
0B@�x
0
Ln
1CA
� the total diode current ID is then:
ID = total current = �In(x0) + Ip(x) = In(x) + Ip(x)
� under d.c. bias conditions, the total diode current ID must be constant
everywhere in the external circuit and in the diode.
� neglecting space{charge layer recombination (i.e. hole and electron
currents are constant in space charge region), ID can be conveniently
calculated using the following method:
ID = Ip(x = 0) + In(x = 00) =qADpp̂n(0)
Lp+qADnn̂p(0
0)
Ln
=qADpn
2i
LpND
0@exp
0@VFVT
1A� 1
1A + qADnn
2i
LnNA
0@exp
0@VFVT
1A� 1
1A
= qAn2i
0B@ Dp
LpND+
Dn
LnNA
1CA0@exp
0@VFVT
1A� 1
1A = Io
0@exp
0@VFVT
1A� 1
1A
� if ND >> NA, then I � In(x = 00) =) total diode current is mostly
electron current due to di�usion of electrons in the p-neutral region.
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PN -Junction Diodes, E&CE 730, January, 2002 61
� if NA >> ND, then I � Ip(x = 0) =) total diode current is mostly
hole current due to di�usion of holes in the n-neutral region.
� for diodes where one side is doped much more heavily than the other
side, the low-doped side will determine the amount of current that will
ow for a given bias.
� If one assumes that there is no carrier recombination in the space
charge layer, the electron and hole currents will be constant with po-
sition in the space charge layer.
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PN -Junction Diodes, E&CE 730, January, 2002 62
x 0 0 x
p type
n
p
pno
p
n
n po
n type
a)
x 0
x 0
In
Ip
In
Ip
Ip
In
Ip
In
Carrier Concentration
Minority Carrier Currents
Space Charge
Layer
0 x
0 x
+
b)
c)
I =
Forward biased pn junction showing a) minority carrier distributions, b)
minority carrier currents, and c) electron and hole currents on both sides
of the junction in the neutral regions.
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PN -Junction Diodes, E&CE 730, January, 2002 63
Narrow Diode Case
( 0 )pn
edge
space charge layer
metal
contact
( )pn
x
n-type neutral region
0 W
ND
Minority Carrier Distribution in a Uniformly-Doped \Narrow" Neutral
Region
� if the width of a neutral region is much less than the minority carrier
di�usion length, then most of the minority carriers in that region will
di�use across the neutral region and recombine at the metal contact
instead of in the semiconductor.
� e.g. for holes in an n-type neutral region this condition implies that:
W << Lp =rDp�p
� mathematically, the assumption thatW << Lp is the same as assum-
ing in�nite minority carrier lifetime so that:
Dpd2p̂ndx2
� p̂n�p�= Dp
d2p̂ndx2
= 0:
� the same boundary conditions as for the wide diode are used for the
narrow diode case such that:
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PN -Junction Diodes, E&CE 730, January, 2002 64
p̂n(0) = pno
0@exp
0@VFVT
1A� 1
1A ; p̂n(W ) = 0
� the excess carriers at the metal contact are still assumed to be zero
since they will recombine at the metal contact.
� therefore the excess hole concentration in the n-neutral region for a
\narrow" neutral region becomes,
p̂n(x) = p̂n(0) 1� x
W
!
� the hole current in the n-neutral region is calculated, as before, at
x = 0.
Ip(x) = Ip(0) = �qADpdpndx
1Ax=0
= qADpp̂n(0)
W
=qADppno
W
0@exp
0@VFVT
1A� 1
1A =
qADpn2i
NDW
0@exp
0@VFVT
1A� 1
1A
� since there is no recombination of holes as they di�use across the n-
neutral region, the hole current given above is constant with respect
to position in the diode.
� if n{neutral region is also \narrow" (W 0 << Ln):
n̂p(x0) = n̂p(0
0)
0B@1� x0
W 0
1CA ; and
In(x0) = In(0
0) =qADnn
2i
NAW 0
0@exp
0@VFVT
1A� 1
1A
� it is possible to have a diode where one neutral region is \wide" and
the other is \narrow."
![Page 75: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/75.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 65
0 W n
n (0)p
p (0)n
P (W n )n
Depletion Layer
a)
+p n
0
b)
W p
A p+n diode with a short n neutral region showing a) structure, and b)
minority carrier distribution in the neutral regions, with the dashed line
corresponding to the hole distribution for a small surface recombination
velocity at the contact.
![Page 76: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/76.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 66
Reverse Bias Breakdown in PN-Junction Diodes
� two mechanisms are principally responsible for breakdown in reverse
biased pn-junction diodes:
1. Avalanche Breakdown
2. Zener Breakdown
x
0
-W p Wn
nno
ppo
= N A= N
D
Metal
Contact
Metal
Contact
W
npo
pno
p-neutral region space charge layer n-neutral region
x
x
0
0 W
np
( )xp
n( )x
Minority Carrier Charge Concentrations at Space Charge Layer
Edges Under Conditions of Reverse Bias
� to understand how Avalanche Breakdown occurs, it is �rst necessary
to consider the minority carrier concentrations at the edges of space
charge layers for reverse biased junctions.
� for VF << 0 (reverse bias):
p̂n(0) = pno
0@exp
0@VFVT
1A� 1
1A � �pno
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PN -Junction Diodes, E&CE 730, January, 2002 67
� therefore, pn(0) = total hole concentration at s.c.l. edge of n{neutral
region � pno � pno = 0 for large reverse bias.
� also, np(00) = total electron concentration at s.c.l. edge of p{neutral
region � npo � npo = 0 for large reverse bias.
� since np(00) and pn(0) are less than thermal equilibrium values under
reverse bias conditions, carriers are thermally generated within the
neutral region where pn(x) < pno in an attempt to re{attain equilib-
rium.2666664in thermal equilibrium pn = n2irecombination occurs if pn > n2igeneration occurs if pn < n2i
Avalanche Breakdown
� thermally generated carriers in the neutral region at the edges of the
space charge layer, where the total minority carrier concentrations are
less than thermal equilibrium values, are swept across a reverse biased
junction by the build-in electric �eld giving rise to a reverse leakage
current.
� these carriers are replaced by di�usion currents of minority carriers in
the neutral region.
� for reverse bias conditions (VF << 0) this source of leakage current is
given by,
I = Io
24exp
0@VFVT
1A� 1
35 = �Io
� additional leakage current results from carriers being thermally gener-
ated within the space charge layer.
� if the reverse electric �eld in the space charge layer is large enough
(e.g. > 3 � 105V=cm) electrons moving across the junction will gain
enough kinetic energy to ionise atoms creating electron-hole pairs.
� the newly created electron-hole pairs are also accelerated by the electric�eld which can lead to more ionisation and the creation of additional
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PN -Junction Diodes, E&CE 730, January, 2002 68
electron-hole pairs resulting in a chain reaction | avalanche multi-
plication process.
� avalanche multiplication is modeled empirically by,
M =1
1� (VR=VBR)n
� whereM is the multiplication factor, VR is the reverse bias, and VBRis the junction breakdown voltage.
� when VR = VBR, M approaches in�nity which implies that the diode
is in complete breakdown where current is limited only by external
resistance.
� n is an empirical factor which usually takes on values ranging from 3
to 6 for silicon devices.
� the maximum electric �eld Emax occurs at the metallurgical junction
in the space charge layer, and for a uniformly doped abrupt junction
is given by,
Emax =0B@2qNAND(Vbi + VR)
�s(NA +ND)
1CA1=2
� from the equation for maximum electric �eld it can be seen that VBRdecreases with increased doping.
� electric �eld lines tend to concentrate at curvatures in di�used pn-
junction resulting in higher electric �elds in these locations and there-
fore lower breakdown voltages than predicted by the above equation.
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PN -Junction Diodes, E&CE 730, January, 2002 69
reverse saturation
current
breakdown
voltage
VBR
0
I
VF
D
( Io
)
Reverse Bias Diode Current Depicting Breakdown Voltage
Concentrated Field Lines
in Curved Space Charge Layer RegionsIncreased Electric Field Line Density at Curved Sidewall Regions of a
PN -Junction
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PN -Junction Diodes, E&CE 730, January, 2002 70
Zener Breakdown
E c
Ec
q VR
p-side
n-side
Ef
Ef
E
tunneling electrons
E v
v
Electron Tunnelling from Valence Band to Conduction Band Through
Narrow Reverse Biased Space Charge Layer in Zener E�ect
� if the impurity concentrations in the vicinity of the junction are high
enough, then the space charge layer will become very narrow, even for
reverse bias voltages.
� if the space charge layer is narrow enough, electrons from the valence
band on the p-side can be made to tunnel through the potential barrier
of the space charge layer to the conduction band on the n-side resulting
in a reverse current which appears to be avalanche breakdown but is
actually reverse tunnelling current.
![Page 81: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/81.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 71
� for tunnelling to occur the reverse bias voltage must be such that �lledstates in the valence band are at the same energy level (or potential)
as empty states in the conduction band so that electrons can tunnel
from the valence band on the p-side to the the conduction band on the
n-side.
� diodes which break down at 6 volts or less are generally breaking downdue to the Zener e�ect.
� usually all diodes designed to be used in breakdown mode (e.g. voltage
references) are called Zener diodes, although only the ones which break
down at the lower voltages are actually doing so because of the reverse
tunnelling e�ect.
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PN -Junction Diodes, E&CE 730, January, 2002 72
Transient Diode Behaviour
( 0 )pn
( )pn
x
edge
space charge layer
metal
contact
pa
( x , )ω
p ( x , )ω ej tω
a
n-type neutral region
0 W
ND
A.C. Small Signal Minority Carrier Hole Distribution in an n-Neutral
Region
� stored minority carrier charge in the neutral regions of a pn-junction
diode contribute to capacitance, known as di�usion capacitance Cd,
in addition of the junction capacitance of the space charge layer.
� the di�usion capacitance can be determined from a small signal a.c.
solution to the time dependent minority carrier continuity equation in
each of the two neutral regions.
v(t) = time dependent applied bias
= d.c. bias plus small signal a.c. voltage
= VF + vaej!t
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PN -Junction Diodes, E&CE 730, January, 2002 73
� for uniform doping in the n-neutral region the hole current and conti-
nuity equations are,
Jp(x; t) = �qDpdp̂n(x; t)
dx;
1
q
@Jp(x; t)
@x= G� Up � @p̂n
@t
� the hole current equation gives,
dJp(x; t)
dx= �qDp
d2p̂n(x; t)
dx2
� if there is no light incident upon the semiconductor then G = 0.
� if there is no recombination in the neutral region (i.e W << Lp) then
Up = 0:
� under these conditions, the continuity equation for holes in the n-
neutral region yields a second order time-dependent di�erential equa-
tion (often called simply the time-dependent minority carrier continu-
ity equation):
Dpd2p̂n(x; t)
dx2� @p̂n(x; t)
@t= 0
� assuming the small signal approximation, the time-dependent hole con-
centration in the n-neutral region can be expressed as the addition of
a d.c. component and an a.c. component such that,
p̂n(x; t) = p̂n(x) + pa(x; !)ej!t
� pa(x; !) is the position and frequency dependent magnitude of time
varying minority carrier concentration in the n-neutral region.
� therefore, the small signal a.c. continuity equation becomes:
Dpd2pa(x; !)
dx2� j!pa(x; !) = 0
� to solve the small signal a.c. continuity equation assume that the
solution pa has the form C exp(mx; !).
![Page 84: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/84.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 74
dpadx
= mC exp(mx; !);d2padx2
= m2C exp(mx; !)
� substituting the above into the di�erential equation yields,
Dpm2C exp(mx; !)� j!C exp(mx; !) = 0
� therefore,
Dpm2 � j! = 0; m = �
vuuuutj!Dp
� the two solutions for m requires two constants C1 and C2.
� the position and frequency dependent amplitude of the time varying
changes in hole concentration in the n-neutral region then takes on the
form,
pa(x; !) = C1 exp
0BB@x
vuuuutj!Dp
1CCA + C2 exp
0BB@�x
vuuuutj!Dp
1CCA
� the boundary conditions are determined as follows:
� at the space charge layer edge (x = 0):
p̂n(0; t) = pno exp
0B@v(t)VT
1CA = pno exp
0B@VF + vae
j!t
VT
1CA
= pno exp
0@VFVT
1A exp
0B@vae
j!t
VT
1CA (for VF >> VT )
� pno exp
0@VFVT
1A0@1 + va
VTej!t
1A for va << VT
= p̂n(0) + pa(0; !)ej!t
![Page 85: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/85.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 75
� therefore,
pa(0; !) =vaVTpno exp
0@VFVT
1A
� at the metal contact (x = W ) where all the excess holes recombine
one obtains:
pa(W;!) = 0
� �nd C1 and C2 using above boundary conditions:
� let pa(0; !) � pa1; h =rj!=Dp; k = hW .
� at x = 0:
C1 + C2 = pa1; C2 = pa1 � C1
� at x = W :
C1ek + C2e
�k = 0; C1ek + (pa1 � C1)e
�k = 0
C1 =�pa1e�kek � e�k
; and C2 =pa1e
k
ek � e�k
� therefore,
pa(x; !) = pa(0; !)
0B@e
Whe�xh � e�Whexh
eWh � e�Wh
1CA
� a.c. hole current is given by:
jp(0; !) = �qDpdpadx
1Ax=0
= qDppa(0; !)h
0B@e
Wh + e�Wh
eWh � e�Wh
1CA
= qDp
0@ vaVT
1A pno exp
0@VFVT
1A0@ 1
W
1Avuuuutj!W
2
Dpcoth
vuuuutj!W2
Dp
� for diode area A:
![Page 86: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/86.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 76
ip(0; !) = Ip(0)
0@ vaVT
1Avuuuutj!W
2
Dpcoth
vuuuutj!W2
Dp
� y = diode input admittance:
y =ip(0)
va=
Ip(0)
VT
vuuuutj!W2
Dpcoth
vuuuutj!W2
Dp
= G(!) + j!Cdh(!)
� G(!) = frequency dependent input conductance.
� Cdh(!) = frequency dependent di�usion capacitance.
� di�usion capacitance =) capacitance due to stored minority carrier
charge in diode.
� using a Taylor Series Expansion for coth:
� (i.e. coth(u) = 1=u + u=3� : : :)
� letrj!W 2=Dp = u.
y =Ip(0)
VTu
0@1u+u
3� : : :
1A
=Ip(0)
VT
0B@1 + u2
3� : : :
1CA
� for low frequencies (!W 2=Dp << 1):
y � Ip(0)
VT
0B@1 + j!W 2
3Dp
1CA =
1
re
0B@1 + j!W 2
3Dp
1CA
=1
re+j!W 2
3reDp= G + j!Cdh
� where re = VT=Ip(0) = low frequency small signal a.c. diode input
resistance.
� Cdh = W 2=3reDp = low frequency small signal a.c. diode input ca-
pacitance.
![Page 87: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/87.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 77
Transit Time
( 0 )pn
edge
space charge layer
metal
contact
( )pn
x
Qh
n-type neutral region
0 W
ND
Stored Minority Carrier Hole Charge in a Uniformly Doped n-Neutral
Region
� total minority carrier charge stored in n{type neutral region:
Qh =qAp̂n(0)W
2(A = diode area)
� d.c. hole current is given by:
Ip(0) =qADpp̂n(0)
W
![Page 88: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/88.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 78
� the ratio of stored minority carrier charge to minority carrier current
yields:
Qh
Ip(0)=qAp̂n(0)W
2� W
qADpp̂n(0)=W 2
2Dp
� the ratio of Qh to Ip(0) has the units of time and can be thought of
as the length of time it takes to move Qh holes through the neutral
region from x = 0 to X = W
� this time constant is called transit time.
� transit time �h for holes in a uniformly doped narrow n-neutral region
is then given by:
�h =W 2
2Dp
� the di�usion capacitance associated with stored charge in the n-neutralregion Cdh can be re-written in terms of the transit time for holes such
that,
Cdh =1
re
0B@W
2
3Dp
1CA =
1
re
0@23�h
1A =
2
3gd�h
� gd is the low frequency small signal input conductance of the diode
and is given by:
gd =1
re=dIDdVF
=d(Io exp(VF=VT ))
dVF=IDVT
� in general there is also a transit time for electrons in p-neutral region
(�e)
![Page 89: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/89.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 79
� the total transit time of minority carriers in the diode �d is given by
the addition of the transit times for electrons in the p-neutral region
and the holes in the n-neutral region such that,
�d = �e + �h
� the total di�usion capacitance of the diode Cd is then given by the
addition of the di�usion capacitances associated with the electrons
and holes.
� for a uniformly doped diode where both the n- and p-neutral regions
are narrow, one obtains:
Cd = Cde + Cdh =2
3gd(�e + �h)
� where the individual electron and hole transit times are given by:
�e =(W 0)2
2Dn; �h =
W 2
2Dp
re C
jC
d
A.C. Small Signal Equivalent Circuit for a PN -Junction Diode
� Cj = junction capacitance, Cd = di�usion capacitance, re = input
resistance (a.c.)
![Page 90: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/90.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 80
Low Forward Bias
Space Charge Layer Recombination
0
n(x)
n(0)
p(0)
W p Wn
p(x)
x
space charge layer
Free Electron and Hole Concentrations in the Space Charge Layer of a
Forward Biased PN -Junction
� in forward bias, carriers are being injected from the n- and p-sides
across the junction into opposite sides of the junction to form the
di�usion currents in the neutral regions.
� some of the electrons and holes recombine in the space charge layer as
they transit across it, giving rise to additional recombination currents
that add to the diode di�usion currents.
� this space charge layer recombination current is particularly important
for low forward biases.
� electron continuity equation
1
q
@Jn@x
=n̂(x)
�n� integrating across space charge layer:
Inr = In(Wn)� In(�Wp) = qAZ Wn
�Wp
n̂(x)
�ndx
� qA
�nav
Z Wn
�Wpn̂(x)dx =
Qe
�nav
![Page 91: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/91.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 81
� where Qe = total number of electrons in the space charge layer, �nav =
average lifetime of electrons in the space charge layer, and Inr = elec-
tron recombination current in the space charge layer.
� likewise for holes:
Ipr � Qh
�pav
� to �nd the amount of electrons Qe and holes Qh in the space charge
layer, one must estimate the free electron and hole concentrations per
unit volume in the space charge layer under forward bias conditions:
n(x) = ni exp
0B@V (x)VT
1CA ; p(x) = ni exp
0B@�V (x)
VT
1CA
� where V (x) � �Ei(x)=q and the zero voltage reference is taken at the
Fermi level.
n(Wn) = ni exp
0B@V (Wn)
VT
1CA
=) n(x) = n(Wn) exp
0B@V (x)� V (Wn)
VT
1CA
p(�Wp) = ni exp
0B@�V (�Wp)
VT
1CA
=) p(x) = p(�Wp) exp
0B@V (�Wp)� V (x)
VT
1CA
� therefore the product of n(x) and p(x) in the space charge layer be-
comes:
n(x)p(x) = n(Wn)p(�Wp) exp
0B@V (x)� V (Wn) + V (�Wp)� V (x)
VT
1CA
= n(Wn)p(�Wp) exp
0B@V (�Wp)� V (Wn)
VT
1CA
![Page 92: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/92.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 82
� recognising that V (Wn)� V (�Wp) = Vbi one can write the
Law of the Junction:
n(x)p(x) = n(Wn)p(�Wp) exp
0@VFVT
1A exp
0@�VbiVT
1A
� if n(Wn) = ND and p(�Wp) = NA then
Vbi = VT ln
0@NAND
n2i
1A
exp
0@�VbiVT
1A = exp
24�VTVT
ln
0@NAND
n2i
1A35 = exp
264ln
0B@ n2iNAND
1CA375
=n2i
NAND� n2inn(Wn)pp(�Wp)
� therefore, in the space charge layer,
n(x)p(x) = n2i exp
0@VFVT
1A
� for VF = 0; n(0) = p(0) = ni.
� for VF > 0; n(0) = p(0) = ni exp�VF2VT
�
� Qe and Qh are proportional to exp�VF2VT
�
� therefore Inr and Ipr are proportional to exp�VF2VT
�
� the total space charge layer current Iscl is then given by:
Iscl = Inr + Ipr = Ior exp
0@ VF2VT
1A
� Ior is a constant.� therefore, the total diode current ID including both neutral region
di�usion current and space charge layer recombination current is given
by:
I = Io
0@exp
0@VFVT
1A� 1
1A + Ior
0@exp
0@ VF2VT
1A� 1
1A
� the �rst term is the ideal neutral region di�usion current, and the
second term is the non-ideal space charge layer recombination current.
![Page 93: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/93.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 83
� the ratio of ideal neutral region di�usion current to non-ideal space
charge layer recombination current can be expressed as,
I(di�usion)
Iscl/ ni exp
0@ VF2VT
1A
� from the above ratio it can be seen that the smaller ni is (i.e. the
larger the bandgap Eg of the semiconductor is), the larger the forward
bias for which non-ideal space charge layer recombination current will
dominate the total diode current.
e.g. ni(Si) << ni(Ge)
� the total diode current ID can be expressed using an ideality factor n
that takes on a value between 1 and 2 to combine the e�ects of neutral
region di�usion current and space charge layer recombination current
such that,
I = Io
0@exp
0@VFVT
1A� 1
1A + Ior
0@exp
0@ VF2VT
1A� 1
1A
= I 0o
0@exp
0@ VFnVT
1A� 1
1A ; 1 < n < 2
![Page 94: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/94.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 84
slope = 1
2 VT
slope = 1
VT
non-ideal diode current
ideal diode current
I
I
VF
0
ln ID
ln
ln
o
or
Forward Diode Current Behaviour including Low Forward Bias
Non-Ideal Current Region due to Space Charge Layer Recombination
![Page 95: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/95.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 85
High Forward Bias
High Level Injection
0 W
nop
DN
space charge layer edge
n-neutral region
metal contact
(x) = nn
(x)n
p
High Level Injection Hole and Electron Concentrations in n-Neutral
Region
� if the forward bias voltage VF is large enough, it is possible to inject
enough minority carriers into the neutral region such that the injected
minority carrier concentration exceeds the impurity concentration |
a condition known as high level injection.
� if the injected minority carrier concentration exceeds the impurity con-
centration in a neutral region, an electric �eld will result.
� even in high level injection, a neutral region will still attempt to remain
charge neutral such that a majority carrier charge of opposite polarity
to the minority carrier charge will be inserted from the metal contact
for every minority carrier charge injected into the neutral region from
the space charge layer side.
� for n{neutral region in HLI:
p+n (x) +N+D = n�n (x); pn(x) >> ND
� therefore, for charge neutrality in HLI:
![Page 96: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/96.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 86
pn(x) � nn(x)
� consider a pn junction diode where NA >> ND (also known as a p+n
diode):
� for such a junction in low level injection when p̂n(x) << ND, we can
write:
In =qADnn
2i
W 0NAexp
0@VFVT
1A << Ip =
qADpn2i
WNDexp
0@VFVT
1A
� if NA >> ND then In � 0 compared to Ip.
� therefore, in the n-neutral region,
In = AJn = qA(�nnnE +Dndnndx
) � 0
� the electric �eld in the n-neutral region is then given by:
E =�Dn
�n
1
nn
dnndx
= �VT 1
nn
dnndx
� for low level injection (LLI): nn(x) � ND:
� therefore, for LLI:dnndx
=dND
dx= 0 for uniformly doped diode; and E = 0
� for high level injection (HLI): pn(x) � nn(x)
� therefore, for HLI:
E = �VT 1
pn
dpndx
![Page 97: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/97.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 87
� the hole current in the n-neutral region for HLI is then given by:
Jp = q�ppnE � qDpdpndx
= q
0@��pVT dpn
dx�Dp
dpndx
1A = �2qDp
dpndx
Vj
VF
n-sidep-side
( in HLI )
anV
0 W
High Level Injection Voltage Drop
� a non-zero electric �eld E in the neutral region results in a voltage drop
Van across the neutral region given by,
Van = V (0)� V (W ) = �Z 0
WEdx = VT
Z 0
W
1
pn
dpndx
dx
= VTZ 0
Wd ln(pn(x)) = VT ln
0B@ pn(0)pn(W )
1CA
� at the metal contact, since the region is in high level injection pn(W ) =
nn(W ).
![Page 98: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/98.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 88
� at the metal contact all of the excess carriers will recombine with
the contact so that the electron concentration is equal to its thermal
equilibrium value such that nn(W ) = ND.
� therefore,
Van = VT ln
0B@ pn(0)pn(W )
1CA = VT ln
0B@pn(0)ND
1CA
� the total applied forward bias VF in HLI equals the applied bias across
the junction plus the voltage drop across the neutral region due to HLI
e�ects such that:
VF = voltage across junction + Van
= VT ln
0B@pn(0)pno
1CA + VT ln
0B@pn(0)ND
1CA
= VT ln
0B@ p
2n(0)
pnoND
1CA = VT ln
0B@ p2n(0)
(n2i=ND) �ND
1CA
= 2VT ln
0B@pn(0)ni
1CA
� the minority carrier concentration at the space charge layer edge of the
n-type neutral region in HLI is:
pn(0) = ni exp
0@ VF2VF
1A
� since the hole current in HLI Ip(0) is proportional (/) to pn(0), thediode current will take on the form:
ID / exp
0@ VF2VT
1A
![Page 99: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/99.jpg)
PN -Junction Diodes, E&CE 730, January, 2002 89
slope = 1
2 VT
slope = 1
VT
ln ID
non-ideal diode current
ideal diode current
I
I
VF
0
ln
ln
o
or
non-ideal diode current
(high level injection)
(scl recombination)
Forward Diode Current Behaviour including Low Forward Bias and High
Forward Bias Non-Ideal Current Regions
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PN -Junction Diodes, E&CE 730, January, 2002 90
SPICE Model for PN-Junction Diode
Static Model
jC
dC = C
D
Rs
+
I
SPICE Diode Equivalent Circuit
� the simple static model is based in the following diode equation:
ID = IS
24exp
0@ qVDnkT
1A� 1
35
� where VD is the forward bias, and IS is the saturation current.
� non-ideal space charge layer recombination is modeled using an emis-
sion coeÆcient or non-ideality factor n, where n is between 1 and
2.
� high level injection is not explicitly modeled in SPICE. Instead the
e�ect if modeled by �tting an e�ective series resistance RS to model
the e�ect of high level injection and series resistance simultaneously,
since both phenomenon result in a similar behaviour of ID at high
currents.
� in practise, RS is estimated at several values of ID and averaged since
the series resistance depends on diode current.
� high currents are then modeled using,
V0
D = RSID + VD
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PN -Junction Diodes, E&CE 730, January, 2002 91
0
I
V
D
-IBV
-5 kT/q
(d)
(b) (a)
(c)
D
-BV
SPICE Reverse Bias Model
� large reverse bias and breakdown are modeled using the following equa-
tions,
ID = IS�exp
�qVDnkT
�� 1
�for � 5VT � VD � 0
= �IS for �BV < VD < �5VT= �IBV for VD = �BV
= �IS�exp
��q(BV +VD)
kT
�� 1 + qBV
kT
�for VD � �BV
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PN -Junction Diodes, E&CE 730, January, 2002 92
Large Signal Model
Cj
Cjo
VJ
VJ
FC
Reverse Bias Forward Bias
VD
depletion model
linear extrapolation
SPICE Junction Capacitance Model
� the large signal model allows time-dependent e�ects to be included.
The simplest implementation in SPICE consists of a large signal ca-
pacitance in parallel with the static model.
� the large signal capacitance in comprised of the addition of the di�usion
capacitance and junction capacitance such that,
C = Cd + Cj
= �d
0@dIDdVD
1A + CJO
0@1� VD
VJ
1A�m for VD � FCVJ
� where FC is a factor less than one (usually about 0.5), VJ is the built-
in voltage, and m is an empirical parameter �tted to measured ca-
pacitance data for reverse bias voltages where di�usion capacitance is
negligible.
� For forward voltages VD beyond FCVJ , the junction capacitance Cj
is determined by linearly extrapolating beyond the depletion model
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PN -Junction Diodes, E&CE 730, January, 2002 93
using a slope for the linear extrapolation that is equal to the slope of
the depletion model at VD = FCVJ .
� the �rst term of C is the di�usion capacitance Cd which is given by the
product of the total transit time �d of minority carriers for both neutral
regions and the large signal input conductance gd which is given by,
gd =dIDdVD
=ISnVT
exp
0@ VDnVT
1A
Small Signal Model
� the small signal model is a linearisation of the large signal model, and
is valid only at a particular d.c. bias voltage and current.
� the junction capacitance is modeled in the same manner as for the large
signal model, however, the di�usion capacitance is modeled using,
Cd = �dgd
� where gd becomes the the small signal low frequency input conductance
given by,
gd =dIDdVD
1A(VD;ID)
� note that gd is the slope of the ID versus VD curve.
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Bipolar Transistors, E&CE 730, January, 2002 94
3 Bipolar Transistors
E&CE 730Physics & Modeling of Semiconductor Devices
Prepared by:
Professor John S. HamelDepartment of Elecrtrical & Computer Engineering
University of WaterlooWaterloo, Ontario, Canada, N2L 3G1
January, 2002
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Bipolar Transistors, E&CE 730, January, 2002 95
Basic Theory and Operation of Bipolar Transistors
W e W b
W e W b
region
emitter
neutral
Nc
Nb
Ne
metal
contact
metal
contact
Xj1
Xj2
0 0
Wscl
region
baseneutral
N(x)space charge layer
emitter-base
space charge layer
collector-base
holeconcentration
electron
concentration
Uniformly Doped Bipolar Transistor
� consider a uniformly doped npn bipolar transistor:
� the collector current Ic is comprised of minority carrier (electron) cur-
rent in the neutral base.
� the base region of a bipolar transistor must be narrow enough so that
there is very little recombination of electrons and holes such that most
of the minority carriers injected from the forward biased emitter-base
junction will survive the trip across the base to the reverse biased
collector-base junction.
� the collector current Ic can be then be calculated using the \narrow"
diode approximation which is valid if the minority carrier di�usion
length Ln in the p-type base region is much larger than the base width
Wb.
Ic = �qAEDndn̂
dx
1Ax=0
=qAEDn(n̂p(0)� n̂p(Wb))
Wb
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Bipolar Transistors, E&CE 730, January, 2002 96
=qAEDnn̂p(0)
Wb=qAEDnnpo
Wb
24exp
0@VbeVT
1A� 1
35
=qAEDnn
2i
WbNb
24exp
0@VbeVT
1A� 1
35
� AE = emitter area, Wb = neutral base width, np = electron concen-
tration in the p-type base region.
� np(Wb) � 0 since the collector-base junction is reverse biased.
W e W b
region
emitter
neutral
Nc
Nb
Ne
metal
contact region
baseneutral
np
(0)p
n(0)
np(W b
)
I cI
b1
pn
(W e ) 0 0
N(x)
Uniformly Doped Bipolar Transistor Depicting Neutral and Space
Charge Regions
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Bipolar Transistors, E&CE 730, January, 2002 97
� the base current Ib is comprised of three principal components:
1. hole current Ib1 due to back injection of holes from the p-type base
into the n-type emitter across the forward biased emitter-base junc-
tion,
2. neutral base recombination current Ib2 (usually this component is
negligible for modern bipolar transistors).
3. emitter-base space charge layer recombination current (dominates
at low forward emitter-base bias voltages).
� if the hole di�usion length Lp in the n-type emitter is considerably
larger than the neutral emitter width We (shallow emitter), then,
Ib1 =qAEDpn
2i
WeNe
24exp
0@VbeVT
1A� 1
35
� if the hole di�usion length Lp in the n-type emitter is considerably
smaller than the neutral emitter width We (deep emitter), then,
Ib1 =qAEDpn
2i
LpNe
24exp
0@VbeVT
1A� 1
35
� considering only the Ib1 component of base current, for a shallow emit-
ter transistor the d.c. common-emitter current gain � is given by,
� =IcIb
=IcIb1
=DnWeNe
DpWbNb
� simple theory predicts that to obtain a high current gain, one needs
a wide, highly doped emitter region and a narrow, lowly doped base
region, or in other words,
WeNe >> WbNb for high �
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Bipolar Transistors, E&CE 730, January, 2002 98
Vbe
slope = 1 / VT
ln Ib
ln I c
cI
Ib
0
Ideal Gummel Plot
� the neutral base recombination component of base current Ib2 can be
calculated from the electron continuity equation,
@In@x
= qAEn̂p�n
� where n̂p is the excess electron concentration in the neutral base regionand �n is the electron lifetime.
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Bipolar Transistors, E&CE 730, January, 2002 99
np
(0)n (x)p
Qn W
bemitter-base
space charge layer edge
space charge layer edge
collector-base
p-type base neutral region
0
Stored Minority Carrier Charge in Uniformly Doped Neutral Base
Region
� integrating the continuity equation gives,
Ib2 = �[In(0)� In(Wb)] = qAE
Z Wb
0
n̂p(x)
�ndx
=qAEn̂p(0)Wb
2�n=qAEn
2iWb
2�nNb
24exp
0@VbeVT
1A� 1
35
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Bipolar Transistors, E&CE 730, January, 2002 100
Heavy Doping E�ects in the Emitter
Ec
Ev
Ed
low-doped
bandgap
Eg
Eg
donor energy level spreading E
g(eff)narrowed bandgap
Bandgap Narrowing in Heavily n-Doped Semiconductor
� if the emitter doping Ne >> 1018cm�3 for silicon, then the bandgap
Eg appears to decrease (by an amount �Eg) due to the impurity atom
energy levels spreading into the conduction or valence bands.
� this apparent bandgap narrowing increases the intrinsic carrier concen-tration, and therefore the equilibrium minority carrier concentration,
making the region appear to be more lightly doped then it really is.
� to take this e�ect into account, the base current due to back injection
into the emitter becomes for a deep emitter,
Ib1 =qAEDpn
2i exp (�Eg=(kT ))
LpNe
24exp
0@VbeVT
1A� 1
35
� bandgap narrowing due to heavy doping results in a dramatic decrease
in current gain compared to simple theory.
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Bipolar Transistors, E&CE 730, January, 2002 101
� combining the equations for Ic and Ib for a uniform doped transistor
with a deep emitter and bandgap narrowing one obtains a reasonably
realistic expression for current gain,
� =
26412
0@Wb
Ln
1A2 + DpWbNb
DnLpNeexp
0@�Eg
kT
1A375�1
Realistic Transistor Impurity Pro�le Modeling
Gaussian Profile
Diffused
(x p =0)
(peak at x p )
Implanted
Gaussian Profile
xp0
No
N(x)
Gaussian Impurity Pro�le for Di�used and Implanted Impurities
� realistic bipolar transistors seldom have uniform impurity pro�les, par-
ticularly in the emitter and base regions.
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Bipolar Transistors, E&CE 730, January, 2002 102
� the methods normally used to introduce n and p-type impurity dopant
atoms to the semiconductor to form a bipolar transistor can result in
complicated vertical and lateral impurity concentrations as a function
of position.
� the concentration of impurity atoms per unit volume as a function of
position within a semiconductor is referred to as the impurity distri-
bution or impurity pro�le.
� the actual shape of the impurity distributions greatly a�ect transistor
behaviour and performance.
� impurities which have been introduced from di�usion and implanta-
tion processes can be modeled approximately by the use of Gaussian
distributions.
� a vertical npn bipolar transistor can be fabricated by di�using a p-
type impurity (e.g. B) into a semiconductor layer of n-type uniform
background concentration to form a base region above the collector.
� the uniform background doping is usually formed by the growth of a
thin n-doped epitaxial layer that becomes the collector on top of a
semiconductor wafer or substrate.
� the emitter is then formed by di�using an n-type impurity (e.g. As or
P) into the top of the base impurity layer.
� each di�usion results in an impurity concentration per unit volume
N(x) that can be approximated by a Gaussian function such that,
N(x) = No exp
264�
0@ xxo
1A2375
� No is the peak impurity concentration, and xo is the characteristic
length.
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Bipolar Transistors, E&CE 730, January, 2002 103
� the surface of the wafer from which the impurity is introduced cor-
responds to x = 0 where N(x) takes on its maximum value or peak
concentration of No.
� to model implantation of impurities where the peak may reside below
the surface at some distance x = xp one can use a modi�ed Gaussian
expression for N(x) such that,
N(x) = No exp
264�
0@x� xp
xo
1A2375
� xp then becomes the depth where Nx has its peak value of No.
N e
Nb
Nepi
Xj2X
j1
wafer
surface
emitter
base
collector
x0
N(x)
n
p
n
Double Di�used Gaussian Vertical Impurity Pro�le for an npn
Bipolar Transistor
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Bipolar Transistors, E&CE 730, January, 2002 104
� the net electrical impurity concentration resulting from the superposi-
tion of the collector, base, and emitter impurity distributions are what
determines the actual impurity pro�le of the transistor.
� the �nal net impurity pro�le N(x) for the entire transistor can then
be modeled by,
N(x) = Ne exp
264�
0@ xxe
1A2375�Nb exp
264�
0@ xxb
1A2375 +Nepi
� Nepi is the collector background doping, Ne and xe describes the dif-
fused emitter impurity pro�le, and Nb and xb describe the di�used
base impurity pro�le.
� the above transistor pro�le is referred to as a Double Di�used Gaus-
sian.
� the impurity concentration for the base di�usion is negative since the
base is comprised of negatively charge acceptor atoms.
� the characteristic lengths and the peak concentrations Ne, Nb along
with the collector concentration Nepi determine the entire vertical
structure of the bipolar transistor.
� a pnp vertical transistor would be modeled using the same equation
by with reversed signs.
� other, more complicated analytic functions are often used to model
realistic impurity pro�les including the use of Gaussians which have
peak concentrations below the surface of the wafer (x > 0), error
functions, multiple Gaussians for the same di�usion, etc.
� numerical programs which are used to model transistor behaviour can
use actual point by point impurity data in tabular form to model the
transistor impurity pro�le more accurately.
� the emitter-base junction xj1 and the collector-base junction xj2 can
be determined for a double di�used Gaussian pro�le by equating the
emitter and base di�usions such that,
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Bipolar Transistors, E&CE 730, January, 2002 105
Ne exp
264�
0@xj1xe
1A2375 = Nb exp
264�
0@xj1xb
1A2375
� which gives for xj1:
xj1 =
0@ln Ne
Nb
1A12 �1=x2e � 1=x2b
�12
� the collector-base junction can be determined in a similar manner by
equating the base and collector impurity pro�les such that,
Nb exp
264�
0@xj2xb
1A2375 = Nepi
� which gives for xj2:
xj2 = xb
0B@ln Nb
Nepi
1CA12
Moll-Ross Relation and the Gummel Integral
� real bipolar transistors seldom, if ever, have uniform base impurity
pro�les.
� the shape of the impurity distribution can have a signi�cant impact
on the collector current.
� consider a bipolar transistor with an arbitrarily doped base region withposition-dependent p-type impurity concentration Nb(x).
� if the current gain � >> 1 then one can write,
Jp � 0 = q
0@�ppE �Dp
dp
dx
1A
� for low level injection conditions (i.e. np(x) << Nb(x)), p(x) � Nb(x).
� the electric �eld resulting from the non-uniform p-type doping in the
base is therefore given by,
E =Dp
�p
1
p
dp
dx= VT
1
Nb(x)
Nb(x)
dx
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Bipolar Transistors, E&CE 730, January, 2002 106
� the electron (collector) current density is then given by,
Jn = �q0@�nnE +Dn
dn
dx
1A = �q
0@�nVT n
p
dp
dx+Dn
dn
dx
1A
= �qDn
p
0@ndpdx
+ pdn
dx
1A = �qDn
p
d(pn)
dx
� if recombination of electrons in the base is negligible, then the collectorcurrent density Jn is constant with respect to position within the base.
Therefore, one can write the relation, (which was �rst attributed to
Moll and Ross),
Jnq
Z Wb
0
p
Dndx = (pn)x=0 � (pn)x=Wb
� Using the Law of the Junction (where VF is the bias across a pn-
junction):
p(x)n(x) = n2i exp
0@VFVT
1A
� one can write for each the emitter-base and collector-base junction:
(pn)x=0 = n2i exp
0@VbeVT
1A ; (pn)x=Wb
= n2i exp
0@VbcVT
1A
Jn =IcAE
=qn2iRWb
0 p=Dndx
24exp
0@VbeVT
1A� exp
0@VbcVT
1A35
� for low level injection p(x) � Nb(x) and using an average electron
di�usivity Dnav (Dn in general will vary with position since it is varies
with impurity concentration) one can write
Jn =IcAE
=qDnavn
2iRWb
0 Nb(x)dx
24exp
0@VbeVT
1A� exp
0@VbcVT
1A35
� the integral in the denominator is referred to as the Gummel Integral
or Gummel Number which is simply the total amount of the neutral
base impurity atoms.
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Bipolar Transistors, E&CE 730, January, 2002 107
� the collector current does not depend upon the shape of the base
impurity pro�le, but depends only upon the total quantity of impurity
atoms.
� the Gummel Number can be related to the base sheet resistance Rbesq
which is an easily measurable quantity.
Rbesq = qZ Wb
0�pNb(x)dx
!�1
= q�pav
Z Wb
0Nb(x)dx
!�1
ohms per square
� if one ignores the di�erences between electron and hole mobilities, one
can compared base sheet resistance directly to the Gummel Number.
� transistors of a given area with larger base sheet resistances will have
larger collector currents and larger current gains.
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Bipolar Transistors, E&CE 730, January, 2002 108
Ebers-Moll Model
IE I
C
αR
ICR
IEF
αFI
EF
ICR
VBCVBE
electrons
electrons
emitter base collectorn p n
BE C
E C
Currents De�ning Injection Version of Ebers-Moll Model
� the Ebers-Moll model was the �rst widely adopted comprehensive
model developed for the bipolar transistor that could be used for circuit
design.
� it is based on the physical fact that a bipolar transistor is simply
two pn-junction diodes connected back-to-back that share a common
neutral region (the base region of the resulting transistor) that inter-
act electrically because the shared neutral region (the base) is narrow
enough to allow minority carriers to cross it without completely re-
combining with majority carriers.
� this survival of minority carriers transiting the shared base region be-
tween the two back-to-back diodes is the key mechanism responsible
for transistor action and underlies all bipolar semiconductor device
operation.
� the interaction between the two diodes allows for the input of the
transistor to exist at a di�erent level of impedance than the output
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Bipolar Transistors, E&CE 730, January, 2002 109
| hence trans-resistance or transistor, which is the fundamental
principle behind all transistors of any type.
� to achieve this trans-resistance requires energy which comes from the
power supply | hence, transistors are referred to as active devices.
� simple equations can be written to describe the terminal currents of
the transistor (IE for emitter current and IC for collector current). All
currents are de�ned as positive going into the terminals.
IE = �(IEF � �RICR) = �IES24exp
0@VbeVT
1A� 1
35 + �RICS
24exp
0@VbcVT
1A� 1
35
IC = �(ICR � �FIEF ) = �ICS24exp
0@VbcVT
1A� 1
35 + �FIES
24exp
0@VbeVT
1A� 1
35
� IES | emitter-base diode saturation current
� ICS | collector-base diode saturation current
� �F | forward common-base current gain
� �R | reverse common-base current gain
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Bipolar Transistors, E&CE 730, January, 2002 110
αR
ICR
IEF
αF
IE
IC
IEF
ICR
IB
Vbc
beV
C
E
B
Injection Version of D.C. Equivalent Circuit for Ebers-Moll Model
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Bipolar Transistors, E&CE 730, January, 2002 111
� recalling the Moll-Ross formulation one can write,
Icoll =qAEDnavn
2iRWb
0 Nb(x)dx
24exp
0@VbeVT
1A� exp
0@VbcVT
1A35
= IS
24exp
0@VbeVT
1A� exp
0@VbcVT
1A35
� if Vbc = 0 one can write,
Icoll = IC = �FIES
24exp
0@VbeVT
1A� 1
35 = IS
24exp
0@VbeVT
1A� 1
35
� if Vbe = 0 one can write,
Icoll = �IE = ��RICS24exp
0@VbcVT
1A� 1
35 = �IS
24exp
0@VbcVT
1A� 1
35
� comparing the Moll-Ross formulation of the collector current and the
Ebers-Moll model allows one to write the reciprocity relation which
is valid for any multi-dimensional arbitrarily doped bipolar transistor
such that,
IS = �RICS = �FIES
� using the reciprocity relation one can re-write the Ebers-Moll model
such that,
IE = �(IS=�F )24exp
0@VbeVT
1A� 1
35 + IS
24exp
0@VbcVT
1A� 1
35
IC = �(IS=�R)24exp
0@VbcVT
1A� 1
35 + IS
24exp
0@VbeVT
1A� 1
35
� using this formulation of the Ebers-Moll model implies that only three
parameters need be measured to characterise the �rst order d.c. be-
haviour of the transistor at a given temperature | namely,
1. IS | collector saturation current
2. �F | forward common-base current gain, (or �F | forward common-
emitter current gain)
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Bipolar Transistors, E&CE 730, January, 2002 112
3. �R | reverse common-base current gain, (or �R | reverse common-
emitter current gain)
� the d.c. common-emitter forward and reverse current gains, �F and
�R, can be expressed such that,
�F =
������ICIB
������ =�F
1� �F; �R =
������IEIB
������ =�R
1� �R
IE
IC
IB
αR
αF
Vbc
beV
ICC
IEC
ICC
IS
IEC
beV
VT
IS
Vbc
VT
C
E
B
=
=
1exp
1exp
Transport Version of D.C. Equivalent Circuit for Ebers-Moll Model
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Bipolar Transistors, E&CE 730, January, 2002 113
Regions of Operation for a Bipolar Transistor
forward bias
forward bias
V
VBC
BE
reverse bias
reverse bias
Active Forward Region
Saturation RegionActive Inverse Region
Cut-Off Region
Regions of Operation of a Bipolar Transistor
� there are four distinct regions in which a bipolar transistor can operatewhich are de�ned combinations of forward and reverse emitter-base Vbeand collector-base Vbc bias.
� the most commonly used region of operation is the forward active
region where the emitter-base junction is forward biased (Vbe > 0),
and the collector-base junction is reversed biased (Vbc � 0).
� the transistor can also be used in reverse where the emitter becomes
the collector and the collector becomes the emitter in terms of func-
tionality.
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Bipolar Transistors, E&CE 730, January, 2002 114
� this region of operation is known as the reverse active region where
the emitter-base junction is reversed biased (Vbe � 0), and the collector-
base junction is forward biased (Vbc > 0). Although the electrical roles
of the emitter and collector regions are reversed for this region of op-
eration, the part of the transistor which functions as an emitter in the
forward active region of operation is always referred to as the emitter
for the other regions of operation.
� if both the emitter-base and collector-base junctions are forward biased
(Vbe > 0, Vbc > 0), then the transistor is said to be saturated.
� if both the emitter-base and collector-base junctions are reverse biased
(Vbe � 0, Vbc � 0), then the transistor is said to be in cuto� since the
transistor is completely o�.
Gummel-Poon Model
� the general form of the Moll-Ross relation involves an integral of the
total hole concentration in the neutral base to model the collector
current Ic.
� this expression is valid for arbitrary levels of carrier injection, includinghigh level injection when the concentration of injected minority carriers
from the forward biased emitter-base junction exceed the background
base impurity concentration.
Ic =qAEDnavn
2iRWb
0 p(x)dx
24exp
0@VbeVT
1A� exp
0@VbcVT
1A35
� for the base region to remain charge neutral, the total number of pos-
itive charges (holes) must equal the total number of negative charges
(electrons and ionised acceptor atoms) in a p-type neutral base region
at each position.
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Bipolar Transistors, E&CE 730, January, 2002 115
� mathematically this can be written,
p+(x) = n�(x) +N�
b (x)
� as the forward emitter-base voltage Vbe increases, the number of holes
begins to increase above Nb(x) in an attempt to retain charge neu-
trality, and according the model for collector current, this will increase
the Gummel Number in the Moll-Ross relation decreasing the collector
current.
� the Moll-Ross relation also predicts that the width of the neutral base
region Wb will a�ect collector current. This width will be a�ected
by the space charge layer widths on the base side of the emitter-base
and collector-base junctions, which in turn will be in uenced by the
voltages, Vbe and Vbc applied to the junctions.
� the Moll-Ross relation can therefore account for all of the variations
in collector current with changes in Vbe and Vbc for a bipolar transistor
with an arbitrarily doped base region and for arbitrary current levels
through the Gummel Integral term.
� the Gummel-Poon model allows for the calculation of this integral from
externally measured transistor terminal characteristics as opposed to
a numerical integration of the actual base impurity pro�le.
� in principle, all of these a�ects can be taken into account from the
Ebers-Moll model through the parameters IS, �F and �R, however,
the Ebers-Moll model provides no means to extract parameters which
are independent of current level or applied voltages.
� the Gummel-Poon model de�nes parameters which are, instead, re-
lated to the Moll-Ross relation, and are therefore independent of cur-
rent level and applied junction voltages.
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Bipolar Transistors, E&CE 730, January, 2002 116
� the Moll-Ross relation can be re-written as,
Ic =qAEDnavn
2iRXco
XeoNb(x)dx
26664qAE
RXcoXeo
Nb(x)dx
qAERXc(Vbc)Xe(Vbe)
Nb(x)dx
3777524exp
0@VbeVT
1A� exp
0@VbcVT
1A35
=qAEDnavn
2iRXco
XeoNb(x)dx
24Qbo
Qb
3524exp
0@VbeVT
1A� exp
0@VbcVT
1A35
=ISqb
24exp
0@VbeVT
1A� exp
0@VbcVT
1A35
� Qb is the actual total majority carrier charge in the neutral base which
will change with current level and applied voltages at the junction.
� Qbo is de�ned to be the total majority carrier charge due to impurities
alone for zero applied voltage at each junction.
� qb is the ratio of the actual neutral base majority carrier charge to the
zero-bias base majority carrier charge.
qb =Qb
Qbo
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Bipolar Transistors, E&CE 730, January, 2002 117
Qf
Qbo
Xj2
Qc
Qr
pr
(x)p(x)
Qe
N b(x)
pf
(x)
X eoX e (Vbe
)Xj1 X co X
c(V
bc)
Physical Sources of Base Charges for Gummel-Poon Model
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Bipolar Transistors, E&CE 730, January, 2002 118
� the total neutral base impurity charge Qb is comprised of several com-
ponents such that,
Qb = Qbo +Qe +Qc +Qf +Qr
� Qe = the majority carrier charge in the neutral base region between
the position of the emitter-base space charge layer for Vbe = 0 and for
the actual applied Vbe.
� if Vbe < 0 (reverse bias), then Qe will be negative.
� Qc = the majority carrier charge in the neutral base region between
the position of the collector-base space charge layer for Vbc = 0 and
for the actual applied Vbc.
� if Vbc < 0 (reverse bias), then Qc will be negative.
� Qf is the extra majority carrier charge in the neutral base region above
the background impurity charge that compensates the extra negative
electrons injected from the forward biased emitter-base junction to
maintain charge neutrality when Vbc = 0 and Vbe > 0.
� Qr is the extra majority carrier charge in the neutral base region above
the background impurity charge that compensates the extra negative
electrons injected from the forward biased collector-base junction to
maintain charge neutrality when Vbe = 0 and Vbc > 0
� qb can be divided into separate normalised charges (ratios of charges)
such that,
qb =Qb
Qbo= 1 +
Qe
Qbo+Qc
Qbo+Qf
Qbo+Qr
Qbo= 1 + qe + qc + qf + qr
� Qe and Qc can be related to the emitter-base and collector-base junc-
tion capacitances, Cje and Cjc such that,
Qe =Z Vbe0
Cje(V )dV ; Qc =Z Vbc0
Cjc(V )dV
qc =1
Qbo
Z Vbc0
Cjc(V )dV � CjcavVbcQbo
� VbcVAF
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Bipolar Transistors, E&CE 730, January, 2002 119
qe =1
Qbo
Z Vbe0
Cje(V )dV � CjeavVbeQbo
� VbeVAR
� Cjeav and Cjcav are average capacitances, VAF and VAR are known as
the forward Early Voltage and the reverse Early Voltage, respec-
tively, which are measurable model parameters.
Qf = qAE
Z Xc(Vbc)
Xe(Vbe)[pf(x)�Nb(x)]dx
= qAE
Z Xc(Vbc)
Xe(Vbe)nf(x)dx � Qnf = �bfIc
Qr = qAE
Z Xc(Vbc)
Xe(Vbe)[pr(x)�Nb(x)]dx
= qAE
Z Xc(Vbc)
Xe(Vbe)nr(x)dx � Qnr = �brIc
� pf(x) is the majority carrier and nf(x) is the minority concentration in
the neutral base region for a forward biased emitter-base junction and
zero biased collector-base junction, Qnf is the total stored minority
carrier concentration under these bias conditions.
� �bf is the forward base transit time.
� pr(x) is the majority carrier and nr(x) is the minority concentration
in the neutral base region for a forward biased collector-base junction
and zero biased emitter-base junction, Qnr is the total stored minority
carrier concentration under these bias conditions.
� �br is the reverse base transit time.
� the normalised forward and reverse injected charges then become,
qf =Qf
Qbo=�bfIcQbo
=�bfISQboqb
24exp
0@VbeVT
1A� 1
35
qr =Qr
Qbo=�brIcQbo
=�brISQboqb
24exp
0@VbcVT
1A� 1
35
� qb then becomes,
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Bipolar Transistors, E&CE 730, January, 2002 120
qb = 1 +VbeVAR
+VbcVAF
+1
Qboqb
0@�bfIS
24exp
0@VbeVT
1A� 1
35 + �brIS
24exp
0@VbcVT
1A� 1
351A
= q1 +q2qb
q1 = 1 +VbeVAR
+VbcVAF
q2 =
0@�bfISQbo
24exp
0@VbeVT
1A� 1
35 + �brIS
Qbo
24exp
0@VbcVT
1A� 1
351A
� solving for qb yields,
q2b � q1qb � q2 = 0; qb =
0BB@q12+
vuuut q12
!2+ q2
1CCA
� for low level injection, q2 << q1 and qb � q1, and for Vbc = 0 and
Vbe >> VT ,
Ic � ISq1
24exp
0@VbeVT
1A� 1
35 � IS
1 + Vbe=VARexp
0@VbeVT
1A
� IS exp
0@VbeVT
1A assuming
VbeVAR
<< 1
� for high level injection, q2 >> q1 and qb � pq2.
Ic � ISpq2
24exp
0@VbeVT
1A� 1
35 � IS
vuuuut Qbo
�bfISexp
0@VbeVT� Vbe
2VT
1A
=
vuuuutQboIS�bf
exp
0@ Vbe2VT
1A
� de�ne Vbe = Vkf where the current changes from low to high level
injection.
� for high level injection the slope of ln(Ic) versus Vbe changes from 1=VTto 1=(2VT ).
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Bipolar Transistors, E&CE 730, January, 2002 121
� call the collector current where this change in the slope of ln(Ic) occursthe forward knee current IKF .
� since both the low level and high level injection forms of Ic are valid
at the transition from low to high level injection one can write,
IKF = IS exp
0@VkfVT
1A =
vuuuutQboIS�bf
exp
0@Vkf2VT
1A
=
vuuuutQbo
�bf
pIKF
� similarly, in inverse active operation (Vbe = 0; Vbc = Vkr > 0),
IKR = IS exp
0@VkrVT
1A =
vuuutQboIS�br
exp
0@ Vkr2VT
1A
=
vuuutQbo
�br
pIKR
� therefore,
IKF =Qbo
�bf; IKR =
Qbo
�br
� the �nal Gummel-Poon model then becomes,
Ic =ISqb
24exp
0@VbeVT
1A� exp
0@VbcVT
1A35
qb =
0BB@q12+
vuuut q12
!2+ q2
1CCA
q1 = 1 +VbeVAR
+VbcVAF
q2 =ISIKF
24exp
0@VbeVT
1A� 1
35 + IS
IKR
24exp
0@VbcVT
1A� 1
35
� the measurable parameters for the Gummel-Poon model then become,
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Bipolar Transistors, E&CE 730, January, 2002 122
1. IS | collector saturation current
2. VAF | forward Early voltage
3. VAR | reverse Early voltage
4. IKF | forward Knee current
5. IKR | reverse Knee current
IE
IC
IB
Vbc
beV
ICC
IEC
βR
βF
beV
VT
Vbc
VT
ICC
IEC
IC
ICC
IS
qb
IEC
IS
qb
C
E
B
1exp 1
=
exp= =
D.C. Equivalent Circuit for Gummel-Poon Model
Low D.C. Forward Bias Voltage Modeling
(Space Charge Layer Recombination Currents )
� both the Ebers-Moll and Gummel-Poon models can be augmented to
include the e�ects of space charge layer recombination on the base
current for low values of forward biasing.
� considering a bipolar transistor operating in the forward active region
of operation (Vbe > 0, Vbc < 0), the base current is comprised of three
components, two of which have already been discussed:
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Bipolar Transistors, E&CE 730, January, 2002 123
1. hole current Ib1 due to back injection of holes from the p-type base
into the n-type emitter across the forward biased emitter-base junc-
tion,
2. neutral base recombination current Ib2 (usually this component is
negligible for modern bipolar transistors).
3. non-ideal recombination current in the emitter-base space charge
layer resulting from the recombination of electrons and holes as
they pass through the space charge layer on their way to the base
and emitter neutral regions, respectively.
� the emitter-base space charge layer recombination is identical to the
space charge layer recombination already discussed for pn-junction
diodes.
surface
recombination
bulkrecombination
emitter-basespace charge layer
oxide layer
emitter
base
Sources of Non-Ideal Emitter-Base Space Charge Layer
Recombination Current
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Bipolar Transistors, E&CE 730, January, 2002 124
Vbe
slope = 1 / VT
ln Ib
ln I c
Ib
cI
0emitter-base
space charge layer
recombination dominates
ideal region
high current effects
(high level injection)(Kirk Effect)
(series resistance)
Realistic Gummel Plot Depicting Low Forward Bias Non-Ideal
Current
� in a realistic bipolar transistor, this e�ect arises from recombination
partly in the space charge layer in the bulk of the silicon below the
emitter di�usion, and partly at the interface between the space charge
layer and the surface �eld oxide used to passivate the silicon surface.
� the amount of recombination depends upon the electron and hole life-
time which is reduced by metallic contamination in the silicon, and
by unsatis�ed silicon and silicon-dioxide bonds at the silicon surface
which provide trapping centres.
� metal contamination arises from processes which a�ect the surface of
the wafer such as metal contacting and metal from processing ma-
chines.
� simple theory predicts that space charge layer recombination current
will vary as exp(Vbe=(2VT )), whereas the recombination currents in the
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Bipolar Transistors, E&CE 730, January, 2002 125
neutral emitter and base regions that make up the remainder of the
base current will vary as exp(Vbe=VT ).
� space charge layer recombination can be included in the models simply
by adding two more \non-ideal" diodes between the base-emitter and
base-collector terminals which have currents given by,
ISE exp
0@ VBENEVT
1A ; ISC exp
0@ VBCNCVT
1A
� the SPICE model parameters for space charge layer recombination
current are:
1. ISE = emitter-base space charge layer recombination saturation
current.
2. NE = non-ideality factor (between 1 and 2) for emitter-base space
charge layer recombination current.
3. ISC = collector-base recombination saturation current.
4. NC = non-ideality factor (between 1 and 2) for collector-base space
charge layer recombination current.
� the diode between the emitter and base terminals models emitter-
base space charge layer recombination current when the emitter-base
junction is forward biased.
� the diode between the collector and base terminals models collector-
base space charge layer recombination current when the collector-base
junction is forward biased.
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Bipolar Transistors, E&CE 730, January, 2002 126
IE
IC
Vbc
beV
ICC
IEC
βR
βF
ICC
IEC
IC
IB
VT
N E
ISE
N CV
T
ISC
C
E
=B
exp 1
exp 1V
BC
VBE
D.C. Equivalent Circuit for Gummel-Poon Model Including E�ects of
Space Charge Layer Recombination
Small Signal Model of the Bipolar Transistor
Small Signal Criterion
� a bipolar transistor is usually operated in the forward active region
of operation where Vbe > 0 and Vbc < 0 in applications where small
signal a.c. models are needed.
� the following model parameters are then applicable to this region of
operation; however they also apply to reverse active operation Vbe < 0
and Vbc > 0).
� small signal analysis applies when the input and output signals of a
device are small enough to avoid non-linear e�ects.
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Bipolar Transistors, E&CE 730, January, 2002 127
� it is possible to derive a rigorous de�nition of what is meant by \small"
for the input signal to a bipolar transistor biased to operate in the
forward active region of operation (Vbe > 0, Vbc < 0) in common-
emitter con�guration.
Ic = IC + ic = IS exp
0@VbeVT
1A = IS exp
0@VBE + vbe
VT
1A
= IS exp
0@VBEVT
1A exp
0@vbeVT
1A
= IS exp
0@VBEVT
1A2641 + vbe
VT+1
2
0@vbeVT
1A2 + :::
375
� IS exp
0@VBEVT
1A241 + vbe
VT
35 if vbe << VT (small signal criterion)
= IC
0@1 + vbe
VT
1A = IC +
ICvbeVT
� Vbe = the total time-dependent input voltage, VBE = the d.c. bias
voltage, vbe = the small signal a.c. voltage superimposed on the d.c.
bias voltage such that Vbe = VBE + vbe
� Ic = the total time-dependent collector current, IC = the d.c. collector
current, ic = the small signal a.c. collector current superimposed on
the d.c. collector current such that Ic = IC + ic
Small Signal Transconductance gm
gm =dICdVBE
=d
dVBE
0@IS
24exp
0@VBEVT
1A� 1
351A =
ICVT
ic =ICVTvbe = gmvbe
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Bipolar Transistors, E&CE 730, January, 2002 128
Small Signal a.c. Input Resistance r�
r� =dVBEdIB
=dVBEdIC
dICdIB
=�ogm
� IB = d.c. base current, �o = small signal a.c. common-emitter current
gain.
Small Signal a.c. Output Resistance ro
ro =dVCEdIC
� VAIC
� VCE = d.c. collector-emitter voltage, VA = Early Voltage.
� for forward operation VA = VAF | the forward Early voltage, and for
reverse operation VA = VAR | the reverse Early Voltage.
Small Signal a.c. Collector-Base Resistance r�
� the collector-emitter voltage will alter the space charge layer width
of the collector-base junction. This will in turn alter the width of
the neutral base and also the total quantity of stored minority carrier
charge in the neutral base. If neutral base recombination is signi�cant,
then changing the quantity of stored minority carrier charge in the
neutral base will change the component of base current Ib2 = Qdb=�nthat arises from neutral base recombination.
r� =dVCEdIb2
� this term is usually only important for lateral bipolar transistors that
have a large base width, and has also been found to be important in
some types of vertical SiGe heterojunction bipolar transistors.
� usually, even for transistors with signi�cant neutral base recombina-
tion, r� >> ro.
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Bipolar Transistors, E&CE 730, January, 2002 129
Charge Storage E�ects
(Junction and Di�usion Capacitances)
� charge storage e�ects on bipolar transistor time-dependent behaviour
are modeled by:
� three nonlinear junction capacitances including,
1. Cje | the emitter-base junction capacitance
2. Cjc | the collector-base junction capacitance
3. Cjs | the collector- substrate junction capacitance
� two nonlinear di�usion capacitances to account for stored minority
carrier charge including,
1. CDE | di�usion capacitance in forward active operation
(Vbe > 0, Vbc < 0).
2. CDC | di�usion capacitance in reverse active operation
(Vbc > 0, Vbe < 0).
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Bipolar Transistors, E&CE 730, January, 2002 130
rb
rb
rex
Cje
Cjc
Cjs
Cjs
Cjs
rc
rc
rc
E
Bn +
n+
p
epin
C
p +p
+
-
n
p
Source of Parasitic Capacitances and Resistances in a PN -Junction
Isolated Bipolar Transistor Process
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Bipolar Transistors, E&CE 730, January, 2002 131
Junction Capacitances
Cje(Vbe) =CJE
(1� Vbe=VJE)ME
Cjc(Vbc) =CJC
(1� Vbc=VJC)MC
Cjs(Vcs) =CJS
(1� Vcs=VJS)MS
� the junction capacitance SPICE model parameters are,
1. CJE | zero bias (Vbe = 0) emitter-base junction capacitance
2. VJE | emitter-base junction built-in voltage
3. ME | emitter-base junction exponential factor
4. CJC | zero bias (Vbc = 0) collector-base junction capacitance
5. VJC | collector-base junction built-in voltage
6. MC | collector-base junction exponential factor
7. CJS | zero bias (Vcs = 0) collector-substrate junction capacitance
8. VJS | collector-substrate junction built-in voltage
9. MS | collector-substrate junction exponential factor
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Bipolar Transistors, E&CE 730, January, 2002 132
Di�usion Capacitance
W e W b
region
emitter
neutral
Wscl
region
base
N(x)space charge layer
emitter-base
space charge layer
collector-base
neutral
collectorQ Q
Q
de db
dc
debQ
Sources of Minority Carrier Stored Charge in a Bipolar Transistor
� stored minority carrier charge in various regions of the bipolar transis-
tor contribute to the overall delay in response of the bipolar transistor
to time varying signal inputs.
� the charge storage regions are,1. emitter neutral region | Qde = emitter stored di�usion charge
2. base neutral region | Qdb = base stored di�usion charge
3. emitter-base space charge layer |Qdbe = emitter-base space charge
layer stored di�usion charge
4. collector-base space charge layer | Qdc = collector-base space
charge layer stored di�usion charge
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Bipolar Transistors, E&CE 730, January, 2002 133
� in general the total stored charge Qdf in the forward active region of
operation (Vbe > 0, Vbc < 0) is di�erent from the total stored charge
Qdr in the reverse active region of operation (Vbc > 0, Vbe < 0),
� the small signal a.c. di�usion capacitance for forward active operation
Cde is de�ned as,
Cde =dQdf
dVbe=dQdf
dIc
dIcdVbe
= �FgmF
� the small signal a.c. di�usion capacitance for reverse active operation
Cdc is de�ned as,
Cdc =dQdr
dVbc=dQdr
dIc
dIcdVbc
= �RgmR
� �F and �R are the overall forward and reverse transit times of the
transistor which can be measured using high frequency techniques.
� gmF and gmR are the low frequency small signal transconductances
given by,
gmF =ISVT
exp
0@VbeVT
1A ; gmR =
ISVT
exp
0@VbcVT
1A
� the di�usion capacitance SPICE model parameters are,
1. �F | forward transit time
2. �R | reverse transit time
� considering forward active operation (VBE > 0, VBC < 0), the forward
transit time �F can be broken down into sub-components of transit
time for each charge storage region such that,
�F = �e + �b + �be + �c
� �e = emitter delay or emitter transit time.
� �b = base delay or base transit time.
� �be = base-emitter space charge layer delay or emitter-base space charge
layer transit time (usually negligible).
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Bipolar Transistors, E&CE 730, January, 2002 134
� �c = collector delay or collector transit time.
� for a uniformly doped shallow emitter transistor in low level injection:
�e =Qde
IC
Qde =qAEn
2iWe
2Neexp
0@VbeVT
1A ; IC =
qAEDnn2i
NbWbexp
0@VbeVT
1A
�e =WeWbNb
2DnNe
� IC is the d.c. collector current.
� AE is the emitter area, We is the neutral emitter width, Wb is the
neutral base width, Ne is the emitter doping, Nb is the base doping,
Dn is the electron di�usivity in the neutral base region.
�b =Qdb
IC
Qdb =qAEn
2iWb
2Wbexp
0@VbeVT
1A ; IC =
qAEDnn2i
NbWbexp
0@VbeVT
1A
�b =W 2
b
2Dn
�be =Qdbe
IC; usually negligible
�c =Wscl
2vth
� Wscl = width of reverse biased collector-base space charge layer, vth =
thermal drift velocity (� 107 cm=sec for silicon).
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Bipolar Transistors, E&CE 730, January, 2002 135
Parasitic Resistances
(Emitter, Base and Collector Series Resistance)
� parasitic refers to electrical behaviour of transistors which originates
from physical sources that are not responsible for transistor action and
which usually decrease transistor performance.
� series resistance arises from the physical material which is required to
contact the emitter, base, and collector regions of a bipolar transistor,
such as semiconductor, metal, silicides, etc.
� in general these resistances can depend upon current and voltage bias
levels; however, for small signal operation it is assumed that they are
constant for a particular bias.
� rb = base series resistance (e.g. 50 to 500 ), rex = series emitter
resistance (e.g. 1 to 10 ), and rc = series collector resistance (e.g. 20
to 500 ).
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Bipolar Transistors, E&CE 730, January, 2002 136
Small Signal Hybrid-� Equivalent Circuit
v πr
πr
oC
dC
je
Cjc
Cjs
rb
rc
rex
rµ
gm
v π
bc
e
Hybrid-� Small Signal A.C. Equivalent Circuit Including Parasitic
Capacitances and Terminal Series Resistances
� by far the most widely used small signal equivalent circuit for the
bipolar transistor is the hybrid-� equivalent circuit.
� this particular circuit model applies only for a particular bias point in
an active region of operation (usually forward active operation), and is
generally valid up to the frequency where the a.c. current gain drops
below unity.
� the basic hybrid-� equivalent circuit includes only the active transistor
elements:
r� =�ogm; ro =
VAIC; cd = gm�f ;
r� usually neglected; gm =ICVT;
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Bipolar Transistors, E&CE 730, January, 2002 137
� cd is the forward di�usion capacitance (same as Cde in the SPICE
model), and �f is the forward transit time (same as �F in the SPICE
model).
� all parameters can be determined from quantities which depend only
upon d.c. bias and not frequency.
� the model parameters which must be extracted from a transistor in
order to determine the hybrid-� equivalent circuit for a particular bias
point are therefore: IC (d.c. collector current), VT = kT=q (thermal
voltage), VA (Early voltage), and �o (a.c. common-emitter current gain
which is not necessarily equal to the d.c. common-emitter current gain
�F ).
� to properly account for the impact of parasitics on high frequency
behaviour, junction capacitances and series resistances must be added.
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Bipolar Transistors, E&CE 730, January, 2002 138
Transition Frequency fT
v πr
πr
oC
dC
je
Cjc
Cjs
rb
rc
rex
rµ
gm
v π
bc
e
Hybrid-� Small Signal A.C. Equivalent Circuit for Transition Frequency
fT Calculation
� by de�nition, the transition frequency fT is the frequency where the
magnitude of the a.c. common-emitter current gain �(!) equals one
in forward active operation in common-emitter con�guration with the
collector terminal a.c. shorted to the emitter terminal (a.c. ground).
� the transition frequency is an important �gure of merit that describes
the absolute highest frequency of operation at which the transistor can
provide useful current gain, and therefore, current ampli�cation.
� the hybrid-� equivalent circuit can be used to determine a simple ex-
pression for fT in terms of device parameters.
� neglecting rex and r� the hybrid-� circuit becomes:
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Bipolar Transistors, E&CE 730, January, 2002 139
v πr
πr
oC
dC
je
Cjc
Cjs
rc
gm
v π
cb
ib
ic
� notice that the collector terminal has been a.c. shorted to ground.
� assuming that the frequency is low enough that the a.c. impedance
of the small signal collector-base capacitance cjc is much larger than
the collector resistance rc, cjc appears in parallel with the small signal
emitter-base junction capacitance cje and the di�usion capacitance cd.
� since cje and cd always appear in parallel, they are often lumped to-
gether as a single input capacitance c� = cje + cd.
� the complex a.c. input impedance z� then becomes,
z� = r�== [1=(j!(c� + cjc))] =r�
1 + j!r�(c� + cjc)
� (== means \in parallel with").
� �(!) = ic=ib.
� neglecting base series resistance rb the a.c. input voltage vbe becomes,
vbe = z�ib =r�ib
1 + j!r�(c� + cjc)
ic = gmvbe =gmr�ib
1 + j!r�(c� + cjc)
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Bipolar Transistors, E&CE 730, January, 2002 140
� since r� = �o=gm:
�(!) =icib=
gmr�1 + j!r�(c� + cjc)
=�o
1 + j!�o(c� + cjc)=gm
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Bipolar Transistors, E&CE 730, January, 2002 141
� for high frequency and large �o,
!�o
0@c� + cjc
gm
1A >> 1
�(!) � gmj!(c� + cjc)
j�(!)j = 1 when ! = !T = 2�fT =gm
c� + cjc
� therefore, the transition frequency is given by,
fT =gm
2�(c� + cjc)
� the magnitude of the a.c. current gain is usually expressed in decibels:
� for
!�o
0@c� + cjc
gm
1A >> 1
20 log10 j�(!)j = 20 log10
0B@ gm!(c� + cjc)
1CA dB
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Bipolar Transistors, E&CE 730, January, 2002 142
log10
f
fβ
20 log10
βo( )
slope =
20 dB per decade
( 6 dB per octave )
dB20 log10
β ( ω )
βo 2
20 log10
)(
f1 f
110
fT
0
current gain
unity
20 dB
10 times increase in frequency
linear extrapolation
3 dB
A.C. Common Emitter Current Gain �(!) versus Frequency
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Bipolar Transistors, E&CE 730, January, 2002 143
� in this frequency range:
{ if the frequency changes by a factor of 10 (one decade), then the
a.c. current gain changes by 20 dB.
{ if the frequency changes by a factor of 2 (one octave), then the a.c.
current gain changes by 6 dB.
{ the current gain{bandwidth product is constant such that:
j�(!)j � ! =gm
(c� + cjc)= !T
� f� is the frequency at which the magnitude of the common-emitter
a.c. current gain reduces by a factor ofp2 of its low frequency value
of �o.
j�j = �or1 + [!�o(c� + cjc)=gm]2
=1p2
� this occurs when
!��o
0@c� + cjc
gm
1A = 1
f� =!�2�
=fT�o
� f� is often called the beta cut-o� frequency and is approximately
the frequency above which one obtains the constant current gain {
bandwidth product discussed above.
� fT can be measured by plotting the measured magnitude of � versus
the logarithm of the frequency. When the frequency is high enough to
obtain a constant current gain { bandwidth product, one can simply
extrapolate the line to higher frequencies until the current gain is 1 and
then read o� the transition frequency from the frequency axis without
having to actually drive the transistor at the fT .
� the hybrid-� equivalent circuit can also be used to determine how the
fT changes with collector current.
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Bipolar Transistors, E&CE 730, January, 2002 144
� the parasitic capacitances cje, cjc in uence the fT at low currents.
�T =1
!T=c� + cjegm
=cje + cjcgm
+cdgm
=cje + cjcgm
+gm�fgm
=cje + cjcgm
+ �f =VTIC
(cje + cjc) + �f
� �T is the total delay time associated with the transistor which includes
the e�ects of both the stored minority carrier charges and the parasitic
junction capacitances.
� the junction capacitances cje; cjc are only weakly dependent on col-
lector current, and forward transit time is, to a �rst approximation,
independent of collector current for low level injection conditions.
IC
π2 τF
1
fT π2 τ
1
Τ=
Cjc+C je
VT )(π2
slope =1
Transition Frequency versus D.C. Collector Current
� plotting the the measured transition frequency fT versus the collector
current IC will yield an approximately straight line for low collector
currents with a slope of 1=(2�VT (cje + cjc)).
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Bipolar Transistors, E&CE 730, January, 2002 145
� at higher collector current, the di�usion capacitance will become signif-
icantly larger than the junction capacitances as more stored minority
carrier charge builds up in the transistor where the fT will reach its
maximum theoretical value of the forward transit time �f .
� in reality, at very high collector currents, the fT begins to fall-o� again
due to other physical e�ects not discussed here. These e�ects can
become important before a bipolar transistor reaches its theoretical
maximum performance frequency.
� usually, bipolar transistors are designed and biased to operate at the
maximum possible fT for maximum speed of operation.
� the variation of fT at low currents can be exploited to extract the cjeand �f if cjc is known.
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Bipolar Transistors, E&CE 730, January, 2002 146
Large Signal Operation
Forward Active Operation
VBE
VBC
V CEI
B
IC
IE
npn
Terminal Current and Voltage Conventions for NPN Bipolar Transistor
�F =ICIE
=IC
IB + IC=
IC=IB1 + IC=IB
=�F
1 + �F
( )BE
T
B
E
C
BEV exp
V
VI=I
IB
C S
=C
I
βF
Ideal Large Signal Model for npn
Bipolar Transistor
Ideal D.C. Large Signal Equivalent Circuit for NPN Bipolar Transistor
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Bipolar Transistors, E&CE 730, January, 2002 147
Early E�ect
log10
Nnet
(x)
cm -3( )
∆
∆VBE
> 0( )
electrons (minority carriers)
0 bW
n
p
n
E
B
C
W b
VCB
electron concentration profile changes
thereby changing collector current
Impact of Changing Collector-Base Voltage on Neutral Base Region
Width Giving Rise to the Early E�ect
� Change in Vcb for a constant VBE results in a change in the neutral
base width Wb which in turn causes IC to change.
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Bipolar Transistors, E&CE 730, January, 2002 148
VAF
CI
VCE
V
VBE3
V
VBE4
BE5
BE2V
BE1
0
Graphical Representation of the Forward Early Voltage VAF
IC(0) = IS exp
0@VBEVT
1A
IC(VCE) = IC(0) +@IC@VCE
VCE
= IC(0) +IC(0)
VAF + VCEVCE
� IC(0) +IC(0)
VAFVCE for VAF >> VCE
� IS
0@1 + VCE
VAF
1A exp
0@VBEVT
1A
� VAF can be less than 20 V for high performance bipolar transistors.
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Bipolar Transistors, E&CE 730, January, 2002 149
Saturation and Inverse Active Operation
� in saturation both the emitter-base and collector-base junctions are
forward biased.log
10N
net(x)
cm -3( )
VBE
> 0
IBE
BCI
nr
(x)
nr
(x)
holes (minority carriers)
W e 0 0 bW
n
p
n
( ) ( VBC
0 )
E
B
C
>
= +n(x) nf
(x)
nf
(x)
p(x)
electrons (minority carriers)
Minority Carrier Distributions Under Saturation Conditions in a Bipolar
Transistor
IC =qAEDnavn
2iRWb
0 p(x)dx
24exp
0@VBEVT
1A� exp
0@VBCVT
1A35
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Bipolar Transistors, E&CE 730, January, 2002 150
� in saturation:
1. VCE is low (typically 0.05 to 0.3 V ).
2. output resistance is low.
3. �F is low (called forced current gain) due to decreasing IC and
increasing IB = IBE + IBC .
IB
= 0
IB
= 0
IC
V CE
Saturation Region
Saturation Region
Inverse Action Region
Forward Active Region
IB4
IB3
IB2
B1I
0
Collector Current versus Collector-Emitter Voltage in Forward Active
Operation for Common Emitter Con�guration
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Bipolar Transistors, E&CE 730, January, 2002 151
Common-Base Avalanche Breakdown in Bipolar
Transistors
VCBI
E
IC
Bipolar Transistor Biased in Forward Active Operation in Common-Base
Con�gurationI
C
IE
= 0
V CB
B V CBO
IE1
IE3
IE2
Collector Current versus Collector-Base Voltage in Forward Active
Operation for Common-Base Con�guration
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Bipolar Transistors, E&CE 730, January, 2002 152
� for IE = 0 (open emitter), the collector-base junction breaks down at
VCB = BVCBO.
� for non-zero emitter current, the common-base current gain becomes
greater than unity during avalanche breakdown.
� de�ning �0
F to be the actual common-base current gain during break-
down and �F to be the current gain for no breakdown,
�0
F =M�F
IC = �F IEM = �0
FIE
where
M =1
(1� VCB=BVCBO)n ; n = 3 to 6, typically for silicon
� For Nepi >> Nb,
BVCBO =�sE2crit2qNepi
� Vbicb
� Ecrit � 3� 105 V=cm, Vbicb = the built-in voltage of the collector-base
junction.
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Bipolar Transistors, E&CE 730, January, 2002 153
Common-Emitter Avalanche Breakdown in Bipolar
TransistorsI
B
VCE
IB
= 0I
B4
IB3
IB2
B1I
0CEV
IC
maxββ <
BV BV<CBO
( )CEO
Common-Emitter Forward Active Output Characteristics under
Conditions of Breakdown
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Bipolar Transistors, E&CE 730, January, 2002 154
log10
Nnet
(x)
cm -3( )
Xj1
Xj2
0 x
CBV
Cn
B
p
E
n
Internal Electron-Hole Generation in Collector-Base Space Charge Layer
under Conditions of Avalanche Breakdown
� electron-hole pairs generated in the collector-base space charge layer
during avalanche breakdown results in holes being swept into the neu-
tral base region.
� these holes further forward bias the emitter-base junction increasing
IC .
� avalanche generated holes swept into the neutral base opposes normal
base current resulting in a net reduction in terminal base current and
an increase in �F .
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Bipolar Transistors, E&CE 730, January, 2002 155
cI
log10
Ic
log10
I b
Ib
0 VBE
base current reduction
due to Avalanche Breakdown
Gummel Plot Depicting Base Current Reduction under Avalanche
Breakdown Conditions
BVCEO � BVCBO
(�F )1n
� e.g. if n = 4 and �F = 100, then BVCEO = BVCBO=3.
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Bipolar Transistors, E&CE 730, January, 2002 156
Zener Breakdown in Bipolar Transistors
� Zener breakdown is most likely to occur across the emitter-base junc-
tion since this junction is usually the most highly doped on either
side.
� as a rule of thumb, Zener breakdown mechanisms can be expected to
occur if both sides of the emitter-base junction are doped over 1018
cm�3.
Punch-Through
� punch-through will occur when the emitter-base and collector-base
space charge layers meet which produces an electrical e�ect similar to
avalanche breakdown except for the base current reduction.
� punch-through is most likely to occur in narrow base transistors for
high reverse collector-base voltages or low forward emitter-base volt-
ages.
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Bipolar Transistors, E&CE 730, January, 2002 157
Temperature Dependence of Common-Emitter Current
Gain
µ A1 Aµ10 100 Aµ 1 mA 10 mAI
C
βF
300
200
100
log10
T = 25 C
T = 125 C
T = -55 C
Typical Temperature and Collector Current Dependence of Forward
D.C. Current Gain
�F / exp
0B@Eg emitter �Eg base
kT
1CA
� typical temperature coeÆcient of �F = + 7000 ppm=C.
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Bipolar Transistors, E&CE 730, January, 2002 158
High Level Injection
n(x)
p(x)
eN
bN
Nepi
0 Wb
depth
x
n-type
p-type
n-type
Electron and Hole Distributions in the Neutral Base of a Bipolar
Transistor under Conditions of High Level Injection
� When the emitter-base junction is suÆciently forward biased, the car-
rier concentration injected into the base rises above the base impurity
concentration.
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Bipolar Transistors, E&CE 730, January, 2002 159
� for p{neutral region in HLI:
n�(x) +N�
A = p+(x); n(x) >> NA
� where NA is the acceptor doping Nb in the base, n are the minority
carrier electrons, and p are the majority carrier holes.
� for charge neutrality in HLI:
n(x) � p(x)
� Since IC >> IB, one can assume that the hole current Ip in the base
region is nearly zero compared to the electron current In.
IB = AEJp = qAE(�ppE �Dpdp
dx) � 0
� the electric �eld in the base region is then given by:
E =Dp
�p
1
p
dp
dx= VT
1
p
dp
dx
� where Einstein's relation Dp=�p = VT has been used.
� for High Level Injection, since n(x) � p(x),
E = VT1
n
dn
dx
� therefore the electron current (which makes up the collector current)
is given by,
IC = AEJn = qAE
0@�nnE +Dn
dn
dx
1A
= 2qAEDndn
dx= 2qAEDn
n(0)� n(Wb)
Wb
= 2qAEDnn(0)�Nb
Wb� 2qAEDn
n(0)
Wb
� a non-zero electric �eld E in the neutral region results in a voltage drop
Van across the neutral region given by,
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Bipolar Transistors, E&CE 730, January, 2002 160
Van = V (Wb)� V (0) = �Z Wb
0Edx = �VT
Z Wb
0
1
n
dn
dxdx
= �VTZ Wb
0d ln(n) = VT ln
0B@ n(0)
n(Wb)
1CA
= VT ln
0B@n(0)Nb
1CA
� The total applied forward bias VF is comprised of the voltage Vj across
the junction itself plus the neutral region voltage drop Van.
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Bipolar Transistors, E&CE 730, January, 2002 161
� The electron concentration n(0) injected into the base region is given
by,
n(0) =n2iNb
exp
0@VjVT
1A ; Vj = VT ln
0B@n(0)Nb
n2i
1CA
VF = Vj + Van
= VT ln
0B@n(0)Nb
n2i
1CA + VT ln
0B@n(0)Nb
1CA
= VT ln
0B@n
2(0)Nb
n2iNb
1CA = 2VT ln
0B@n(0)ni
1CA
n(0) = ni exp
0@ VF2VT
1A
IC =2qAEDnni
Wbexp
0@ VF2VT
1A
� By de�nition, high level injection begins when the electron concentra-
tion injected into the base equals the base doping (i.e. n(0) = Nb).
� The collector current IHLI for which this occurs is therefore given by,
IHLI =2qAEDnNb
Wb
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Bipolar Transistors, E&CE 730, January, 2002 162
The Kirk E�ect
ε
ε
ε
epiN
epiN
epiN
area = V cb
area = V cb
area = V cb
nc N
epi<
nc N
epi=
nc N
epi>
n c
n c
Wbo
Wbo
W kW
b
N(x)
x
N(x)
x
N(x)
x
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Bipolar Transistors, E&CE 730, January, 2002 163
dEdx
=p� n +ND �NA
�s
for nc < Nepi;dEdx
=Nepi � nc
�s> 0
for nc > Nepi;dEdx
=Nepi � nc
�s< 0
� Reversal of the electric �eld in the collector-base space charge layer
results in the space charge layer moving to the Nepi - n+ buried layer
boundary thereby electrically widening the neutral base.
� The collector current IK for the onset of the Kirk E�ect when the
electron concentration in the collector space charge layer equals the
collector epitaxial doping (i.e. nc = Nepi) can be shown to be,
IK = qAEvthNepi
0B@1 + Vcb
Vrt epi
1CA
� where vth = 107 cm=sec is the the drift saturation velocity for silicon,
and Vrt epi is the reverse collector-base voltage required to cause the
collector-base space charge layer to reach through to the edge of the
buried layer.
Vrt epi =qNepiW
2epi
2�s
![Page 174: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/174.jpg)
Bipolar Transistors, E&CE 730, January, 2002 164
Lateral Base Widening
(The Van der Ziel and Agouridis E�ect)
L L
Wbo
L
Wb
emitterbase
B
� Once collector current exceeds the Kirk current IK , the vertical com-
ponent of IC will increase much more slowly since IC is inversely pro-
portionally to the electrically neutral base width Wb = Wbo +Wk.
� For currents above IK , IC will therefore tend to ow more outside the
portion of base region directly beneath the emitter di�usion, resulting
in appreciable laterally directed or sidewall electron current ow.
� A simple model for the behaviour of IC above the Kirk current can be
derived assuming the the vertical portion of IC beneath the emitter
remains constant at IK .
![Page 175: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/175.jpg)
Bipolar Transistors, E&CE 730, January, 2002 165
IC = JKBL + JKBL0
= JKB(L + L0
)
L0
=ICJKB
� L = L
0@ICIK� 1
1A
W0
b =rW 2
bo + (L0)2=4
B = emitter stripe length
L = emitter stripe width
L0
= lateral current widening dimension
Wbo = vertical neutral base width before Kirk e�ect
Wb = vertical neutral base width after Kirk e�ect
W0
b = e�ective base width due to lateral current ow
JK = Kirk current density (A=cm2).
![Page 176: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/176.jpg)
Bipolar Transistors, E&CE 730, January, 2002 166
Quasi-Saturation
VBC internal
V CB applied
IC I
C R epi
� When the ohmic drop ICRepi across the collector epitaxial layer at-
tains a value greater than the applied collector-base junction terminal
voltage, the internal collector-base junction becomes forward biased.
� The undepleted vertical epitaxial layer below the collector-base space
charge layer contributes signi�cantly to the overall internal collector
resistance.
ICRepi � VBC internal = VCB applied
� Assuming that the collector-base junction becomes noticeably forward
biased when its internal voltage exceeds 0.5 volts, one can write an
expression for the collector current at which quasi-saturation occurs,
ICQS =VCB applied + 0:5
Repi
Repi =1
q�nNepi
0@Wepi �Wscl
AE
1A
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Bipolar Transistors, E&CE 730, January, 2002 167
Emitter Current Crowding
IB
IB
Jcentre
VBE centre
Jedge
V BB
base
b b
emitter
� Lateral ohmic drops along the undepleted intrinsic pinched base region
beneath the emitter di�usion results in a de-biasing of the centre of
the emitter-base junction.
� This results in emitter current being larger near the edge of the emitter-
base junction sidewalls than in the centre { a condition referred to as
\emitter current crowding".
VBE centre = VBE edge � VBB0
JedgeJcentre
= exp
0@VBB0VT
1A
� If VBB0 > VT = 26mV then signi�cant emitter current crowding oc-
curs.
� High current e�ects which result in decreasing current gain and tran-
sition frequency are driven by current density phenomena.
� Emitter current crowding reduces the overall e�ective emitter area
resulting in the onset of high current e�ects for lower collector currents.
![Page 178: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/178.jpg)
Bipolar Transistors, E&CE 730, January, 2002 168
� The e�ective emitter area resulting from emitter current crowding can
be estimated by a formula [Hauser] which is modelled in SPICE as,
Leff
L=
sinZ cosZ
Z; Z tanZ =
IBRB
2VT
RB for two base contacts =L
4B�bWb
�b = base conductivity
Wb = neutral base width
B = emitter stripe length
L = emitter stripe width
� For Z tanZ � 1,
Leff � L
1 + (IBRB)=(2VT )
b b
emitter
basep
n
collector-base
space charge layer
localised base widening due to Kirk Effect and Emitter Current Crowding
buried layern +
Non-Uniform \Base Push-out" at High Collector Currents in the
Presence of Emitter Current Crowding
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Bipolar Transistors, E&CE 730, January, 2002 169
Increase in Forward Transit Time �F at High Currents
Ic
ln
τ F
IKF
� Lateral Base widening from the Van der Ziel and Agouridis E�ect
reduces the transition frequency by increasing the base transit time �b.
� The increased base transit time �0
b resulting from lateral base widening
is given by,
�0
b =(W
0
b)2
2Dn=W 2
bo
2Dn+(L
0
)2=4
2Dn
= �b
2641 +
0@ L
2Wbo
1A2
0@ ICJKBL
� 1
1A2375
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Bipolar Transistors, E&CE 730, January, 2002 170
� In SPICE the increase in forward transit time (of which base transit
time is one component) with collector current is modelled by,
�FF = �F
2641 +XTF
0@ ICIC + ITF
1A2 exp
0@ VBC1:44VTF
1A375
�F is the low current forward transit time.
XTF corresponds to the geometrical terms involving L and Wbo.
ITF corresponds approximately to the Kirk current.
VTF models the in uence of extra stored charge in the neutral base from
a forward biased collector-base junction in saturation conditions.
� Model parameters XTF , ITF , and VTF are usually determined from
indirect methods (i.e. �tting to measured fall-o� in fT versus IC at
high collector currents).
![Page 181: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/181.jpg)
Bipolar Transistors, E&CE 730, January, 2002 171
Base Resistance
emitter
bb
lb
b
B
L
R
base
RBX BI
Components of Base Resistance in a Bipolar Transistor
� Base resistance limits the rate at which the input capacitance of a
bipolar transistor can be charged and discharged, thereby limiting the
response speed.
RBX =RSBX(lb=bb) +Rcontact
nb
RSBX = extrinsic base di�usion sheet resistance.
nb = number of base contacts.
Rcontact = base contact resistance.
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Bipolar Transistors, E&CE 730, January, 2002 172
� RBI is the intrinsic base resistance of the \pinched" neutral base region
beneath the emitter di�usion, and for low currents can be estimated
by,
RBI =
0@ 1
Fb
1A0B@ L=B
q�pNbWb
1CA
� Fb is a factor which takes into account the number of base contacts
and the distributed ow of base current underneath the emitter region.
� For two base contacts, Fb = 12 (a factor of 2 for parallel base current
ow from two base contacts, a factor of 2 since each base current
component ows half the width of the emitter stripe width L, and
a factor of 3 assuming a linearly decreasing lateral base current ow
underneath the emitter).
� For one base contact Fb = 3.
� Emitter current crowding decreases the intrinsic base resistance RBI
and can be modelled by the following [Hauser],
RBI = RBM + 3 (RB �RBM)
0@tanZ � Z
Z tan2Z
1A
RBM = minimum base resistance that occurs at high currents.
RB = the base resistance for low currents.
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Bipolar Transistors, E&CE 730, January, 2002 173
� In SPICE, Z is modelled approximately by,
Z � �1 +r1 + (144IB)=(�2IrB)
(24=�2)rIB=IrB
IrB = the base current where the base resistance falls halfway to its
minimum value.
� If IrB is set to zero in SPICE then RBI is modelled using,
RBI = RBM +RB �RBM
qb
where qb is the same normalise charge used for the Gummel-Poon model
of IC .
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Bipolar Transistors, E&CE 730, January, 2002 174
SPICE Model Parameter Extraction
VBC
= 0
VBE V
T
slope = 1 N F
slope = 1 N SE
ln ISE
0
ideal region
CI
IB
ln IC
ln IB
ln I S
Extraction of NF , NE , IS, ISE
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Bipolar Transistors, E&CE 730, January, 2002 175
Measurement Set-up to Obtain Gummel Plots
A
AA
A
VBE
IB
IC
VBE
IB
IC
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Bipolar Transistors, E&CE 730, January, 2002 176
Forward Output Characteristics including Measurement
Set-up
IB
VCE
IB
= 0I
B4
IB3
IB2
B1I
0CEV
IC
maxββ <
BV BV<CBO
( )CEO
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Bipolar Transistors, E&CE 730, January, 2002 177
Extraction of Maximum Forward Common-Emitter
Current Gain �F
βF
VBC
= 0
IC
log10
( )
VBC
= 0
VBE
βF
= IC
I B
0
ideal region
CI
IB
ln IC
ln IB
� �F is the d.c. value of the maximum forward common-emitter current
gain as opposed to the a.c. value.
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Bipolar Transistors, E&CE 730, January, 2002 178
Extraction of Series Resistances
� Series resistances RE, RB, and RC should be extracted as close as
possible for the operating conditions under which the transistor will
operate in the particular application.
Measurement Set-up to Extract D.C. Emitter Resistance
RE
VCE
IB
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Bipolar Transistors, E&CE 730, January, 2002 179
Extraction of Emitter Resistance RE (\Fly-Back E�ect")
slope =
1
R E
βR is small during saturation
βR
VCE
BI
0
rapidly increases as
transistor comes out ofsaturation
VCE = VT ln
0@1 + �R
�R
1A + IBRE
� The emitter resistance should be obtained from the inverse of the slope
of the IB versus VCE characteristic for open collector as close as possible
to the yback region.
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Bipolar Transistors, E&CE 730, January, 2002 180
Extraction of D.C. Collector Resistance RC
slope = 1
slope =
1
RC sat
RC linear
CEV
CI
B1I
IB2
IB3
IB4
0
� RC linear is the normal active operation value of RC which is used for
linear operation of the transistor (e.g. small signal a.c. operation).
� RC linear is obtained from the inverse of the slope of the line drawn
through the \knees" of the output characteristics.
� RC linear should be used for correct modelling of the fT and charge
storage e�ects.
� It is often diÆcult to determine precisely where the \knees" of the
output characteristics actually are.
� RC sat is obtained from the inverse of the slope of the saturation line
in the output characteristics.
� If RC sat is determined in this fashion, corrections must be made for
internal saturation e�ects.
VCE sat = VT ln
0B@1 + (IC=IB)(1� �R)
�R[1� IC=(�FIB)]
1CA + IERE + ICRC
![Page 191: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/191.jpg)
Bipolar Transistors, E&CE 730, January, 2002 181
� First term in above equation for VCE sat can be eliminated if IB versus
VCE is measured for di�erent forced values of IC such that the forced
current gain IC=IB remains constant but less than the maximum for-
ward active region current gain �F .
� This approach assumes that RE << RC and that �R, �F , RE, and
RC are all constant over the range of base and collectors currents used
in the measurement.
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Bipolar Transistors, E&CE 730, January, 2002 182
Alternative More Accurate Method to Extract RC
VCE
BI
( 2 µA/div )I
C
used to
determine
RC linear
slope =
1
R E
VCE
0(5 mV/div)
= 0( 0.2 mA/div)
used to
determine
R C sat
IB
CIforced steps
IC
forced
VBE
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Bipolar Transistors, E&CE 730, January, 2002 183
Expanded View of RC Extraction Method Using Forced
Collector Current Steps
VCE
BI
IB2
B1I
IC1
IC2
IC1
B1I I
B2
IC2
∆ V
∆ V
IC2
IC1
0
=
RC
=
� RC sat is determined for high values of IB where the transistor is
saturated.
� RC linear is determined for low values of IB as close as is practical to
the \knees" of the forced collector current IB versus VCE curves.
� Changes in IB and IC for the measurement should be small.
� The output characteristics should be inspected to determine the bias
operating point before measuring RC .
![Page 194: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/194.jpg)
Bipolar Transistors, E&CE 730, January, 2002 184
Collector Resistance Components in an Integrated Bipolar
Transistor
n
n
n
p
emitter
base
buried layer RCL
n RCV
collectort
epi
p
N epi
Rcontact
� RC can be divided roughly into two principal components:
1. RCL which is bias independent and comprised of the heavy doped
buried layer and collector sinker regions.
2. RCV which is bias dependent and comprised of the low doped un-
depleted portion of the collector epitaxial region below the emitter.
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Bipolar Transistors, E&CE 730, January, 2002 185
� RCV changes with:
1. the width of the collector-base space charge layer (due to changes
in VCB),
2. conductivity modulation in saturation due to a forward biased
collector-base junction, and
3. conductivity modulation from electrons in the neutral epitaxial col-
lector at high collector currents.
� Advanced methods exist to determine these separate components of
RC such as exploiting the substrate current from the parasitic pnp
transistor in pn-junction isolated bipolar processes [Park].
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Bipolar Transistors, E&CE 730, January, 2002 186
Base Resistance (RB) Extraction
� The measured value of RB depends strongly upon the operating point
of the transistor as well as the technique used to measure it.
� RB should be measured using a technique which corresponds to the
operating conditions under which the transistor is expected to operate
in an application.
� Several categories of techniques exist to measure RB including,
1. noise measurement techniques which should be used if RB is being
measured to determine its contribution to noise.
2. pulse measurement techniques which should be used if the transis-
tor is to be operated in switching applications (e.g digital).
3. small signal measurement techniques which should be used if the
transistor is to be used in linear small signal applications.
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Bipolar Transistors, E&CE 730, January, 2002 187
Input Impedance Circle Method to Extract rb
rπ
rog
mv π
cπv π
b
e
c
Small Signal Hybrid-Pi Equivalent Circuit of a Bipolar Transistor Biased
in the Forward Active Region
Zin = rb +r�
1 + j!r�c�
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Bipolar Transistors, E&CE 730, January, 2002 188
Extraction of A.C. Base Resistance rb
πr+brr
bRe (Z in )
in)Im (Z
cπ c
π
infinityωω 0( = short circuit )
open circuit=( )
deviation from lumped hybrid-pi
equivalent circuit at high frequencies
due to distributed effects
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Bipolar Transistors, E&CE 730, January, 2002 189
\Ning and Tang" Method for Extracting Emitter and Base
Resistance [Ning]
ln Ib
ln I c
∆ V
0BE
V
Ibo
coI
CI
BI
1.21.00.8
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Bipolar Transistors, E&CE 730, January, 2002 190
Components of Emitter and Base Resistance Involved in
\Ning and Tang" Method
VBE
IB
EI
VCER
BI+ R BX
RE
base
b
emitter
R
R BX BIR
E
IBo = IB exp
0B@IERE + IB(RBI +RBX)
VT
1CA
VTIC
ln
0@IBoIB
1A =
IERE + IBRBI + IBRBX
IC
=(IC + IB)RE + IBRBI + IBRBX
IC
= RE +RBI
�+RE +RBX
�
� RBI=� is assumed to be approximately constant with respect to bias.
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Bipolar Transistors, E&CE 730, January, 2002 191
RE
RE
)V T
(
1
β
+
RBI
β
+ RBX
slope =emitter current crowding
effect of
ln
I
IIC
Bo
B
Extraction of D.C. Resistance Components Using \Ning and Tang"
Method
� RBI=� is usually 1 to 2 ohms.
� Usually RBX >> RE and RE >> RBI=�.
� RBI can be determined from geometrical consideration.
� Ignores e�ects of emitter current crowding.
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Bipolar Transistors, E&CE 730, January, 2002 192
Junction Capacitance Model Parameter Extraction
0V
A
Cjo
Cj
reverse bias forward bias
Extraction of Zero Bias Junction Capacitances
Cj(VA) =Cjo
(1� VA=Vbi)m
� m = 0.5 for an abrupt step junction, m = 0.33 for a linear junction.
� Vbi = typically 0.5 to 0.7 V .
� To measure the various junction capacitances connect the respective
two transistor terminals to a capacitance bridge and leave the other
terminals open.
� Measurement frequency for a bridge is usually small enough to ignore
series ohmic losses.
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Bipolar Transistors, E&CE 730, January, 2002 193
Extraction of Junction Capacitance Parameters
V A V bi
log10
( C meas C k )
slope = - m
log10
( 1 )
Cmeas =Cjo
(1� VA=Vbi)m + Ck
� Ck is comprised of stray capacitance, pin capacitance, and pad capac-
itance, which are all assumed to be independent of transistor bias.
� One way to eliminate Ck is to plot log10(Cmeas�Ck) versus log10(Vbi�VA) using guess values for Ck and Vbi iteratively until a straight line is
obtained from which the slope will give the m power law.
� There is no unique solution for Vbi and m for a given Ck and Cj,
however, this is not important provided the model gives the correct
junction capacitance.
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Bipolar Transistors, E&CE 730, January, 2002 194
Extraction of Early Voltages VAF and VAR
VBE V
CE
VBE
C( V BC
= 0 )
VCE
( V BC= 0 )
IB
IC
I
=
slope = goF
IC =IS
1 + VBE=VAR + VBC=VAF
24exp
0@VBEVT
1A� exp
0@VBCVT
1A35
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Bipolar Transistors, E&CE 730, January, 2002 195
� The small signal forward output conductance is given by,
goF =dICdVCE
1AVBE=constant;VBC=0
= � d
dVBC
0B@ IS1 + VBE=VAR + VBC=VAF
24exp
0@VBEVT
1A� 1
351CA
=IC(VBC = 0)
VAF (1 + VBE=VAR)
� The small signal reverse output conductance is given by,
goR =dIEdVEC
1AVBC=constant;VBE=0
= � d
dVBE
0B@ IS1 + VBE=VAR + VBC=VAF
24exp
0@VBCVT
1A� 1
351CA
=IE(VBE = 0)
VAR (1 + VBC=VAF )
� Solving expressions for forward and reverse output conductances si-
multaneously yields for the forward and reverse Early voltages,
VAF =IC(VBC = 0)IE(VBE = 0)� goFgoRVBEVBC
goFIE(VBE = 0) + goFgoRVBE
VAR =IC(VBC = 0)IE(VBE = 0)� goFgoRVBEVBC
goRIC(VBC = 0) + goFgoRVBC
![Page 206: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/206.jpg)
Bipolar Transistors, E&CE 730, January, 2002 196
Knee Current Extraction
ln Ib
ln I c
corrected I C
BI
CI
0BE
V
IE
RE
= VBE
VB EB
RB
I
BoI
Correcting Gummel Plot for Series Resistance Losses
� Corrections must be made to the measured Gummel Plots to allow for
the voltage drops across the series resistances before the model knee
currents IKF and IKR can be extracted.
� Extrapolate the ideal portion of the IB curve to higher currents and
assume that this plot is a plot of IB versus the internal emitter-base
voltage VB0E0 .
� Subtract the voltage drop between the measured IB and the extrap-
olated ideal IBo from the IC curve for a various measured VBE 's to
obtain a corrected IC curve.
� Sometimes this technique produces a corrected IC curve which has an
ideality less than unity due to emitter sidewall injection e�ects.
![Page 207: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/207.jpg)
Bipolar Transistors, E&CE 730, January, 2002 197
ln I c
VB E
0V T
slope = 1ln I
KF
slope = 1 2
Extraction of \Knee" Currents IKF and IKR
� Use the corrected IC versus VB0E0 Gummel Plots in active forward and
inverse operation to determine IKF and IKR.
� IKF is extracted for VBC = 0 and IKR is extracted for VBE = 0
� One can also use �F versus IC to �t IKF and �R versus IE to �t IKR
using the Gummel-Poon model at high currents.
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MOS Transistors, E&CE 730, January, 2002 198
4 MOS Transistors
E&CE 730Physics & Modeling of Semiconductor Devices
Prepared by:
Professor John S. HamelDepartment of Elecrtrical & Computer Engineering
University of WaterlooWaterloo, Ontario, Canada, N2L 3G1
January, 2002
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MOS Transistors, E&CE 730, January, 2002 199
Band Diagrams of an MOS Capacitor
(n-channel enhancement mode MOSFET)
x0
E c
E fs
Ev
E iE
fm
gateelectrode
gateoxide
semiconductor substrate
tox
(p-type)
Positive Energy E
Positive Voltage V
� Fermi level Ef is \ at" for zero gate current.
� Efm, Efs are the gate electrode (metal or polysilicon) and substrate
Fermi levels.
� "Flat Band" conditions imply that the energy bands are \ at" such
that there are no internal potential changes within the substrate.
� If there is a contact potential di�erence �ms between the gate electrodeand substrate, and/or �xed oxide and interface charges, a gate voltage
must be applied to reach \ at band".
![Page 210: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/210.jpg)
MOS Transistors, E&CE 730, January, 2002 200
Accumulation in an MOS Capacitor
(n-channel enhancement mode MOSFET)
E i
E fs
E c
Ev
V s < 0
holes
Positive Voltage V
Efm
(VGS < 0)
Efm
(VGS = 0 )
Positive Energy E
x0
Vox
p-type
� For negative gate voltage (VGS < 0), the negative potential induced at
the gate oxide { substrate interface attracts holes above the equilibrium
hole concentration associated with the substrate doping NA.
V =�Ei
q; Efs = 0
p = ni exp
0@Ei �Efs
kT
1A = ni exp
0@� V
VT
1A
ps = ni exp
0@�Vs
VT
1A
� where Vs < 0 is the \surface" potential at the substrate surface at the
gate oxide { substrate interface.
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MOS Transistors, E&CE 730, January, 2002 201
Depletion in an MOS Capacitor
(n-channel enhancement mode MOSFET)
Vox
E iE fs
EvV s > 0E
fm(VGS > 0 )
Efm
(VGS = 0 )
Positive Energy E
Positive Voltage V
Wdep
E c
x0
φf
p-type
� For positive gate voltage, a positive induced voltage at the substrate
surface repels majority carrier holes in the p-type substrate resulting
in a depletion or space charge layer forming beneath the gate oxide.
� The width of the depletion layer can be approximated by,
Wdep =
vuuut2�sVsqNA
� The space charge layer contains negative �xed p-type ionic charge thatis not compensated by free positively charged holes.
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MOS Transistors, E&CE 730, January, 2002 202
Strong Inversion in an MOS Capacitor
(n-channel enhancement mode MOSFET)
Vox
E iE fs
Ev
E c
Efm
(VGS = 0 ) φf
x0
W m
Efm
(VGS = Vth
)
electrons
V s φf= 2
φf
Positive Voltage V
Positive Energy E
p-type
� A suÆciently large positive gate voltage increases the concentration
of free electrons at the surface which electrically \screen" holes in the
substrate such thatWdep =Wm, whereWm is the maximum depletion
width.
� When Vs = 2�F , the concentration of electrons per unit volume at the
surface becomes equal to the concentration of equilibrium holes in the
substrate bulk, and Wdep is assumed to be equal to Wm.
� \Strong Inversion" is de�ned to be when Vs = 2�F , where a \channel"
of free conducting electrons is formed.
�F = VT ln
0@NA
ni
1A ; Wm =
vuuuut2�s(2�F )qNA
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MOS Transistors, E&CE 730, January, 2002 203
MOS Diode Capacitance
(n-channel enhancement mode MOSFET)
C ox
Co
����������������������������������������������������������������������
����������������������������������������������������������������������
gate electrode
gate oxidetox
substrate
depletion layer
B
G
G
S
Cdfixed interfacecharge
Cox =�oxtox
per unit area; area = WL
Cd = depletion capacitance =�sWdep
per unit area
� Total MOS diode capacitance CT is given by,
1
CT=
1
Cox+
1
Cd + Co
� where Co is the capacitance associated with interface charge which can
be trapped in energy states caused by crystalline imperfections at the
surface.
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MOS Transistors, E&CE 730, January, 2002 204
Variation of Gate Capacitance with Gate Voltage
for an MOS Diode
(n-channel enhancement mode MOSFET)
Cox
Cmin
accumulation strong inversion
depletion
C gate
V g0
� Neglecting trapped interface charge capacitance Co,
1
CT=
1
Cox+
1
Cd
Cd =�sWdep
=
vuuutq�sNA
2Vs
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MOS Transistors, E&CE 730, January, 2002 205
Threshold Voltage (Vth)
in an Enhancement Mode n-Channel MOSFET
Level 1 Model
Vox
E iE fs
Ev
E c
Efm
(VGS = 0 ) φf
x0
W m
Efm
(VGS = Vth
)
electrons
V s φf= 2
φf
Positive Voltage V
Positive Energy E
p-type
� The threshold voltage Vth is the gate voltage VGS that results in the
onset of strong inversion where Vs = 2�F .
� When VGS = Vth, it is assumed that there are no free electrons at the
surface, and that Wdep = Wm.
� The total depletion charge Qd per unit area is,
Qd = �qNAWm = �2rq�sNA�F ; �F = VT ln
0@NA
ni
1A
� Using,
VGS = Vox + Vs; Vox =�Qd
Cox; Vs = 2�F
� Therefore,
Vth =�Qd
Cox+ 2�F
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MOS Transistors, E&CE 730, January, 2002 206
E�ects of Contact Potential �msand Oxide and Interface Charges on Vth
� The work function of a material is the energy required to remove an
electron from the material.
� Physically, the work function is the energy di�erence between the Fermi
level of the material and an energy level known as the vacuum level
Evac where it is assumed that the material no longer has any in uence
on the energy of the removed electron.
� When two materials are brought into contact, electrons move from one
material to the other because the energy of these carriers is in general
di�erent in the two materials.
� Since no net electric �eld exists in the separate materials before com-
ing into contact, the transfer of electrons from higher to lower energy
after the materials come into contact results in an electric �eld arising
between the two materials.
� The material with the largest work function has the electrons with
the lowest energy, since it takes more energy to remove them from the
material then from a material with a smaller work function.
� This results in the material with the smaller work function being at a
higher potential relative to the material with the larger work function.
� This potential di�erence is referred to as the \contact potential".
� If the work function of the gate electrode is less than that of the sub-
strate, then the potential of the gate will be higher than that of the
substrate.
� If the work function energy di�erence between gate electrode and sub-
strate �m � �s = �ms is negative, then a net negative electron charge
will transfer to the substrate from the gate (via outside source-body
connections) for VGS = 0.
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MOS Transistors, E&CE 730, January, 2002 207
� A negative �ms will therefore decrease the positive VGS required to
reached strong inversion in an n-channel enhancement mode MOS-
FET. Therefore a negative �ms will decrease Vth such that,
Vth = �ms +�Qd
Cox+ 2�F
� where in the Vth formula, �ms is expressed in units of voltage V =
�E=q and is actually the negative of the contact potential.
� Other charges exist within the gate oxide and at the interface that will
also cause Vth to deviate from simple theory.
� These charges are always positive and are denoted by an e�ective in-
terface charge Qi per unit area. Qi can be comprised of:
{ Qm: \mobile" ionic charge trapped (due to impurities such as
Sodium) in the gate oxide that can move under high electric �elds
and at elevated temperatures which can cause Vth to drift over pe-
riods of minutes to hours to days, and even over periods of months.
{ Qot: \trapped" oxide charge due to structural imperfections.
{ Qf : \�xed" oxide charges due to non-stoichiometric SiOx from
excess silicon ions.
{ Qit: dangling bonds at the Si{SiO2interface due to termination of
the silicon lattice.
� Since Qi is always positive, it e�ectively decreases the required gate
voltage to achieve strong inversion. Therefore,
Vth =
0@�ms � Qi
Cox
1A + �Qd
Cox+ 2�F = Vfb +
�Qd
Cox+ 2�F
� whereVfb =
0@�ms � Qi
Cox
1A
� Vfb is the \ at band" voltage, or the gate voltage required to eliminate
any internal potential in the substrate such that the energy bands do
not change with position in the vicinity of the substrate surface.
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MOS Transistors, E&CE 730, January, 2002 208
� At VGS = Vfb, all gate voltage appears across the gate oxide and
Vs = 0.
� The above formula for Vth is valid for both n and p-channel MOSFET's.
� For a p-channel MOSFET, however, �F is negative and Qd is positive
such that,
�F = �VT ln0@ND
ni
1A ; Qd = 2
rq�sND�F
� where ND is the n-type substrate doping.
� In SPICE, PHI = 2�F is usually taken to be always positive such that,
�F = VT ln
0@NSUB
ni
1A
� where NSUB is either the n- or p-type substrate doping level.
� To account for the changes in sign for Vth calculations, an internal typeparameter is used where type = 1 for n-channel and type = �1 for
p-channel devices.
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MOS Transistors, E&CE 730, January, 2002 209
E�ect of Substrate Voltage on Vth(The \Body E�ect")
��������������������������������������������������������
��������������������������������������������������������
p-type
substrate VBS < 0
Wm
depletion layergate oxide
� If the body (or substrate bulk contact) to source di�usion voltage VBSis negative, the width of the depletion layer between the gate Wm will
increase for a given applied gate voltage VGS.
� The increased negative charge in the depletion layer requires an in-
creased VGS to reach inversion thereby increasing Vth.
� The maximum depletion layer width Wm at the onset of strong inver-
sion is,
Wm =
vuuuut2�(2�F � VBS)
qNA
� The depletion charge per unit area is then,
Qd = �qNAWm = �r2q�sNA(2�F � VBS)
� resulting in a modi�ed expression for Vth such that,
Vth = Vfb � Qd
Cox+ 2�F
= Vfb +
0B@p2q�sNA
Cox
1CAr2�F � VBS + 2�F
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MOS Transistors, E&CE 730, January, 2002 210
= Vfb + r2�F � VBS + 2�F
� where the \Body E�ect" parameter is given by,
=
p2q�sNA
Cox
� To implement the above expression for Vth so that it can be used for
both n-channel and p-channel devices it can be written,
Vth = VTO +GAMMA
�pPHI � VBS �
pPHI
�
� where the zero substrate bias threshold voltage VTO is given by,
VTO = Vfb + type�GAMMA
pPHI + PHI
�
� and where is denoted by GAMMA in SPICE, and PHI = 2�F .
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MOS Transistors, E&CE 730, January, 2002 211
MOSFET Drain Current IDSLevel 1 Model
X j
Leffy = y = 0
VBS
V DS
VGS
x
y
VGS thV-=DSV
����������������������������������������������
��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
n+ Source n+ Drain
W
L
l (y)
Substrate or Bulkp-
SourceDrain
Gate
gate oxide
location where
pinch-off
� For VGS > Vth, it is assumed that signi�cant free electron charge Qn
exists within the channel.
� The gate voltage then becomes,
VGS = Vfb �0B@Qd(y) +Qn(y)
Cox
1CA + 2�F + Vc(y)
� where Qd(y) and Qn(y) vary with position along the channel beneath
the gate due to a changing channel potential Vc(y).
� The channel potential varies with position if there is a non-zero drain-
to-source voltage VDS which tends to reduce the voltage di�erence
between gate and substrate reducing the net charge at position y along
the channel.
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MOS Transistors, E&CE 730, January, 2002 212
Vc (y)
VGS Vth-
VDS
yLeff
� Solving for the depletion charge per unit area Qd(y) gives,
Qd(y) = �r2q�sNA(2�F � VBS + Vc(y))
� Neglecting e�ect of channel potential on Qd results in,
Qd(y) � �r2q�NA(2�F � VBS)
� The gate-to-source voltage is then approximated by,
VGS =
0@Vfb � Qd
Cox+ 2�F
1A� Qn(y)
Cox+ Vc(y)
= Vth � Qn(y)
Cox+ Vc(y)
� yielding for the channel inversion charge Qn(y),
Qn(y) = �Cox (VGS � Vth � Vc(y))
� Drain current IDS is composed primarily of electron drift current under
conditions of strong inversion such that,
IDS = In drift = qA(y)�n(y)nchannel(y)E(y)� �n(y) � an average constant channel mobility �n.
� The lateral electric �eld E(y) = �dVc(y)=dy
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MOS Transistors, E&CE 730, January, 2002 213
� Qn(y) = �qn(y)l(y), where l(y) is the thickness of the inversion layer
which gets progressively thinner towards the drain end of the channel.
� Cross-sectional area for current ow is A(y) = Wl(y).
� IDS then becomes,
IDS = �nWQn(y)dVc(y)
dy
� Substituting for Qn(y) yields,
IDSdy = ��nWCox [VGS � Vth � Vc(y)] dVc(y)
� Using the fact that IDS must be constant along the entire channel
from the source where y = 0 to the end of the e�ective channel length
y = Leff , integration yields,
�IDSZ Leff0
dy = ��nWCox
Z VDS0
[VGS � Vth � Vc(y)] dVc(y)
� giving for the Level 1 drain current model,
IDS =�nWCox
Leff
264(VGS � Vth)VDS � V 2
DS
2
375
� The above equation for IDS is valid provided a continuous channel
exists between the source and drain.
� Once VDS � VGS�Vth, the channel region closest to the drain end is nolonger in strong inversion thus creating a \pinch-o�" region adjacent
to the drain di�usion.
� When pinch-o� occurs, to a �rst order approximation IDS no longer
increases since the potential at the drain end of the inversion layer will
remain at VGS � Vth.
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MOS Transistors, E&CE 730, January, 2002 214
VDS (V)
IDS µA( )
V GS =
V DS VGS Vth VDSAT= - =
0 1 2 3 54
Linear Region
Saturation Region
1.5 V
2 V
3
4
5 V
V
V
� The drain current versus drain voltage characteristic IDS versus VDSthen becomes divided into two regions of operation.
� A \linear" region exists for small VDS where IDS is approximately
linearly related to VDS.
� A \saturation" region exists where to �rst order the drain current
\saturates" or is independent of the drain voltage. This occurs for
higher drain voltages where VDS > VGS � Vth, such that:
IDS =�nWCox
2Leff(VGS � Vth)
2
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MOS Transistors, E&CE 730, January, 2002 215
Implementation of the SPICE Level 1 MOSFET Model
( e.g. in Berkeley SPICE 3)
� The Threshold voltage is modelled by,
Vth = VTO +GAMMA
�pPHI � VBS �
pPHI
�
� In the linear region for VGS > Vth and VDS � VDSat, IDS is modelled
by,
IDS =KPW
(L� 2LD)
24VGS � Vth � VDS
2
35VDS(1 + LAMBDAVDS)
� In the saturation region where VDS > VDSat, IDS is modelled by,
IDS =KPW
2(L� 2LD)(VGS � Vth)
2 (1 + LAMBDAVDS)
� where VDSat is given by,
VDSat = VGS � Vth
� VTO is the threshold voltage for VBS = 0.
� KP = UOCox, Cox = �ox=TOX
� UO is the channel mobility �n for n-channel and �p for p-channel
devices.
� GAMMA = =p2q�sNSUB=Cox.
� PHI = 2�F .
� LD = lateral di�usion of source and drain di�usions.
� NSUB = NA = substrate doping.
� The e�ective channel length Leff is modelled by,
Leff =
0@L� 2LD
1 + �VDS
1A
� LAMBDA (�) models e�ective channel length shortening with increas-
ing VDS.
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MOS Transistors, E&CE 730, January, 2002 216
� The channel length modulation parameter is included in both the linear
and saturation regions so that the current and its �rst derivative are
continuous.
� VTO and GAMMA are known as \electrical parameters" while NSUB
and TOX are \process parameters". For all SPICE models, both kinds
of parameters can be entered with the convention that electrical param-
eters will always override the value computed from process parameters.
� For example if KP is not speci�ed but UO is, KP will be computed
from the entered TOX or its default value.
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MOS Transistors, E&CE 730, January, 2002 217
IDS µA( )
VGS(V)
VTO = 1 V
VTO = 1.2 V
VBS =
VBS =
0 1 2 3 54
1
2
3
40 V
-5 VW = 100 micons
L = 100 microns
Variations in drain current with VTO in transfer characteristics for Level
1 model.I
DS µA( )
VDS (V)
VTO =
VTO =
0 1 2 3 54
10
20
30
401 V
1.2 V
GS =
3 V
4 V
5 V
V 2 V
Variations in drain current with VTO in output characteristics for Level 1
model.
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MOS Transistors, E&CE 730, January, 2002 218
IDS µA( )
VGS(V)
VBS =
VBS =
µo= 800
µo = 850
0 1 2 3 54
1
2
3
40 V
-5 V
( )
)(
KP = 29.30
KP = 34.60
Variations in drain current with KP or � in transfer characteristics for
Level 1 model.I
DS µA( )
VDS (V)
0 1 2 3 54
10
20
30
40
GS =
3 V
4 V
5 V
V 2 V
KP = 29.30
KP = 34.60
Variations in drain current with KP or � in output characteristics for
Level 1 model.
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MOS Transistors, E&CE 730, January, 2002 219
IDS µA( )
VGS(V)
VBS =
VBS =
N B = 1015 cm -32 x
= 0.744 V1/2γ
N B = 1015 cm -3
= 0.526 V1/2γ
0 1 2 3 54
1
2
3
40 V
-5 V
Variations in drain current with or NA in transfer characteristics for
Level 1 model.I
DS µA( )
VGS(V)
Tox = 120 nm
Tox = 100 nm
VBS = 0 V
VBS = -5 V
0 1 2 3 54
1
2
3
4
Variations in drain current with tox in transfer characteristics for Level 1
model.
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MOS Transistors, E&CE 730, January, 2002 220
IDS µA( )
VDS (V)
TOX = 120 nm
TOX = 100 nm
0 1 2 3 54
10
20
30
40
GS =
3 V
4 V
5 V
V 2 V
Variations in drain current with tox in output characteristics for Level 1
model.I
DS µA( )
VDS (V)
GS =V 2 V
λ = 0.02 V -1
= 0 V -1
λ
0 1 2 3 54
10
20
30
40
3 V
4 V
5 V
Variations in drain current with � in output characteristics for Level 1
model.
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MOS Transistors, E&CE 730, January, 2002 221
Physical Basis of the SPICE Level 2
MOSFET Model
� Level 2 includes the e�ect of channel potential Vc(y) on the depletion
charge Qd(y) and drain current IDS.
Qd(y) = �q2q�sNA [2�F � VBS + Vc(y)]
12
� The electron charge in the channel Qn(y) then becomes,
Qn(y) = �Cox [VGS � Vfb � 2�F � Vc(y)]�Qd(y)
= �Cox [VGS � Vfb � 2�F � Vc(y)]
+ Cox [2�F � VBS + Vc(y)]12
� where Cox =p2q�sNA has been used.
� Drain current is expressed as per the derivation for the Level 1 model,
IDS = �nWQn(y)dVc(y)
dy
� Integrating along the length of the e�ective channel yields,
�IDSZ Leff0
dy = ��nWCox
Z VDS0
[VGS � Vfb � 2�F � Vc(y)]
� [2�F � VBS + Vc(y)]12 dVc(y)
� The Level 2 drain current model then becomes,
IDS =�nWCox
Leff
264(VGS � Vfb � 2�F )VDS � V 2
DS
2
�2
3 "(2�F � VBS + VDS)
32 � (2�F � VBS)
32
#35
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MOS Transistors, E&CE 730, January, 2002 222
Saturation Drain Voltage VDSatin the SPICE Level 2 Model
� Including the e�ect of channel potential on the depletion charge Qd(y)
allows for a more accurate determination of the drain voltage VDSatwhere drain current enters the saturation region.
� Assuming that saturation occurs when the channel potential Vc(y) =
VDSat at the same place in the channel where the channel charge
Qn(y) = 0 yields,
Qn(y) = �Cox [VGS � Vfb � 2�F � VDSat]�Qd(y)
= �Cox [VGS � Vfb � 2�F � VDSat]
� Cox [2�F � VBS + VDSat]12
= 0
� Solving for VDSat yields,
VDSat =
264VGS � Vfb � 2�F +
2
2
375�
264VGS � Vfb � VBS +
2
4
37512
� To compare, the Level 1 Model assumes a VDSat of,
VDSat = VGS � Vth
= VGS � Vfb � r2�F � VBS � 2�F
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MOS Transistors, E&CE 730, January, 2002 223
Calculation of Work Function Di�erence (�ms)
� SPICE MOSFET models Levels 2 and 3 allow for the inclusion of the
in uence of the work function di�erences between the gate electrode
and the substrate on Vth.
� It is easier to calculate �ms if initially units of energy are assumed.
Conversion to units of voltage are then required for inclusion in Vthmodels.
φm
φs
χs
E c
E v
E g
2
φf
E fs
vacE
Evac
Efm
gateoxide
gate electrode semiconductor substrate
(p-type)(metal)
E i
Work function calculation for NMOS transistor with metal gate
electrode and p-type substrate.
� For a metal gate electrode and a p-type substrate in an n-channel
MOSFET, it is easy to see that,
�ms = �m � �s = �m � (�s + Eg=2 + �F )
� where �s is referred to as the \electron aÆnity" of the semiconductor
substrate, and Eg is the band gap energy.
� For an Al gate and a p-type silicon substrate, �m � 4:1 eV , �s = 4:05
eV , and Eg = 1:12 eV . Therefore,
�ms = �m � (�s + Eg=2 + �F )
= 4:1� 4:05� 0:56� �F = �0:51� �F
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MOS Transistors, E&CE 730, January, 2002 224
� �F is the contact potential of the doped silicon relative to intrinsic
silicon. For SPICE this quantity is generally treated as a positive
quantity for both p- and n-type substrates and is given by,
�F = VT ln
0@NSUB
ni
1A
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MOS Transistors, E&CE 730, January, 2002 225
� For a metal gate electrode in PMOS transistor (n-type substrate) a
similar approach yields for �ms.
φm
vacE
Efm
gateoxide
χs
E c
E v
Evac
E fs
iEφ
f
E g 2
φs
semiconductor substrate(n-type)
gate electrode(metal)
� Therefore, for the metal gate p-channel MOSFET,
�ms = �m � �s = �m � (�s + Eg=2� �F )
= 4:1� (4:05 + 0:56� �F ) = �0:51 + �F
� If the gate electrode is made from polysilicon, there are four more
possibilities for �ms, namely, an n-doped polysilicon gate with either
an n-doped substrate or a p-doped substrate, and a p-doped polysilicon
gate with either an n-doped or p-doped substrate.
� Polysilicon gates are usually heavily doped (either n or p type) such
that the silicon is \degenerately doped".
� The Fermi level in a degenerately doped semiconductor is assumed to
be coincident with either the conduction band energy Ec for a heavily
doped n+ polysilicon electrode, or coincident with the valence band
energy Ev for a heavily doped p+ polysilicon electrode.
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MOS Transistors, E&CE 730, January, 2002 226
φs
χs
E c
E v
vacE
Evac
gateoxide
E g 2χ
sφ
m
E v
iE
E cE
fmφ
f
iE
E fs
semiconductor substrategate electrode
=
(n+ polysilicon)
=
(p-type)
� For an n+-doped polysilicon gate electrode and a p-type substrate, �msis given by,
�ms = �s � (�s + Eg=2 + �F ) = �Eg=2� �F
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MOS Transistors, E&CE 730, January, 2002 227
vacE
gateoxide
χs
φm
E v
iE
E cE
fm
φs
χs
E c
E v
Evac
E g 2
iE
φf
E fs
semiconductor substrategate electrode
=
=
(n-type)(n+ polysilicon)
� For an n+-doped polysilicon gate electrode and an n-type substrate,
�ms is given by,
�ms = �s � (�s + Eg=2� �F ) = �Eg=2 + �F
![Page 238: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/238.jpg)
MOS Transistors, E&CE 730, January, 2002 228
vacE
E v
iE
E c
χsφ
m
E g
Efm
gateoxide
φs
χs
E c
E v
Evac
E g 2
iE
φf
E fs=
semiconductor substrate
(n-type)(p+ polysilicon)
gate electrode
� For an p+-doped polysilicon gate electrode and an n-type substrate,
�ms is given by,
�ms = (�s + Eg)� (�s + Eg=2� �F ) = Eg=2 + �F
![Page 239: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/239.jpg)
MOS Transistors, E&CE 730, January, 2002 229
vacE
E v
iE
E c
χsφ
m
E g
Efm
gateoxide
φs
χs
E c
E v
Evac
E g 2
iE
φf
E fs=
semiconductor substrate(p-type)
gate electrode(p+ polysilicon)
� For a p+-doped polysilicon gate electrode and a p-type substrate, �msis given by,
�ms = (�s + Eg)� (�s + Eg=2 + �F ) = Eg=2� �F
� A general formula for �ms neglecting the work function for metal gates
can be written as,
�ms = type
24�TPGEg
2� kT
qln
0@NSUB
ni
1A35
� TPG is the user-speci�ed gate electrode type:
{ TPG = 0 for metal gate.
{ TPG = -1 for polysilicon gate doped the same type as substrate.
{ TPG = +1 for polysilicon gate doped the opposite type to substrate.
� and type is an internal parameter which is equal to�1 for an n-channeldevice and +1 for a p-channel devices.
� The above formula does not include the work function of the metal
electrode, however, many versions of SPICE include this e�ect as well.
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MOS Transistors, E&CE 730, January, 2002 230
Basic Threshold Voltage Implementation
in SPICE Level 2 Model
� For an n-channel device (ignoring the internal type parameter), the
zero substrate bias threshold voltage VTO is modelled by,
VTO = �ms � qNss
Cox+ 2�F +
r2�F
�ms = �TPGEg
2� kT
qln
0@NSUB
ni
1A
� qNss = Qi = e�ective interface charge, where Nss is the surface state
density.
� TPG is the gate electrode type:
{ TPG = 0 for metal gate.
{ TPG = -1 for polysilicon gate doped the same type as substrate.
{ TPG = +1 for polysilicon gate doped the opposite type to substrate.
� VTO can also be user speci�ed as per Level 1 which overrides calculation
using above model.
� Early versions of SPICE appear to require VTO to be user speci�ed in
the Level 1 model.
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MOS Transistors, E&CE 730, January, 2002 231
Drain Current Implementation
in SPICE Level 2 Model
� For VDS < VDSat
IDS =KPW
(1� LAMBDAVDS)(L� 2LD)
264(VGS � Vfb � PHI)VDS � V 2
DS
2
�2
3GAMMA
"(PHI � VBS + VDS)
32 � (PHI � VBS)
23
#35
� For VDS = VDSat, VDS is simply replaced by VDSat in the above equa-
tion to calculate IDSat, where
VDSat =
264VGS � Vfb � PHI +
G2AMMA
2
375
�GAMMA
264VGS � Vfb � VBS +
G2AMMA
4
37512
� For VDS > VDSat
IDS =IDSat
(1� LAMBDAVDS)
� The at-band voltage Vfb does not appear to be a user de�ned model
parameter in common versions of SPICE for the Level 2 model, but
can be calculated using
Vfb = �ms � qNSS
Cox
� The drain current model for Level 2 (including the formula for VDSat)
gives better results than the Level 1 model, but still does not give suf-
�cient agreement with experimental data even when short and narrow
channel e�ects are absent.
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MOS Transistors, E&CE 730, January, 2002 232
Variation of Channel Mobility with Gate Electric Field
SPICE Level 2 Model
� The electric �eld resulting from the potential di�erence between the
gate electrode and the inversion layer in the channel reduces carrier
mobility for high vertical electric �eld strengths.
Qn
Qd
QG
������������������������������������������������
n+ drainn+ source
x
= 0
x
y
� This phenomenon is modelled in the Level 2 model by reducing the
KP parameter at high electric �elds.
K0
P = KP
2640@ �s�ox
1A UcTOX(VGS � Vth � UtVDS)
375Ue
� The above equation can be derived approximately by using Gauss's
law such that the electric �eld perpendicular to the channel Ex(y) ata position y along the channel is given by,
jEx(y)j = jQn(y)j�sWL
� where the channel inversion charge is given by,
jQn(y)j = Cox [VGS � Vth � Vc(y)]
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MOS Transistors, E&CE 730, January, 2002 233
� The Vc(y) term in the above equation indicates that the electric �eld
perpendicular to the channel charge will depend upon both the gate
and drain bias voltages.
� An average electric �eld can be calculated assuming that Vc(y) �UtVDS.
� The above equations lead to an average electric �eld perpendicular to
the channel such that,
jExj �0@�ox�s
1A264(VGS � Vth � UtVDS)
tox
375
� Uc is the critical electric �eld above which the mobility is assumed to
decrease.
� Combining these equations, the modi�ed KP0
term can be seen as the
ratio of the critical electric �eld to the average electric �eld perpendic-
ular to the channel multiplied by the unmodi�ed KP term with an
additional �tting parameter Ue.
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MOS Transistors, E&CE 730, January, 2002 234
Theory of Sub-Threshold Conduction
� Drift current dominates for VGS > Vth, however di�usion current dom-
inates for gate voltages below the threshold voltage.
� The dependence of drain current on gate and drain voltages can be ap-proximated by using a simple di�usion equation involving the gradient
of channel charge across the channel length.
IDS diffusion =qA(y)Dn(y) [n(y = 0)� n(y = Leff)]
Leff
� wheren(0) =
0B@ n
2i
NA
1CA exp
0@VsVT
1A ; n(Leff) =
0B@ n
2i
NA
1CA exp
0@Vs � VDS
VT
1A ;
� The cross sectional area of current ow is,
A(y) = Wxeff
� where xeff is the e�ective channel thickness in the vertical direction.
xeff can be estimated by calculating the vertical distance over which
the channel charge concentration n decreases by 1=e.
� The channel charge in the vertical x direction is related to the vertical
potential (x) across the channel by,
n(x) =
0B@ n
2i
NA
1CA exp
0B@ (x)VT
1CA
� which decreases by 1=e when (x) decreases by VT = kT=q.
� The surface electric �eld Es is then approximately,
Es � VTxeff
=
vuuut2qNAVs�s
� yielding for xeff ,
xeff � VT
vuuut �s2qNAVs
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MOS Transistors, E&CE 730, January, 2002 235
� The cross sectional area A(y) then becomes,
A(y) = Wxeff = WVT
vuuut �s2qNAVs
� Substituting into the di�usion expression for IDS diffusion yields,
IDS diffusion =
0BB@WV 2
T �nL
0@ niNA
1A2
vuuutq�sNA
2
1CCA
�241� exp
0@�VDSVT
1A35 exp
0@VsVT
1AV �1=2
s
� To �rst order, the subthreshold drain current dependents exponentiallyon gate voltage much in the same manner as a bipolar transistor's
collector current is exponentially dependent upon emitter-base bias.
� In fact, in subthreshold conduction, a MOSFET is actually a low gain
bipolar transistor where the base width is de�ned by the e�ective chan-
nel length.
� Also, it can be seen that drain current becomes virtually independent of
VDS once VDS >> VT , where the thermal voltage VT is approximately
26 mV at room temperature.
� The term exp(Vs=VT ) introduces a \non-ideality" to the drain current
in subthreshold conduction, since the surface potential Vs is only a
fraction of the applied gate voltage VGS. This non-ideality has seri-
ous implications for how much voltage swing on the gate it takes to
e�ectively turn o� a MOSFET.
� In low voltage applications this can severely limit the reduction in o�-
state leakage current (and therefore battery lifetime) in low voltage
low power memory and microprocessor chips intended for portable
products.
� The gate voltage swing required to reduce the drain current by an orderof magnitude (factor of ten) is known as the \subthreshold swing" S,
which ideally we would like to be as small as possible.
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MOS Transistors, E&CE 730, January, 2002 236
� The surface potential Vs can be expressed in terms of the gate volt-
age VGS by considering the MOS diode as two capacitances in series,
namely the gate oxide capacitance Cox and the depletion layer capac-
itance Cd in the substrate at the gate oxide { substrate interface.
Q G
Q G
V = VGS ox V+ s
Vox
V sC d
C ox
B = S
G
VGS
� Recognising the following relationships,
Vox =QG
Cox; Vs =
QG
Cd; VGS =
QG
CT; VGS = Vox + Vs
� where CT is the total gate capacitance comprised of Cox in series with
Cd such that,
CT =CoxCd
Cox + Cd=
Cd
1 + Cd=Cox
� a relationship between Vs and VGS can be obtained such that,
Vs =
0B@ 1
1 + Cd=Cox
1CAVGS =
1
nVGS
� where n is an ideality factor that depends upon the ratio of gate oxide
to depletion layer capacitance.
� In other words, if the gate oxide capacitance is much larger than the
depletion layer capacitance, most of the gate voltage drops across the
substrate (e.g. VGS � Vs) and will therefore have the largest in uence
on turning the MOSFET o� in subthreshold conduction.
� Any fraction of the VGS dropped across the gate oxide layer will not
contribute to variations in Vs that are required to reduce the drain
current in subthreshold conduction.
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MOS Transistors, E&CE 730, January, 2002 237
� The same phenomenon occurs in bipolar transistors, where the emitter-
base junction capacitance partially reduces the emitter-base bias volt-
age required to inject minority carriers into the base region for control-
ling the collector current. Any potential dropped across the emitter-
base junction capacitance is e�ectively moving majority carrier charge
and not in uencing minority carrier transport.
� The subthreshold swing is related to the ideality factor and can be
estimated to be,
S = ln 10
0@ dVGSd ln IDS
1A � nVT ln 10
� The larger S is, the larger the gate voltage swing required to reduce
the drain current by a �xed ratio.
� Ignoring the impact of VDS on subthreshold drain current, and ignoring
the V �1=2s term, the subthreshold drain current takes on the simple
approximate form of,
IDS subthreshold = Ion exp
0@VGS � Von
nVT
1A
� The basic Level 2 model assumes this dependence, where IDS is cal-
culated using the strong inversion model for VGS � Von where Von is
given by,
Von = Vth + nVT
� andn = 1 +
qNFS
Cox+Cd
Cox
� qNFS is the capacitance associated with \surface fast state charges"
that are associated with traps at the interface which can �ll and empty
with mobile carrier charge during changes in VGS. This capacitance
appears electrically in parallel with the depletion capacitance and is
characterised by a density per unit area factor NFS.
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MOS Transistors, E&CE 730, January, 2002 238
� Recognising that the depletion charge Qd(y) is given by,
jQd(y)j =q2q�sNA
r2�F � VBS + Vc(y)
= Cox
r2�F � VBS + Vc(y)
� Cd can be approximated (for a zero channel potential Vc(y)) by,
Cd =dQd
dVBS=
Coxp2�F � VBS
� The basic Level 2 model introduces a discontinuity between subthresh-
old and strong inversion regions of operation which can lead to non-
convergent circuit simulations.
� More advanced models introduce continuous models over the two re-
gions of operation such that the total drain current (di�usion plus
drift) components are included in all operating regions (at the expense
of additional computational e�ort).
![Page 249: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/249.jpg)
MOS Transistors, E&CE 730, January, 2002 239
Short and Narrow Channel E�ects in MOSFETs
X j
Leffy = y = 0
VBS
V DS
VGS
x
y
l d
l d
���������������������������������������
���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
��������
��������
���������������
���������������
��������������������
��������������������
��������
n+ Source n+ Drain
W
L
l (y)
Substrate or Bulkp-
SourceDrain
Gate
gate oxide
pinch-off
-
source depletionlayer drain depletion layer
� As the channel length is reduced, departures from \long channel" be-
haviour may occur.
� These departures arise as a result of a 2-D potential distribution and
high electric �elds in the channel region.
� For a given channel doping concentration, the channel length is more
strongly a�ected by source and drain depletion layer widths when these
widths become comparable to the channel length.
� Potential distributions in the channel now depend on both the trans-
verse electric �eld Ex (which is controlled by the gate and body biases)
and the longitudinal electric �eld Ey (which is controlled by the drain
bias).
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MOS Transistors, E&CE 730, January, 2002 240
� The gradual channel approximation assumes that the transverse elec-
tric �eld perpendicular to the channel is much larger than the longi-
tudinal electric �eld parallel to the channel.
� The Level 1 and Level 2 models are implicitly assuming the gradual
channel approximation in determining the channel charge solely from
transverse �eld considerations, followed by drain current determina-
tion from longitudinal �eld considerations, where the two-dimensional
coupling between �elds is ignored.
� In MOSFET's which exhibit short and/or narrow channel e�ects, this
approximation cannot be used to model transistor behaviour.
� The 2-D channel potential distribution results in a number of complex
characteristics including,
{ subthreshold behaviour degradation.
{ dependence of Vth on channel length and biasing voltages.
{ failure of current saturation due to punch-through where source
and drain depletion layer potentials meet beneath the gate.
� Small geometry MOSFET's also lead to higher internal electric �elds
if the bias voltages are not also decreased to compensate.
� As electric �elds are increased parallel to the channel, channel mobil-
ity becomes �eld-dependent as the relation between drift velocity and
�eld deviates from a linear behaviour. Eventually the drift velocity
saturates at the thermal velocity for high electric �eld.
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MOS Transistors, E&CE 730, January, 2002 241
� For very high electric �elds, avalanche breakdown phenomena in the
drain depletion layer results in carrier multiplication and electron-hole
production. Holes are then attracted to the body or substrate contact
resulting in substrate current.
� Holes generated from carrier multiplication can also forward bias a
parasitic bipolar transistor formed between the n+ source { p substrate
{ n+ drain structure.
� High electric �elds also produce \hot" electrons that are capable of
jumping the potential barrier of the gate oxide resulting in oxide charg-
ing and gate currents.
� Oxide charging can in turn lead to threshold voltage shifts.
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MOS Transistors, E&CE 730, January, 2002 242
Variation of Channel Length in the Saturation Region of
Operation
DS(for V = V Dsat )
Point C assumed to be wherecarriers reach saturated driftvelocity.
Point P assumed to be transitionbetween linear and saturated drain current models.
������������������������������������������������
��������
��������
������������������
���������������������������� ������������
n+ drainn+ source
x
y
L eff
l d
Gate
DSV
substrate or body
PC
LD LD
L
� Increases in VDS beyond VDSat results in the channel pinch-o� point
P moving towards the source decreasing channel length.
� This phenomenon is known as \channel length modulation".
� The channel potential Vc(y = P ) = VDSat, with VDS � VDSat being
dropped across the depletion layer between the substrate and the drain
along the channel.
� Leff = L� 2LD is then replaced by Leff � ld in drain current expres-
sions.
� If the dependence of IDS on VDS in saturation is assumed to be of the
form,
IDS =IDS (for ld = 0)
1� �VDS
� then � becomes,
� =ld
LeffVDS
� The most general approach to solve for ld is to solve the 2-D Poisson
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MOS Transistors, E&CE 730, January, 2002 243
equation,
@2V (x; y)
@2x+@2V (x; y)
@2y=��(x; y)
�s
� where V (x; y) is the 2-D potential distribution beneath the gate in
the vicinity of the pinch-o� region, and �(x; y) is the 2-D net charge
(space charge and free carriers) beneath the gate in the vicinity of the
pinch-o� region.
� The simplest model for ld is obtained if it is assumed that the potential
and net charge distributions are 1-D and that the net charge originates
only from a space charge layer in a uniformly doped substrate such
that,
ld =
vuuuut2�s(VDS � VDSat)
qNA
� This simple model over estimates the output conductance (or variation
in drain current versus drain voltage) since it ignores the presence of
fringing �elds due to the gate electrode.
� An improved model assumes a �nite electric �eld boundary condition
Ep (as oppose to a zero electric �eld) in the channel at the point P
arising from the gate bias.
� This assumption results in,
ld =
vuuuut0@ 2�sqNA
1A (VDS � VDSat) +
0@ �sqNA
1A2 E2p �
0@ �sqNA
1A Ep
� The Level 3 Model assumes that Ep is given by,
Ep = IDSatK
GDSatLeff
� and that ld is given by,
ld =
vuuuut0@2�sKqNA
1A (VDS � VDSat) +
0@ �sqNA
1A2 E2p �
0@ �sqNA
1A Ep
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MOS Transistors, E&CE 730, January, 2002 244
� where K is a �tting parameter (used to multiply the �rst term in the
ld expression as well as to calculate Ep), and where the conductance
term GDSat is evaluated from,
GDSat =dIDSdVDS
1AVDS=VDSat
� The e�ects of drift velocity saturation can be included to model the
impact of free charge in the vicinity of the pinch-o� region on channel
length modulation by assuming that the electric �eld at the pinch-o�
point Ep is given by,
Ep = vsat2�
� where vsat is a user speci�ed parameter (VMAX) that represents the
value of the saturated drift velocity.
� The Level 2 model uses this approach where ld is given by,
ld =
vuuuut0B@ 2�sK
qNANeff
1CA (VDS � VDSat) +
0B@ �sqNANeff
1CA2 0@vsat2�
1A2
�0B@ �sqNANeff
1CA0@vsat2�
1A
� where Neff is a unit-less �tting parameter to modify the substrate
doping NA.
� Typical values of VMAX are 5� 106 cm=sec.
� If VMAX is not speci�ed, then some versions of SPICE will calculate
it dependent upon the bias levels present and the geometry of the
MOSFET.
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MOS Transistors, E&CE 730, January, 2002 245
E�ects of Channel Length and Width
on Threshold Voltage
W = 20 micronsL varying
L = 20 micronsW varying
0.5
0.8
0.3
thV
Channel Length L or
Channel Width W
1 2 3 4 5 180
� For a �xed channel widthW , the threshold voltage Vth decreases with
decreasing L.
� For a �xed channel length L, the threshold voltage Vth increases with
decreasing W .
� A decrease in Vth with decreasing L becomes noticeable when L be-
comes comparable to Xsd and Xdd, the source and drain depletion
widths, respectively. When this happens, a MOSFET is considered to
be a \short channel" device.
� When W becomes comparable to Wm, the maximum depletion layer
width in the saturation region of operation, the MOSFET begins to
behave as a \narrow channel" device.
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MOS Transistors, E&CE 730, January, 2002 246
Variation of Vth with Channel Length L
in the SPICE Level 2 Model
DSV = 0.1 V
Wm
X jX j Xc cX
Wm
X j X j
Wm
Wm
∆ Qd
2
Qd
2
∆ Qd
Qd
∆ QdQ
d= +
x
y
substrate or body
W m
L
L
n+ source n+ drain
� For short channels, source and drain depletion regions reduce the de-
pletion charge that the gate voltage is required to induce to reach
strong inversion in the channel.
� Simple models assume that the depletion charge per unit area induced
by the gate voltage at VGS = Vth is simply Qd = qNAWm.
� In short channel devices, the source and drain depletion regions reduce
this charge to Q0
d which is less than Qd thereby reducing Vth.
� \charge sharing" and \empirical approaches" are two modelling ap-
proaches used to estimate the true Q0
d to use in determining Vth in
short channel devices.
� Charge sharing models account for reduction in Vth through the shar-
ing of the channel depletion region charge between the gate and the
source/drain junctions.
� The models assume a priori geometrical forms for the source and drain
depletion regions and their boundaries.
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MOS Transistors, E&CE 730, January, 2002 247
� Channel depletion charge is divided into two regions: one associated
with the gate and one associated with the source and drain junctions.
� The simplest charge sharing approach assumes the following:
{ substrate is uniformly doped.
{ source and drain are at zero or low potential
(i.e. VDS = 0).
{ source and drain junction geometry is cylindrical with radius Xj.
{ charges at source and drain ends of the channel are shared equally
between gate and source/drain junctions resulting in a trapezoidal
shape for the gate controlled depletion charge.
{ channel depletion width is equal to that of the source/drain deple-
tion width.
(i.e. Xds = Xdd = Wm =r(2�s(2�F � VBS)=(qNA)).
� Based upon the above assumptions, Q0
d can be calculated as follows:
Qd = qNAWm
Q0
d = Qd(Trapezoid Area)
LWm= qNAWm
0BB@Wm(L + L
0
)
2
1CCA0@ 1
LWm
1A
= qNAWm
0BB@(L + L
0
)
2L
1CCA
� Using trigonometry,
Xc = Xj
0BB@vuuuut1 + 2Wm
Xj� 1
1CCA
� Recognising that L = L0 + 2Xc yields,
Q0
d = qNAWm
26641� Xj
L
0BB@vuuuut1 + 2Wm
Xj� 1
1CCA3775
= qNAWmFl
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MOS Transistors, E&CE 730, January, 2002 248
� Using,
Wm =
vuuuut2�s(2�F � VBS)
qNA; =
p2q�sNA
Cox
� gives,Q
0
d = CoxFlr2�F � VBS
where,
Fl =
26641� Xj
L
0BB@vuuuut1 + 2Wm
Xj� 1
1CCA3775
� A modi�ed can be de�ned such that,
0
= Fl
� The channel length dependent Vth then becomes,
Vth = Vfb + 2�F + 0r2�F � VBS
X jX j
X j X j
X sdX
dd
X cdXcs L
DSV
Wm (y)x
y
X sd
Xdd
substrate or body
L
n+ source n+ drain
� Dependence on source and drain voltages can be included by using
Xsd and Xdd for the source and drain depletion widths, respectively,
instead of Wm in the simpler model, where,
Xsd =
vuuuut2�s(2�F � VBS)
qNA; Xdd =
vuuuut2�s(2�F � VBS + VDS)
qNA;
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MOS Transistors, E&CE 730, January, 2002 249
� Using a similar derivation method as for the simpler model,
Xcs = Xj
0BB@vuuuut1 + 2Xsd
Xj� 1
1CCA ; Xcd = Xj
0BB@vuuuut1 + 2Xdd
Xj� 1
1CCA
� Recognising that L = L0
+Xcs +Xcd gives the dependence of Vth on
channel length L in the Level 2 model such that,
Fl = 1�2664Xj
2L
0BB@vuuuut1 + 2Xsd
Xj� 1
1CCA + Xj
2L
0BB@vuuuut1 + 2Xdd
Xj� 1
1CCA3775
� It is instructive to calculate the change in threshold voltage �Vth whicharises from including the in uence of short channel e�ects.
� Vth for a long channel device is,Vth long channel = Vfb + 2�F +
r2�F � VBS
� Vth including short channel e�ects is given by,
Vth short channel = Vfb + 2�F + Flr2�F � VBS
� Therefore,�Vth = Vth long channel � Vth short channel
= r2�F � VBS (1� Fl)
= r2�F � VBS
2664Xj
L
0BB@vuuuut1 + 2Wm
Xj� 1
1CCA3775
=
0@Qd
Cox
1A0@Xj
L
1A0BB@vuuuut1 + 2Wm
Xj� 1
1CCA
� From the above equation for �Vth several conclusions can be made
regarding the in uence of device structure on short channel e�ects:
{ Greater gate oxide thickness results in smaller Cox and therefore
greater short channel e�ects. For this reason, as channel length is
decreased in deep sub-micron MOSFET's, the gate oxide should be
made thinner to assist in suppressing short channel e�ects.
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MOS Transistors, E&CE 730, January, 2002 250
{ Lower substrate doping NA results in greaterWm for given terminal
voltage magnitudes which increases short channel e�ects. For this
reason small geometry MOSFET's require higher substrate doping
levels.
{ Larger source and drain junction depths Xj result in greater short
channel e�ects. For this reason source and drain junctions depths
must be decreased as channel length is decreased.
{ Higher body-to-source bias voltage VBS results in larger Wm and
greater short channel e�ects.
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MOS Transistors, E&CE 730, January, 2002 251
Variation of Vth with Channel Width W
in the SPICE Level 2 Model
������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
2
∆ Q w
2
∆ Q w
����������������������������������������������������������������������
����������������������������������������������������������������������
����������������������������������������������������������������������
����������������������������������������������������������������������
Wm
W
Field Oxide Field Oxidegate oxide
Gate Electrode
p+ dopant p+ dopant
� Tapering of gate oxide from thin to thick oxide at the sides of the
active channel region results in a gate controlled depletion region at
the edges of the device near the isolation oxide (LOCOS) resulting in
increased Vth.
� When the gate width W becomes comparable to the depletion layer
thickness Wm, the extra depletion charge at the gate edges �Qw out-
side the active gate area becomes a signi�cant part of the total deple-
tion charge Qd.
� The narrow channel e�ect can be taken into account by modifying the
expression for Vth such that,
Vth = Vfb + 2�F + 0r2�F � VBS +
�Qw
Cox
� Modelling the narrow channel impact of Vth amounts to estimating
�Qw.
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MOS Transistors, E&CE 730, January, 2002 252
Wm
Wm
2
∆ Q w
2
∆ Q w
2
∆ Q w
π2
Wm
W
L
W m
AA
� Ignoring short channel e�ects, the total depletion charge is,
QT = Qd +�Qw = qNAWmWL+�Qw
� where Qd is the total depletion charge here (as opposed to per unit
area in previous derivations) in the absence of any short or narrow
channel e�ects.
� Therefore,Qd
QT=
Qd
Qd +�Qw=
1
1 + (�Qw=Qd)
� Also,Qd
QT=
qNAWmWL
qNAL(WmW + 2A)=
1
1 + (2A)=(WWm)
![Page 263: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/263.jpg)
MOS Transistors, E&CE 730, January, 2002 253
� Therefore, assuming that the cross-sectional area of �Qw=2 forms a
quarter circle,
�Qw
2=
QdA
WmW=qNAWm(�=4)W
2m
WmW
=q�NAW
2m
4W=q�NA
4W
0B@2�s(2�F � VBS)
qNA
1CA =
��s(2�F � VBS)
2W
� Therefore,
�Qw =��s(2�F � VBS)
W
� The threshold voltage taking into account short and narrow channel
e�ects is then,
Vth = Vfb + 2�F + 0r2�F � VBS +
��sWCox
(2�F � VBS)
� The Level 2 model uses a slightly di�erent model for the narrow chan-
nel e�ect which involves an empirical parameter Æ (called DELTA in
SPICE) such that,
Vth = Vfb + 2�F + 0r2�F � VBS +
��sÆ
4WCox(2�F � VBS)
![Page 264: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/264.jpg)
MOS Transistors, E&CE 730, January, 2002 254
IDS µA( )
VGS(V)
W = 100 micronsL = 100 micronsVDS = 50 mV
VBS = 0 V
VBS = -5 V
UC = 10 4
V/cm
UC = 10 5
V/cm
0 1 2 3 54
1
2
3
4
Variations in drain current with Uc in transfer characteristics for Level 2
model.I
DS µA( )
VGS(V)
Ue = 0
Ue = 0.1
Ue = 0.2
VBS = 0 V
VBS = -5 V
0 1 2 3 54
1
2
3
4
Variations in drain current with Ue in transfer characteristics for Level 2
model.
![Page 265: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/265.jpg)
MOS Transistors, E&CE 730, January, 2002 255
IDS µA( )
VDS (V)
GS =V 2 V
Ue = 0.2
Ue = 0
0 1 2 3 54
10
20
30
40
3 V
4 V
5 V
Variations in drain current with Ue in output characteristics for Level 2
model.I
DS
VGS(V)0 0.5 1.0 1.5 2.0 2.5
NFS = 0 (default)
NFS-3
= 2 x 10 11
cm
NFS = 5 x 1011cm -3
NFS = 1011
cm -3
V DS = 0.5 V
VBS = 0 V
(A)
10
10
10
10
10
10
10
10
-5
-6
-7
-8
-9
-10
-11
-12
Transfer characteristics in weak inversion region for Level 2 model.
![Page 266: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/266.jpg)
MOS Transistors, E&CE 730, January, 2002 256
VSB (V)
(V)V TH
W = 100 micronsL = 5 microns
X j= 1.5 microns
W = 100 micronsL = 5 microns
X j = 1 micron
W = 100 microns= 0.8 micronsDL
V = 0.05 VDS
0 2 4 6 8 10
0.5
1.0
1.5
2.0W = L = 100 microns
Impact of body e�ect on Vth for short-channel MOS transistor according
to Level 2 model.
VSB (V)
(V)V TH
0 2 4 6 8 10
∆
-0.3
0.0
-0.2
-0.1
X = 0.5 microns
X j
j= 0.1 microns
Measurements
Dependence of Vth on XJ and VDS as predicted by Level 2 model
compared with measurements for a short channel MOSFET.
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MOS Transistors, E&CE 730, January, 2002 257
IDS µA( )
VGS(V)
VDS = 2 V
W = 100 microns
L = 5 micronsV BS = 0 V
X j = 2 microns
X j = 2 microns
VBS = -5 V
X j = 0 microns
VBS = -5 VV BS = 0 V
X j = 0 microns
0 1 2 3 54
1/2
1
2
3
4
Square root drain current dependence on XJ and VBS in transfer
characteristics for a short channel MOSFET according to Level 2 model.
VGS(V)
VBS = -5 V
X j = 0 microns
X j = 2 microns
X j = 0 microns
VBS = 0 V
IDS µA( )
L = 5 microns
VDS = 50 mV
W = 100 microns
0 1 2 3 54
60
80
40
20
Drain current dependence on XJ and VBS in transfer characteristics for a
short channel MOSFET according to Level 2 model.
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MOS Transistors, E&CE 730, January, 2002 258
W = 100 micrions
L = 5 microns
VDS (V)
IDS µA( )
VGS = 1.5 V
X j = 2 microns
X j = 2 micronsVGS = 1.2 V
X j = 0 microns
VGS = 1.2 V
X j = 0 microns
VGS = 1.5 V
0 1 2 3 54
5
20
10
15
Drain current dependence on XJ and VBS in output characteristics for a
short channel MOSFET according to Level 2 model.I
DS µA( )
VDS (V)
V =GS
2 V
V =GS
3 V
V =GS
4 V
V =GS
5 V
v max = 5 x 10 4
m/sv max =
0 1 2 3 54
250
500
750
1000
W = 100 microns
L = 5 microns
0
Variations of drain current with VMAX in output characteristics
according to Level 2 model.
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MOS Transistors, E&CE 730, January, 2002 259
IDS µA( )
VGS(V)
δ = 0
δ = 1
BS = 0 VV
= -5 VBSV
0 1 2 3 54
0.20
0.15
0.10
0.05
VDS = 50 mV
W = 5 microns
L = 100 microns
Variations of drain current with Æ in transfer characteristics according to
Level 2 model.
![Page 270: Principle - University of Waterloojhamel/notes_730.pdf · 2002. 1. 7. · Engineering Univ ersit y of W aterlo o W aterlo o, On tario, Canada Jan uary, 2002. ii Principle T extbook](https://reader036.fdocuments.us/reader036/viewer/2022071523/613cc9a94c23507cb6359ae4/html5/thumbnails/270.jpg)
MOS Transistors, E&CE 730, January, 2002 260
Gate Capacitance
QD
QS
QG
QB
Drain
Source
Gate Bodyi
i
i
ig
d
b
s
� The total internal charge associated with the source, drain, gate and
bulk charges is a function of the terminal voltages such that,
Qj = f(vg; vs; vd; vb)
� where vg is the gate voltage, vs is the source voltage, vd is the drainvoltage, and vb is the bulk or body voltage.
� All voltages include time dependence.
� Charge conservation demands,
QG +QS +QD +QB = 0
� where QG is the charge on the gate electrode controlled by the gate
voltage, QS is the internal charge controlled by the source voltage ,
QD is the internal charge controlled by the drain voltage, and QB is
the internal charge controlled by the bulk voltage ,
� Current conservation demands,
ig + is + id + ib = 0
� where ig is the gate current, is is the source current, id is the drain
current, and ib is the bulk current,
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MOS Transistors, E&CE 730, January, 2002 261
� The \quasi-static approximation" is used which implies that steady
state charge distributions are established instantaneously when the
terminal voltages change. It assumes that the total quantity of charge
takes times to change, but the time the charge takes to reach a partic-
ular distribution is neglected.
� The quasi-static approximation works well except if time constants
associated with the free carrier stored charge in the channel becomes
comparable to time constants associated with charges from space charge
regions and overlap capacitances (i.e. in long channel devices at high
frequencies).
� The various time-dependent terminal currents are,
ig(t) = �IG(v(t)) + dQG
dt; is(t) = �IS(v(t)) + dQS
dt
id(t) = �ID(v(t)) + dQD
dt; ib(t) = �IB(v(t)) + dQB
dt
� where IG(t), IS(t), ID(t), and IB(t) are the quasi-static conduction
currents which have the same value at a particular time t as they
would under steady state conditions for given instantaneous values of
terminal voltages v(t).
� IG(t) and IB(t) are assumed to be equal to zero.
� Therefore,
is + id = IDS(v(t)) +dQI(t)
dt
� where QI(t) = QS(t) +QD(t).
� Assuming that the source and drain regions do not contribute signif-
icantly to the depletion charge beneath the gate, it can be assumed
that QI(t) is comprised of only free channel inversion charge, leaving
QB(t) to represent the entire space charge layer or depletion charge
beneath the gate.
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MOS Transistors, E&CE 730, January, 2002 262
� Charge conservation still demands that,
QG(t) +QI(t) +QB(t) = 0
� whereQI = W
Z L0QI(y)dy; QB = W
Z L0QB(y)dy
� The most basic model implemented in Level's 1, 2, 3, and 4 (BSIM)
in SPICE is the Meyer Model.
� The Meyer model su�ers from charge conservation and does not take
into account the fact that the free channel inversion charge is shared
between the source and drain terminals (i.e. charge partitioning).
� In the Meyer model the gate capacitance is broken into three compo-
nents, namely the gate-to-source capacitance CGS, the gate-to-drain
capacitance CGD, and the gate-to-bulk capacitance CGB.
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MOS Transistors, E&CE 730, January, 2002 263
Strong Inversion Meyer Model for Gate Capacitance in the
Linear Region of Operation
� In strong inversion, the inversion channel charge QI(y) is given by,
QI(y) = Qn(y) = �Cox[VGS � Vth � V (y)]
� where V (y) is the lateral channel potential Vc(y).� A change of integration variables yields,
�WZ Leff0
Qn(y)dy = �WZ VDS0
Qn(y)dy
dVdV
� From previous derivations for drain current in the Level 1 model,
IDSdy = �nWCox[VGS � Vth � V ]dV
� Therefore,dy
dV=
�nWCox(VGS � Vth � V )
IDS
=Leff(VGS � Vth � V )
(VGS � Vth)VDS � V 2DS=2
=2Leff(VGS � Vth � V )
(VGS � Vth)2 � (VGD � Vth)2
� where VDS = VGS�VGD was used in the last line of the above equation.
� The total inversion charge then becomes,
QI = �WZ Leff0
Qn(y)dy
=2WLeffCox
(VGS � Vth)2 � (VGD � Vth)2
Z VDS0
(VGS � Vth � V )2dV
=
0@2WLeffCox
3
1A264(VGS � Vth)
3 � (VGD � Vth)3
(VGS � Vth)2 � (VGD � Vth)2
375
� where VDS = VGS � VGD was again used in the last line of the above
equation.
� The total gate charge QG is the addition of the inversion charge and
the bulk charge such that,
QG = �QI �QB
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MOS Transistors, E&CE 730, January, 2002 264
� In strong inversion it is assumed that the bulk or depletion charge
does not change due to the free carrier channel charge screening the
depletion charges beneath the gate from any changes in gate voltage.
� The components from gate capacitance then become,
CGS =@QG
@VGS
1AdVGD=dVGB=0
=2
3WLeffCox
2641� (VGD � Vth)
2
(VGD + VGS � 2Vth)2
375
CGD =@QG
@VGD
1AdVGS=dVGB=0
=2
3WLeffCox
2641� (VGS � Vth)
2
(VGD + VGS � 2Vth)2
375
CGB =@QG
@VGB
1AdVGS=dVGD=0
= 0
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MOS Transistors, E&CE 730, January, 2002 265
Meyer Model for Gate Capacitance in the Saturation
Region of Operation
� In saturation, the Level 1 model assumes the simple form of VDSat =
VGS � Vth.
� Recognising that VDS = VGS � VGD, implies that VGD = Vth in satu-
ration.
� Substituting VGD = Vth into the strong inversion linear region capaci-
tance equations yields,
CGS =2
3WLeffCox; CGD = 0; CGB = 0
� Extrinsic components of capacitance are also added to the above in-
trinsic components.
� The extrinsic components arise from drain and source electrodes over-
lapping the gate oxide along the gate width, as well as the gate elec-
trode overlapping the transition from gate oxide to �eld oxide along
the gate length.
� Therefore,CGS = CGS intrinsic +GGSOW
CGD = CGD intrinsic +GGDOW
CGB = GGBOLeff
� where CGSO is the overlap capacitance per unit length of gate width
W of the source electrode, CGDO is the overlap capacitance per unit
length of gate widthW of the drain electrode, and CGBO is the overlap
capacitance per unit length of gate length Leff of the gate electrode,
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MOS Transistors, E&CE 730, January, 2002 266
CGB
C
CGSO C GS C
GDC
GDO
JI dsC
J
BS
Extrinsic Part
Intrinsic Part
S D
G
B
C GBO
BD
Large Signal Model for a MOSFET Including Capacitances
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MOS Transistors, E&CE 730, January, 2002 267
Threshold Voltage in Non-Uniformly Doped MOSFETs
� Vth is usually adjusted to a desired value by implanting the surface of
the substrate to increase its doping.
Potential
Surface
1.00.1
0yL
eff
L eff y
S D
0
L = 6.25 microns
L = 1.25 microns
L = 1.25 microns, VDS = 5 Volts
, V
, DSV = 0.5 Volts
DS = 0.5 Volts
� a deeper implant is sometimes used to reduce the e�ect of \drain-
induced-barrier-lowering" (DIBL) which can a�ect short channel MOS-
FET's.
� For large VDS in short channel MOSFET's, the extension of the drain
depletion layer into the channel region reduces the gate controlled
charge.
� Electric �eld penetration into the channel region lowers the potential
barrier at the source resulting in increased injection of electrons by the
source giving rise to an increased drain current.
� The impact of DIBL on Vth can be accounted for by assuming a linear
dependence on VDS such that,
Vth(VDS) = Vth(VDS < 0:1V )� �VDS
� Sometimes the drain is referred to as a \second gate" and the param-
eter � is referred to as the \coeÆcient of static feedback".
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MOS Transistors, E&CE 730, January, 2002 268
� DIBL can be the principle factor dominating the output resistance in
short channel MOSFET's in saturation.
� If the substrate doping is non-uniform beneath the gate, the conven-
tional model for Vth is not valid, i.e.
Vth = Vfb + 2�F + r2�F � VBS
N(x)
N o
0.62 N o
xR p
� Ion-implantation results in a Gaussian-like impurity pro�le beneath
the gate.
� Assuming a true Gaussian impurity pro�le, the peak impurity concen-
tration No at the \range" depth RP can be expressed in terms of the
total \dose" of impurity atoms implanted per unit area Di and the
straggle �RP such that,
No =Di
�RPp�
� The resulting impurity pro�le for a Gaussian is,
N(x) = No exp
264�(x�RP )
2
2�R2P
375
� Typical doses can range from 1010 to 1012 atoms per cm2.
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MOS Transistors, E&CE 730, January, 2002 269
1018
1017
1016
1015
1014
Nb
N A
N(x)
x
0.0 1.0microns
sN
Xi
Channel Impurity Profilefor nmos with n+ poly gateor pmos with p+ poly gate
or
� To avoid intractable analytic expressions for Vth, the non-uniform im-
purity pro�le can be approximated by a step pro�le such that the
area under the step pro�le plot is the same as that under the true
non-uniform pro�le.
� Equal areas in a plot of impurity pro�les versus depth amounts to
maintaining the same dose Di between the true and step pro�les.
� For enhancement mode MOSFET's, two possible scenarios can arise.
� One scenario is for a substrate pro�le of one conductivity type (p or
n-type) which could appear in an NMOS with an n+ polysilicon gate
electrode or a PMOS with a p+ polysilicon gate electrode.
1018
1017
1016
1015
1014
X i
sN
Nb or N
A
N(x)
x
0.0 1.0microns
0x
N(x)
Channel Impurity Profilefor pmos with n+ poly gate
p-type
n-type
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MOS Transistors, E&CE 730, January, 2002 270
� Another scenario would involve a substrate that has been counter-
doped at the substrate surface to adjust Vth such that a pn-junction
forms beneath the gate, which could appear in a PMOS with an n+
polysilicon gate electrode.
� Di�erent models are required for the di�erent substrate doping scenar-
ios.
Dose = 12 x 1011
cm-2
8 x 1011
4 x 1011
4
6
Vth
2 φF
- VBS
V1/2
0
V
0
� Altering the impurity pro�le at the surface of the substrate results in a
more complex behaviour in threshold voltage with respect to changes
in VBS.
� As the depletion layer moves deeper into the substrate with increasing
VBS, the e�ective at �rst appears higher in the higher substrate dop-
ing at the surface, and then decreases as the depletion layer penetrates
the lower uniformly doped portion of the substrate.
� The general physical relation for Vth used to develop a model for a
uniformly-doped substrate still holds for non-uniformly doped sub-
strates such that,
Vth = Vfb + Vsi � Qb
Cox
� where Vsi is the surface potential at strong inversion and is not neces-
sarily equal to 2�F as for the uniform-doped substrate case.
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MOS Transistors, E&CE 730, January, 2002 271
� Vfb is the \ at-band" voltage which is the gate voltage which results
in zero space charge beneath the gate.
� The at-band voltage Vfb is generally treated as a parameter for MOS-
FET's with a non-uniformly doped substrate.
� There are several de�nitions which can lead to a model for Vsi,
1. The substrate doping NA (or Nb) can be replaced by the surface
doping Ns such that,
Vsi = 2VT ln
0@Ns
ni
1A
2. The minority carrier concentration at the surface is equal to the
majority carrier concentration N(Wm) at the boundary of the de-
pletion layer when the depletion layer is at its maximum depthWm.
This leads to expressions such as,
Vsi = VT ln
0B@N(Wm)NA
n2i
1CA
3. The variation in the inversion and depletion layer charge densities
Qn and Qd with respect to surface potential Vs are equal such that,
dQn
dVs=dQd
dVs
which can be shown to be equivalent to,
Vsi = VT ln
0@NavNA
n2i
1A ; Nav =
1
Wm
Z Wm
0N(x)dx
� The above three de�nitions can lead to di�erences in Vth by as much
as 0.2 Volts.
� The �rst de�nition is often used due to simplicity but can be inaccurate
for heavy implant doses.
� The depletion charge Qd can be evaluated using,
Qd = �qZ Wm
0N(x)dx
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MOS Transistors, E&CE 730, January, 2002 272
� Vth then becomes,
Vth = Vfb + Vsi � q
Cox
Z Wm
0N(x)dx
XiN
A
Ns
x
N (x)
0
� Assuming an equivalent step pro�le containing the same dose Di as
the true implanted pro�le, the \areas" of the pro�le are equated to the
dose such that,
(Ns �NA)Xi =Z1
0(N(x)�NA)dx = Di
� yielding an equivalent uniformly doped surface concentration Ns of
Ns =Di
Xi+NA
� where Di and Xi become new model parameters.
� In a \shallow implant" model it is assumed that the implanted dose
forms an in�nitely thin sheet of dopant (i.e a delta function) resulting
in a simple expression for Vth such that,
Vth = Vfb + 2�F +qDi
Cox+
r2�F � VBS
� Here it is assumed that and Vsi are still controlled by the uniform
substrate doping NA as per non-implanted MOSFET's.
� The in�nitely thin shallow implant implicitly assumes that the thresh-
old voltage changes without any change in depletion layer width Wm.
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MOS Transistors, E&CE 730, January, 2002 273
� Various empirical approaches have been adopted.
� Recognising that the slope of Vth decreases with increasing back bias
VBS in MOSFET's with non-uniformly doped substrates, the SPICE
Level 4 (BSIM) model uses,
Vth = Vfb + 2�F + r2�F � VBS + o(2�F � VBS)
� where in general o will be a negative number.
� Comparing the BSIM model for Vth with the Level 1 model, it can
be seen that the a modi�ed im has been introduced which is VBSdependent such that,
im = + or2�F � VBS
� In the SPICE Level 4 (BSIM) model, Vth including user-de�ned pa-
rameters is modelled by ,
Vth = VFB + PHI +K1
r2�F � VBS �K2(PHI � VBS)� �VDS
� where PHI = 2�F .
� The body e�ect coeÆcient K1 and the drain/source depletion charge-
sharing coeÆcient K2 together model the e�ects of non-uniform dop-
ing, and DIBL is included via the zero bias drain-induced barrier-
lowering coeÆcient �.
� In BSIM, o is replaced by�K2 to handle both the non-uniform doping
e�ect (in conjunction withK1) as well as other e�ects which can reduce
Vth such as the drain and source depletion charges.
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MOS Transistors, E&CE 730, January, 2002 274
Drain Current Expressions
for SPICE Level 3 and Level 4 (BSIM) Models
Using Taylor Series Expansions
� The 3/2 power in the drain current expression of the Level 2 model
results in a computationally complex IDS equation as well as making
it nearly impossible to arrive at closed form current and capacitance
equations for short-channel devices.
� The square root dependence of depletion charge Qd(y) on channel po-
tential V (y) is the source of the 3/2 power in the �nal IDS expressions
of the Level 1 and 2 models.
Qd(y) = �Cox [2�F � VBS + V (y)]1=2
� Qd(y) can be approximated by a �rst order Taylor series expression.
� The Taylor series expansion of a function f(x) about a point a is givento �rst order by,
f(x) = f(a) + f0
(a)(x� a) + :::
� Let x = V + Vo and a = Vo, such that x � a = V , where Vo =
2�F � VBS. Therefore,
f(V + Vo) = [2�f � VBS + V (y)]1=2 = [V (y) + Vo]1=2 =
� The �rst derivative of f(V + Vo) is,
f0
(V + Vo) =1
2[2�F � VBS + V (y)]�1=2
� V (y) = 0 at x = Vo. Therefore,
f(a) = [2�F � VBS]1=2
� and,f0
(a) =1
2[2�F � VBS]
�1=2
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MOS Transistors, E&CE 730, January, 2002 275
� Therefore, to a �rst order approximation,
[2�F � VBS + V (y)]1=2 � [2�F � VBS]1=2 +
1
2[2�F � VBS]
�1=2V (y)
=r2�F � VBS + ÆV (y)
� whereÆ =
0:5p2�F � VBS
� The depletion charge Qd(y) is then approximated by,
Qd(y) �r2�F � VBS +
0:5V (y)p2�F � VBS
� The above expression for Qd(y) over-estimates the depletion charge
controlled by the gate for large VDS due to the assistance given by the
drain depletion charge.
� A modi�ed semi-empirical expression forQd(y) is sometimes employed
with an added g parameter to reduce Qd(y) such that,
Qd(y) � �Cox
264r2�F � VBS +
0:5gV (y)p2�F � VBS
375
� The correction factor g is found to vary from 0.5 to 0.8.
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MOS Transistors, E&CE 730, January, 2002 276
� Neglecting the g parameter for simplicity (g = 1), the inversion charge
Qn(y) is then approximated by,
Qn(y) = �Cox[VGS � Vfb � 2�F � V (y)]�Qd(y)
= �Cox[VGS � Vfb � 2�F � V (y)]
+Cox [2�F � VBS + V (y)]1=2
� �Cox[VGS � Vfb � 2�F � V (y)]
+Cox [(2�F � VBS)1=2 + ÆV (y)]
= �Cox[VGS � Vfb � 2�F � (1 + Æ )V (y)]
+Cox [2�F � VBS]1=2
= �Cox[VGS � Vfb � 2�F � (2�F � VBS)1=2 � (1 + Æ )V (y)]
= �Cox[VGS � Vth � (1 + Æ )V (y)]
= �Cox[VGS � Vth � �V (y)]
� where � = (1 + Æ ) and Vth is,
Vth = Vfb � 2�F � (2�F � VBS)1=2
� The drain current IDS can then be derived from,
IDS = �nWQn(y)dV (y)
dy
� Substituting the simpli�ed expression for Qn(y) and integrating leads
to,
�Z Leff0
IDSdy = ��nWCox
Z VDS0
[VGS � Vth � �V (y)]dV
� Since IDS is not a function of y, integration yields a new model for
drain current in the linear region of operation not including short or
narrow channel e�ects such that,
IDS =�nWCox
Leff
�(VGS � Vth)VDS � 0:5�V 2
DS
�
= ��(VGS � Vth)VDS � 0:5�V 2
DS
�
� where,� =
�nWCox
Leffand � = (1 + Æ ):
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MOS Transistors, E&CE 730, January, 2002 277
� The Level 3 SPICE model assumes,
Æ =0:5p
2�F � VBS
� The Level 4 (BSIM) SPICE model assumes,
Æ =0:5p
2�F � VBS
2641� 1
a1 + a2(2�F � VBS)
375
� where a1 and a2 give a best least square �t tor2�F � VBS + V (y).
� The drain current in saturation is determined by assuming,
@IDS@VDS
1AVGS
= 0
� when VDS = VDSat.
@IDS@VDS
1AVGS
= � [(VGS � Vth)� �VDSat] = 0
� Thus VDSat ignoring small geometry e�ects is given by,
VDSat =VGS � Vth
�
� The saturated drain current then becomes,
IDSat = IDS(VDS = VDSat) = �(VGS � Vth)
2
2�
� This model for drain current is a \piece-wise" model in that there is
a discontinuity between linear and saturation regions as in the lower
level models.
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MOS Transistors, E&CE 730, January, 2002 278
Short Channel E�ects in Drain Current SPICE Level 3 and
Level 4 (BSIM) Models
Drift Velocity 10 cm/sec6
10
1.0 2.0
Electric Field 10 V/cm4
Hole (Si)
Electron (Si)
critical electric field c
v sat
� Degradation of channel surface mobility �s due to vertical electric �elds
resulting from the gate voltage in the channel is modelled by,
�s =�o
1 + �(VGS � Vth)
� The drift velocity in the direction of the channel is also a�ected by the
lateral electric �eld Ey since in principle drift velocity is not linearly
related to electric �elds for high �elds above the critical electric �eld
Ec.� The drift velocity of channel carriers can be modelled with reasonable
accuracy for Ey > Ec by,
vdrift =�sEy
[1 + (Ey=Ec)v]1=v
� where v = 2 for electrons and v = 1 for holes.
� Typical saturated drift velocities vsat for n-channel MOSFET's range
from 6 to 9 � 106 cm=sec, and for p-channel MOSFET's from 4 to
8� 106 cm=sec.
� The above expression is too complicated to incorporate into closed-
form short channel expressions for drain current.
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MOS Transistors, E&CE 730, January, 2002 279
� Instead it has been assumed that v = 1 for both electrons and holes,
and that Ec = vsat=�s resulting in,
vdrift �0B@ �sEy1 + �sEy=vsat
1CA
� In strong inversion, drain current is dominated by drift current such
that,
IDS = �qn(y)A(y)vdrift(y) = �WQn(y)vdrift(y)
= �WQn(y)
0B@ �sEy1 + �sEy=vsat
1CA
� where,Qn(y) = �Cox[VGS � Vth � �V (y)]
� and,� = (1 + Æ Fl); Vth = Vfb + 2�F + Fl
r2�F � VBS � �VDS
� where Fl is used to model short channel e�ects on Vth and �, and �
includes e�ects of DIBL.
� Using Ey = dV=dy and substituting into the drain current expression
yields,
IDS
241 + �s
vsat
dV
dy
35 = �sWCox[VGS � Vth � �V (y)]
dV
dy
� Integration yields,
IDSZ Leff0
241 + �s
vsat
dV
dy
35 dy = IDS
Z Leff0
dy +Z VDS0
�svsat
dV
= �sWCox
Z VDS0
[VGS � Vth � �V (y)]dV
� Therefore,
IDS =�sWCox
Leff [1 + (�sVDS)=(vsatLeff)]
�(VGS � Vth)VDS � 0:5�V 2
DS
�
� where Leff = L� 2LD.
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MOS Transistors, E&CE 730, January, 2002 280
� Using,
� =�sWCox
Leff; Ec = vsat
�s
� the most popular form for the drain current model in the linear region
of operation used in Level 3 and Level 4 (BSIM) SPICE models is
given by,
IDS =�
[1 + VDS=(LeffEc)]�(VGS � Vth)VDS � 0:5�V 2
DS
�
� From the above expression for drain current it can be seen that if the
product of LeffEc is much larger than VDS, then the MOSFET will
behave like a long channel device.
� If the gate oxide is thinner, then �s will be lower resulting in a larger
Ec = vsat=�s since vsat is constant. This will in turn increase the
LeffEc product resulting in improved MOSFET behaviour commen-
surate with long channel behaviour.
� For long channel MOSFET's the saturation condition was arrived at
by assuming either,
Qn(Leff) = 0 or@IDS linear
@VDS
1AVDS=VDSat
= 0
� The above de�nition can no longer be assumed for a short channel
device where the drift velocity is assumed to saturate at some limited
velocity, which in turn implies that Qn(Leff) is not zero at the pinch-
o� point when VDS = VDSat.
� An alternative de�nition for saturation more appropriate to short chan-
nel devices is to assume that IDS = IDSat when the drift velocity at
y = Leff (i.e. at the drain end of the channel) reaches vsat.
� Using this de�nition, IDSat can be expressed as,
IDSat = �WQn(y)vdrift(y) = �WQn sat � vsat = �WQn sat�sEc
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MOS Transistors, E&CE 730, January, 2002 281
� where Qn sat is the inversion charge per unit area at y = Leff where
the channel potential V (y) = V (Leff) = VDSat such that,
Qn sat = �Cox[VGS � Vth � �VDSat]
DS(for V = V Dsat )
Point C assumed to be wherecarriers reach saturated driftvelocity.
Point P assumed to be transitionbetween linear and saturated drain current models.
������������������������������������������������
��������
��������
������������������
���������������������������� ��������������
n+ drainn+ source
x
y
L eff
l d
Gate
DSV
substrate or body
PC
LD LD
L
� At a point just to the left of where the carriers reach the saturated
drift velocity vsat, the drain current is still given by the linear region
model but where VDS = VDSat so that current continuity is maintained
across the channel. Therefore,
IDSat =�sWCox
Leff [1 + (�sVDSat)=(vsatLeff)]
�(VGS � Vth)VDSat � 0:5�V 2
DSat
�
� Equating the two expressions for IDSat, VDsat can be solved yielding,
VDSat = LeffEc2664vuuuut1 + 2(VGS � Vth)
�LeffEc � 1
3775
� Multiplying the numerator and denominator of the above expression
by,2664vuuuut1 + 2(VGS � Vth)
�LeffEc + 1
3775
� yields a more appropriate expression for VDsat which is used in the
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MOS Transistors, E&CE 730, January, 2002 282
SPICE Level 4 (BSIM) model,
VDSat =2(VGS � Vth)
�
2664vuuuut1 + 2(VGS � Vth)
�LeffEc + 1
3775�1
= 2VDSat; lc
2664vuuuut1 + 2(VGS � Vth)
�LeffEc + 1
3775�1
� where VDSat; lc is the long channel VDSat.� For large LeffEc products, this expression approaches the long channelVDSat as expected.
� For small LeffEc products which occur in short channel devices, this
expression shows that VDSat will decrease relative to the long channel
VDSat with increasing gate voltage.
� The SPICE Level 3 model uses a slightly di�erent approach to arrive
at VDSat.
� The drift velocity dependence on lateral electric �eld Ey is assumed to
be of the form,
vdrift =�sEy
[1 + Æo(Ey=Ec)]� which amounts to assuming that vsat = �sEc=Æo, or that vsat is higherthan �sEc for Æo < 1.
� Following the same procedure as before, a more general expression for
VDsat can be derived such that,
VDSat =(1� Æo)Vge + LeffEc
(1� 2Æo)
2664�1 +
vuuuut1 + 2VgeLeffEc(2Æo � 1)
((1� Æo)Vge + LeffEc)23775
� where,
Vge =VGS � Vth
�
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MOS Transistors, E&CE 730, January, 2002 283
� After all of this complexity, the SPICE Level 3 model assumes that
Æo = 0 resulting in,
VDSat = Vge + LeffEc �rV 2ge + (LeffEc)2
� where Ec reverts to vsat=�s. vsat is called VMAX as a user speci�ed
parameter in the Level 3 model.
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MOS Transistors, E&CE 730, January, 2002 284
IDS
VGS(V)
-6x 10
= -5 VBSV
BS = 0 VVV = 1 V
VDS = 50 mV
µ O= 800 cm2 / (V.s)
TO
Level 3
= 0.05 V-1θ
= 0.08 V-1
θ
0 1 2 3 54
(A)
1
2
3
4
Variations of drain current in linear region with � in transfer
characteristics according to Level 3 model.
VDS (V)
IDS µA( )
η = 1.0
VGS = 3 V
VGS = 4 V
VGS = 5 V
VGS = 2 V
η = 1.5
0 1 2 3 54
5
10
Variations of drain current with � in output characteristics according to
Level 3 model.
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MOS Transistors, E&CE 730, January, 2002 285
VDS (V)
IDS
VGS = 3 V
VGS = 4 V
VGS = 5 V
VGS = 2 V
v max = 3 x 103
m/s
2 x 103
m/sv max =
0 1 2 3 54
5
10
(mA)
Variations of drain current with VMAX in output characteristics
according to Level 3 model.
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MOS Transistors, E&CE 730, January, 2002 286
Hot-Carrier E�ects in MOSFETs
and Fowler Nordheim Tunnelling
��������������������������������������������������������
holeselectrons
I b
I gI ds
V GSDS
V
n+ source n+ drain
substrate or body
GateOxide Injection
Impact Ionisation
minority carriers
ParasiticBipolar Transistor
p-type
� The maximum electric �eld experienced by carriers in the channel
region near the drain end increases as channel length decreases if the
supply voltage is kept constant.
� As carriers move from the source to drain they can acquire enough
kinetic energy in the high �eld region to have an energy higher then
the thermal equilibrium energy kT - hence becoming \hot carriers"
giving rise to \channel hot carrier e�ects".
� Hot carriers result in impact ionisation in the vicinity of the drain
resulting in the creation of additional electron-hole pairs.
� The extra electrons contribute to increased drain current.
� The holes will be collected at the substrate contact giving rise to a
substrate or body current IB.
� Holes travelling through the substrate can raise the potential of the
substrate relative to the source, forward biasing the source-body diode
and turning on the source-body-drain parasitic bipolar transistor in
parallel with the MOSFET.
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MOS Transistors, E&CE 730, January, 2002 287
� Turning on of the parasitic bipolar transistor can lead to latch-up
conditions in circuits.
� Substrate currents from a large number of MOSFET's can a�ect vari-
ous MOSFET circuits (e.g. DRAM's).
GateOxideSilicon
cE
vE
Fowler-Nordheim
Direct Tunnelling
Tunnelling
Injection Over Barrier
Hot Carriers
� Some of the hot carriers can acquire enough kinetic energy to surmount
the Si � SiO2 interface barrier (approx 3.2 eV for electrons and 4.9
eV for holes) and thus become injected into the gate oxide.
� Most of the carriers injected into the gate oxide will be collected as
gate current IG.
10-4
10-5
10-3
10-2
10-7
10-6
I
I g
Ib
d
31 5 7 9 11 1310
-16
10-15
10-14
10-13
10-12
10-11
L = 1.3 microns
VDS
= 7.5 V
bI
dI
(A)
I g (A)
Gate Voltage, V
ox = 200 Ao
t
GS (V)
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MOS Transistors, E&CE 730, January, 2002 288
� Gate current is usually orders of magnitude smaller than substrate
current due to the high energy that must be acquired to surmount the
gate oxide energy barrier.
� Carriers can also tunnel through the gate oxide energy barrier by ei-
ther direct tunnelling or �eld-assisted tunnelling known as \Fowler-
Nordheim Tunnelling".
� For direct tunnelling to occur the gate oxide must be very thin (less
then 100 angstroms) and the electric �eld must be very high (greater
than 106 V=cm).
� Fowler-Nordheim Tunnelling can occur for thicker oxides where carriers
posses kinetic energy closer to the energy barrier height.
� Hot carriers injected into the gate oxide can be trapped by electrically
active defects in the SiO2 thus modifying the �xed oxide charge density
that will in turn cause a shift in the threshold voltage.
� Hot carriers accelerated towards the gate oxide can generate new de-
fects at the silicon-oxide interface increasing the fast-interface state
density. These fast interface states will cause a threshold voltage shift
and will decrease channel mobility due to increased Coulombic scat-
tering.
� Hot carriers injected towards and into the gate oxide will cause signif-
icant device degradation over time with shifts in threshold voltage, a
reduction in transconductance, and an increase in sub-threshold swing.
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MOS Transistors, E&CE 730, January, 2002 289
Correlation of Process Parameters and Model Parameters
� In integrated circuit technology, the �nal dimensions of structures on
�nished wafers usually di�er from their intended drawn dimensions due
to several processing e�ects such as lateral expansion of local oxidation,
imperfect etching, mask alignment tolerances, etc.
������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
��������������������������������������������
��������������������������������������������
������������������������������������
������������������������������������
������������������������������������������������������������������������
������������������������������������������������������������������������
������������������������
������������������������
������������������������
������������������������
V
V out
ssddV
Gate Poly Electrode
P-WellMask
p+ p+ n+ n+
p-well
n-substrate
polysilicon gate
gate oxide
field oxide
L
W S D SD
Metal
P+ Mask
� Further, since MOS transistor dimensions are determined by the width
of the crossing polysilicon and by the lateral di�usion of source and
drain, transistor width to length ratioW=L can vary appreciably from
the intended value.
� In addition to line-width variations, there are many other process re-
lated variations such as changes in oxide thickness, sheet resistances,
threshold voltage, etc., which result in the spread in device perfor-
mance.
� Process variations can be accounted for in circuit design from simula-
tions that use statistical MOS device models.
� Traditionally the statistical models, which represent the process uc-
tuations, are simply the worst-case and best-case device model param-
eters which represent the worst and best case device performance.
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MOS Transistors, E&CE 730, January, 2002 290
� \Interdie" and \intradie" uctuations can exist, interdie uctuations
occurring between individual die on a particular wafer, between wafers,
and also between process lots.
� Several methods exist to generate worst case parameters.
� If the circuit functions are known, ascertaining the worst-case condi-
tions is not generally diÆcult.
� For example, the transistor current drive Idrive resulting from satu-
rated drain current, is a convenient transistor performance parameter
in MOS digital circuit design. Higher Idrive results in faster switching
transistors.
� For a given nominal device length L and width W , Idrive will be a
function of the n model parameters p1; p2; :::; pi; :::pn corresponding
to the adopted MOSFET model equations.
� The purpose is to �nd sets of these parameters pi (i = 1; 2; :::; n)
which lead to optimum circuit performance and maximum yield.
� It is common to take account of the statistical variation in the process
through worse case parameters, sometimes referred to as \corner design
parameters" or \worse case �les" (WCF).
oxt
V th
L∆
∆W
Low
Low
High
Low
High
High
Low
High
oxt
V th
L∆
∆W
TYPICAL
(TT)
FS
SLOW(SS)
FAST(FF)
SF
� There are �ve types of WCF related to the relative performance of
the p-channel and the n-channel MOSFET's, namely, FF for both
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MOS Transistors, E&CE 730, January, 2002 291
devices being \fast", SS for both devices being \slow", SF for the
PMOS being slow and the NMOS being fast, FS for the PMOS being
fast and the NMOS being slow, and TT for both devices being typical
or nominal.
� Ideally these WCF should be based on parameters extracted from a
large data set that represents the true statistical variation of the circuit
performance parameters due to process variations.
� Since chip design and process development often proceed in parallel, it
is often necessary to determine the WCF from a data set which gives
transistor performance variation on a limited number of devices.
� A limited set of measured model parameter data, or model parameter
data generated from a CAD package which can accurately relate tran-
sistor behavior to random process parameter variations, can be used
in conjunction with statistical device models to generate the WCF.
� The �rst step is to extract optimised model parameters from all of the
test devices using either measured or simulated device characteristics.
� Then, using standard statistical analysis, the mean and standard de-
viation of each model parameter is determined.
� Model parameters which are more than three standard deviations are
excluded.
� A sensitivity analysis is then carried out to determine the relationship
between a particular model parameter and the circuit performance
parameter (e.g. Idrive).
� For example, the sensitivity Si of Idrive to a model parameter pi is
given by,
Si = pi
0@�Idrive
�pi
1A
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MOS Transistors, E&CE 730, January, 2002 292
T
F
S
V DS
IDS
.
.........
.
..
Data Generated from Process Modelling
Measured Data
or
� The WCF are then the set of complete model parameter �les which
result in the �ve cases FF; SF; FS; SS; TT .
� The drawbacks of using this approach include the inability to pre-
dict how many devices on a wafer will exhibit the predicted perfor-
mance limits, the lack of accounting for correlations between the var-
ious model parameters, and the tendency to over-estimate the actual
process spread.
� For example, parameter sets may be obtained which cannot occur
in a real device due to correlations which exist between the various
parameters.
� In an attempt to address the correlation diÆculties with the above
method to determine WCF, the \Principal Factor Method" uses the
observation that most of the device parameter variations can be ex-
plained by considering variations in four parameters or principal factors
�L, �W , Cox, and Vfb.
� An advantage of the Principal Factor Method is that these principal
factors are essentially statistically independent of one another.
� The other model parameters pi are then related to these four principal
factors by,
pi = ao + a1�L + a2�W + a3Cox + a4Vfb
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MOS Transistors, E&CE 730, January, 2002 293
� where ao, a1, a2, a3, and a4 are called the regression coeÆcients which
are estimated using a measured data set from a large number of devices.
� The Principal Factor Method is useful when there is not a large mea-
sured statistical data set available and is superior to simple sensitivity
analysis, but still generates conservative WCF.
� Statistical analysis with parameter correlation is required to improve
upon the accuracy of generating the WCF over the above methods,
which requires the study of the probability distribution of each indi-
vidual parameter.