Previously - Penn Engineeringese370/fall2012/lectures/Day... · 2012. 10. 2. · Day12.pptx Author:...

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Penn ESE370 Fall2012 -- DeHon 1

ESE370: Circuit-Level

Modeling, Design, and Optimization for Digital Systems

Day 12: October 1, 2012 Variation

Previously •  Understand how to model

transistor behavior •  Given that we know its parameters

– Vdd, Vth, tOX, COX, W, L, NA …


CGC

CGCS

CGCB

But… •  We don’t know its parameters (perfectly) 1. Fabrication parameters have error range 2. Identically drawn devices differ 3. Parameters change with environment

(e.g. Temperature) 4. Parameters change with time (aging)

Why I am more concerned with robustness than precision.


Today

•  Sources of Variation – Fabrication – Operation – Aging

•  Coping with Variation – Margin – Corners – Binning


Fabrication


Process Shift •  Oxide thickness •  Doping level •  Layer alignment •  Growth and Etch rates and times

– Depend on chemical concentrations •  How precisely can we control those?

•  Vary machine-to-machine, day-to-day •  Impact all transistors on wafer


2

Systematic Spatial

•  Parameters change consistently across wafer or chip based on location

•  Chemical-Mechanical Polishing (CMP) – Dishing

•  Lens distortion


FPGA Systematic Variation

•  65nm •  Virtex 5

Penn ESE370 Fall2012 -- DeHon 8 [Tuan et al. / ISQED 2010]


Oxide Thickness

[Asenov et al. TRED 2002]


Line Edge Roughness

•  1.2µm and 2.4µm lines

From: http://www.microtechweb.com/2d/lw_pict.htm

Optical Sources

•  What is the shortest wavelength of visible light?

•  How compare to 45nm feature size?



Phase Shift Masking

Source http://www.synopsys.com/Tools/Manufacturing/MaskSynthesis/PSMCreate/Pages/default.aspx

Today’s chips use λ=193nm

3


Line Edges (PSM)

Source: http://www.solid-state.com/display_article/122066/5/none/none/Feat/Developments-in-materials-for-157nm-photoresists


Intel 65nm SRAM (PSM)

Source: http://www.intel.com/technology/itj/2008/v12i2/5-design/figures/Figure_5_lg.gif


Statistical Dopant

Placement

[Bernstein et al, IBM JRD 2006]

Random Trans-to-Trans

•  Random dopant fluctuation •  Local oxide variation •  Line edge roughness •  Etch and growth rates

– Stochastic process

•  Transistors differ from each other in random ways



Source: Noel Menezes, Intel ISPD2007

Impact

•  Changes parameters – W, L, tOX, Vth

•  Change transistor behavior – W? – L? –  tOX?


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Example: Vth

•  Many physical effects impact Vth – Doping, dimensions, roughness

•  Behavior highly dependent on Vth


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Vth Variability @ 65nm

[Bernstein et al, IBM JRD 2006]


Impact of Vth Variation?

•  Higher VTH? – Not drive as strongly –  Id,sat∝ (Vgs-VTH)2 – Performance?

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Impact Performance

•  Vth Ids Delay (Ron * Cload)


Impact of Vth Variation


Think NMOS Vgs = Vdd

FPGA Logic Variation

•  Xilinx Virtex 5 •  65nm

Penn ESE370 Fall2012 -- DeHon 24 [Wong, FPT2007]

•  Altera Cyclone-II

•  90nm

[Tuan et al. / ISQED 2010]

5


Impact of Vth Variation?

•  Lower VTH? – Not turn off as well leaks more

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Penn ESE370 Fall2012 -- DeHon 26 Borkar (Intel) Micro 37 (2004)

2004

Operation

Temperature Voltage


Temperature Changes •  Different ambient environments

– January in Maine – July in Philly – Air conditioned machine room

•  Self heat from activity of chip •  Quality of heat sink (attachment thereof)


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Self Heating


Borkar (Intel) Micro 37 (2004)

Thermal Profile for Processor


[Reda/IEEE Tr Emerging CAS v1n2 2011]

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Temperature (on current?)

•  High temperature – More free thermal energy

•  Easier to conduct •  Lowers Vth

–  Increase rate of collision •  Lower saturation velocity •  Lower saturation voltage •  Lower peak Ids slows down

•  One reason don’t want chips to run hot Penn ESE370 Fall2012 -- DeHon

31

Temperature and Ids


Temperature (leakage?)

•  High temperature Lowers Vth


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Voltage

•  Power supply isn’t perfect •  Differs from design to design

– Board to board? – How precise is regulator?

•  IR-drop in distribution •  Bounce with current spikes


Aging

Hot Carrier NBTI


Hot Carriers

•  Trap electrons in oxide – Also shifts Vth


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NBTI •  Negative Bias Temperature Instability

–  Interface traps, Holes •  Long-term negative gate-source voltage

– Affects PFET most •  Increase Vth

•  Partially recoverable? •  Temperature dependent


[Stott, FPGA2010] Another reason not to run hot.

Measured Accelerated Aging (Cyclone III, 65nm FPGA)


[Stott, FPGA2010]

Coping with Variation


Variation

•  See a range of parameters – L: Lmin – Lmax

– Vth: Vth,min – Vth,max



Impact of Vth Variation

•  Higher VTH – Not drive as strongly –  Id,sat∝ (Vgs-VTH)2

•  Lower VTH – Not turn off as well leaks more

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Variation •  Margin for expected variation •  Must assume Vth can be any value in range

–  Speed assume Vth slowest value

Pro

babi

lity

Dis

tribu

tion

VTH

Ion,min=Ion(Vth,max) Id,sat∝ (Vgs-Vth)2

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Gaussian Distribution


From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg

Impact

•  Given – Vth,nom = 250mV – Sigma 25mV

•  What maximum Vth should expect to see for a circuit of – 100 transistors? – 1000 transistors? – 109 transistors?


Class ended here


Variation

•  See a range of parameters – L: Lmin – Lmax

– Vth: Vth,min – Vth,max

•  Validate design at extremes – Work for both Vth,min and Vth,max ? – Design for worst-case scenario


Margining

•  Also margin for – Temperature – Voltage – Aging: end-of-life


Process Corners •  Many effects independent •  Many parameters •  With N parameters,

– Look only at extreme ends (low, high) – How many cases?

•  Try to identify the {worst,best} set of parameters – Slow corner of design space, fast corner

•  Use corners to bracket behavior Penn ESE370 Fall2012 -- DeHon

48

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Simple Corner Example


Vthp

Vthn 150mV

150mV

350mV

350mV

What happens at various corners?

Process Corners •  Many effects independent •  Many parameters •  Try to identify the {worst,best} set of

parameters – E.g. Lump together things that make slow

•  Vthn, Vthp, temperature, Voltage •  Try to reduce number of unique corners

– Slow corner of design space •  Use corners to bracket behavior


Range of Behavior

•  Still get range of performances •  Any way to exploit the fact some are faster?


Pro

babi

lity

Dis

tribu

tion

Delay


Speed Binning

Pro

babi

lity

Dis

tribu

tion

Delay

Discard Sell Premium

Sell nominal

Sell cheap

Midterm 1 •  Contents should not be a surprise

–  Identify CMOS/non-CMOS –  Identify CMOS function – Any logic function CMOS gate – Noise Margins – Transistor Equations

•  All regions and identify operating regions •  variation

– Circuit quasistatic configuration and switching delay


Admin

•  HW4 •  First midterm next Monday •  Previous midterm

– Solutions linked to 2011 syllabus – Solutions linked to 2010 syllabus

•  But only one midterm in 2010 so parts more advanced than where we are now

•  Review on Sunday – Time?


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Idea

•  Parameters Approximate •  Differ

– Chip-to-chip, transistor-to-transistor, over time

•  Robust design accommodates – Tolerance and Margins – Doesn’t depend on precise behavior


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