Preview of “L02 VHDL1.pptx” - Lunds tekniska högskola · 2012-09-04 ·...

Introduc)on*to*Structured*VLSI*Design*3VHDL*I Joachim Rodrigues

Lund University / EITF35/ Joachim Rodrigues 2012

Overview

•  VHDL History •  Entity-Architectures •  Concurrency •  Processes •  Concurrency •  Signals/Variables


Two*HDLs*used*today*

– VHDL&&and&Verilog&–  Syntax&and&``appearance''&of&the&two&languages&are&very&different&&

– CapabiliAes&and&scopes&are&quite&similar&– Both&are&industrial&standards&and&are&supported&by&most&soEware&tools&


VHDL*

Very*High*Speed*Integrated*Circuit*(VHSIC)**Hardware**Descrip)on**Language*

**

A Technology Independent, Standard Hardware description Language (HDL), used for digital system modeling, simulation, and synthesis


Why*VHDL?*

There&are&several&hardware&descripAon&languages&available;&VHDL&(Europe),&Verilog&(USA),&and&System&C&are&the&most&common.&

&Advantages&of&VHDL&•  IEEE&standard.&•  Supported&by&all&CAD&Tools.&•  Technology&independent.&•  Common&–&Specially&in&Europe.&&•  Flexible&–&Delay&modeling,&Matrices,&etc.&&&•  Supports&easy&modeling&of&various&abstracAon&levels.&&*


VHDL*History*

•  1981&–&VHSIC&IniAated&(US&DoD)&•  1985&–&VHDL&version&7.2&(IBM&and&TI)&•  1987&–&IEEE&standard,&VHDL&1076&–&1987&•  1993&–&Revised*standard,*VHDL*1164*–*1993*(std_logic_1164)&&•  2008&^&Accellera&approved&VHDL&4.0&also&informally&known&as&VHDL&2008&


VHDL*History*

VHDL&was&developed&as&a&language&for&modeling&and&simulaAon.&

&Consequence:&Mismatch&between&simulaAon&and&synthesis&^^&Most&constructs&in&VHDL&are&fine&for&simulaAon,&but&cannot&be&synthesized,&e.g.,&a"er,&'me,&etc.&

&With&restricAons,&VHDL&can&be&used&for&synthesis.&


VHDL*vs*SoJware*

•  VHDL&allows&the&descripAon&of&a&concurrent&system.&VHDL&is&a&dataflow&language,&unlike&procedural&compuAng&languages&s&(C,&C++,&assembly&code)&which&all&run&sequenAally,&one&instrucAon&at&a&Ame.&

•  key&advantage&of&VHDL:&allows&the&behavior&of&the&required&system&to&be&described&(modeled)&and&verified&(simulated)&before&synthesis&tools&translate&the&design&into&real&hardware&(gates&and&wires).&


Design*of*Digital*Systems*

•  VHDL&is&used&to&design&digital&systems&–  SimulaAon&–  Synthesis&

•  Goal&–  Reliable&design&process,&with&minimum&cost&and&Ame&–  Minimal&design&errors&–  Synthesizable&code&


Basic*Design*Methodology*

Requirements*

Simulate)RTL*Model*

Gate3level*Model*

Synthesize)

Simulate) Test*Bench*

Simulate)

Synthesize)

Simulate)


A*Digital*Design*in*VHDL*

A*digital*design*in*VHDL**requires**&•  DefiniAon&of&required&packages&(libraries),&e.g.,&std_logic_1164.&•  An&ENTITY&(corresponds&to&the&interface&of&a&component).&•  An&ARCHITECTURE&(describes&its&behavior). &&&An&enAty&may&have&several&architectures&*Op)onal:*A&CONFIGURATION&that&connects&an&ARCHITECTURE&to&an&ENTITY.&&


En)ty*3*Adder*

The&ENTITY&is&the&interface&of&a&component.&It&contains&all&IO^ports&(port&map)&and&possibly&generics.&

library IEEE; use IEEE.std_logic_1164.all; entity Adder is generic (N: integer); port(

A : in std_logic_vector (N-1 downto 0); B : in std_logic_vector (N-1 downto 0); S : out std_logic_vector (N-1 downto 0) ); end Adder;

B

S

A

+

Adder

N

N

N


En)ty3*Port*Declara)on*

Examples*of*declara)ons**

•  &1^bit&input&port&–  clk: in std_logic;

•  &8^bit&input&port,&MSB&leE&(commonly*used!!)&–  a : in std_logic_vector (7 downto 0);

•  &8^bit&output&port&–  S : out std_logic_vector (7 downto 0);

Possible&values&of&std_logic&&are:&'U',&'0',&'1',&'^',&'Z',&'X�&&�clk�&port&is&special&for&clock&pins&and&no&�in�&or&�out�&for&signal&names&

&Lund University / EITF35/ Joachim Rodrigues 2012

En)ty*3*Generics*

Used&to&pass&certain&properAes&into&a&design&to&make&it&more&general.&Typically:&

•  Bus&widths&•  Delays&&The&value&can&be&set&in&the&enAty&declaraAon&(default&value),&component&declaraAon,&or&component&instanAaAon.&


*Architecture*

•  An&architecture&is:&–  a&panern,&a&template,&a&way&of&doing&it&

•  Developing&a&good&architecture&involves:&–  CoordinaAon&and&opAmizaAon&across&many&

levels&of&abstracAon.&–  ...under&a&large&set&of&constraints&and&

requirements&(that&is&changing&over&Ame).&–  An&iteraAve&process&involving&design&and&

analysis.&�Exploring&the&design&space�.&


Architecture*Basically*two*types*of*architectures:**

•  Behavioral: using sequential processes

•  Structural: top level, component instantiation, concurrent processes&

Behavioral

Behav.

Behavioral Beh.

Be.

Behav.

Be.

Fully&behavioral&

ParAally&beh.&&&struct.&

Pipelined&structural&&


B

A

Adder

N

N

N

Architecture - behavioral

S +

Architecture defines behavior of the circuit

architecture behavioral of Adder is begin

s <= A+B; end architecture behavioral;


Architecture - behavioral

• Behavioral architecture

–  Describes the algorithm performed by the module, FSM

–  May contain •  Process statements •  Sequential statements •  Signal assignment statements •  Wait statements (not synthesizable)


Architecture - Structural

Structural architecture

–  Implements a module as a composition of components (modules)

–  contains •  signal declarations, for internal interconnections

–  Entity ports are treated as signals •  component instances

–  instances of previously declared entity/architecture pairs •  port maps in component instances

–  connect signals to component ports


Structural description

•  In structural view, a circuit is constructed by smaller parts.

•  Structural description specifies the types of parts and connections.

•  Essentially a textual description of a schematic

•  Done by using �component� in VHDL –  First declared (make known) –  Then instantiated (used)


Structural*descrip)on*

•  In&structural&view,&a&circuit&is&constructed&by&smaller&parts.&

•  Structural&descripAon&specifies&the&types&of&parts&and&connecAons.&

•  EssenAally&a&textual&descripAon&of&a&schemaAc&

•  Done&by&using&�component�&in&VHDL&–  First&declared&(make&known)&&–  Then&instan'ated&(used)&


Architecture - Mixing Behavioral and Structural

An architecture may contain both behavioral and structural parts –  process statements and component instances

•  collectively called concurrent statements –  processes can read and assign to signals

Example: Register-Transfer-Level (RTL) model

–  data path described structurally (component) –  control section described behaviorally


Components...

•  …that are instantiated in a structural descprition must first be declared

•  … appear in the declaration part of the architecure body

•  … may be declared in a package.

Declaration: Instantiation component FF is port (D,Q,clk); end component;

FF1:FF port map(D=>D, Q=>Q,clk=>clk);


Example: Structural Architecture

instantiate


Architecture body-Concurrency

•  All statements in an architecture body are concurrent •  Simplified syntax

•  An entity declaration can be associated with multiple architecture bodies


Exercise: Sketch the block diagram

instantiate


RTL- Implementation

27

32

48

Y=A*B+C

A

B C

Y

We&have&complete&control&(acAve&chioice)&over&the&registers:&inferred&by&the&RTL&developer&if (clock='1' and clock'event) then

The&content&of&the&cloud&is&misty:&we&can&specify&funcAonality&but&we&do&not&know&how&it&will&be&realized,&e.g.,&logic&gates&or&LUTs&


Combinational and Sequential Logic

CombinaAonal&circuit:&–&No&internal&state&–&Output&is&a&funcAon&of&inputs&only&–&No&latches/FFs&or&closed&feedback&loop&&SequenAal&circuit:&–&With&internal&state&–&Output&is&a&funcAon&of&inputs&and&internal&state&


Concurrent*Statements*and*Processes*

•  Concurrent*statements*(simple*processes):*–  a <= b; –  c <= a + b; –  d <= a And B;

•  Process*statements:*namelabel:&process*(a,*b,*…*sensi/vity)list)*&&variable&declara'ons…&begin*&&sequen'al&statements…&–  if&…&then&…&[else&|&elsif&…]&end&if;&–  for&n&in&0&to&7&loop…&–  case&b&is&…&–  s&:=&z&sll&shamt;&–  i&:=&a&+&b;&77variable&assignment,&only&in&processes&–  c&<=&i;&77concurrent&signal&assignment!&end*process*namelabel;&&

All*processes*are*“executed”*in*parallel*(think*of*gates*and*wires,*not*variables)*


VHDL Process

•  Contains a set of sequential statements to be executed sequentially

•  The whole process is a concurrent statement •  Can be interpreted as a circuit part enclosed inside a black

box

•  Two types of process –  A process with a sensitivity list –  A process with wait statement


A process with a sensitivity list

Syntax

process(sensitivity_list) declarations; begin sequential statement; sequential statement; . . . end process;

• A&process&is&like&a&circuit &part,&which&can&be&– acAve&(ac'vated)&&– inacAve&(suspended)&

• A&process&is&acAvated&when&a&signal&in&the&sensiAvity&list&changes&its&value&

• Process&statements&will&be&executed&sequenAally&unAl&the&end&of&the&process&

Sensistivity list will be ignored during synthesis


Good: process(a,b,c) begin y <= a and b and c; end process;

Process Example

bad: process(a) begin y <= a and b and c; end process;

3-input and circuit

For a combinational circuit, all inputs need to be included in the sensitivity list


A*process*with*wait*statement*

•  Process&has&no&sensiAvity&list&•  Process&conAnues&the&execuAon&

unAl&a&wait&statement&is&reached&and&then&suspended&

•  Forms&of&wait&statement:&–  wait&on&signals;&–  wait&un)l&boolean_expression;&–  wait&for&Ame_expression;&

•  OEen&used&in&the&testbench&

process begin y <= a and b and c; wait on a, b, c; end process;

&• A&process&can&have&mulAple&wait&statements&

• Process&with&sensiAvity&list&is&preferred&for&proper&modeling&


Signals*

•  Declared&in&the&architecture&body's&declaraAon&secAon&&Signal&declaraAon:&

signal signal_name, signal_name, ... : data_type

•  Signal&assignment:& signal_name <= projected_waveform;

•  Ports&in&enAty&declaraAon&are&considered&as&signals&


Signals*cont’d*

•  EnAAes&are&connected&by&signals&(wires)&•  Syntax:&

signal signal_names : signal_type; •  The&value&of&a&signal&is&given&by&the&voltage&level&of&the&wire&

(technology*dependent)&

High

Low

Abnormal

0

O.33Vcc

0.73Vcc

VccVOH3min

VIH3min

VIL3max

VOL3max

High9State3DC3noise3margin

Low393state3DC3noise3margin


Signals cont’d

•  Signals&are&metal&wires&of&arbitrary&length.&&–  Metal&has&inducAve,&resisAve,&and&capicAve&parasiAcs&which&introduce&delay.&

–  Real&parasiAcs&are&known&aEer&rouAng&•  Signals&connect&the&gates&in&a&design&•  Value&of&a&signal&is&determined&by&evaluaAng&an&expression&

–  Result&of&the&evaluaAon&must*match*the*type*of&the&signal&

•  Timing&info&ignored&in&synthesis&and&δ^delay&(simulaAon)&is&used

A <= b and c; Q <= '0'; Q <= D; y <= a + b + 1 after 10 ns;


Sequen)al*signal*assignment*statement*

•  Syntax

sig_name <= value_expression;

•  Syntax&is&idenAcal&to&the&simple&concurrent&signal&assignment&

•  &CauAon:&–  Inside&a&process,&a&signal&

can&be&assigned&mulAple&Ames,&but&only&the&last&assignment&takes&effect&&

process(a,b,c,d) begin -- yentry := y y <= a or c; -- yexit := a or c; y <= a and b;-- yexit := a and b; y <= c and d;-- yexit := c and d; end process; -- y <= yexit

is equal to

process(a,b,c,d) begin y <= c and d; end process;

What happens if the 3 statements are concurrent statements?


Delta-delay

architecture behav of encoder is signal abar_s,bbar_s : std_logic; begin -- behav z(3) <= not (a and b and enable); --(1) z(0) <= not (abar_s and bbar_s and enable); --(2) bbar_s <= not b; --(3) Z(2) <= not (a and bbar_s and enable) --(4) abar_s <= not a; --(5) Z(1) <= not (abar_s and b and enable) --(6) end behav;

CASE: event on b at time T

Target signals on (1,3,6) updated after T+Δ

Thus, event on bbar_s will trigger (2,4) and target signals are updated after T+2Δ

(5) will not be triggered at all


Delta-delay cont’d &Signals&are&updated&aEer&�0ns�,&or&aEer&delta&delay:&A&delta3delay**

–  represents&a&infinitesimally&small&delay&– Models&HW&where&a&minimal&amount&of&Ame&is&needed&for&a&change&to&occur.&&

–  Allows&for&ordering&od&events&that&occur&at&the&same&simulaAon&Ame&during&a&simulaAon&

&•  Each&unit&of&simulaAon&Ame&consists&of&an&infinite&number&of&delta^&delays&

•  An&event&always&occurs&at&simulaAon&Ame&+&a&mulAple&of&delta^delays&&

&Lund University / EITF35/ Joachim Rodrigues 2012

Variables

Declared and used inside a process Variable declaration:

variable variable_name, ... : data_type Variable assignment: variable_name := value_expression;

Contains no �timing info� (immediate assignment) No direct hardware counterpart


Variables cont’d

•  Variables declared and used inside a process are local •  Variables declared outside a process may be shared by

several processes (shared variables) •  Retain their value throughout simulation Example: process (...) variable index :integer :=0; begin index:=index +1;


Variable assignment statement

•  Syntax var_name := value_expression;

•  Assignment takes effect immediately

•  No time dimension (i.e., no delay)

•  Behave like variables in C •  Difficult to map to hardware

(depending on context)

process(a,b,c) variable tmp: std_logic; begin tmp := '0'; tmp := tmp or a; tmp := tmp or b; y <= tmp; end process;


process(a,b,c) variable tmp0, tmp1, tmp2: std_logic; begin tmp0 := '0';

tmp1 := tmp0 or a; tmp2 := tmp1 or b; y <= tmp2;

end process;

Variable assignment statement- Interpretation

We need to rephrase the code from the previous slide


Concurrency

•  Statements in the architecural body are concurrent –  Ordering of this statements NOT important

•  Example of statements –  Signal assignment

» a<= b and c » d<= not a

•  Processes –  Statements within a process are sequential


Exercise: Sketch a conceptual block diagram (one element per process)


Questions?

Preview of “L02 VHDL1.pptx” - Lunds tekniska högskola · 2012-09-04 ·...

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