IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 16, NO. 1, MARCH 2016 43

Prevention of Cracking From RDL Stress andDicing Defects in Glass Substrates

Scott McCann, Yoichiro Sato, Venkatesh Sundaram, Rao R. Tummala, and Suresh K. Sitaraman

Abstract—Glass substrates have outstanding electrical prop-erties, tailorable coefficient of thermal expansion (CTE), highmechanical rigidity, availability in large and thin panel form, andsmooth surface for fine line fabrication, and thus, have gainedincreased attention and interest in microelectronics industry since2010. While thin glass packaging offers such a plethora of benefits,glass is a brittle material and thus is prone to failure when copperwiring and polymer layers are deposited on it. This experimentaland theoretical work aims to understand the mechanics of glasscracking as a result of stress development from multilayer wiring,defect formation from panel dicing, and thermal cycling, thendesign a solution to prevent such cracks and demonstrate thissolution. Dicing defects are simulated by adding a crack intothe free edge of the glass and the energy available for crackpropagation, G, is determined through a finite element basedfracture mechanics approach. Moisture is well known to lowersurface energy, resulting in a lower critical energy release ratefor glass (GC) in the presence of moisture or water and, at thedefect sizes measured, G reaches GC , indicating that the sampleswill crack while dicing in water. With thinner dielectric material,optimized dicing process, improved glass-polymer adhesion, andsolder resist pullback, it is seen that glass cracking and glass-polymer delamination can be eliminated during dicing and sub-sequent thermal cycling.

Index Terms—Advanced packaging reliability, dicing, fracturemechanics, glass.

I. INTRODUCTION

G LASS has gained traction recently as a possible candidatefor microelectronic packaging substrate [1], [2]. This

is because of its outstanding electrical and high-temperatureproperties as well as its low cost potential [3]. In comparisonto organic substrate materials such as FR-4, glass is rigid, hasa high glass transition temperature, has a tailorable CTE, andprovides a smooth surface for lithography [4]. All of theseproperties lead to lower warpage [5], fine line lithography [6],[7] and fine pitch I/Os [8] while keeping the package thin. Glassis an electrical insulator with very low electrical loss and highresistivity [9]. However, glass has poor thermal conductivity,

Manuscript received August 7, 2015; revised November 16, 2015; acceptedNovember 29, 2015. Date of publication December 11, 2015; date of cur-rent version March 4, 2016. This work was supported by the Low CostGlass Interposers & Packages (LGIP) global industry consortium at GeorgiaTech PRC.

S. McCann and S. K. Sitaraman are with the Mechanical Engineering,Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail: smccann6@gatech.edu).

Y. Sato is with Asahi Glass Corporation, Ltd., Tokyo 100-8405, Japan.V. Sundaram and R. R. Tummala are with the Electrical and Computer

Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250 USA.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TDMR.2015.2507978

even though better than organic substrates currently used, andthus, thermal management should be addressed through othermeans such as through glass vias [10]. As a brittle material,glass is prone to cracking when subjected to stresses and defectsare created on to its surfaces.

Multilayer wiring or redistribution layers (RDL) formed bysequential deposition of polymer and copper is carried outon glass panels to create glass substrates for microeletronicpackages. Thermo-mechanical stresses develop due to CTEmismatch between RDL materials and glass upon thermal ex-cursions. Once fabricated, glass panels must be singulated intoindividual substrates by a mechanical or other dicing method.Such singulation or dicing could create large enough defects[11], that when combined with stresses from RDL, could leadto crack propagation ultimately resulting in glass substratecracking [12], [13].

Through glass vias (TGVs) are often included in packagingdue to the improved electrical performance as well as improvedthermal performance. Our and others’ work has studied thedrilling [14], [15] and metallization [15], [16], showing greaterthan 99.7% yield. In [17], the reliability of TGVs was investi-gated using thermal cycling and HAST and found no crackingof the glass or lifting of the routing in the vicinity of the TGVs.This work focuses on cracking from RDL stress and dicingdefects and does not include vias.

The primary objective of this work is to design, fabricate,and demonstrate multi-layered RDLs on glass substrates thatwill not crack during dicing or thermal cycling. Also, this workaims to explore ways to enhance interfacial adhesion betweenglass and polymer dielectric so that the multilayered substratewill not delaminate. Through physics-based numerical simula-tions and experiments, this work has developed a successfulimplementation of RDL layers on glass together with bladedicing methods for glass to be an acceptable substrate formicroelectronic applications.

II. FABRICATION, DICING, AND RELIABILITY TESTING

Glass panels were fabricated using class 1000 clean-roomprocesses applicable to substrate fabrication. Fabrication beganwith a 150 × 150 mm bare glass panel, which was cleanedand laminated with a layer of 10–22.5 μm polymer, ZEONIF™ZS-100. To promote adhesion between glass and polymer,silane was deposited through an aqueous alcohol solution. Thepolymer was cured in a conventional oven at 180 ◦C. Coppertraces were deposited through a semi-additive process (SAP).The SAP started with an electroless copper seed layer, ontop of which dry film photoresist was laminated, exposed and

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44 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 16, NO. 1, MARCH 2016

Fig. 1. Schematic of four metal layer glass substrate.

developed, and then copper was electroplated. The photoresistwas then stripped and the seed layer was etched, leaving5–10 μm of copper, which was then annealed. This processwas two sided, creating layers of polymer and copper traceson both sides simultaneously. The processes were repeated toadd a second layer of ZEONIFTM ZS-100 and copper traceson each side, for a total of four metal layers, which constitutedthe redistribution layers (RDL). Finally, a dry film passivationwas laminated, exposed, developed, and cured. During sequen-tial fabrication a number of chemicals were used for etching,stripping, and plating with different pH values. It was seen thatthe panel did not crack during any one of these processes. Thisis due to two reasons. First, the fabrication was done at the panellevel, and therefore, the glass panel did not have any starterdefect. Second, all of the chemicals that were used for etching,stripping, and plating processes were completely rinsed out,and thus, there was no residual chemical to bring about anychange in the critical energy release rate of the glass panel.Each panel had a six by six array of 18.4 × 18.4 mm substrates,the structure of which is shown in Fig. 1. These demonstrationsamples do not include any vias.

Once all layers were deposited and patterned, the glasspanels were then singulated into individual substrates by dicingmethods. In this work, blade dicing or mechanical dicing [11]was used, although other dicing options such as score andbreak, laser dicing, and laser ablation are available for glasspanels. In initial research (prior to this work) with mechanicaldicing, cohesive cracking of the glass, originating from thediced edge, occurred immediately after dicing. This was whilethe samples were still in the dicing tool or within two hoursof dicing, still attached to the tape. Such glass cracking upondicing has been reported by Koizumi, who termed the crackingfailure from the free edge “SeWaRe” [12]. However, not allfabricated substrates exhibited this failure, and such uncrackedsubstrates were subsequently subjected to preconditioning andthermal reliability test conditions.

Reliability testing includes preconditioning and temperaturecycling testing (TCT). The preconditioning includes a 24 hour120 ◦C bake, 60% RH at 30 ◦C for 168 hours, and three260 ◦C reflows. The TCT is from −40 ◦C to 125 ◦C withfifteen minute dwells and fifteen minute ramps. This testingfollows detailed procedures outlined in JEDECTM Standard020D.1 [18], JESD22-A113F [19], and JESD22-A104D, theJEDECTM Standard on Temperature Cycling [20].

TABLE IDETAILS FOR SAMPLE BATCH 1 (ALL DIMENSIONS ARE IN μm)

TABLE IIEXPERIMENTAL RESULTS FROM FABRICATION, DICING,

PRE-CONDITIONING, AND TEMPERATURE CYCLING

Samples were inspected after dicing, preconditioning, and50, 250, 500, and 1000 temperature cycles. Inspection was doneusing an optical microscope and a C-mode scanning acousticmicroscope (CSAM). From this inspection, crack progress, ifany, was documented and analyzed.

III. INITIAL EXPERIMENTAL DATA

The first set of samples was fabricated, diced, and reliabilitytested. Table I shows the details for all samples fabricated. Asseen in this table, Batch 1 had two 22.5 μm thick polymerlayers and two 10 μm thick copper layers on each side of thesubstrate. Pullback is a change to the solder resist mask used inBatches 3a and 3b, which will be discussed in a later section.

After dicing, some of the samples cracked immediately,while still on the tape, often seen in prior work. For the samplesthat did not crack after dicing, the experimental results after pre-conditioning and 50 temperature cycles are shown in Table II.The samples are labeled by Batch Number-Sample Number,e.g. 1-A4 is Sample A4 from Batch 1. In Table II, the samplesare classified by using stop light colors as status indicators:Green indicates no failure. Only dicing-induced pock markswere seen. Yellow indicates some interfacial delamination be-tween polymer and glass; however, no glass cracking was ob-served. Red indicates glass cracking. Fig. 2 shows micrographsfor the three cases.

Two types of glass cracking have been observed for dicing-induced failures. The first is cohesive cracking of the glass,which occurs during, or very shortly after, blade dicing. Thesecond is a result of a three-step process, which starts withdicing defects, then the glass-polymer interface delaminates,and finally the crack kinks into the glass. These two types offailures can be seen in Figs. 2–4. Figs. 3 and 4 are scanningelectron microscopy images of a glass substrate edge andcorner, respectively, after crack propagation. The delaminationcase has been covered in depth in our previous work [13].

From Table II, the Batch 1 samples that did not crackafter dicing, showed some interfacial delamination after

McCANN et al.: PREVENTION OF CRACKING FROM RDL STRESS AND DICING DEFECTS IN GLASS SUBSTRATES 45

Fig. 2. Optical inspection of glass substrate edge to show failure classification:(a) pock marks after dicing (green), (b) interfacial delamination between glassand polymer (orange), and (c) cracking of glass substrate after interfacialfailure (red).

Fig. 3. SEM of glass substrate edge after crack propagation, showing dicing-induced defects, delamination, and cohesive cracking of the glass.

Fig. 4. SEM of glass substrate corner after crack propagation, showing delam-ination of glass-polymer interface.

Fig. 5. (a) Finite-element model mesh example and (b) zoomed-in defect withcontour integral.

TABLE IIIMATERIAL PROPERTIES USED IN MODELING

preconditioning, and cracked after 50 temperature cycles, thefirst inspection point during TCT. For the samples to passthe reliability criteria, they need to survive 1000 temperaturecycles.

IV. DICING SIMULATION

Although samples 1-A4 and 1-A5 did not fail during dic-ing, the earlier samples did fail during dicing, and thus, thissection studies such dicing-induced failures through fracturemechanics approach. Finite-element models were created usingANSYS 14.5™ to predict the occurrence of glass crackingfailure. Fig. 5(a) shows an example of the 2D plane-strain finiteelement model. Table III shows the material properties usedin the model; reference temperatures are chosen based on thefabrication process. Copper was deposited as an electroless seedlayer at 34 ◦C and then plated electrolytically at 40 ◦C using11 or 14A of DC current, then etched and annealed at 180 ◦C.For such plated structures, the total stress at room temperatureis less than 20 MPa [21], [22]. As the residual stresses aremuch less than the thermally-induced CTE-mismatch stresses,this work does not account for copper residual stresses. Cureshrinkage can be introduced through an artificial increase ofcure or reference temperature [23]. For the dielectric polymer,the in-plane cure shrinkage is 0.2 percent and the vertical cureshrinkage is 15 percent. Thus, it is sufficient to increase thestress-free temperature to account for this shrinkage. As thistemperature increase is small, this work has not addressed

46 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 16, NO. 1, MARCH 2016

the shrink age effect beyond this. The geometry mimics thefabricated substrate, with a glass core and build-up polymer,copper, and passivation layers. The model employs symmetryat the left hand side. A dicing-induced horizontal flaw wasintroduced on the free edge on the right, which was placed15 μm from the glass-polymer interface. The location of theflaw is arbitrary and can be anywhere along the thickness ofthe glass. Regardless of the location, except close to the glass-polymer interface, the trends presented in the following sectionare applicable.

A typical mesh near the crack tip is shown in Fig. 5(b). Acontour integral approach was used within the finite-elementsoftware to calculate the energy release rate using J-integral,where J is defined as,

J =

∮Γ

(Wdy − T · ∂u

∂xds

)(1)

where Γ is the counterclockwise curve surrounding the cracktip, x and y are in-plane directions (as shown in Fig. 5(a)), u isthe displacement vector, ds is the infinitesimal distance alongthe path, T is the traction, and W is the strain-energy densitydefined as,

W =

ε∫0

σijdεij (2)

where σij and dεij are the stress and strain tensors, respectively[27]. For a linear, brittle, isotropic material, such as glass, J isequal to the strain energy release rate, G [28]. If G reaches thecritical energy release rate, GC , then the crack will propagateand the glass will crack. The strain energy release rates obtainedthrough the contour integral approach were cross checked usingthe Virtual Crack Closure Technique (VCCT) [29] and found tobe near identical to the J integral results.

Starting with different reference temperatures for differentmaterials, the glass substrate with polymer, copper, and solderresist layers was cooled to room temperature, and the energyavailable for horizontal crack propagation into the glass wasdetermined using J-integral as discussed above as well as in ourearlier conference publication [13]. The initial crack size in themodel was guided by experimental confocal imaging of variousglass substrates where it was seen that the dicing-induced flawswould be in the range of 2 to 10 um, as shown in Table I. Afterdicing, the diced edge surface was mapped using an OlympusLEXT™ 3D confocal microscope. In addition to confocal mea-surements, cross sections of cracked and uncracked sampleswere imaged to validate defect sizes.

Blade dicing is done in the presence of water to cool the bladeand remove debris. During dicing, crack propagation is morelikely due to not only stress by RDL layers and defect formationin dicing but also lowering of surface energy and fracturetoughness of glass in the presence of water. For example, thecritical stress intensity factor of borosilicate glass drops from0.8 MPa

√m in air to about 0.4 MPa

√m in the presence of

water [30]. Therefore, the obtained energy release rates werecompared to the critical energy release rate of borosilicate glassin water, 1.98 J/m2. Multiple models were constructed with

Fig. 6. Energy release rate as a function of initial defect size during dicing fora crack 15 μm from the glass-polymer interface.

TABLE IVDETAILS FOR SAMPLE BATCHES 2a AND 2b

(ALL DIMENSIONS ARE IN μm)

a range of horizontal crack sizes and the energy release rateavailable was examined, as shown in Fig. 6. As seen, an initialdefect size as small as 10 μm might be close enough to resultin glass cracking failure in some of the samples in Batch 1(90 μm polymer, 40 μm copper).

Reducing the build-up thickness reduces the tensile stresson the free edge of the glass, and thus, simulations were runwith reduced build-up layer thicknesses, as given in Table IV.Results for the reduced thickness build-ups are shown in Fig. 6,alongside Batch 1. When thin build-up layers are used, asexpected with lower stresses, cracks do not propagate even withlarge dicing defects.

V. DICING OPTIMIZATION AND THINNER

STACK UP EXPERIMENTS

The models suggest that with thinner polymer and copperlayers, there should be less chances for cracking, and to provethis, two new Sample Batches, 2a and 2b, were fabricated,diced, and reliability tested, as described in the Fabrication,Dicing, and Reliability Testing section. Sample Batch 2a had17.5 μm thick polymer for a total thickness of 70 μm, and10 μm thick copper layers for a total thickness of 40 μm;

McCANN et al.: PREVENTION OF CRACKING FROM RDL STRESS AND DICING DEFECTS IN GLASS SUBSTRATES 47

TABLE VEXPERIMENTAL RESULTS FROM FABRICATION, DICING, ANDTEMPERATURE CYCLING FOR SAMPLE BATCHES 2a AND 2b

Batch 2b had 10 μm thick polymer for a total thickness of40 μm and 5 μm thick copper layers for a total thickness of20 μm. Both structures followed the schematic in Fig. 1 andfull details are presented in Table IV. In addition to the build-upthickness changes, a dicing optimization was performed [11].Prior to dicing optimization, the typical defect size was mea-sured to be 2.1–7.8 μm (Table I); after dicing optimization, thetypical defect size was 1.2–6.6 μm (Table IV).

The experimental results after dicing, preconditioning,50 temperature cycles, and 1000 temperature cycles for Batches2a and 2b are shown in Table V. Table V uses the same statusindicator color scheme as in Table II.

Similar to the first round of samples, the new samples showedpock marks after dicing and delamination after preconditioning.However, at 50 temperature cycles, the glass substrate did notcrack. These samples continued thermal cycling and passed1000 cycles without glass cracking. This demonstrates thatthinner build-up, which is expected to develop lower stresses,reduce the available energy for crack propagation below thecritical level, preventing crack propagation in glass.

Although glass cracking was eliminated through thinnerbuild-up layers, it was seen that there was some delaminationat the glass-polymer interface with thermal cycling, and thus, asolution to eliminate delamination was desired.

VI. ADHESION IMPROVEMENT AND

SOLUTION DEMONSTRATION

While cohesive cracking of the glass was not seen withthinner build-up layers, large glass-polymer interfacial delami-nations could ultimately result in cohesive cracking after kink-ing into brittle materials [31]. The criteria for such kink andcohesive cracking depends on the ratio of the critical energyrelease rate of the interface to the critical energy release rate ofthe material [32] and mode mix [33], [34]. To improve adhesionof the glass-polymer interface, the fabrication process waschanged to include a plasma clean (after the chemical cleaningand before silane treatment) and the silane application waschanged from liquid to vapor. The plasma clean roughens thesurface of the glass, which improves adhesion. Vapor depositionof the silane, although expensive and time-consuming, alsoimproves adhesion compared to the liquid silane process.

To demonstrate a complete solution to glass cracking, twomore sample batches were fabricated with the improved adhe-sion. The optimized blade dicing was used. Sample Batch 3ahad 17.5 μm thick polymer for a total thickness of 70 μm and10 μm thick copper layers for a total thickness of 40 μm;Sample Batch 3b had 10 μm thick polymer for a total thickness

TABLE VIDETAILS FOR SAMPLE BATCHES 3a AND 3b

(ALL DIMENSIONS ARE IN μm)

Fig. 7. Schematic of solder resist pullback. Pullback distance is measuredfrom edge of dicing street.

of 40 μm and 5 μm thick copper layers for a total thickness of20 μm. Full details are presented in Table VI.

At the free edge, the axial and interfacial shear stresses dropto zero to satisfy the boundary conditions. The shear stresswhich causes delamination reaches a peak value at approxi-mately the magnitude of the thickness and then drops to zero[35]. The thickness of the build-up can be reduced locally nearthe free edge by pulling back the build-up material, and thus,the magnitude of the stress can be reduced near the crack tip.Pullback has more effect when more material is removed. Forpractical fabrication, pullback was implemented on the solderresist only by changing the passivation mask to include a widedicing street. The distance of the pullback is measured fromthe edge of the dicing street, as illustrated in Fig. 7. SampleBatches 3a and 3b had the solder resist pulled back from thedicing street by 150 μm as shown in the schematic in Fig. 7.The pulling back of solder resist reduces the energy availablefor crack propagation, as illustrated in Fig. 6. By comparingthe energy release rate for identical samples without and withpullback (Batch 2a vs. Batch 3a and Batch 2b vs. Batch 3b), it isseen that the energy release rates are reduced by 10–20 percentwhen the initial defect size is below the pullback length. Whenthe initial defect size is greater than the pullback length, theenergy release rates are near identical regardless of pullback.

The effect of passivation pullback and full pullback distanceis investigated during blade dicing by adding pullback to themodel described in Dicing Simulation and changing the lengthof the passivation pullback for a 10 μm crack, as shown inFig. 8 for Sample Batches 3a and 3b. For both passivationsamples, the available energy release rates start at the values

48 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 16, NO. 1, MARCH 2016

Fig. 8. Effect of passivation pullback and full pullback on energy release rateduring dicing.

TABLE VIIEXPERIMENTAL RESULTS FROM FABRICATION, DICING, ANDTEMPERATURE CYCLING FOR SAMPLE BATCHES 3a AND 3b

seen in samples without pullback, which is Sample Batches 2aand 2b, respectively, and approaches an asymptotic value asthe pullback length increases. For the full pullback cases, theasymptotic values are zero because there is no build-up materialremaining on the substrate. However, larger pullback lengthsmean no passivation is covering an area and no interconnectionsor lines can be made, wasting space on the substrate. Fromthese results, a 150 μm passivation pullback captures 87 percentof the benefit of a very large pullback for the thicker build-upstructure and 95 percent of the benefit for the thinner build-upstructure. While larger pullbacks have more effect, the benefitcomes at the cost of lost space, and thus is a compromiseis made and the 150 μm passivation pullback is chosen forsample fabrication. Expanding the pullback concept to includeall layers, or full pullback, is under investigation and will bereported in future work.

The experimental results after dicing, preconditioning,50 temperature cycles, and 1000 temperature cycles for SampleBatches 3a and 3b are shown in Table VII, which uses thesame status indicator color scheme as in Table II. All samplesfrom Batches 3a and 3b passed 1000 temperature cycles withoutany crack propagation in glass or delamination of the glass-polymer interfaces, fully demonstrating a solution to dicing-

Fig. 9. (a) CSAM and (b) optical inspection of corners of sample 3b-F2 after1000 temperature cycles.

induced glass cracking failures. As an example, Fig. 9 showsSample 3b-F2 after 1000 temperature cycles. The pock markdicing pattern was seen. However, no interfacial delaminationor glass cracking was observed through 1000 cycles.

VII. CONCLUSION

In this experimental and theoretical work, cohesive crackpropagation in glass substrates due to RDL stresses and dicing-induced defects was studied. Crack propagation can occurduring blade dicing, when glass has lower surface energy due tothe presence of moisture, or due to a sequence of dicing-induceddefects, glass-polymer delamination, and the interfacial crackkinking into the glass.

To prevent crack propagation, a solution of thinner build-up,blade dicing optimization, adhesion improvement, and pullbackwas proposed and demonstrated. Starting from samples thatfailed immediately after dicing or during reliability testing, theproposed solution successfully passed dicing, preconditioning,and 1000 temperature cycles without glass cracking or interfa-cial delamination. This solution enables glass substrates withbuild-ups of up to 70 μm dielectric polymer and 40 μm copper

McCANN et al.: PREVENTION OF CRACKING FROM RDL STRESS AND DICING DEFECTS IN GLASS SUBSTRATES 49

to be fabricated with existing blade dicing technology. Addi-tional samples and other solution methods are being exploredand tested, and the results from those studies will be reported ina future publication.

ACKNOWLEDGMENT

The authors would like to acknowledge Yutaka Takagi andthe fabrication team as well as Vanessa Smet and the assemblyteam from GT PRC, Frank Wei from Disco, Sathya Raghavan,and CASPaR lab members for their invaluable contributionsand support.

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Authors’ photographs and biographies not available at the time of publication.