1

Presenter: Min Yu,Lo

112/04/19

Keita Nakajima, Takuji Hieda, Ittetsu Taniguchi. Hiroyuki Tomiyama, Hiroaki Takada 2012 Third International Conference on Networking and Computing

112/04/192

NoC design◦ The design of NoCs at Register-Transfer-Level (RTL) is time-

consuming. It is also very difficult to modify and/or change the network architecture if the design is not suitable for the target application.

NoC Simulator design Availability (Simulation time ) Scalability (Simulation of Various sizes NoC architecture) Retargetability (Simulation of Various processor) Full system verification

This paper proposed NoC simulator◦ In the proposed simulator, each CPU core is emulated by a

QEMU, and the network part including NoC routers is modeled with SystemC.

Accelerated this NoC simulator◦ This NoC simulator can be executed on multiple host

computers since the SystemC simulator and QEMUs are connected via standard TCP sockets.

112/04/193

112/04/194

JPEG encoding application benchmark program. Changed the number of cores on the NoC Simulator.◦ Simulated six NoC architectures(9,18,36,54,72,90,108). Run this simulator on two host computers. ◦ The distributed simulation on the dual host computers is 43% faster

than the single-host simulation.

112/04/195

Show this simulator supports any CPU core supported by QEMU since this use QEMU without modification.

In order to test the retargetability of the simulator, Changed the ISA of target cores and measured the simulation times.