Presented By: Rodney Fluharty Dec. 07, 2000. Who is ARM? Advanced Risc Microprocessor is the...
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Transcript of Presented By: Rodney Fluharty Dec. 07, 2000. Who is ARM? Advanced Risc Microprocessor is the...
![Page 1: Presented By: Rodney Fluharty Dec. 07, 2000. Who is ARM? Advanced Risc Microprocessor is the industry's leading provider of 16/32-bit embedded RISC microprocessor.](https://reader033.fdocuments.us/reader033/viewer/2022051517/56649f395503460f94c56c4b/html5/thumbnails/1.jpg)
Presented By: Rodney FluhartyDec. 07, 2000
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Who is ARM?Who is ARM?
• Advanced Risc Microprocessor is the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions.
• Licenses their high-performance, power-efficient RISC processors, peripherals, and system-chip designs to leading international electronics companies.
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Who uses ARM technology?
Atmel, Cirrus Logic (www.cirrus.com), Fujitsu, Mitel (www.mitel.com), IBM, LG Semicon (www.lgsemicon.co.kr/), LSI Logic, Lucent Technologies (www.lucent.com), National Semiconductor, NEC, Oki, Samsung, Seiko Epson (www.epson.co.jp/), Sharp, Texas Instruments, Toshiba, and VLSI.
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Why Don’t I see “ARM” chips?
• They are sold as VC (virtual components) and IP (intellectual property).
• Their designs are embedded and only the technology is ARM’s.
• Much cheaper to use existing technology.
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Brief Overview of ARM 940T• Member of ARM 9 family.
• Complete CPU subsystem (Bus, Cache, Core)
• Harvard Architecture: Separate Data and Instruction Memory.
• 31 general-purpose registers with 16 simultaneously visible.
• Core is a 32-bit RISC processor.
• Do not support Virtual Addressing.
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Core Block DiagramCore Block Diagram
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Microprocessor Block DiagramMicroprocessor Block Diagram
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Number CrunchingNumber Crunching
• Single-cycle 16X32-bit multiply-accumulate (MAC) unit
• Integer based only.
• Floating point would require a co-processor.
• Lack Integer divides (must synthesize division)
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Bus Architecture/Clocking Bus Architecture/Clocking MethodologiesMethodologies
• Separate data/instruction busses.
• Two clock inputs (BCLK, FCLK).
3 Modes of clocking:
• FastBus: Used with high speed memory;• BCLK controls ARM91TDMI, cache ops, AMBA
Bus.
• FCLK ignored.
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• Synchronous - Used for low-speed memory; both clock inputs used.
• BCLK controls bus
• FCLK controls core, cache.– Rules for Synchronous
» FCLK > BCLK
» BCLK transition must occur when FCLK high.
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• Asynchronous - Used for low-speed memory; both clock inputs used.
• BCLK controls bus
• FCLK controls core, cache.– Rules for Synchronous
» FCLK > BCLK
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Cache DescriptionCache Description
• Instruction/Data Cache = 4Kb
• 8 word write buffer
• Each cache comprises four, fully-associative 1kb segments.
• Single-cycle reads, one/two cycle writes (depending on sequence of instructions).
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Cache Description ContinuedCache Description Continued
•Implements “Read-on-miss replacement” policy.
•Selection by randomly clocked rows (unless locked).
•Can use “Write-back” or “Write-through”
•Implement both “Valid” and “Dirty” bits.
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Cache ArchitectureCache Architecture
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PipeliningPipelining• 5 Stage pipeline (fetch, decode, execute,
memory, write-back).
• Implements bubble insertion.
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Introduction to ThumbIntroduction to Thumb
• Why waste memory on instructions if not necessary?
• 16 bit subset of the 32 bit instruction set.
• Thumb module located in pipeline.
• Decompresses 16 bit instruction to 32 bit equivalent with no delays.
• Up to 30% code density improvement.
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A Closer LookA Closer Look
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How much does this affect?How much does this affect?
• 36 of the ARM’s native instructions have been adapted to Thumb technology.
• These did not benefit from the full 32 bit instruction.
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Jazelle TechnologyJazelle Technology• Java was developed for embedded systems, so it
makes sense to optomize an embedded processor for Java!
• Historically:– Java source code is converted to a Java byte code.– Machine had to convert byte code to instructions at
execution time.– This can be very slow on low-power embedded
hardware (cell phones, set-top boxes, handhelds).
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Wake me up when it’s loaded...Wake me up when it’s loaded...
• Original hardware solutions involved costly external co-processors.
• ARM’s solution: Add one more instruction and about 12,000 gates to the decode.
• Enter ‘BXJ Rm’ and the ARM goes into Java mode eliminating the slower JVM
• Certain registers are re-assigned to Java.• Still ARM and Thumb compatible.
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Let the numbers speakLet the numbers speak
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ConclusionConclusion
• ARM continues to produce high quality, embedded processors.
• ARM has developed new technologies to optomize hardware.
• Newer products such as the ARM10 or StrongARM (@600MHz) will likely appear in everyday life.