Presentation for Advanced VLSI Course

presented by:Shahab adin Rahmanian

Instructor:Dr S. M.Fakhraie

Major reference:3D Interconnection and Packaging: Impending Reality or Still a Dream?

By:Eric Beyne

December 2004

Overview

Introduction : Why 3D-interconnects? Classification of 3D-technologies 3D-SIP 3D-SOC 3D-IC Conclusion

Introduction : Why 3D?Drivers for 3D interconnects & packaging :

Size reduction: minimal area/volume of an electronic system

Solving the “interconnect bottleneck” :

Long interconnects are too slow Long interconnects consume too much power

Hetero-integration: “Seamless” mixing of different microelectronic

technologies at the wafer level

The Interconnect Bottleneck

Driven by technology scaling, SOC devices are

partioned in functional blocks (“tiles”) Within a “tile”:

Operations can be performed within a single clock cycle Interconnects : Local and intermediate interconnect levels on

the die

The interconnect between the tiles : “Global” interconnect levels : longest on chip interconnect lines,

significantly less interconnects than on local & intermediate levels

Speed-limiting factor on the chip : require repeaters Significant source for area & power consumption.

The Interconnect Bottleneck

If the functional “tiles” on the chip could be stacked in

the 3rd dimensions, the chip area would be reduced,resulting in much shorter global interconnect lines.

Logic & Memory

2D interconnectLong lines betweenLogic & MemoryThrough bus

SOC solution: Large die Large size Memory cells

3D interconnectShort, direct

linesBetween Logic

&Memory banks

3D-Interconnect technology

Current developments in packaging technologyare delivering the key enabling technologies forbuilding true 3D stacked devices:

Thinning of wafers, below 50 µm , as thin as the active layer. Wafer-to-wafer bonding, up to 300 mm diameter wafers. Die-to-wafer bonding: singulated “top” die are bonded to “bottom”

die on a base waferWafer-through-hole technologies: realization of electrically

isolated connections through the silicon substrate. Many of these technologies were originally developed inthe field of MEMS technology and are now finding theirapplication in IC packaging technologies.

Different 3D-interconnect“flavors”

3D-SIP : 3D-”System-in-a-Package” Stacking of multiple die in a single package Stacking of multiple SIP-packages 3D-interconnects at the traditional chip pin-out level

3D-SOC : 3D-”System-on-a-Chip” Stacking of wafers or die-to-wafer with 3D-global

interconnectivity at the “tile”-level 3D-IC :

Stacking of wafers with interconnectivity at local level (gate or transistor level)

3D-SIPDie stacking in a single

package Assembly by wire bonding of stacked die in a single

package has been shown by several packaging vendors.Main limitation : interconnectivity interposer substrate does

not allow for complex rerouting among the die. Only possible for specific applications, such as standard

memory stacking, or die with specific I/O pad rerouting. Requires “Known-good-die”(KGD)

3D-SIPStacking of chip-scale SiP-

packages Improving the Yield and manufacturability of

3D-SIP by stacking of 2D-SIP “sub-systems” Each layer is an SIP package Each layer has the same size Each layer is fully tested before final assembly Many different technologies may be used for each

individual layer Results in :

Generic 3D technology Best yield and manufacturability

Limitations : Relatively low 3D interconnectivity Lack of standardization of package sizes

3D-SIP visionary application:E-cube

E-Cube: distributed, fully autonomous system for realizing “ambient intelligent” systems.

3D-SIP application Example

3D-SIP bluetooth rf radio, measuring 7mmx7mmx2.5mm,Rf-front-end CSP stacked on a digital base band CSP.

3D-SOC Stacking of die at the wafer level

Reduced critical global interconnect lengths by stacking

3D-interconnectivitiy at the “tile” level Requires a significantly higher 3D-wiring density

than 3D-SiP

Technology components: “Die-to-wafer” transfer & bonding : different chip sizes allowedUses very thin Si : 50 µm and below

Ultra Thin Chip Stacking, UTCS

Objective: To Realize 3D-VLSI structures, based on the integration of thinned standard die, in a modified multilayer thin film technology :

3D Wiring scheme UTCS

3D interconnectivity around the perimeter of the die:> 100 connections per mm2 and per layer

Wafer thinning200 mm wafer CMOS wafer, thinned down to50 µm thickness.

Thinning of standard CMOSwafers, down to 10 - 15 µm

Thinning of standard CMOSwafers, down to 10 - 15 µm

Embedded test die

15 µm thin Si-die, transferred to a host substrate and

electrically connected to that substrate

Why ultra thin die & thindielectrics ?

Thermal : thermal resistance dielectrics between die in the stack result in an increase of the thermal resistance

1 µm BCB dielectric =10 µm SiO2 =1 mm Si 10 µm BCB between two 1 cm2 die : 0.5 K/W thermal resistance Interface thermal resistance Die/BCB : for 1 cm2 die : 0.3 to 0.75 K/W (experimental)

Mechanical : thermo-mechanical stress limits the

maximum height of the stack to 3 layers.

Why ultra thin die & thindielectrics ?

Electrical: thin dielectrics allow for a tighterinterconnect line pitch for the same cross-talk level

Impact of wafer thinning on the

electrical performance Test chip: 20x20 mm, IMEC 0.35 µm CMOS

process development test reticle. Processing:

Mechanical wafer thinning down to 50 µm Face-down bonding test wafer to a dummy carrier wafer Plasma thinning test die down to 10-15 µm Singulation die Transfer of thinned die to a carrier substrate

Measurements: Transistor parameters before and after thinning.

Electrical measurements

Vtlin versus Ldes for CMOS transistors, measured beforeand after thinning and stacking on a host Si wafer.

3D-IC3D-local interconnects at “gate-

level” “Scaling-driven” technology: integrates more transistors per unit area. Differences with 3D-SOC :

3D-interconnects are local interconnects: several orders of magnitude more connections required than 3D-SOC.

3D-interconnects block substantial areas for transistorlogic : lower effective integration density

No solution for long, global interconnect lines Requires “wafer-to-wafer” bonding : equal size stacked die.

Highly complex technology, questionable yield & economics

ConclusionsIn order to be successful, 3D-Interconnect andpackaging technologies need to becomemanufacturable technologies (high yield) :

high degree of parallel processing of individual layers, testing of these intermediate layers stacking of “known-good-devices”.

This goal is likely to be reached first for 3D-SIP,

followed by 3D-SOC. This is confirmed by the emergence of such technologies in actual products.

It is much further out for 3D-IC technologies.

References

[1] Eric Beyne “3D Interconnection and Packaging: Impending Reality or Still a Dream?”ISSCC 2004 Pictures from Reference [1]

[2] G.Carchon et.al., IEEE-CPMT, vol. 24, pp. 510-519, 2001.