Preliminary measurements for the 8 channel prototype of SPD

discriminator ASIC

I. The 8 channel prototype.

II. Status of the test.

III. Noise.

IV. Gain.

V. Test plan.

VI. Schedule for PRR and production.

LHCb Calo Electronics Meeting – December 2003 – Clermont-Ferrand

I. The 8 channel prototype (I).

• Random signal shape (20-30 phe/MIP): shaping methods discarded integration.integration.

• Only about 80% of signal in 25 ns (no dead time for integration allowed) + response to consecutive events Dual channel: synchronous system + Pile-up correctionDual channel: synchronous system + Pile-up correction

• PMT gain limited by aging (DC current) 100fC/MIP in hotest cells.

• 5-10 MIP range to perform tail correction.

• Robust to temperature variations (band gap reference).

• Small cavity Power consumption < 1W. Prototype at 3.3V (0.6 W)

I. The 8 channel prototype (II).

• Area: 30 mm2.

• Package: naked die (10), JLCC68 (10) and EDQUAD TQFP 64 (30).

• Target package is EDQUAD TQFP 64 for size and power dissipation.

• Ceramic JLCC68 is also requested because better knowledge of its performance (used for previous prototypes) .

II. Status of the test.

• 10 JLCC + 10 naked dies were receive at beginning of November .

• 46 EDQUAD TQFP were received last week.

• Automated test system is under development.

• Hardware (test boards and VHDL code for FPGA used for DAQ) is finished.

• Software (Labview and C) for data taking and on-line analysis is almost finished.

• Digital interface has been completely tested with random sequences write/read and is fully functional.

• Power consumption is as expected: 180 mA (0.6 W).

• Consumption of different supply pins is in agreement with simulation.

• Some further “manual” measurements have been done.

III. Noise (I): 50 PMT load (input resistor).

• Sigma of differential histogram between 1 and 2 mV r.m.s.• Measurement error is not negligible compared with transition width.• Possible contributions of pick-up noise should be studied.

-4,00

-3,00

-2,00

-1,00

0,00

1,00

2,00

3,00

4,00

-90 -85 -80 -75 -70 -65 -60 -55 -50

Threshold [mV]

-d<

Vo

D>

/dt

[V]

Differentiated Histogram Chip 1 Ch 3-1 Differentiated Histogram Chip 1 - Ch 3-2 Histogram Chip 1 Ch 3-1 Histogram Chip 1 Ch 3-2

III. Noise (II): 390 PMT load (input resistor).

• Sigma of differential histogram between 1 and 2 mV r.m.s.• Noise increase is not seen.• Measurement error is not negligible compared with transition width.• Possible contributions of pick-up noise should be studied.

-4,00

-3,00

-2,00

-1,00

0,00

1,00

2,00

3,00

4,00

-100 -90 -80 -70 -60 -50 -40

Threshold [mV]

-d<

VoD

>/d

t [V

]

Differentiated Histogram Chip 1 Ch 5-1 Differentiated Histogram Chip 1 Ch 5-2 Histogram Chip 1 Ch 5-1 Histogram Chip 1 Ch 5-2

IV. Gain (I): pulse injection.

• A step pulse is differentiated through a series capacitor: the charge over RLPMT must be Q=Cac x Vstep (Vstep is the pulse amplitude).

• The pulse must be much longer than 25ns

• The time constant of the circuit <<25ns to inject all the charge in 1 period.

• The 95 % of the signal is on 25 ns (gain has been corrected).

50-400 O hm

RLPM T

C a c

1p FVste p

IV. Gain (II): results.

• Gain for 390 PMT load : 1mV/fC.• Linear range 1 pC of input charge or 1 V of threshold.• Input referred noise (ENC) between 1 and 2 fC.• MIP signal between 100 fC and 50 fC (after first compensation of PMT non-uniformities).

Gain for Ch 5-1

-1500,000

-1000,000

-500,000

0,000

500,000

1000,000

1500,000

-1,50E+03 -1,00E+03 -5,00E+02 0,00E+00 5,00E+02 1,00E+03 1,50E+03

Input charge [fC]

Thre

shol

d to

0->

1 [m

V]

Vth/Q C1

V. Test plan.

1. Offset per subchannel (function of pile-up compensation subtractor).

2. Noise per subchannel (function of pile-up compensation subtractor and PMT load).

3. Cross-talk between subchannel threshold (same Vref).

4. Low frequency noise (random trigger vs. sync. trigger).

5. Linearity (function of pile-up compensation subtractor).

6. Matching and calibration of of pile-up compensation.

7. Cross-talk between channels.

8. Pedestal stability with time.

9. Aging.

10. Tª dependence.

11. ESD test on inputs and control pins.

12. Possible effects of pick-up noise cause by massive switching of digital outputs (PCB dependent).

VI. Schedule.

• If no serious troubles are found systematic measurements might be finished by end of January 2004.

• When should we ask to pass the PRR?

• If no defects are find and PRR is passed on February chip will be ready for production in March?

• According to CMP it is possible “start production when you want”, different from a MPW run.

• Sharing production masks with PS VFE chip might save some money... It has been asked to CMP/AMS. Are the schedules for both chips compatible?