Precision 1:4 LVPECL Fanout Buffer

April 2014

ZL40202Precision 1:4 LVPECL Fanout Buffer

Data Sheet

Ordering Information

ZL40202LDG1 16 Pin QFN TraysZL40202LDF1 16 Pin QFN Tape and Reel

Matte Tin

Package size: 3 x 3 mm

-40oC to +85oC

Features

Inputs/Outputs

• Accepts differential or single-ended input• LVPECL, LVDS, CML, HCSL, LVCMOS

• Four precision LVPECL outputs

• Operating frequency up to 750 MHz

Power

• Option for 2.5 V or 3.3 V power supply

• Core current consumption of 62 mA

• On-chip Low Drop Out (LDO) Regulator for superior power supply noise rejection

Performance

• Ultra low additive jitter of 39 fs RMS

1Microsemi C

Copyright 2014, Microsemi Cor

Figure 1 - Funct

Bufferclk_pclk_n

Applications

• General purpose clock distribution

• Low jitter clock trees

• Logic translation

• Clock and data signal restoration

• Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC

• PCI Express generation 1/2/3 clock distribution

• Wireless communications

• High performance microprocessor clock distribution

orporationporation. All Rights Reserved.

ional Block Diagram

out3_pout3_n

out2_pout2_n

out1_pout1_n

out0_pout0_n

ZL40202 Data Sheet

Table of Contents

2Microsemi Corporation

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.3 Device Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.4.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.4.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.0 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

ZL40202 Data Sheet

List of Figures


Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 3 - LVPECL Input DC Coupled Thevenin Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 4 - LVPECL Input DC Coupled Parallel Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 5 - LVPECL Input AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 6 - LVDS Input DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 7 - LVDS Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 8 - CML Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 9 - HCSL Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 10 - CMOS Input DC Coupled Referenced to VDD/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 11 - CMOS Input DC Coupled Referenced to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 12 - Simplified Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 13 - LVPECL Basic Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 14 - LVPECL Parallel Output Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 15 - LVPECL Parallel Thevenin-Equivalent Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 16 - LVPECL AC Output Termination for Externally Terminated LVPECL Inputs . . . . . . . . . . . . . . . . . . . . 13Figure 17 - LVPECL AC Output Termination for Internally Terminated LVPECL Inputs. . . . . . . . . . . . . . . . . . . . . 13Figure 18 - LVPECL AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 19 - Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 20 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 21 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 22 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

ZL40202 Data Sheet

Change Summary

Page Item Change

1 Applications Added PCI Express clock distribution.

5 Pin Description Added exposed pad to Pin Description.

6, 7 Figure 3 and Figure 4

13 Figure 16 Corrected LVPECL interface circuit.

18 Figure 21 Clarification of VID and VOD.

Below are the changes from the February 2013 to the April 2014 issue:

Page Item Change

7 Figure 4 Changed text to indicate the circuit is not recommended for VDD_driver=2.5V.

7 Figure 5 Changed pull-up and pull-down resistors from 2kOhm to 100 Ohm.

Below are the changes from the November 2012 issue to the February 2013 issue:

Removed 22 Ohm series resistors from Figure 3 and 4. These resistors are not required; however there is no impact to performance if the resistors are included.


ZL40202 Data Sheet

1.0 Package DescriptionThe device is packaged in a 16 pin QFN

14

16

6

42

out3_n

vdd

out3_p

NC

clk_

p

vdd

gnd

out0_n

out2

_n

out2

_p

out1

_n

812 10

out1

_p

clk_

n

NC

out0_p

gnd

Figure 2 - Pin Connections

2.0 Pin Description

Pin # Name Description

1, 4 clk_p, clk_n, Differential Input (Analog Input). Differential (or singled ended) input signals. For all input signal configuration see “Clock Inputs” on page 6

15,14, 12, 11, 10, 9, 7, 6

out0_p, out0_nout1_p, out1_nout2_p, out2_nout3_p, out3_n

Differential Output (Analog Output). Differential outputs.

8, 13 vdd Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal.

5, 16 gnd Ground. 0 V.

2, 3 NC No Connection. Leave unconnected.

Exposed Pad Device GND.


ZL40202 Data Sheet

3.0 Functional Description

The ZL40202 is an LVPECL clock fanout buffer with four identical output clock drivers capable of operating at frequencies up to 750MHz.

Inputs to the ZL40202 are externally terminated to allow use of precision termination components and to allow full flexibility of input termination. The ZL40202 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL, LVDS, CML or HCSL input signals; single ended input signals can also be accepted. A pin compatible device with internal termination is also available.

The ZL40202 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.

The device block diagram is shown in Figure 1; its operation is described in the following sections.

3.1 Clock Inputs

The ZL40202 is adaptable to support different types of differential and singled-ended input signals depending on the passive components used in the input termination. The application diagrams in the following figures allow the ZL40202 to accept LVPECL, LVDS, CML, HCSL and single-ended inputs.

50 Ohms

50 Ohms

VDD_driver

VDD

VDD_driver=3.3V: R1 = 50 ohmNot recommended for VDD_driver=2.5V

ZL40202

clk_p

clk_n

Zo = 50 Ohms

Zo = 50 Ohms

R1

LVPECLDriver

Figure 3 - LVPECL Input DC Coupled Thevenin Equivalent


ZL40202 Data Sheet

VDD_driver

R2 R2

R1 R1

VDD_driver

VDD

VDD_driver=3.3V: R1=127 ohm, R2=82 ohmVDD_driver=2.5V: R1=250 ohm, R2=62.5 ohm

ZL40202

clk_p

clk_n

Zo = 50 Ohms

Zo = 50 Ohms

LVPECLDriver

Figure 4 - LVPECL Input DC Coupled Parallel Termination

R R

VDD_driver

VDDVDD_driver=3.3V: R = 143 ohmVDD_driver=2.5V: R = 82 ohm

ZL40202

clk_p

clk_n

Zo = 50 Ohms

Zo = 50 Ohms

LVPECLDriver

VDD

100Ohm

100Ohm

100Ohm

100Ohm

100 nF

100 nF

Figure 5 - LVPECL Input AC Coupled Termination


ZL40202 Data Sheet

Zo = 50 Ohms

VDD_driver

VDD

ZL40202

clk_p

clk_nZo = 50 Ohms

100 Ohms

LVDSDriver

Figure 6 - LVDS Input DC Coupled

VDD

2 KOhm

VDD_driver

VDD

ZL40202

clk_p

clk_n

Zo = 50 Ohms

Zo = 50 Ohms

2 KOhm

2 KOhm

2 KOhm

100 Ohm LVDSDriver

100 nF

100 nF

Figure 7 - LVDS Input AC Coupled


ZL40202 Data Sheet

VDD

2 KOhm

VDD_driver

VDD

ZL40202

clk_p

clk_n

Zo = 50 Ohms

Zo = 50 Ohms

2 KOhm

2 KOhm

2 KOhm

CMLDriver

100 nF100 nF

VDD_driver

50Ohm

50Ohm

Figure 8 - CML Input AC Coupled

VDD

2 KOhm

VDD_driver

VDD

ZL40202

clk_p

clk_n

Zo = 50 Ohms

Zo = 50 Ohms

2 KOhm

2 KOhm

2 KOhm

HCSLDriver

100 nF

100 nF

50Ohm

50Ohm

Figure 9 - HCSL Input AC Coupled


ZL40202 Data Sheet

VDD_driverVDD_driver VDD

ZL40202

clk_p

clk_n

CMOSDriver

R

R

C

Vref = VDD_driver/2

R = 10 kohm, C = 100 nF

Figure 10 - CMOS Input DC Coupled Referenced to VDD/2

VDDVDD_driver

VDD

ZL40202

clk_p

clk_n

CMOSDriver

R2

C

RA

R3

R1

Figure 11 - CMOS Input DC Coupled Referenced to Ground

Table 1 - Component Values for Single Ended Input Reference to Ground

VDD_driver R1 (kΩ) R2 (kΩ) R3 (kΩ) RA (kΩ) C (pF)

1.5 1.25 3.075 open 10 10

1.8 1 3.8 open 10 10

2.5 0.33 4.2 open 10 10

3.3 0.75 open 4.2 10 10

* For frequencies below 100 MHz, increase C to avoid signal integrity issues.


ZL40202 Data Sheet

3.2 Clock Outputs

LVPECL has a very low output impedance and a differential signal swing between 1V and 1.6 V. A simplified diagram for the output stage is shown in Figure 12.The LVPECL to LVDS output termination is not shown since there is a separate device that has the same input and LVDS outputs.

out_p

out_n

Figure 12 - Simplified Output Driver

The methods to terminate the ZL40202 LVPECL drivers are shown in the following figures.

LVPECLReceiver

50 Ohms

50 Ohms

VDD VDD_Rx

Zo = 50 Ohms

Zo = 50 Ohms

ZL40202clk_p

clk_n

VDD ‐ 2

Figure 13 - LVPECL Basic Output Termination


ZL40202 Data Sheet

LVPECLReceiver

50 Ohms

50 Ohms

VDD VDD_Rx

Zo = 50 Ohms

Zo = 50 Ohms

ZL40202clk_p

clk_n

RFor VDD = 2.5 V: R = 20 OhmsFor VDD = 3.3 V: R = 50 Ohms

Figure 14 - LVPECL Parallel Output Termination

R2 R2

VDD VDD_Rx

Zo = 50 Ohms

Zo = 50 Ohms

ZL40202clk_p

clk_n

For VDD = 2.5 V: R1 = 250 Ohms, R2 = 62.5 OhmsFor VDD = 3.3 V: R1 = 127 Ohms, R2 = 82 Ohms

VDD

R1 R1

LVPECLReceiver

Figure 15 - LVPECL Parallel Thevenin-Equivalent Output Termination


ZL40202 Data Sheet

VDD VDD_Rx

Zo = 50 Ohms

Zo = 50 Ohms

ZL40202clk_p

clk_n

100 nF

100 nFR

LVPECLReceiver

R2R

VDD= 3.3V: R = 120 OhmVDD = 2.5 V: R = 60 Ohm

VDD_Rx

R2

R1R1

Figure 16 - LVPECL AC Output Termination for Externally Terminated LVPECL Inputs

VDD VDD_Rx

Zo = 50 Ohms

Zo = 50 Ohms

ZL40202clk_p

clk_n

100 nF

100 nFR

LVPECLReceiver

2K Ohm

2K Ohm

R


2K Ohm

2K Ohm

Figure 17 - LVPECL AC Output Termination for Internally Terminated LVPECL Inputs

F o r V D D _ R x = 3 . 3 V : R 1 = 8 2 O h m s , R 2 = 1 2 7 O h m sF o r V D D _ R x = 2 . 5 V : R 1 = 6 2 . 5 O h m s , R 2 = 2 5 0 O h m s


ZL40202 Data Sheet

VDD VDD_Rx

Zo = 50 Ohms

Zo = 50 Ohms

ZL40202clk_p

clk_n

100 nF

100 nFR

CMLReceiver

50Ohm

50Ohm

R


Figure 18 - LVPECL AC Output Termination for CML Inputs


ZL40202 Data Sheet

3.3 Device Additive Jitter

The ZL40202 clock fan out buffer is not intended to filter clock jitter. The jitter performance of this type of device is characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as it passes through the device. The additive jitter of the ZL40202 is random and as such it is not correlated to the jitter of the input clock signal.

The square of the resultant random RMS jitter at the output of the ZL40202 is equal to the sum of the squares of the various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to power supply noise. There may be additional deterministic jitter sources that are not shown in Figure 19.

+Jin

2 Jout2= Jin

2+Jadd2+Jps

2

Jadd2

Jps2

Jin = Random input clock jitter (RMS)Jadd = Additive jitter due to the device (RMS)Jps = Additive jitter due to power supply noise (RMS)Jout = Resultant random output clock jitter (RMS)

+

Figure 19 - Additive Jitter


ZL40202 Data Sheet


3.4 Power Supply

This device operates with either a 2.5V supply or 3.3V supply.

3.4.1 Sensitivity to power supply noise

Power supply noise from sources such as switching power supplies and high-power digital components such as FPGAs can induce additive jitter on clock buffer outputs. The ZL40202 is equipped with a low drop out (LDO) power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The LDO regulator on the ZL40202 allows this device to have superior performance even in the presence of external noise sources. The on-chip regulation, recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from power supply noise.

The performance of these clock buffers in the presence of power supply noise is detailed in ZLAN-403, “Power Supply Rejection in Clock Buffers” which is available from Applications Engineering.

3.4.2 Power supply filtering

For optimal jitter performance, the device should be isolated from the power planes connected to its power supply pins as shown in Figure 20.

• 10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating• 0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating• Capacitors should be placed next to the connected device power pins• a 0.3 ohm resistor is recommended for the filter shown in Figure 20

Figure 20 - Decoupling Connections for Power Pins

VDD

0.3 Ohms0.1 µF

10 µF

ZL40202

8

13

3.4.3 PCB layout considerations

The power nets in Figure 20 can be implemented either as a plane island or routed power topology without changing the overall jitter performance of the device.

ZL40202 Data Sheet

Absolute Maximum Ratings*

Parameter Sym. Min. Max. Units

1 Supply voltage VDD_R -0.5 4.6 V

2 Voltage on any digital pin VPIN -0.5 VDD V

3 LVPECL output current Iout 30 mA

4 Soldering temperature T 260 °C

5 Storage temperature TST -55 125 °C

6 Junction temperature Tj 125 °C

7 Voltage on input pin Vinput VDD V

8 Input capacitance each pin Cp 500 fF

4.0 AC and DC Electrical Characteristics

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.* Voltages are with respect to ground (GND) unless otherwise stated

Recommended Operating Conditions*

Characteristics Sym. Min. Typ. Max. Units

1 Supply voltage 2.5 V mode VDD25 2.375 2.5 2.625 V

2 Supply voltage 3.3 V mode VDD33 3.135 3.3 3.465 V

3 Operating temperature TA -40 25 85 °C* Voltages are with respect to ground (GND) unless otherwise stated

DC Electrical Characteristics - Current Consumption

Characteristics Sym. Min. Typ. Max. Units Notes

1 Supply current LVPECL drivers - unloaded

Idd_unload 62 mA Unloaded

2 Supply current LVPECL drivers - loaded (all outputs are active)

Idd_load 140 mA Including power to RL = 50

DC Electrical Characteristics - Inputs and Outputs - for 3.3 V Supply


1 Differential input common mode voltage

VCM 1.1 2.0 V

2 Differential input voltage difference VID 0.25 1 V

3 LVPECL output high voltage VOH VDD-1.40

V


ZL40202 Data Sheet

* This parameter is measured from 125 MHz to 750 MHz

* This parameter is measured from 125 MHz to 750 MHz

Figure 21 - Differential Voltage Parameter

* Supply voltage and operating temperature are as per Recommended Operating Conditions

4 LVPECL output low voltage VOL VDD-1.62

V

5 LVPECL output differential voltage* VOD 0.5 0.9 V



1 Differential input common mode voltage

VCM 1.1 1.6 V

2 Differential input voltage difference VID 0.25 1 V

3 LVPECL output high voltage VOH VDD-1.40

V

4 LVPECL output low voltage VOL VDD-1.62

V

5 LVPECL output differential voltage* VOD 0.4 0.9 V

outx_p

outx_nVOD

VOH

VOL

outx_p – outx_n

GNDVCM

0 2*VOD

clk_p – clk_n

0 2*VID

clk_p

clk_nVID

GND

AC Electrical Characteristics* - Inputs and Outputs (see Figure 22) - for 2.5 and 3.3 V supplies.


1 Maximum Operating Frequency 1/tp 750 MHz

2 Input to output clock propagation delay tpd 0 1 2 ns

3 Output to output skew tout2out 50 100 ps

4 Part to part output skew tpart2part 80 300 ps

5 Output clock Duty Cycle degradation tPWH/ tPWL -2% 0% 2% Duty Cycle

6 LVPECL Output slew rate rsl 0.75 1.2 V/ns




ZL40202 Data Sheet

Input

tP

tPWL

tpd

tPWH

Output

Figure 22 - Input To Output Timing


ZL40202 Data Sheet

Additive Jitter at 2.5 V*

Output Frequency (MHz) Jitter

Measurement

Filter

Typical

RMS (fs)

Notes

1 125 12 kHz - 20 MHz 112

2 212.5 12 kHz - 20 MHz 80

3 311.04 12 kHz - 20 MHz 70

4 425 12 kHz - 20 MHz 65

5 500 12 kHz - 20 MHz 56

6 622.08 12 kHz - 20 MHz 46

7 750 12 kHz - 20 MHz 44

Additive Jitter at 3.3 V*

Output Frequency (MHz) Jitter

Measurement

Filter

Typical

RMS (fs)

Notes

1 125 12 kHz - 20 MHz 112

2 212.5 12 kHz - 20 MHz 82

3 311.04 12 kHz - 20 MHz 72

4 425 12 kHz - 20 MHz 63

5 500 12 kHz - 20 MHz 52

6 622.08 12 kHz - 20 MHz 43

7 750 12 kHz - 20 MHz 39

5.0 Performance Characterization

*The values in this table were taken with an approximate input slew rate of 0.8 V/ns

*The values in this table were taken with an approximate input slew rate of 0.8 V/ns

Additive Jitter from a Power Supply Tone*

Carrier frequency Parameter Typical Units Notes

125MHz 25 mV at 100 kHz 159 fs RMS

750MHz 25 mV at 100 kHz 82 fs RMS

* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test, measurements were taken over the full temperature and voltage range for VDD = 3.3 V. The magnitude of the interfering tone is measured at the DUT.


ZL40202 Data Sheet

6.0 Typical Behavior

Typical Phase Noise at 622.08 MHz Typical Waveform at 155.52 MHz

Input Slew Rate versus Additive Jitter Propagation Delay versus Temperature

Note: This is for a single device. For more details see the characterization section.

VOD versus Frequency

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0 5 10 15 20

Volta

ge

Time (ns)

25

50

75

100

0.5 1 1.5 2 2.5 3

Addi

tive

Jitte

r (fs

RM

S)

Slew Rate (V/ns)

212.5 MHz

311.04 MHz

425 MHz

500 MHz

622.08 MHz

0.35

0.4

0.45

0.5

-50 -30 -10 10 30 50 70 90

Prop

agat

ion

Dela

y (n

s)

Temperature (°C)

0.6

0.65

0.7

0.75

0 200 400 600 800

Volta

ge

Frequency (MHz)


ZL40202 Data Sheet

Power Supply Tone Magnitude versus PSRR (at 100 kHz) at 125 MHz

Power Supply Tone Magnitude versus Additive Jitter (at 100 kHz) at 125 MHz

Power Supply Tone Frequency (at 25 mV) versus PSRR at 125 MHz

Power Supply Tone Frequency (at 25 mV) versus Additive Jitter at 125 MHz

-85

-80

-75

-70

-65

20 30 40 50 60 70 80 90 100

PSRR

(dB)

Power Supply Tone Magnitude at 100 kHz (mV pk-pk)

100

200

300

400

500

600

700

20 30 40 50 60 70 80 90 100

Jitte

r (fs

RM

S)

Power Supply Tone Magnitude at 100 kHz (mV pk-pk)

-85

-80

-75

0 100 200 300 400 500 600

PSRR

(dB)

Power Supply Tone Frequency at 25 mV (kHz)

150

175

200

225

250

275

300

0 100 200 300 400 500 600

Addi

tive

Jitte

r (fs

RM

S)

Power Supply Tone Frequency at 25 mV (kHz)


ZL40202 Data Sheet

7.0 Package Thermal Characteristics

* Proper thermal management must be practiced to ensure that Tjmax is not exceeded.

Thermal Data

Parameter Symbol Test Condition Value Unit

Junction to Ambient Thermal Resistance ΘJA Still Air1 m/s2 m/s

67.961.658.1

oC/W

Junction to Case Thermal Resistance ΘJC Still Air 44.1 oC/W

Junction to Board Thermal Resistance ΘJB Still Air 23.2 oC/W

Maximum Junction Temperature* Tjmax 125 oC

Maximum Ambient Temperature TA 85 oC


20204LZ Data Sheet

8.0 Mechanical Drawing

24

Microsemi Corporation

© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.

Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense and security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has approximately 3,400 employees globally. Learn more at www.microsemi.com.

Microsemi Corporate Headquarters OneOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996E-mail: [email protected]

ZL40202

Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. However, Microsemi assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Microsemi or licensed from third parties by Microsemi, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Microsemi, or non-Microsemi furnished goods or services may infringe patents or other intellectual property rights owned by Microsemi.

This publication is issued to provide information only and (unless agreed by Microsemi in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Microsemi without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical and other products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Microsemi’s conditions of sale which are available on request.

For more information about all Microsemi productsvisit our website at

www.microsemi.com

TECHNICAL DOCUMENTATION – NOT FOR RESALE

http://www.microsemi.com

mailto:[email protected]

http://www.microsemi.com

Precision 1:4 LVPECL Fanout Buffer

Documents

Transcript of Precision 1:4 LVPECL Fanout Buffer