Ppc Assembly Intro

7/29/2019 Ppc Assembly Intro

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Introduction to PowerPC

Assembly


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Assembly and Machine

InstructionsPowerPC machine instructions:

Each instruction is 32-bit (4-byte) long

Instructions are divided into fields

Example:ADDI r1, r2, 64

Letop-code = 14, D = 1, A = 2, IMM = 64

(ADDI: Add a register and an immediate)

op-code D A IMM

6-bit 5-bit 5-bit 16-bit


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InstructionsAssembler: Translate assembly program

into object code

Translate assembly instruction with binarymachine instruction

Translate data declarations into data

memory binary format Translate labels into addresses/symbols


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InstructionsMnemonic forms of 32-bit machine instructions Common forms:opcoderD, rA, rB

opcoderD, rA, IMMbxxlabel

Additional supports for Pseudo instruction

Labels

Directives

Others


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InstructionsTypical instruction types

Integer load and store

Integer arithmetic, compare, logic and shift

Floating point load and store

Float point arithmetic, compare, logic,

Branch instructions

Miscellaneous: e.g. system calls


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PowerPC Registers

General purpose registers (GRP) 32 32-bit registers: r0 to r31

Register usage Dedicated: data area anchor, stack pointer

Volatile: Caller save

Nonvolatile: Callee save

Floating point registers 32 64-bit registers: fr0 to fr31


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PowerPC Registers

Register R0 is different from R1-R31

Sometimes it is zeroaddi r1, r0, 100 ; r1


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PowerPC Registers

Condition Register (CR) Conditions of integer

arithmetic operations

Floating Point Status andCondition Register (FPSCR)

Conditions of integerarithmetic operations

Integer Exception Register(XER):

Overflow and carry bits

Link register (LR)

To hold return address

Count register (CTR)

To hold loop count(associated with specialbranch instructions)


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Load and Store

Move data between registers and memory

Load or store

Read or write memory?Data size

To read/write one byte, two bytes, or a wholeword?

Extension Register is always 32-bit (for 32-bit MPC555) Extend data as signed or unsigned number?

Addressing mode How is the address given?


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Load and StoreAssume $r3 = 0x20000000

mem(0x20000200) = 0x12345678 (big endian)

Load byte with zero extension

lbz r5, 0x200(r3) ; r5 = 0x00000012lbz r5, 0x201(r3) ; r5 = 0x00000034

Load half word with zero extension

lhz r5, 0x200(r3) ; r5 = 0x00001234

lhz r5, 0x202(r3) ; r5 = 0x00005678

Load word with zero extensionlwz r4, 0x200(r5) ; r4 = 0x12345678


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Load and Store

Memory addressing mode: how to calculate effect ive add ress(EA)

DisplacementEA = base register value + offset (displacement)lwz r4, 0x1000(r3) ; EA = r3 + 0x1000

Register IndexedEA = base register value + index register value

lwzx r5, r3, r4 ; EA = r3 + r4

Suffix x represents register indexed


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Load and Store

How to fill a register when a byte or half-word?

A register is always 32-bit for MPC555

Zero extension: Fill the leftmost bitswith zeros

Algebraic extension: Fill the leftmostbits with the sign bit value


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Load and StoreAlgebraic extension: use a suffix

Assume $r3 = 0x20000000 and mem(0x20000200) =0x87654321 (big endian)

Load byte with algebraic extensionlba r5, 0x0200(r3) ; r5 = 0xFFFFFF87

lba r5, 0x0202(r3) ; r5 = 0x00000043

Load half word with algebraic extension

lha r5, 0x0200(r3) ; r5 = 0xFFFF8765

lha r5, 0x0202(r3) ; r5 = 0x00004321


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Load and Store

Which load instructions should be usedto load m and n?

short m;unsigned short n;


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Load and Store

Suppose $r3 = 0x20000000, r4 = 0x00001000

mem(0x20001000) = 0x87654321 (big-endian)

What will be the value in register r3?lbz r5, 0x1000(r3)

lba r5, 0x1000(r3)

lhzx r5, r3, r4

lhax r5, r3, r4


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Load and Store

Store instructions Three data sizes: byte, half-word, word

Two addressing modes: displacement or register indexed

No extension issue

Examples: stb r5, 0x1000(r3)

sth r5, 0x1000(r3)

stwx r5, r3, r4


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Integer Arithmetic and Logic

Common arithmetic operations: add, subf, neg, mul,div

Common bitwise logic: and, or, xor, nand

Examples:addr5, r3, r4 ; r5 = $r3 + $r4subf r5, r3, r4 ; r5 = $r4 - $r3or r5, r3, r4 ; r5 = $r3 | $r4

Check PowerPC manual for others


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Integer Arithmetic and Logic

Use immediate operands: Add i suffix

Examples:addi r5, r3, 100 ; r5 = r3 + 100addi r5, r0, 200 ; r5 = 0 + 200 = 200ori r5, r3, 0x1 ; r5 = r3 | r4

How large can the immediate operand be?


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Integer Arithmetic and LogicEvery instruction is encoded into 32-bit binary

op rD, rA, IMM (arithmetic/logic with one immediate)

op rD, d(rA) (load/store using displacement)

op rD, rA, rB (arithmetic/logic using three registers)

op rD, rA, rB (load with register indexed)

op rS, rA, rB (store with register indexed)

op-code D/S Other bitsA B

op-code D A IMM/d

6-bit 5-bit 5-bit 16-bit

6-bit 5-bit 5-bit 11-bit5-bit


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Integer Shift OperationsLogic and arithmetic shifts

slw: shift left word

srw: shift right word

sraw: shift right algebraic (arithmetic)Examples

slw r5, r3, r4

sraw r5, r3, r4

slwi r5, r3, 1


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Branch Instructions

Branch condition Use conditions in the CR register

Branch Target address The branch target used to fill PC if the branch is taken


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Branch Instructions

Condition register CR

Four condition bits:

LT: Less than zero?GT: Greater than zero?EQ: Equal zero?SO: Summary of Overflow

CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7

LT GT EQ SO4-bit

eight fields, 32-bit


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Branch Instructions

How to set condition?

Compare words

cmpw rA, rBcmpwi rA, IMM

In CR0:LT = 1 if rA < rB

GT = 1 if rA > rBEQ = 1 if rA = rB

(SO: dont care now)


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Branch InstructionsCompare unsigned signed words (compare logical)

cmplw rA, rB ; set CR0 for unsigned; comparison of rA and rB

cmplwi rA, IMM ; use immediate value


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Branch Instructions

Use LT, GT, EQ, SO bits in condition register

bxx target

Examples:blttarget ; branch taken if LT = 1

bgt target ; branch if GT = 1

beqtarget ; taken if EQ = 1

bletarget ; taken if GT = 0

b target ; unconditional branch


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Branch Instructions

C Program

if (x > y)

z = 1;else

z = 0;

cmpw r3, r4

ble else

addi r31, r0, 1

b doneelse:

addi r31, r0, 0

done:

Notes:

Revised from CodeWarrior disassemble

x r3; y r4; z r31

li r31, 1 => addi r31, 0, 1; li called simplified mnemonic

(pseudo-instruction)


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Constant and Absolute

AddressEach instruction is only 32-bit; how to handle 32-bit

constants?

Solution: Use addis and ori addis: add immediate shifted by 16-bit

ori: or immediate

Example: Place 0x20001000 into R3addis r3, r0, 0x2000 ; r3 = 0x20000000

ori r3, r3, 0x1000 ; r3 = 0x20001000


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AddressPseudo instructions

Instructions that do not represent native machineinstructions

; load immediate

li rA, IMM ; addi, rA, r0, IMM

; load immediate and shift by 16-bit

lis rA, IMM ; addis, rA, r0, IMM


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AddressHow to set up a 32-bit address?

char *pDIPSwitch1 = (char *) 0x4000000B;*pDIPSwitch1 = 0x0F;

PowerPC Assembly:


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PowerPC Assembly Exercise

Exercise: Simple assignments Use_a,_b as the address ofa andb

a = b;

a = 10;


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Answer: a = 10;; assume a is of int type

; r3 to hold 10li r3, 10 ; set up the value

lis r0, _a@h ; set up base addr

stw r3, _a@l(r0) ; store a


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Exercise: Arithmetic Expressions

c = a + b;

e = (a & b) | (c & d);


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Answers: c = a + b;; assume a, b, c are of int type

; r3 a, r4 b, r5 c

lis r0, _a@h ; set up base addr

lwz r3, _a@l(r0) ; load a

lis r0, _b@h ; set up base addr

lwz r4, _b@l(r0) ; load b

add r5, r3, r4 ; a + b

lis r0, _c@h ; set up base addr

stw r5, _c@l(r3) ; store c


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Exercise: If statement

if (x > y)

max = x;

else

max = y;

1. Write goto version

2. Translate into PowerPC assembly


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Exercise: Calculate the parity bit of n

m = n;

parity = 0;

do {

parity ^= (m & 1);

m >>= 1;

} while (m != 0);


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Exercise: Calculate the sum of X[N]

sum = 0;

for (i = 0; i < N; i ++) {

sum += X[i];

}

1. Write goto version

2. Translate into PowerPC assembly

Ppc Assembly Intro

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